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Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[cris-mirror.git] / drivers / net / ethernet / realtek / r8169.c
blobe55638c7505a787e501fbae2dbcb1751b92f5859
1 /*
2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
9 */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/tcp.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/firmware.h>
28 #include <linux/pci-aspm.h>
29 #include <linux/prefetch.h>
30 #include <linux/ipv6.h>
31 #include <net/ip6_checksum.h>
32
33 #include <asm/io.h>
34 #include <asm/irq.h>
35
36 #define RTL8169_VERSION "2.3LK-NAPI"
37 #define MODULENAME "r8169"
38 #define PFX MODULENAME ": "
39
40 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
42 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
44 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
45 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
47 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
48 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
49 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
50 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
51 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
52 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
53 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
54 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
55 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
56 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
57 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
58 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
59
60 #ifdef RTL8169_DEBUG
61 #define assert(expr) \
62 if (!(expr)) { \
63 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
64 #expr,__FILE__,__func__,__LINE__); \
65 }
66 #define dprintk(fmt, args...) \
67 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
68 #else
69 #define assert(expr) do {} while (0)
70 #define dprintk(fmt, args...) do {} while (0)
71 #endif /* RTL8169_DEBUG */
72
73 #define R8169_MSG_DEFAULT \
74 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
75
76 #define TX_SLOTS_AVAIL(tp) \
77 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
78
79 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
80 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
81 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
82
83 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
84 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
85 static const int multicast_filter_limit = 32;
86
87 #define MAX_READ_REQUEST_SHIFT 12
88 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
89 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
90
91 #define R8169_REGS_SIZE 256
92 #define R8169_NAPI_WEIGHT 64
93 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
94 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
95 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
96 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
97
98 #define RTL8169_TX_TIMEOUT (6*HZ)
99 #define RTL8169_PHY_TIMEOUT (10*HZ)
100
101 /* write/read MMIO register */
102 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
103 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
104 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
105 #define RTL_R8(reg) readb (ioaddr + (reg))
106 #define RTL_R16(reg) readw (ioaddr + (reg))
107 #define RTL_R32(reg) readl (ioaddr + (reg))
108
109 enum mac_version {
110 RTL_GIGA_MAC_VER_01 = 0,
111 RTL_GIGA_MAC_VER_02,
112 RTL_GIGA_MAC_VER_03,
113 RTL_GIGA_MAC_VER_04,
114 RTL_GIGA_MAC_VER_05,
115 RTL_GIGA_MAC_VER_06,
116 RTL_GIGA_MAC_VER_07,
117 RTL_GIGA_MAC_VER_08,
118 RTL_GIGA_MAC_VER_09,
119 RTL_GIGA_MAC_VER_10,
120 RTL_GIGA_MAC_VER_11,
121 RTL_GIGA_MAC_VER_12,
122 RTL_GIGA_MAC_VER_13,
123 RTL_GIGA_MAC_VER_14,
124 RTL_GIGA_MAC_VER_15,
125 RTL_GIGA_MAC_VER_16,
126 RTL_GIGA_MAC_VER_17,
127 RTL_GIGA_MAC_VER_18,
128 RTL_GIGA_MAC_VER_19,
129 RTL_GIGA_MAC_VER_20,
130 RTL_GIGA_MAC_VER_21,
131 RTL_GIGA_MAC_VER_22,
132 RTL_GIGA_MAC_VER_23,
133 RTL_GIGA_MAC_VER_24,
134 RTL_GIGA_MAC_VER_25,
135 RTL_GIGA_MAC_VER_26,
136 RTL_GIGA_MAC_VER_27,
137 RTL_GIGA_MAC_VER_28,
138 RTL_GIGA_MAC_VER_29,
139 RTL_GIGA_MAC_VER_30,
140 RTL_GIGA_MAC_VER_31,
141 RTL_GIGA_MAC_VER_32,
142 RTL_GIGA_MAC_VER_33,
143 RTL_GIGA_MAC_VER_34,
144 RTL_GIGA_MAC_VER_35,
145 RTL_GIGA_MAC_VER_36,
146 RTL_GIGA_MAC_VER_37,
147 RTL_GIGA_MAC_VER_38,
148 RTL_GIGA_MAC_VER_39,
149 RTL_GIGA_MAC_VER_40,
150 RTL_GIGA_MAC_VER_41,
151 RTL_GIGA_MAC_VER_42,
152 RTL_GIGA_MAC_VER_43,
153 RTL_GIGA_MAC_VER_44,
154 RTL_GIGA_MAC_VER_45,
155 RTL_GIGA_MAC_VER_46,
156 RTL_GIGA_MAC_VER_47,
157 RTL_GIGA_MAC_VER_48,
158 RTL_GIGA_MAC_VER_49,
159 RTL_GIGA_MAC_VER_50,
160 RTL_GIGA_MAC_VER_51,
161 RTL_GIGA_MAC_NONE = 0xff,
162 };
163
164 enum rtl_tx_desc_version {
165 RTL_TD_0 = 0,
166 RTL_TD_1 = 1,
167 };
168
169 #define JUMBO_1K ETH_DATA_LEN
170 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
171 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
172 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
173 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
174
175 #define _R(NAME,TD,FW,SZ,B) { \
176 .name = NAME, \
177 .txd_version = TD, \
178 .fw_name = FW, \
179 .jumbo_max = SZ, \
180 .jumbo_tx_csum = B \
181 }
182
183 static const struct {
184 const char *name;
185 enum rtl_tx_desc_version txd_version;
186 const char *fw_name;
187 u16 jumbo_max;
188 bool jumbo_tx_csum;
189 } rtl_chip_infos[] = {
190 /* PCI devices. */
191 [RTL_GIGA_MAC_VER_01] =
192 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
193 [RTL_GIGA_MAC_VER_02] =
194 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
195 [RTL_GIGA_MAC_VER_03] =
196 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
197 [RTL_GIGA_MAC_VER_04] =
198 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
199 [RTL_GIGA_MAC_VER_05] =
200 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
201 [RTL_GIGA_MAC_VER_06] =
202 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
203 /* PCI-E devices. */
204 [RTL_GIGA_MAC_VER_07] =
205 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
206 [RTL_GIGA_MAC_VER_08] =
207 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
208 [RTL_GIGA_MAC_VER_09] =
209 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
210 [RTL_GIGA_MAC_VER_10] =
211 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
212 [RTL_GIGA_MAC_VER_11] =
213 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
214 [RTL_GIGA_MAC_VER_12] =
215 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
216 [RTL_GIGA_MAC_VER_13] =
217 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
218 [RTL_GIGA_MAC_VER_14] =
219 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
220 [RTL_GIGA_MAC_VER_15] =
221 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
222 [RTL_GIGA_MAC_VER_16] =
223 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
224 [RTL_GIGA_MAC_VER_17] =
225 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
226 [RTL_GIGA_MAC_VER_18] =
227 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
228 [RTL_GIGA_MAC_VER_19] =
229 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
230 [RTL_GIGA_MAC_VER_20] =
231 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
232 [RTL_GIGA_MAC_VER_21] =
233 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
234 [RTL_GIGA_MAC_VER_22] =
235 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
236 [RTL_GIGA_MAC_VER_23] =
237 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
238 [RTL_GIGA_MAC_VER_24] =
239 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
240 [RTL_GIGA_MAC_VER_25] =
241 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
242 JUMBO_9K, false),
243 [RTL_GIGA_MAC_VER_26] =
244 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
245 JUMBO_9K, false),
246 [RTL_GIGA_MAC_VER_27] =
247 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
248 [RTL_GIGA_MAC_VER_28] =
249 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
250 [RTL_GIGA_MAC_VER_29] =
251 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
252 JUMBO_1K, true),
253 [RTL_GIGA_MAC_VER_30] =
254 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
255 JUMBO_1K, true),
256 [RTL_GIGA_MAC_VER_31] =
257 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
258 [RTL_GIGA_MAC_VER_32] =
259 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
260 JUMBO_9K, false),
261 [RTL_GIGA_MAC_VER_33] =
262 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
263 JUMBO_9K, false),
264 [RTL_GIGA_MAC_VER_34] =
265 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
266 JUMBO_9K, false),
267 [RTL_GIGA_MAC_VER_35] =
268 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
269 JUMBO_9K, false),
270 [RTL_GIGA_MAC_VER_36] =
271 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
272 JUMBO_9K, false),
273 [RTL_GIGA_MAC_VER_37] =
274 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
275 JUMBO_1K, true),
276 [RTL_GIGA_MAC_VER_38] =
277 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
278 JUMBO_9K, false),
279 [RTL_GIGA_MAC_VER_39] =
280 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
281 JUMBO_1K, true),
282 [RTL_GIGA_MAC_VER_40] =
283 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2,
284 JUMBO_9K, false),
285 [RTL_GIGA_MAC_VER_41] =
286 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
287 [RTL_GIGA_MAC_VER_42] =
288 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3,
289 JUMBO_9K, false),
290 [RTL_GIGA_MAC_VER_43] =
291 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2,
292 JUMBO_1K, true),
293 [RTL_GIGA_MAC_VER_44] =
294 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_2,
295 JUMBO_9K, false),
296 [RTL_GIGA_MAC_VER_45] =
297 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_1,
298 JUMBO_9K, false),
299 [RTL_GIGA_MAC_VER_46] =
300 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_2,
301 JUMBO_9K, false),
302 [RTL_GIGA_MAC_VER_47] =
303 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_1,
304 JUMBO_1K, false),
305 [RTL_GIGA_MAC_VER_48] =
306 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_2,
307 JUMBO_1K, false),
308 [RTL_GIGA_MAC_VER_49] =
309 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
310 JUMBO_9K, false),
311 [RTL_GIGA_MAC_VER_50] =
312 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
313 JUMBO_9K, false),
314 [RTL_GIGA_MAC_VER_51] =
315 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
316 JUMBO_9K, false),
317 };
318 #undef _R
319
320 enum cfg_version {
321 RTL_CFG_0 = 0x00,
322 RTL_CFG_1,
323 RTL_CFG_2
324 };
325
326 static const struct pci_device_id rtl8169_pci_tbl[] = {
327 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
328 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
329 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
330 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
331 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
332 { PCI_VENDOR_ID_DLINK, 0x4300,
333 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
334 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
335 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
336 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
337 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
338 { PCI_VENDOR_ID_LINKSYS, 0x1032,
339 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
340 { 0x0001, 0x8168,
341 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
342 {0,},
343 };
344
345 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
346
347 static int rx_buf_sz = 16383;
348 static int use_dac = -1;
349 static struct {
350 u32 msg_enable;
351 } debug = { -1 };
352
353 enum rtl_registers {
354 MAC0 = 0, /* Ethernet hardware address. */
355 MAC4 = 4,
356 MAR0 = 8, /* Multicast filter. */
357 CounterAddrLow = 0x10,
358 CounterAddrHigh = 0x14,
359 TxDescStartAddrLow = 0x20,
360 TxDescStartAddrHigh = 0x24,
361 TxHDescStartAddrLow = 0x28,
362 TxHDescStartAddrHigh = 0x2c,
363 FLASH = 0x30,
364 ERSR = 0x36,
365 ChipCmd = 0x37,
366 TxPoll = 0x38,
367 IntrMask = 0x3c,
368 IntrStatus = 0x3e,
369
370 TxConfig = 0x40,
371 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
372 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
373
374 RxConfig = 0x44,
375 #define RX128_INT_EN (1 << 15) /* 8111c and later */
376 #define RX_MULTI_EN (1 << 14) /* 8111c only */
377 #define RXCFG_FIFO_SHIFT 13
378 /* No threshold before first PCI xfer */
379 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
380 #define RX_EARLY_OFF (1 << 11)
381 #define RXCFG_DMA_SHIFT 8
382 /* Unlimited maximum PCI burst. */
383 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
384
385 RxMissed = 0x4c,
386 Cfg9346 = 0x50,
387 Config0 = 0x51,
388 Config1 = 0x52,
389 Config2 = 0x53,
390 #define PME_SIGNAL (1 << 5) /* 8168c and later */
391
392 Config3 = 0x54,
393 Config4 = 0x55,
394 Config5 = 0x56,
395 MultiIntr = 0x5c,
396 PHYAR = 0x60,
397 PHYstatus = 0x6c,
398 RxMaxSize = 0xda,
399 CPlusCmd = 0xe0,
400 IntrMitigate = 0xe2,
401 RxDescAddrLow = 0xe4,
402 RxDescAddrHigh = 0xe8,
403 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
404
405 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
406
407 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
408
409 #define TxPacketMax (8064 >> 7)
410 #define EarlySize 0x27
411
412 FuncEvent = 0xf0,
413 FuncEventMask = 0xf4,
414 FuncPresetState = 0xf8,
415 IBCR0 = 0xf8,
416 IBCR2 = 0xf9,
417 IBIMR0 = 0xfa,
418 IBISR0 = 0xfb,
419 FuncForceEvent = 0xfc,
420 };
421
422 enum rtl8110_registers {
423 TBICSR = 0x64,
424 TBI_ANAR = 0x68,
425 TBI_LPAR = 0x6a,
426 };
427
428 enum rtl8168_8101_registers {
429 CSIDR = 0x64,
430 CSIAR = 0x68,
431 #define CSIAR_FLAG 0x80000000
432 #define CSIAR_WRITE_CMD 0x80000000
433 #define CSIAR_BYTE_ENABLE 0x0f
434 #define CSIAR_BYTE_ENABLE_SHIFT 12
435 #define CSIAR_ADDR_MASK 0x0fff
436 #define CSIAR_FUNC_CARD 0x00000000
437 #define CSIAR_FUNC_SDIO 0x00010000
438 #define CSIAR_FUNC_NIC 0x00020000
439 #define CSIAR_FUNC_NIC2 0x00010000
440 PMCH = 0x6f,
441 EPHYAR = 0x80,
442 #define EPHYAR_FLAG 0x80000000
443 #define EPHYAR_WRITE_CMD 0x80000000
444 #define EPHYAR_REG_MASK 0x1f
445 #define EPHYAR_REG_SHIFT 16
446 #define EPHYAR_DATA_MASK 0xffff
447 DLLPR = 0xd0,
448 #define PFM_EN (1 << 6)
449 #define TX_10M_PS_EN (1 << 7)
450 DBG_REG = 0xd1,
451 #define FIX_NAK_1 (1 << 4)
452 #define FIX_NAK_2 (1 << 3)
453 TWSI = 0xd2,
454 MCU = 0xd3,
455 #define NOW_IS_OOB (1 << 7)
456 #define TX_EMPTY (1 << 5)
457 #define RX_EMPTY (1 << 4)
458 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
459 #define EN_NDP (1 << 3)
460 #define EN_OOB_RESET (1 << 2)
461 #define LINK_LIST_RDY (1 << 1)
462 EFUSEAR = 0xdc,
463 #define EFUSEAR_FLAG 0x80000000
464 #define EFUSEAR_WRITE_CMD 0x80000000
465 #define EFUSEAR_READ_CMD 0x00000000
466 #define EFUSEAR_REG_MASK 0x03ff
467 #define EFUSEAR_REG_SHIFT 8
468 #define EFUSEAR_DATA_MASK 0xff
469 MISC_1 = 0xf2,
470 #define PFM_D3COLD_EN (1 << 6)
471 };
472
473 enum rtl8168_registers {
474 LED_FREQ = 0x1a,
475 EEE_LED = 0x1b,
476 ERIDR = 0x70,
477 ERIAR = 0x74,
478 #define ERIAR_FLAG 0x80000000
479 #define ERIAR_WRITE_CMD 0x80000000
480 #define ERIAR_READ_CMD 0x00000000
481 #define ERIAR_ADDR_BYTE_ALIGN 4
482 #define ERIAR_TYPE_SHIFT 16
483 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
484 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
485 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
486 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
487 #define ERIAR_MASK_SHIFT 12
488 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
489 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
490 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
491 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
492 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
493 EPHY_RXER_NUM = 0x7c,
494 OCPDR = 0xb0, /* OCP GPHY access */
495 #define OCPDR_WRITE_CMD 0x80000000
496 #define OCPDR_READ_CMD 0x00000000
497 #define OCPDR_REG_MASK 0x7f
498 #define OCPDR_GPHY_REG_SHIFT 16
499 #define OCPDR_DATA_MASK 0xffff
500 OCPAR = 0xb4,
501 #define OCPAR_FLAG 0x80000000
502 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
503 #define OCPAR_GPHY_READ_CMD 0x0000f060
504 GPHY_OCP = 0xb8,
505 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
506 MISC = 0xf0, /* 8168e only. */
507 #define TXPLA_RST (1 << 29)
508 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
509 #define PWM_EN (1 << 22)
510 #define RXDV_GATED_EN (1 << 19)
511 #define EARLY_TALLY_EN (1 << 16)
512 };
513
514 enum rtl_register_content {
515 /* InterruptStatusBits */
516 SYSErr = 0x8000,
517 PCSTimeout = 0x4000,
518 SWInt = 0x0100,
519 TxDescUnavail = 0x0080,
520 RxFIFOOver = 0x0040,
521 LinkChg = 0x0020,
522 RxOverflow = 0x0010,
523 TxErr = 0x0008,
524 TxOK = 0x0004,
525 RxErr = 0x0002,
526 RxOK = 0x0001,
527
528 /* RxStatusDesc */
529 RxBOVF = (1 << 24),
530 RxFOVF = (1 << 23),
531 RxRWT = (1 << 22),
532 RxRES = (1 << 21),
533 RxRUNT = (1 << 20),
534 RxCRC = (1 << 19),
535
536 /* ChipCmdBits */
537 StopReq = 0x80,
538 CmdReset = 0x10,
539 CmdRxEnb = 0x08,
540 CmdTxEnb = 0x04,
541 RxBufEmpty = 0x01,
542
543 /* TXPoll register p.5 */
544 HPQ = 0x80, /* Poll cmd on the high prio queue */
545 NPQ = 0x40, /* Poll cmd on the low prio queue */
546 FSWInt = 0x01, /* Forced software interrupt */
547
548 /* Cfg9346Bits */
549 Cfg9346_Lock = 0x00,
550 Cfg9346_Unlock = 0xc0,
551
552 /* rx_mode_bits */
553 AcceptErr = 0x20,
554 AcceptRunt = 0x10,
555 AcceptBroadcast = 0x08,
556 AcceptMulticast = 0x04,
557 AcceptMyPhys = 0x02,
558 AcceptAllPhys = 0x01,
559 #define RX_CONFIG_ACCEPT_MASK 0x3f
560
561 /* TxConfigBits */
562 TxInterFrameGapShift = 24,
563 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
564
565 /* Config1 register p.24 */
566 LEDS1 = (1 << 7),
567 LEDS0 = (1 << 6),
568 Speed_down = (1 << 4),
569 MEMMAP = (1 << 3),
570 IOMAP = (1 << 2),
571 VPD = (1 << 1),
572 PMEnable = (1 << 0), /* Power Management Enable */
573
574 /* Config2 register p. 25 */
575 ClkReqEn = (1 << 7), /* Clock Request Enable */
576 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
577 PCI_Clock_66MHz = 0x01,
578 PCI_Clock_33MHz = 0x00,
579
580 /* Config3 register p.25 */
581 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
582 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
583 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
584 Rdy_to_L23 = (1 << 1), /* L23 Enable */
585 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
586
587 /* Config4 register */
588 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
589
590 /* Config5 register p.27 */
591 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
592 MWF = (1 << 5), /* Accept Multicast wakeup frame */
593 UWF = (1 << 4), /* Accept Unicast wakeup frame */
594 Spi_en = (1 << 3),
595 LanWake = (1 << 1), /* LanWake enable/disable */
596 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
597 ASPM_en = (1 << 0), /* ASPM enable */
598
599 /* TBICSR p.28 */
600 TBIReset = 0x80000000,
601 TBILoopback = 0x40000000,
602 TBINwEnable = 0x20000000,
603 TBINwRestart = 0x10000000,
604 TBILinkOk = 0x02000000,
605 TBINwComplete = 0x01000000,
606
607 /* CPlusCmd p.31 */
608 EnableBist = (1 << 15), // 8168 8101
609 Mac_dbgo_oe = (1 << 14), // 8168 8101
610 Normal_mode = (1 << 13), // unused
611 Force_half_dup = (1 << 12), // 8168 8101
612 Force_rxflow_en = (1 << 11), // 8168 8101
613 Force_txflow_en = (1 << 10), // 8168 8101
614 Cxpl_dbg_sel = (1 << 9), // 8168 8101
615 ASF = (1 << 8), // 8168 8101
616 PktCntrDisable = (1 << 7), // 8168 8101
617 Mac_dbgo_sel = 0x001c, // 8168
618 RxVlan = (1 << 6),
619 RxChkSum = (1 << 5),
620 PCIDAC = (1 << 4),
621 PCIMulRW = (1 << 3),
622 INTT_0 = 0x0000, // 8168
623 INTT_1 = 0x0001, // 8168
624 INTT_2 = 0x0002, // 8168
625 INTT_3 = 0x0003, // 8168
626
627 /* rtl8169_PHYstatus */
628 TBI_Enable = 0x80,
629 TxFlowCtrl = 0x40,
630 RxFlowCtrl = 0x20,
631 _1000bpsF = 0x10,
632 _100bps = 0x08,
633 _10bps = 0x04,
634 LinkStatus = 0x02,
635 FullDup = 0x01,
636
637 /* _TBICSRBit */
638 TBILinkOK = 0x02000000,
639
640 /* ResetCounterCommand */
641 CounterReset = 0x1,
642
643 /* DumpCounterCommand */
644 CounterDump = 0x8,
645
646 /* magic enable v2 */
647 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
648 };
649
650 enum rtl_desc_bit {
651 /* First doubleword. */
652 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
653 RingEnd = (1 << 30), /* End of descriptor ring */
654 FirstFrag = (1 << 29), /* First segment of a packet */
655 LastFrag = (1 << 28), /* Final segment of a packet */
656 };
657
658 /* Generic case. */
659 enum rtl_tx_desc_bit {
660 /* First doubleword. */
661 TD_LSO = (1 << 27), /* Large Send Offload */
662 #define TD_MSS_MAX 0x07ffu /* MSS value */
663
664 /* Second doubleword. */
665 TxVlanTag = (1 << 17), /* Add VLAN tag */
666 };
667
668 /* 8169, 8168b and 810x except 8102e. */
669 enum rtl_tx_desc_bit_0 {
670 /* First doubleword. */
671 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
672 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
673 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
674 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
675 };
676
677 /* 8102e, 8168c and beyond. */
678 enum rtl_tx_desc_bit_1 {
679 /* First doubleword. */
680 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
681 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
682 #define GTTCPHO_SHIFT 18
683 #define GTTCPHO_MAX 0x7fU
684
685 /* Second doubleword. */
686 #define TCPHO_SHIFT 18
687 #define TCPHO_MAX 0x3ffU
688 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
689 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
690 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
691 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
692 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
693 };
694
695 enum rtl_rx_desc_bit {
696 /* Rx private */
697 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
698 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
699
700 #define RxProtoUDP (PID1)
701 #define RxProtoTCP (PID0)
702 #define RxProtoIP (PID1 | PID0)
703 #define RxProtoMask RxProtoIP
704
705 IPFail = (1 << 16), /* IP checksum failed */
706 UDPFail = (1 << 15), /* UDP/IP checksum failed */
707 TCPFail = (1 << 14), /* TCP/IP checksum failed */
708 RxVlanTag = (1 << 16), /* VLAN tag available */
709 };
710
711 #define RsvdMask 0x3fffc000
712
713 struct TxDesc {
714 __le32 opts1;
715 __le32 opts2;
716 __le64 addr;
717 };
718
719 struct RxDesc {
720 __le32 opts1;
721 __le32 opts2;
722 __le64 addr;
723 };
724
725 struct ring_info {
726 struct sk_buff *skb;
727 u32 len;
728 u8 __pad[sizeof(void *) - sizeof(u32)];
729 };
730
731 enum features {
732 RTL_FEATURE_WOL = (1 << 0),
733 RTL_FEATURE_MSI = (1 << 1),
734 RTL_FEATURE_GMII = (1 << 2),
735 };
736
737 struct rtl8169_counters {
738 __le64 tx_packets;
739 __le64 rx_packets;
740 __le64 tx_errors;
741 __le32 rx_errors;
742 __le16 rx_missed;
743 __le16 align_errors;
744 __le32 tx_one_collision;
745 __le32 tx_multi_collision;
746 __le64 rx_unicast;
747 __le64 rx_broadcast;
748 __le32 rx_multicast;
749 __le16 tx_aborted;
750 __le16 tx_underun;
751 };
752
753 struct rtl8169_tc_offsets {
754 bool inited;
755 __le64 tx_errors;
756 __le32 tx_multi_collision;
757 __le16 tx_aborted;
758 };
759
760 enum rtl_flag {
761 RTL_FLAG_TASK_ENABLED,
762 RTL_FLAG_TASK_SLOW_PENDING,
763 RTL_FLAG_TASK_RESET_PENDING,
764 RTL_FLAG_TASK_PHY_PENDING,
765 RTL_FLAG_MAX
766 };
767
768 struct rtl8169_stats {
769 u64 packets;
770 u64 bytes;
771 struct u64_stats_sync syncp;
772 };
773
774 struct rtl8169_private {
775 void __iomem *mmio_addr; /* memory map physical address */
776 struct pci_dev *pci_dev;
777 struct net_device *dev;
778 struct napi_struct napi;
779 u32 msg_enable;
780 u16 txd_version;
781 u16 mac_version;
782 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
783 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
784 u32 dirty_tx;
785 struct rtl8169_stats rx_stats;
786 struct rtl8169_stats tx_stats;
787 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
788 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
789 dma_addr_t TxPhyAddr;
790 dma_addr_t RxPhyAddr;
791 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
792 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
793 struct timer_list timer;
794 u16 cp_cmd;
795
796 u16 event_slow;
797
798 struct mdio_ops {
799 void (*write)(struct rtl8169_private *, int, int);
800 int (*read)(struct rtl8169_private *, int);
801 } mdio_ops;
802
803 struct pll_power_ops {
804 void (*down)(struct rtl8169_private *);
805 void (*up)(struct rtl8169_private *);
806 } pll_power_ops;
807
808 struct jumbo_ops {
809 void (*enable)(struct rtl8169_private *);
810 void (*disable)(struct rtl8169_private *);
811 } jumbo_ops;
812
813 struct csi_ops {
814 void (*write)(struct rtl8169_private *, int, int);
815 u32 (*read)(struct rtl8169_private *, int);
816 } csi_ops;
817
818 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
819 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
820 void (*phy_reset_enable)(struct rtl8169_private *tp);
821 void (*hw_start)(struct net_device *);
822 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
823 unsigned int (*link_ok)(void __iomem *);
824 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
825 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
826
827 struct {
828 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
829 struct mutex mutex;
830 struct work_struct work;
831 } wk;
832
833 unsigned features;
834
835 struct mii_if_info mii;
836 dma_addr_t counters_phys_addr;
837 struct rtl8169_counters *counters;
838 struct rtl8169_tc_offsets tc_offset;
839 u32 saved_wolopts;
840 u32 opts1_mask;
841
842 struct rtl_fw {
843 const struct firmware *fw;
844
845 #define RTL_VER_SIZE 32
846
847 char version[RTL_VER_SIZE];
848
849 struct rtl_fw_phy_action {
850 __le32 *code;
851 size_t size;
852 } phy_action;
853 } *rtl_fw;
854 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
855
856 u32 ocp_base;
857 };
858
859 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
860 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
861 module_param(use_dac, int, 0);
862 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
863 module_param_named(debug, debug.msg_enable, int, 0);
864 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
865 MODULE_LICENSE("GPL");
866 MODULE_VERSION(RTL8169_VERSION);
867 MODULE_FIRMWARE(FIRMWARE_8168D_1);
868 MODULE_FIRMWARE(FIRMWARE_8168D_2);
869 MODULE_FIRMWARE(FIRMWARE_8168E_1);
870 MODULE_FIRMWARE(FIRMWARE_8168E_2);
871 MODULE_FIRMWARE(FIRMWARE_8168E_3);
872 MODULE_FIRMWARE(FIRMWARE_8105E_1);
873 MODULE_FIRMWARE(FIRMWARE_8168F_1);
874 MODULE_FIRMWARE(FIRMWARE_8168F_2);
875 MODULE_FIRMWARE(FIRMWARE_8402_1);
876 MODULE_FIRMWARE(FIRMWARE_8411_1);
877 MODULE_FIRMWARE(FIRMWARE_8411_2);
878 MODULE_FIRMWARE(FIRMWARE_8106E_1);
879 MODULE_FIRMWARE(FIRMWARE_8106E_2);
880 MODULE_FIRMWARE(FIRMWARE_8168G_2);
881 MODULE_FIRMWARE(FIRMWARE_8168G_3);
882 MODULE_FIRMWARE(FIRMWARE_8168H_1);
883 MODULE_FIRMWARE(FIRMWARE_8168H_2);
884 MODULE_FIRMWARE(FIRMWARE_8107E_1);
885 MODULE_FIRMWARE(FIRMWARE_8107E_2);
886
887 static void rtl_lock_work(struct rtl8169_private *tp)
888 {
889 mutex_lock(&tp->wk.mutex);
890 }
891
892 static void rtl_unlock_work(struct rtl8169_private *tp)
893 {
894 mutex_unlock(&tp->wk.mutex);
895 }
896
897 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
898 {
899 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
900 PCI_EXP_DEVCTL_READRQ, force);
901 }
902
903 struct rtl_cond {
904 bool (*check)(struct rtl8169_private *);
905 const char *msg;
906 };
907
908 static void rtl_udelay(unsigned int d)
909 {
910 udelay(d);
911 }
912
913 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
914 void (*delay)(unsigned int), unsigned int d, int n,
915 bool high)
916 {
917 int i;
918
919 for (i = 0; i < n; i++) {
920 delay(d);
921 if (c->check(tp) == high)
922 return true;
923 }
924 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
925 c->msg, !high, n, d);
926 return false;
927 }
928
929 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
930 const struct rtl_cond *c,
931 unsigned int d, int n)
932 {
933 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
934 }
935
936 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
937 const struct rtl_cond *c,
938 unsigned int d, int n)
939 {
940 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
941 }
942
943 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
944 const struct rtl_cond *c,
945 unsigned int d, int n)
946 {
947 return rtl_loop_wait(tp, c, msleep, d, n, true);
948 }
949
950 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
951 const struct rtl_cond *c,
952 unsigned int d, int n)
953 {
954 return rtl_loop_wait(tp, c, msleep, d, n, false);
955 }
956
957 #define DECLARE_RTL_COND(name) \
958 static bool name ## _check(struct rtl8169_private *); \
959 \
960 static const struct rtl_cond name = { \
961 .check = name ## _check, \
962 .msg = #name \
963 }; \
964 \
965 static bool name ## _check(struct rtl8169_private *tp)
966
967 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
968 {
969 if (reg & 0xffff0001) {
970 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
971 return true;
972 }
973 return false;
974 }
975
976 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
977 {
978 void __iomem *ioaddr = tp->mmio_addr;
979
980 return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
981 }
982
983 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
984 {
985 void __iomem *ioaddr = tp->mmio_addr;
986
987 if (rtl_ocp_reg_failure(tp, reg))
988 return;
989
990 RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
991
992 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
993 }
994
995 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
996 {
997 void __iomem *ioaddr = tp->mmio_addr;
998
999 if (rtl_ocp_reg_failure(tp, reg))
1000 return 0;
1001
1002 RTL_W32(GPHY_OCP, reg << 15);
1003
1004 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1005 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1006 }
1007
1008 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1009 {
1010 void __iomem *ioaddr = tp->mmio_addr;
1011
1012 if (rtl_ocp_reg_failure(tp, reg))
1013 return;
1014
1015 RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
1016 }
1017
1018 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1019 {
1020 void __iomem *ioaddr = tp->mmio_addr;
1021
1022 if (rtl_ocp_reg_failure(tp, reg))
1023 return 0;
1024
1025 RTL_W32(OCPDR, reg << 15);
1026
1027 return RTL_R32(OCPDR);
1028 }
1029
1030 #define OCP_STD_PHY_BASE 0xa400
1031
1032 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1033 {
1034 if (reg == 0x1f) {
1035 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1036 return;
1037 }
1038
1039 if (tp->ocp_base != OCP_STD_PHY_BASE)
1040 reg -= 0x10;
1041
1042 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1043 }
1044
1045 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1046 {
1047 if (tp->ocp_base != OCP_STD_PHY_BASE)
1048 reg -= 0x10;
1049
1050 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1051 }
1052
1053 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1054 {
1055 if (reg == 0x1f) {
1056 tp->ocp_base = value << 4;
1057 return;
1058 }
1059
1060 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1061 }
1062
1063 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1064 {
1065 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1066 }
1067
1068 DECLARE_RTL_COND(rtl_phyar_cond)
1069 {
1070 void __iomem *ioaddr = tp->mmio_addr;
1071
1072 return RTL_R32(PHYAR) & 0x80000000;
1073 }
1074
1075 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1076 {
1077 void __iomem *ioaddr = tp->mmio_addr;
1078
1079 RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1080
1081 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1082 /*
1083 * According to hardware specs a 20us delay is required after write
1084 * complete indication, but before sending next command.
1085 */
1086 udelay(20);
1087 }
1088
1089 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1090 {
1091 void __iomem *ioaddr = tp->mmio_addr;
1092 int value;
1093
1094 RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1095
1096 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1097 RTL_R32(PHYAR) & 0xffff : ~0;
1098
1099 /*
1100 * According to hardware specs a 20us delay is required after read
1101 * complete indication, but before sending next command.
1102 */
1103 udelay(20);
1104
1105 return value;
1106 }
1107
1108 DECLARE_RTL_COND(rtl_ocpar_cond)
1109 {
1110 void __iomem *ioaddr = tp->mmio_addr;
1111
1112 return RTL_R32(OCPAR) & OCPAR_FLAG;
1113 }
1114
1115 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1116 {
1117 void __iomem *ioaddr = tp->mmio_addr;
1118
1119 RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1120 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1121 RTL_W32(EPHY_RXER_NUM, 0);
1122
1123 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1124 }
1125
1126 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1127 {
1128 r8168dp_1_mdio_access(tp, reg,
1129 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1130 }
1131
1132 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1133 {
1134 void __iomem *ioaddr = tp->mmio_addr;
1135
1136 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1137
1138 mdelay(1);
1139 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1140 RTL_W32(EPHY_RXER_NUM, 0);
1141
1142 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1143 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
1144 }
1145
1146 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1147
1148 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1149 {
1150 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1151 }
1152
1153 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1154 {
1155 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1156 }
1157
1158 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1159 {
1160 void __iomem *ioaddr = tp->mmio_addr;
1161
1162 r8168dp_2_mdio_start(ioaddr);
1163
1164 r8169_mdio_write(tp, reg, value);
1165
1166 r8168dp_2_mdio_stop(ioaddr);
1167 }
1168
1169 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1170 {
1171 void __iomem *ioaddr = tp->mmio_addr;
1172 int value;
1173
1174 r8168dp_2_mdio_start(ioaddr);
1175
1176 value = r8169_mdio_read(tp, reg);
1177
1178 r8168dp_2_mdio_stop(ioaddr);
1179
1180 return value;
1181 }
1182
1183 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1184 {
1185 tp->mdio_ops.write(tp, location, val);
1186 }
1187
1188 static int rtl_readphy(struct rtl8169_private *tp, int location)
1189 {
1190 return tp->mdio_ops.read(tp, location);
1191 }
1192
1193 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1194 {
1195 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1196 }
1197
1198 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1199 {
1200 int val;
1201
1202 val = rtl_readphy(tp, reg_addr);
1203 rtl_writephy(tp, reg_addr, (val & ~m) | p);
1204 }
1205
1206 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1207 int val)
1208 {
1209 struct rtl8169_private *tp = netdev_priv(dev);
1210
1211 rtl_writephy(tp, location, val);
1212 }
1213
1214 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1215 {
1216 struct rtl8169_private *tp = netdev_priv(dev);
1217
1218 return rtl_readphy(tp, location);
1219 }
1220
1221 DECLARE_RTL_COND(rtl_ephyar_cond)
1222 {
1223 void __iomem *ioaddr = tp->mmio_addr;
1224
1225 return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1226 }
1227
1228 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1229 {
1230 void __iomem *ioaddr = tp->mmio_addr;
1231
1232 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1233 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1234
1235 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1236
1237 udelay(10);
1238 }
1239
1240 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1241 {
1242 void __iomem *ioaddr = tp->mmio_addr;
1243
1244 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1245
1246 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1247 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
1248 }
1249
1250 DECLARE_RTL_COND(rtl_eriar_cond)
1251 {
1252 void __iomem *ioaddr = tp->mmio_addr;
1253
1254 return RTL_R32(ERIAR) & ERIAR_FLAG;
1255 }
1256
1257 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1258 u32 val, int type)
1259 {
1260 void __iomem *ioaddr = tp->mmio_addr;
1261
1262 BUG_ON((addr & 3) || (mask == 0));
1263 RTL_W32(ERIDR, val);
1264 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1265
1266 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1267 }
1268
1269 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1270 {
1271 void __iomem *ioaddr = tp->mmio_addr;
1272
1273 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1274
1275 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1276 RTL_R32(ERIDR) : ~0;
1277 }
1278
1279 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1280 u32 m, int type)
1281 {
1282 u32 val;
1283
1284 val = rtl_eri_read(tp, addr, type);
1285 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1286 }
1287
1288 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1289 {
1290 void __iomem *ioaddr = tp->mmio_addr;
1291
1292 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1293 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1294 RTL_R32(OCPDR) : ~0;
1295 }
1296
1297 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1298 {
1299 return rtl_eri_read(tp, reg, ERIAR_OOB);
1300 }
1301
1302 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1303 {
1304 switch (tp->mac_version) {
1305 case RTL_GIGA_MAC_VER_27:
1306 case RTL_GIGA_MAC_VER_28:
1307 case RTL_GIGA_MAC_VER_31:
1308 return r8168dp_ocp_read(tp, mask, reg);
1309 case RTL_GIGA_MAC_VER_49:
1310 case RTL_GIGA_MAC_VER_50:
1311 case RTL_GIGA_MAC_VER_51:
1312 return r8168ep_ocp_read(tp, mask, reg);
1313 default:
1314 BUG();
1315 return ~0;
1316 }
1317 }
1318
1319 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1320 u32 data)
1321 {
1322 void __iomem *ioaddr = tp->mmio_addr;
1323
1324 RTL_W32(OCPDR, data);
1325 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1326 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1327 }
1328
1329 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1330 u32 data)
1331 {
1332 rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1333 data, ERIAR_OOB);
1334 }
1335
1336 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1337 {
1338 switch (tp->mac_version) {
1339 case RTL_GIGA_MAC_VER_27:
1340 case RTL_GIGA_MAC_VER_28:
1341 case RTL_GIGA_MAC_VER_31:
1342 r8168dp_ocp_write(tp, mask, reg, data);
1343 break;
1344 case RTL_GIGA_MAC_VER_49:
1345 case RTL_GIGA_MAC_VER_50:
1346 case RTL_GIGA_MAC_VER_51:
1347 r8168ep_ocp_write(tp, mask, reg, data);
1348 break;
1349 default:
1350 BUG();
1351 break;
1352 }
1353 }
1354
1355 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1356 {
1357 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1358
1359 ocp_write(tp, 0x1, 0x30, 0x00000001);
1360 }
1361
1362 #define OOB_CMD_RESET 0x00
1363 #define OOB_CMD_DRIVER_START 0x05
1364 #define OOB_CMD_DRIVER_STOP 0x06
1365
1366 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1367 {
1368 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1369 }
1370
1371 DECLARE_RTL_COND(rtl_ocp_read_cond)
1372 {
1373 u16 reg;
1374
1375 reg = rtl8168_get_ocp_reg(tp);
1376
1377 return ocp_read(tp, 0x0f, reg) & 0x00000800;
1378 }
1379
1380 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1381 {
1382 return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1383 }
1384
1385 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1386 {
1387 void __iomem *ioaddr = tp->mmio_addr;
1388
1389 return RTL_R8(IBISR0) & 0x02;
1390 }
1391
1392 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1393 {
1394 void __iomem *ioaddr = tp->mmio_addr;
1395
1396 RTL_W8(IBCR2, RTL_R8(IBCR2) & ~0x01);
1397 rtl_msleep_loop_wait_low(tp, &rtl_ocp_tx_cond, 50, 2000);
1398 RTL_W8(IBISR0, RTL_R8(IBISR0) | 0x20);
1399 RTL_W8(IBCR0, RTL_R8(IBCR0) & ~0x01);
1400 }
1401
1402 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1403 {
1404 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1405 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1406 }
1407
1408 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1409 {
1410 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1411 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1412 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1413 }
1414
1415 static void rtl8168_driver_start(struct rtl8169_private *tp)
1416 {
1417 switch (tp->mac_version) {
1418 case RTL_GIGA_MAC_VER_27:
1419 case RTL_GIGA_MAC_VER_28:
1420 case RTL_GIGA_MAC_VER_31:
1421 rtl8168dp_driver_start(tp);
1422 break;
1423 case RTL_GIGA_MAC_VER_49:
1424 case RTL_GIGA_MAC_VER_50:
1425 case RTL_GIGA_MAC_VER_51:
1426 rtl8168ep_driver_start(tp);
1427 break;
1428 default:
1429 BUG();
1430 break;
1431 }
1432 }
1433
1434 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1435 {
1436 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1437 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1438 }
1439
1440 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1441 {
1442 rtl8168ep_stop_cmac(tp);
1443 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1444 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1445 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1446 }
1447
1448 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1449 {
1450 switch (tp->mac_version) {
1451 case RTL_GIGA_MAC_VER_27:
1452 case RTL_GIGA_MAC_VER_28:
1453 case RTL_GIGA_MAC_VER_31:
1454 rtl8168dp_driver_stop(tp);
1455 break;
1456 case RTL_GIGA_MAC_VER_49:
1457 case RTL_GIGA_MAC_VER_50:
1458 case RTL_GIGA_MAC_VER_51:
1459 rtl8168ep_driver_stop(tp);
1460 break;
1461 default:
1462 BUG();
1463 break;
1464 }
1465 }
1466
1467 static int r8168dp_check_dash(struct rtl8169_private *tp)
1468 {
1469 u16 reg = rtl8168_get_ocp_reg(tp);
1470
1471 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
1472 }
1473
1474 static int r8168ep_check_dash(struct rtl8169_private *tp)
1475 {
1476 return (ocp_read(tp, 0x0f, 0x128) & 0x00000001) ? 1 : 0;
1477 }
1478
1479 static int r8168_check_dash(struct rtl8169_private *tp)
1480 {
1481 switch (tp->mac_version) {
1482 case RTL_GIGA_MAC_VER_27:
1483 case RTL_GIGA_MAC_VER_28:
1484 case RTL_GIGA_MAC_VER_31:
1485 return r8168dp_check_dash(tp);
1486 case RTL_GIGA_MAC_VER_49:
1487 case RTL_GIGA_MAC_VER_50:
1488 case RTL_GIGA_MAC_VER_51:
1489 return r8168ep_check_dash(tp);
1490 default:
1491 return 0;
1492 }
1493 }
1494
1495 struct exgmac_reg {
1496 u16 addr;
1497 u16 mask;
1498 u32 val;
1499 };
1500
1501 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1502 const struct exgmac_reg *r, int len)
1503 {
1504 while (len-- > 0) {
1505 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1506 r++;
1507 }
1508 }
1509
1510 DECLARE_RTL_COND(rtl_efusear_cond)
1511 {
1512 void __iomem *ioaddr = tp->mmio_addr;
1513
1514 return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1515 }
1516
1517 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1518 {
1519 void __iomem *ioaddr = tp->mmio_addr;
1520
1521 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1522
1523 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1524 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1525 }
1526
1527 static u16 rtl_get_events(struct rtl8169_private *tp)
1528 {
1529 void __iomem *ioaddr = tp->mmio_addr;
1530
1531 return RTL_R16(IntrStatus);
1532 }
1533
1534 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1535 {
1536 void __iomem *ioaddr = tp->mmio_addr;
1537
1538 RTL_W16(IntrStatus, bits);
1539 mmiowb();
1540 }
1541
1542 static void rtl_irq_disable(struct rtl8169_private *tp)
1543 {
1544 void __iomem *ioaddr = tp->mmio_addr;
1545
1546 RTL_W16(IntrMask, 0);
1547 mmiowb();
1548 }
1549
1550 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1551 {
1552 void __iomem *ioaddr = tp->mmio_addr;
1553
1554 RTL_W16(IntrMask, bits);
1555 }
1556
1557 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1558 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1559 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1560
1561 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1562 {
1563 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1564 }
1565
1566 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1567 {
1568 void __iomem *ioaddr = tp->mmio_addr;
1569
1570 rtl_irq_disable(tp);
1571 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1572 RTL_R8(ChipCmd);
1573 }
1574
1575 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1576 {
1577 void __iomem *ioaddr = tp->mmio_addr;
1578
1579 return RTL_R32(TBICSR) & TBIReset;
1580 }
1581
1582 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1583 {
1584 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1585 }
1586
1587 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1588 {
1589 return RTL_R32(TBICSR) & TBILinkOk;
1590 }
1591
1592 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1593 {
1594 return RTL_R8(PHYstatus) & LinkStatus;
1595 }
1596
1597 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1598 {
1599 void __iomem *ioaddr = tp->mmio_addr;
1600
1601 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1602 }
1603
1604 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1605 {
1606 unsigned int val;
1607
1608 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1609 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1610 }
1611
1612 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1613 {
1614 void __iomem *ioaddr = tp->mmio_addr;
1615 struct net_device *dev = tp->dev;
1616
1617 if (!netif_running(dev))
1618 return;
1619
1620 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1621 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1622 if (RTL_R8(PHYstatus) & _1000bpsF) {
1623 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1624 ERIAR_EXGMAC);
1625 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1626 ERIAR_EXGMAC);
1627 } else if (RTL_R8(PHYstatus) & _100bps) {
1628 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1629 ERIAR_EXGMAC);
1630 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1631 ERIAR_EXGMAC);
1632 } else {
1633 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1634 ERIAR_EXGMAC);
1635 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1636 ERIAR_EXGMAC);
1637 }
1638 /* Reset packet filter */
1639 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1640 ERIAR_EXGMAC);
1641 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1642 ERIAR_EXGMAC);
1643 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1644 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1645 if (RTL_R8(PHYstatus) & _1000bpsF) {
1646 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1647 ERIAR_EXGMAC);
1648 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1649 ERIAR_EXGMAC);
1650 } else {
1651 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1652 ERIAR_EXGMAC);
1653 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1654 ERIAR_EXGMAC);
1655 }
1656 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1657 if (RTL_R8(PHYstatus) & _10bps) {
1658 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1659 ERIAR_EXGMAC);
1660 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1661 ERIAR_EXGMAC);
1662 } else {
1663 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1664 ERIAR_EXGMAC);
1665 }
1666 }
1667 }
1668
1669 static void __rtl8169_check_link_status(struct net_device *dev,
1670 struct rtl8169_private *tp,
1671 void __iomem *ioaddr, bool pm)
1672 {
1673 if (tp->link_ok(ioaddr)) {
1674 rtl_link_chg_patch(tp);
1675 /* This is to cancel a scheduled suspend if there's one. */
1676 if (pm)
1677 pm_request_resume(&tp->pci_dev->dev);
1678 netif_carrier_on(dev);
1679 if (net_ratelimit())
1680 netif_info(tp, ifup, dev, "link up\n");
1681 } else {
1682 netif_carrier_off(dev);
1683 netif_info(tp, ifdown, dev, "link down\n");
1684 if (pm)
1685 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1686 }
1687 }
1688
1689 static void rtl8169_check_link_status(struct net_device *dev,
1690 struct rtl8169_private *tp,
1691 void __iomem *ioaddr)
1692 {
1693 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1694 }
1695
1696 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1697
1698 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1699 {
1700 void __iomem *ioaddr = tp->mmio_addr;
1701 u8 options;
1702 u32 wolopts = 0;
1703
1704 options = RTL_R8(Config1);
1705 if (!(options & PMEnable))
1706 return 0;
1707
1708 options = RTL_R8(Config3);
1709 if (options & LinkUp)
1710 wolopts |= WAKE_PHY;
1711 switch (tp->mac_version) {
1712 case RTL_GIGA_MAC_VER_34:
1713 case RTL_GIGA_MAC_VER_35:
1714 case RTL_GIGA_MAC_VER_36:
1715 case RTL_GIGA_MAC_VER_37:
1716 case RTL_GIGA_MAC_VER_38:
1717 case RTL_GIGA_MAC_VER_40:
1718 case RTL_GIGA_MAC_VER_41:
1719 case RTL_GIGA_MAC_VER_42:
1720 case RTL_GIGA_MAC_VER_43:
1721 case RTL_GIGA_MAC_VER_44:
1722 case RTL_GIGA_MAC_VER_45:
1723 case RTL_GIGA_MAC_VER_46:
1724 case RTL_GIGA_MAC_VER_47:
1725 case RTL_GIGA_MAC_VER_48:
1726 case RTL_GIGA_MAC_VER_49:
1727 case RTL_GIGA_MAC_VER_50:
1728 case RTL_GIGA_MAC_VER_51:
1729 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1730 wolopts |= WAKE_MAGIC;
1731 break;
1732 default:
1733 if (options & MagicPacket)
1734 wolopts |= WAKE_MAGIC;
1735 break;
1736 }
1737
1738 options = RTL_R8(Config5);
1739 if (options & UWF)
1740 wolopts |= WAKE_UCAST;
1741 if (options & BWF)
1742 wolopts |= WAKE_BCAST;
1743 if (options & MWF)
1744 wolopts |= WAKE_MCAST;
1745
1746 return wolopts;
1747 }
1748
1749 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1750 {
1751 struct rtl8169_private *tp = netdev_priv(dev);
1752 struct device *d = &tp->pci_dev->dev;
1753
1754 pm_runtime_get_noresume(d);
1755
1756 rtl_lock_work(tp);
1757
1758 wol->supported = WAKE_ANY;
1759 if (pm_runtime_active(d))
1760 wol->wolopts = __rtl8169_get_wol(tp);
1761 else
1762 wol->wolopts = tp->saved_wolopts;
1763
1764 rtl_unlock_work(tp);
1765
1766 pm_runtime_put_noidle(d);
1767 }
1768
1769 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1770 {
1771 void __iomem *ioaddr = tp->mmio_addr;
1772 unsigned int i, tmp;
1773 static const struct {
1774 u32 opt;
1775 u16 reg;
1776 u8 mask;
1777 } cfg[] = {
1778 { WAKE_PHY, Config3, LinkUp },
1779 { WAKE_UCAST, Config5, UWF },
1780 { WAKE_BCAST, Config5, BWF },
1781 { WAKE_MCAST, Config5, MWF },
1782 { WAKE_ANY, Config5, LanWake },
1783 { WAKE_MAGIC, Config3, MagicPacket }
1784 };
1785 u8 options;
1786
1787 RTL_W8(Cfg9346, Cfg9346_Unlock);
1788
1789 switch (tp->mac_version) {
1790 case RTL_GIGA_MAC_VER_34:
1791 case RTL_GIGA_MAC_VER_35:
1792 case RTL_GIGA_MAC_VER_36:
1793 case RTL_GIGA_MAC_VER_37:
1794 case RTL_GIGA_MAC_VER_38:
1795 case RTL_GIGA_MAC_VER_40:
1796 case RTL_GIGA_MAC_VER_41:
1797 case RTL_GIGA_MAC_VER_42:
1798 case RTL_GIGA_MAC_VER_43:
1799 case RTL_GIGA_MAC_VER_44:
1800 case RTL_GIGA_MAC_VER_45:
1801 case RTL_GIGA_MAC_VER_46:
1802 case RTL_GIGA_MAC_VER_47:
1803 case RTL_GIGA_MAC_VER_48:
1804 case RTL_GIGA_MAC_VER_49:
1805 case RTL_GIGA_MAC_VER_50:
1806 case RTL_GIGA_MAC_VER_51:
1807 tmp = ARRAY_SIZE(cfg) - 1;
1808 if (wolopts & WAKE_MAGIC)
1809 rtl_w0w1_eri(tp,
1810 0x0dc,
1811 ERIAR_MASK_0100,
1812 MagicPacket_v2,
1813 0x0000,
1814 ERIAR_EXGMAC);
1815 else
1816 rtl_w0w1_eri(tp,
1817 0x0dc,
1818 ERIAR_MASK_0100,
1819 0x0000,
1820 MagicPacket_v2,
1821 ERIAR_EXGMAC);
1822 break;
1823 default:
1824 tmp = ARRAY_SIZE(cfg);
1825 break;
1826 }
1827
1828 for (i = 0; i < tmp; i++) {
1829 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1830 if (wolopts & cfg[i].opt)
1831 options |= cfg[i].mask;
1832 RTL_W8(cfg[i].reg, options);
1833 }
1834
1835 switch (tp->mac_version) {
1836 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1837 options = RTL_R8(Config1) & ~PMEnable;
1838 if (wolopts)
1839 options |= PMEnable;
1840 RTL_W8(Config1, options);
1841 break;
1842 default:
1843 options = RTL_R8(Config2) & ~PME_SIGNAL;
1844 if (wolopts)
1845 options |= PME_SIGNAL;
1846 RTL_W8(Config2, options);
1847 break;
1848 }
1849
1850 RTL_W8(Cfg9346, Cfg9346_Lock);
1851 }
1852
1853 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1854 {
1855 struct rtl8169_private *tp = netdev_priv(dev);
1856 struct device *d = &tp->pci_dev->dev;
1857
1858 pm_runtime_get_noresume(d);
1859
1860 rtl_lock_work(tp);
1861
1862 if (wol->wolopts)
1863 tp->features |= RTL_FEATURE_WOL;
1864 else
1865 tp->features &= ~RTL_FEATURE_WOL;
1866 if (pm_runtime_active(d))
1867 __rtl8169_set_wol(tp, wol->wolopts);
1868 else
1869 tp->saved_wolopts = wol->wolopts;
1870
1871 rtl_unlock_work(tp);
1872
1873 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1874
1875 pm_runtime_put_noidle(d);
1876
1877 return 0;
1878 }
1879
1880 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1881 {
1882 return rtl_chip_infos[tp->mac_version].fw_name;
1883 }
1884
1885 static void rtl8169_get_drvinfo(struct net_device *dev,
1886 struct ethtool_drvinfo *info)
1887 {
1888 struct rtl8169_private *tp = netdev_priv(dev);
1889 struct rtl_fw *rtl_fw = tp->rtl_fw;
1890
1891 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1892 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1893 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1894 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1895 if (!IS_ERR_OR_NULL(rtl_fw))
1896 strlcpy(info->fw_version, rtl_fw->version,
1897 sizeof(info->fw_version));
1898 }
1899
1900 static int rtl8169_get_regs_len(struct net_device *dev)
1901 {
1902 return R8169_REGS_SIZE;
1903 }
1904
1905 static int rtl8169_set_speed_tbi(struct net_device *dev,
1906 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1907 {
1908 struct rtl8169_private *tp = netdev_priv(dev);
1909 void __iomem *ioaddr = tp->mmio_addr;
1910 int ret = 0;
1911 u32 reg;
1912
1913 reg = RTL_R32(TBICSR);
1914 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1915 (duplex == DUPLEX_FULL)) {
1916 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1917 } else if (autoneg == AUTONEG_ENABLE)
1918 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1919 else {
1920 netif_warn(tp, link, dev,
1921 "incorrect speed setting refused in TBI mode\n");
1922 ret = -EOPNOTSUPP;
1923 }
1924
1925 return ret;
1926 }
1927
1928 static int rtl8169_set_speed_xmii(struct net_device *dev,
1929 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1930 {
1931 struct rtl8169_private *tp = netdev_priv(dev);
1932 int giga_ctrl, bmcr;
1933 int rc = -EINVAL;
1934
1935 rtl_writephy(tp, 0x1f, 0x0000);
1936
1937 if (autoneg == AUTONEG_ENABLE) {
1938 int auto_nego;
1939
1940 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1941 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1942 ADVERTISE_100HALF | ADVERTISE_100FULL);
1943
1944 if (adv & ADVERTISED_10baseT_Half)
1945 auto_nego |= ADVERTISE_10HALF;
1946 if (adv & ADVERTISED_10baseT_Full)
1947 auto_nego |= ADVERTISE_10FULL;
1948 if (adv & ADVERTISED_100baseT_Half)
1949 auto_nego |= ADVERTISE_100HALF;
1950 if (adv & ADVERTISED_100baseT_Full)
1951 auto_nego |= ADVERTISE_100FULL;
1952
1953 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1954
1955 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1956 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1957
1958 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1959 if (tp->mii.supports_gmii) {
1960 if (adv & ADVERTISED_1000baseT_Half)
1961 giga_ctrl |= ADVERTISE_1000HALF;
1962 if (adv & ADVERTISED_1000baseT_Full)
1963 giga_ctrl |= ADVERTISE_1000FULL;
1964 } else if (adv & (ADVERTISED_1000baseT_Half |
1965 ADVERTISED_1000baseT_Full)) {
1966 netif_info(tp, link, dev,
1967 "PHY does not support 1000Mbps\n");
1968 goto out;
1969 }
1970
1971 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1972
1973 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1974 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1975 } else {
1976 giga_ctrl = 0;
1977
1978 if (speed == SPEED_10)
1979 bmcr = 0;
1980 else if (speed == SPEED_100)
1981 bmcr = BMCR_SPEED100;
1982 else
1983 goto out;
1984
1985 if (duplex == DUPLEX_FULL)
1986 bmcr |= BMCR_FULLDPLX;
1987 }
1988
1989 rtl_writephy(tp, MII_BMCR, bmcr);
1990
1991 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1992 tp->mac_version == RTL_GIGA_MAC_VER_03) {
1993 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1994 rtl_writephy(tp, 0x17, 0x2138);
1995 rtl_writephy(tp, 0x0e, 0x0260);
1996 } else {
1997 rtl_writephy(tp, 0x17, 0x2108);
1998 rtl_writephy(tp, 0x0e, 0x0000);
1999 }
2000 }
2001
2002 rc = 0;
2003 out:
2004 return rc;
2005 }
2006
2007 static int rtl8169_set_speed(struct net_device *dev,
2008 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
2009 {
2010 struct rtl8169_private *tp = netdev_priv(dev);
2011 int ret;
2012
2013 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
2014 if (ret < 0)
2015 goto out;
2016
2017 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
2018 (advertising & ADVERTISED_1000baseT_Full) &&
2019 !pci_is_pcie(tp->pci_dev)) {
2020 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
2021 }
2022 out:
2023 return ret;
2024 }
2025
2026 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2027 {
2028 struct rtl8169_private *tp = netdev_priv(dev);
2029 int ret;
2030
2031 del_timer_sync(&tp->timer);
2032
2033 rtl_lock_work(tp);
2034 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
2035 cmd->duplex, cmd->advertising);
2036 rtl_unlock_work(tp);
2037
2038 return ret;
2039 }
2040
2041 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
2042 netdev_features_t features)
2043 {
2044 struct rtl8169_private *tp = netdev_priv(dev);
2045
2046 if (dev->mtu > TD_MSS_MAX)
2047 features &= ~NETIF_F_ALL_TSO;
2048
2049 if (dev->mtu > JUMBO_1K &&
2050 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
2051 features &= ~NETIF_F_IP_CSUM;
2052
2053 return features;
2054 }
2055
2056 static void __rtl8169_set_features(struct net_device *dev,
2057 netdev_features_t features)
2058 {
2059 struct rtl8169_private *tp = netdev_priv(dev);
2060 void __iomem *ioaddr = tp->mmio_addr;
2061 u32 rx_config;
2062
2063 rx_config = RTL_R32(RxConfig);
2064 if (features & NETIF_F_RXALL)
2065 rx_config |= (AcceptErr | AcceptRunt);
2066 else
2067 rx_config &= ~(AcceptErr | AcceptRunt);
2068
2069 RTL_W32(RxConfig, rx_config);
2070
2071 if (features & NETIF_F_RXCSUM)
2072 tp->cp_cmd |= RxChkSum;
2073 else
2074 tp->cp_cmd &= ~RxChkSum;
2075
2076 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2077 tp->cp_cmd |= RxVlan;
2078 else
2079 tp->cp_cmd &= ~RxVlan;
2080
2081 tp->cp_cmd |= RTL_R16(CPlusCmd) & ~(RxVlan | RxChkSum);
2082
2083 RTL_W16(CPlusCmd, tp->cp_cmd);
2084 RTL_R16(CPlusCmd);
2085 }
2086
2087 static int rtl8169_set_features(struct net_device *dev,
2088 netdev_features_t features)
2089 {
2090 struct rtl8169_private *tp = netdev_priv(dev);
2091
2092 features &= NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX;
2093
2094 rtl_lock_work(tp);
2095 if (features ^ dev->features)
2096 __rtl8169_set_features(dev, features);
2097 rtl_unlock_work(tp);
2098
2099 return 0;
2100 }
2101
2102
2103 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
2104 {
2105 return (skb_vlan_tag_present(skb)) ?
2106 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
2107 }
2108
2109 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
2110 {
2111 u32 opts2 = le32_to_cpu(desc->opts2);
2112
2113 if (opts2 & RxVlanTag)
2114 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
2115 }
2116
2117 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
2118 {
2119 struct rtl8169_private *tp = netdev_priv(dev);
2120 void __iomem *ioaddr = tp->mmio_addr;
2121 u32 status;
2122
2123 cmd->supported =
2124 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
2125 cmd->port = PORT_FIBRE;
2126 cmd->transceiver = XCVR_INTERNAL;
2127
2128 status = RTL_R32(TBICSR);
2129 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
2130 cmd->autoneg = !!(status & TBINwEnable);
2131
2132 ethtool_cmd_speed_set(cmd, SPEED_1000);
2133 cmd->duplex = DUPLEX_FULL; /* Always set */
2134
2135 return 0;
2136 }
2137
2138 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
2139 {
2140 struct rtl8169_private *tp = netdev_priv(dev);
2141
2142 return mii_ethtool_gset(&tp->mii, cmd);
2143 }
2144
2145 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2146 {
2147 struct rtl8169_private *tp = netdev_priv(dev);
2148 int rc;
2149
2150 rtl_lock_work(tp);
2151 rc = tp->get_settings(dev, cmd);
2152 rtl_unlock_work(tp);
2153
2154 return rc;
2155 }
2156
2157 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2158 void *p)
2159 {
2160 struct rtl8169_private *tp = netdev_priv(dev);
2161 u32 __iomem *data = tp->mmio_addr;
2162 u32 *dw = p;
2163 int i;
2164
2165 rtl_lock_work(tp);
2166 for (i = 0; i < R8169_REGS_SIZE; i += 4)
2167 memcpy_fromio(dw++, data++, 4);
2168 rtl_unlock_work(tp);
2169 }
2170
2171 static u32 rtl8169_get_msglevel(struct net_device *dev)
2172 {
2173 struct rtl8169_private *tp = netdev_priv(dev);
2174
2175 return tp->msg_enable;
2176 }
2177
2178 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
2179 {
2180 struct rtl8169_private *tp = netdev_priv(dev);
2181
2182 tp->msg_enable = value;
2183 }
2184
2185 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
2186 "tx_packets",
2187 "rx_packets",
2188 "tx_errors",
2189 "rx_errors",
2190 "rx_missed",
2191 "align_errors",
2192 "tx_single_collisions",
2193 "tx_multi_collisions",
2194 "unicast",
2195 "broadcast",
2196 "multicast",
2197 "tx_aborted",
2198 "tx_underrun",
2199 };
2200
2201 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
2202 {
2203 switch (sset) {
2204 case ETH_SS_STATS:
2205 return ARRAY_SIZE(rtl8169_gstrings);
2206 default:
2207 return -EOPNOTSUPP;
2208 }
2209 }
2210
2211 DECLARE_RTL_COND(rtl_counters_cond)
2212 {
2213 void __iomem *ioaddr = tp->mmio_addr;
2214
2215 return RTL_R32(CounterAddrLow) & (CounterReset | CounterDump);
2216 }
2217
2218 static bool rtl8169_do_counters(struct net_device *dev, u32 counter_cmd)
2219 {
2220 struct rtl8169_private *tp = netdev_priv(dev);
2221 void __iomem *ioaddr = tp->mmio_addr;
2222 dma_addr_t paddr = tp->counters_phys_addr;
2223 u32 cmd;
2224 bool ret;
2225
2226 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
2227 cmd = (u64)paddr & DMA_BIT_MASK(32);
2228 RTL_W32(CounterAddrLow, cmd);
2229 RTL_W32(CounterAddrLow, cmd | counter_cmd);
2230
2231 ret = rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
2232
2233 RTL_W32(CounterAddrLow, 0);
2234 RTL_W32(CounterAddrHigh, 0);
2235
2236 return ret;
2237 }
2238
2239 static bool rtl8169_reset_counters(struct net_device *dev)
2240 {
2241 struct rtl8169_private *tp = netdev_priv(dev);
2242
2243 /*
2244 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
2245 * tally counters.
2246 */
2247 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
2248 return true;
2249
2250 return rtl8169_do_counters(dev, CounterReset);
2251 }
2252
2253 static bool rtl8169_update_counters(struct net_device *dev)
2254 {
2255 struct rtl8169_private *tp = netdev_priv(dev);
2256 void __iomem *ioaddr = tp->mmio_addr;
2257
2258 /*
2259 * Some chips are unable to dump tally counters when the receiver
2260 * is disabled.
2261 */
2262 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
2263 return true;
2264
2265 return rtl8169_do_counters(dev, CounterDump);
2266 }
2267
2268 static bool rtl8169_init_counter_offsets(struct net_device *dev)
2269 {
2270 struct rtl8169_private *tp = netdev_priv(dev);
2271 struct rtl8169_counters *counters = tp->counters;
2272 bool ret = false;
2273
2274 /*
2275 * rtl8169_init_counter_offsets is called from rtl_open. On chip
2276 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
2277 * reset by a power cycle, while the counter values collected by the
2278 * driver are reset at every driver unload/load cycle.
2279 *
2280 * To make sure the HW values returned by @get_stats64 match the SW
2281 * values, we collect the initial values at first open(*) and use them
2282 * as offsets to normalize the values returned by @get_stats64.
2283 *
2284 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
2285 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
2286 * set at open time by rtl_hw_start.
2287 */
2288
2289 if (tp->tc_offset.inited)
2290 return true;
2291
2292 /* If both, reset and update fail, propagate to caller. */
2293 if (rtl8169_reset_counters(dev))
2294 ret = true;
2295
2296 if (rtl8169_update_counters(dev))
2297 ret = true;
2298
2299 tp->tc_offset.tx_errors = counters->tx_errors;
2300 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
2301 tp->tc_offset.tx_aborted = counters->tx_aborted;
2302 tp->tc_offset.inited = true;
2303
2304 return ret;
2305 }
2306
2307 static void rtl8169_get_ethtool_stats(struct net_device *dev,
2308 struct ethtool_stats *stats, u64 *data)
2309 {
2310 struct rtl8169_private *tp = netdev_priv(dev);
2311 struct device *d = &tp->pci_dev->dev;
2312 struct rtl8169_counters *counters = tp->counters;
2313
2314 ASSERT_RTNL();
2315
2316 pm_runtime_get_noresume(d);
2317
2318 if (pm_runtime_active(d))
2319 rtl8169_update_counters(dev);
2320
2321 pm_runtime_put_noidle(d);
2322
2323 data[0] = le64_to_cpu(counters->tx_packets);
2324 data[1] = le64_to_cpu(counters->rx_packets);
2325 data[2] = le64_to_cpu(counters->tx_errors);
2326 data[3] = le32_to_cpu(counters->rx_errors);
2327 data[4] = le16_to_cpu(counters->rx_missed);
2328 data[5] = le16_to_cpu(counters->align_errors);
2329 data[6] = le32_to_cpu(counters->tx_one_collision);
2330 data[7] = le32_to_cpu(counters->tx_multi_collision);
2331 data[8] = le64_to_cpu(counters->rx_unicast);
2332 data[9] = le64_to_cpu(counters->rx_broadcast);
2333 data[10] = le32_to_cpu(counters->rx_multicast);
2334 data[11] = le16_to_cpu(counters->tx_aborted);
2335 data[12] = le16_to_cpu(counters->tx_underun);
2336 }
2337
2338 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2339 {
2340 switch(stringset) {
2341 case ETH_SS_STATS:
2342 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2343 break;
2344 }
2345 }
2346
2347 static const struct ethtool_ops rtl8169_ethtool_ops = {
2348 .get_drvinfo = rtl8169_get_drvinfo,
2349 .get_regs_len = rtl8169_get_regs_len,
2350 .get_link = ethtool_op_get_link,
2351 .get_settings = rtl8169_get_settings,
2352 .set_settings = rtl8169_set_settings,
2353 .get_msglevel = rtl8169_get_msglevel,
2354 .set_msglevel = rtl8169_set_msglevel,
2355 .get_regs = rtl8169_get_regs,
2356 .get_wol = rtl8169_get_wol,
2357 .set_wol = rtl8169_set_wol,
2358 .get_strings = rtl8169_get_strings,
2359 .get_sset_count = rtl8169_get_sset_count,
2360 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2361 .get_ts_info = ethtool_op_get_ts_info,
2362 };
2363
2364 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2365 struct net_device *dev, u8 default_version)
2366 {
2367 void __iomem *ioaddr = tp->mmio_addr;
2368 /*
2369 * The driver currently handles the 8168Bf and the 8168Be identically
2370 * but they can be identified more specifically through the test below
2371 * if needed:
2372 *
2373 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2374 *
2375 * Same thing for the 8101Eb and the 8101Ec:
2376 *
2377 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2378 */
2379 static const struct rtl_mac_info {
2380 u32 mask;
2381 u32 val;
2382 int mac_version;
2383 } mac_info[] = {
2384 /* 8168EP family. */
2385 { 0x7cf00000, 0x50200000, RTL_GIGA_MAC_VER_51 },
2386 { 0x7cf00000, 0x50100000, RTL_GIGA_MAC_VER_50 },
2387 { 0x7cf00000, 0x50000000, RTL_GIGA_MAC_VER_49 },
2388
2389 /* 8168H family. */
2390 { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 },
2391 { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 },
2392
2393 /* 8168G family. */
2394 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
2395 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
2396 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2397 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2398
2399 /* 8168F family. */
2400 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
2401 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2402 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2403
2404 /* 8168E family. */
2405 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
2406 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
2407 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2408 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2409
2410 /* 8168D family. */
2411 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
2412 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
2413 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
2414
2415 /* 8168DP family. */
2416 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2417 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
2418 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
2419
2420 /* 8168C family. */
2421 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
2422 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
2423 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
2424 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
2425 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2426 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
2427 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
2428 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
2429 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
2430
2431 /* 8168B family. */
2432 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2433 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
2434 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2435 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2436
2437 /* 8101 family. */
2438 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
2439 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
2440 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
2441 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
2442 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
2443 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2444 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2445 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
2446 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
2447 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2448 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2449 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2450 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
2451 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2452 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
2453 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2454 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2455 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
2456 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2457 /* FIXME: where did these entries come from ? -- FR */
2458 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2459 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2460
2461 /* 8110 family. */
2462 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2463 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2464 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2465 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2466 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2467 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2468
2469 /* Catch-all */
2470 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
2471 };
2472 const struct rtl_mac_info *p = mac_info;
2473 u32 reg;
2474
2475 reg = RTL_R32(TxConfig);
2476 while ((reg & p->mask) != p->val)
2477 p++;
2478 tp->mac_version = p->mac_version;
2479
2480 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2481 netif_notice(tp, probe, dev,
2482 "unknown MAC, using family default\n");
2483 tp->mac_version = default_version;
2484 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2485 tp->mac_version = tp->mii.supports_gmii ?
2486 RTL_GIGA_MAC_VER_42 :
2487 RTL_GIGA_MAC_VER_43;
2488 } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2489 tp->mac_version = tp->mii.supports_gmii ?
2490 RTL_GIGA_MAC_VER_45 :
2491 RTL_GIGA_MAC_VER_47;
2492 } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2493 tp->mac_version = tp->mii.supports_gmii ?
2494 RTL_GIGA_MAC_VER_46 :
2495 RTL_GIGA_MAC_VER_48;
2496 }
2497 }
2498
2499 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2500 {
2501 dprintk("mac_version = 0x%02x\n", tp->mac_version);
2502 }
2503
2504 struct phy_reg {
2505 u16 reg;
2506 u16 val;
2507 };
2508
2509 static void rtl_writephy_batch(struct rtl8169_private *tp,
2510 const struct phy_reg *regs, int len)
2511 {
2512 while (len-- > 0) {
2513 rtl_writephy(tp, regs->reg, regs->val);
2514 regs++;
2515 }
2516 }
2517
2518 #define PHY_READ 0x00000000
2519 #define PHY_DATA_OR 0x10000000
2520 #define PHY_DATA_AND 0x20000000
2521 #define PHY_BJMPN 0x30000000
2522 #define PHY_MDIO_CHG 0x40000000
2523 #define PHY_CLEAR_READCOUNT 0x70000000
2524 #define PHY_WRITE 0x80000000
2525 #define PHY_READCOUNT_EQ_SKIP 0x90000000
2526 #define PHY_COMP_EQ_SKIPN 0xa0000000
2527 #define PHY_COMP_NEQ_SKIPN 0xb0000000
2528 #define PHY_WRITE_PREVIOUS 0xc0000000
2529 #define PHY_SKIPN 0xd0000000
2530 #define PHY_DELAY_MS 0xe0000000
2531
2532 struct fw_info {
2533 u32 magic;
2534 char version[RTL_VER_SIZE];
2535 __le32 fw_start;
2536 __le32 fw_len;
2537 u8 chksum;
2538 } __packed;
2539
2540 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2541
2542 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2543 {
2544 const struct firmware *fw = rtl_fw->fw;
2545 struct fw_info *fw_info = (struct fw_info *)fw->data;
2546 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2547 char *version = rtl_fw->version;
2548 bool rc = false;
2549
2550 if (fw->size < FW_OPCODE_SIZE)
2551 goto out;
2552
2553 if (!fw_info->magic) {
2554 size_t i, size, start;
2555 u8 checksum = 0;
2556
2557 if (fw->size < sizeof(*fw_info))
2558 goto out;
2559
2560 for (i = 0; i < fw->size; i++)
2561 checksum += fw->data[i];
2562 if (checksum != 0)
2563 goto out;
2564
2565 start = le32_to_cpu(fw_info->fw_start);
2566 if (start > fw->size)
2567 goto out;
2568
2569 size = le32_to_cpu(fw_info->fw_len);
2570 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2571 goto out;
2572
2573 memcpy(version, fw_info->version, RTL_VER_SIZE);
2574
2575 pa->code = (__le32 *)(fw->data + start);
2576 pa->size = size;
2577 } else {
2578 if (fw->size % FW_OPCODE_SIZE)
2579 goto out;
2580
2581 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2582
2583 pa->code = (__le32 *)fw->data;
2584 pa->size = fw->size / FW_OPCODE_SIZE;
2585 }
2586 version[RTL_VER_SIZE - 1] = 0;
2587
2588 rc = true;
2589 out:
2590 return rc;
2591 }
2592
2593 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2594 struct rtl_fw_phy_action *pa)
2595 {
2596 bool rc = false;
2597 size_t index;
2598
2599 for (index = 0; index < pa->size; index++) {
2600 u32 action = le32_to_cpu(pa->code[index]);
2601 u32 regno = (action & 0x0fff0000) >> 16;
2602
2603 switch(action & 0xf0000000) {
2604 case PHY_READ:
2605 case PHY_DATA_OR:
2606 case PHY_DATA_AND:
2607 case PHY_MDIO_CHG:
2608 case PHY_CLEAR_READCOUNT:
2609 case PHY_WRITE:
2610 case PHY_WRITE_PREVIOUS:
2611 case PHY_DELAY_MS:
2612 break;
2613
2614 case PHY_BJMPN:
2615 if (regno > index) {
2616 netif_err(tp, ifup, tp->dev,
2617 "Out of range of firmware\n");
2618 goto out;
2619 }
2620 break;
2621 case PHY_READCOUNT_EQ_SKIP:
2622 if (index + 2 >= pa->size) {
2623 netif_err(tp, ifup, tp->dev,
2624 "Out of range of firmware\n");
2625 goto out;
2626 }
2627 break;
2628 case PHY_COMP_EQ_SKIPN:
2629 case PHY_COMP_NEQ_SKIPN:
2630 case PHY_SKIPN:
2631 if (index + 1 + regno >= pa->size) {
2632 netif_err(tp, ifup, tp->dev,
2633 "Out of range of firmware\n");
2634 goto out;
2635 }
2636 break;
2637
2638 default:
2639 netif_err(tp, ifup, tp->dev,
2640 "Invalid action 0x%08x\n", action);
2641 goto out;
2642 }
2643 }
2644 rc = true;
2645 out:
2646 return rc;
2647 }
2648
2649 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2650 {
2651 struct net_device *dev = tp->dev;
2652 int rc = -EINVAL;
2653
2654 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2655 netif_err(tp, ifup, dev, "invalid firmware\n");
2656 goto out;
2657 }
2658
2659 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2660 rc = 0;
2661 out:
2662 return rc;
2663 }
2664
2665 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2666 {
2667 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2668 struct mdio_ops org, *ops = &tp->mdio_ops;
2669 u32 predata, count;
2670 size_t index;
2671
2672 predata = count = 0;
2673 org.write = ops->write;
2674 org.read = ops->read;
2675
2676 for (index = 0; index < pa->size; ) {
2677 u32 action = le32_to_cpu(pa->code[index]);
2678 u32 data = action & 0x0000ffff;
2679 u32 regno = (action & 0x0fff0000) >> 16;
2680
2681 if (!action)
2682 break;
2683
2684 switch(action & 0xf0000000) {
2685 case PHY_READ:
2686 predata = rtl_readphy(tp, regno);
2687 count++;
2688 index++;
2689 break;
2690 case PHY_DATA_OR:
2691 predata |= data;
2692 index++;
2693 break;
2694 case PHY_DATA_AND:
2695 predata &= data;
2696 index++;
2697 break;
2698 case PHY_BJMPN:
2699 index -= regno;
2700 break;
2701 case PHY_MDIO_CHG:
2702 if (data == 0) {
2703 ops->write = org.write;
2704 ops->read = org.read;
2705 } else if (data == 1) {
2706 ops->write = mac_mcu_write;
2707 ops->read = mac_mcu_read;
2708 }
2709
2710 index++;
2711 break;
2712 case PHY_CLEAR_READCOUNT:
2713 count = 0;
2714 index++;
2715 break;
2716 case PHY_WRITE:
2717 rtl_writephy(tp, regno, data);
2718 index++;
2719 break;
2720 case PHY_READCOUNT_EQ_SKIP:
2721 index += (count == data) ? 2 : 1;
2722 break;
2723 case PHY_COMP_EQ_SKIPN:
2724 if (predata == data)
2725 index += regno;
2726 index++;
2727 break;
2728 case PHY_COMP_NEQ_SKIPN:
2729 if (predata != data)
2730 index += regno;
2731 index++;
2732 break;
2733 case PHY_WRITE_PREVIOUS:
2734 rtl_writephy(tp, regno, predata);
2735 index++;
2736 break;
2737 case PHY_SKIPN:
2738 index += regno + 1;
2739 break;
2740 case PHY_DELAY_MS:
2741 mdelay(data);
2742 index++;
2743 break;
2744
2745 default:
2746 BUG();
2747 }
2748 }
2749
2750 ops->write = org.write;
2751 ops->read = org.read;
2752 }
2753
2754 static void rtl_release_firmware(struct rtl8169_private *tp)
2755 {
2756 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2757 release_firmware(tp->rtl_fw->fw);
2758 kfree(tp->rtl_fw);
2759 }
2760 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2761 }
2762
2763 static void rtl_apply_firmware(struct rtl8169_private *tp)
2764 {
2765 struct rtl_fw *rtl_fw = tp->rtl_fw;
2766
2767 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2768 if (!IS_ERR_OR_NULL(rtl_fw))
2769 rtl_phy_write_fw(tp, rtl_fw);
2770 }
2771
2772 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2773 {
2774 if (rtl_readphy(tp, reg) != val)
2775 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2776 else
2777 rtl_apply_firmware(tp);
2778 }
2779
2780 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2781 {
2782 static const struct phy_reg phy_reg_init[] = {
2783 { 0x1f, 0x0001 },
2784 { 0x06, 0x006e },
2785 { 0x08, 0x0708 },
2786 { 0x15, 0x4000 },
2787 { 0x18, 0x65c7 },
2788
2789 { 0x1f, 0x0001 },
2790 { 0x03, 0x00a1 },
2791 { 0x02, 0x0008 },
2792 { 0x01, 0x0120 },
2793 { 0x00, 0x1000 },
2794 { 0x04, 0x0800 },
2795 { 0x04, 0x0000 },
2796
2797 { 0x03, 0xff41 },
2798 { 0x02, 0xdf60 },
2799 { 0x01, 0x0140 },
2800 { 0x00, 0x0077 },
2801 { 0x04, 0x7800 },
2802 { 0x04, 0x7000 },
2803
2804 { 0x03, 0x802f },
2805 { 0x02, 0x4f02 },
2806 { 0x01, 0x0409 },
2807 { 0x00, 0xf0f9 },
2808 { 0x04, 0x9800 },
2809 { 0x04, 0x9000 },
2810
2811 { 0x03, 0xdf01 },
2812 { 0x02, 0xdf20 },
2813 { 0x01, 0xff95 },
2814 { 0x00, 0xba00 },
2815 { 0x04, 0xa800 },
2816 { 0x04, 0xa000 },
2817
2818 { 0x03, 0xff41 },
2819 { 0x02, 0xdf20 },
2820 { 0x01, 0x0140 },
2821 { 0x00, 0x00bb },
2822 { 0x04, 0xb800 },
2823 { 0x04, 0xb000 },
2824
2825 { 0x03, 0xdf41 },
2826 { 0x02, 0xdc60 },
2827 { 0x01, 0x6340 },
2828 { 0x00, 0x007d },
2829 { 0x04, 0xd800 },
2830 { 0x04, 0xd000 },
2831
2832 { 0x03, 0xdf01 },
2833 { 0x02, 0xdf20 },
2834 { 0x01, 0x100a },
2835 { 0x00, 0xa0ff },
2836 { 0x04, 0xf800 },
2837 { 0x04, 0xf000 },
2838
2839 { 0x1f, 0x0000 },
2840 { 0x0b, 0x0000 },
2841 { 0x00, 0x9200 }
2842 };
2843
2844 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2845 }
2846
2847 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2848 {
2849 static const struct phy_reg phy_reg_init[] = {
2850 { 0x1f, 0x0002 },
2851 { 0x01, 0x90d0 },
2852 { 0x1f, 0x0000 }
2853 };
2854
2855 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2856 }
2857
2858 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2859 {
2860 struct pci_dev *pdev = tp->pci_dev;
2861
2862 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2863 (pdev->subsystem_device != 0xe000))
2864 return;
2865
2866 rtl_writephy(tp, 0x1f, 0x0001);
2867 rtl_writephy(tp, 0x10, 0xf01b);
2868 rtl_writephy(tp, 0x1f, 0x0000);
2869 }
2870
2871 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2872 {
2873 static const struct phy_reg phy_reg_init[] = {
2874 { 0x1f, 0x0001 },
2875 { 0x04, 0x0000 },
2876 { 0x03, 0x00a1 },
2877 { 0x02, 0x0008 },
2878 { 0x01, 0x0120 },
2879 { 0x00, 0x1000 },
2880 { 0x04, 0x0800 },
2881 { 0x04, 0x9000 },
2882 { 0x03, 0x802f },
2883 { 0x02, 0x4f02 },
2884 { 0x01, 0x0409 },
2885 { 0x00, 0xf099 },
2886 { 0x04, 0x9800 },
2887 { 0x04, 0xa000 },
2888 { 0x03, 0xdf01 },
2889 { 0x02, 0xdf20 },
2890 { 0x01, 0xff95 },
2891 { 0x00, 0xba00 },
2892 { 0x04, 0xa800 },
2893 { 0x04, 0xf000 },
2894 { 0x03, 0xdf01 },
2895 { 0x02, 0xdf20 },
2896 { 0x01, 0x101a },
2897 { 0x00, 0xa0ff },
2898 { 0x04, 0xf800 },
2899 { 0x04, 0x0000 },
2900 { 0x1f, 0x0000 },
2901
2902 { 0x1f, 0x0001 },
2903 { 0x10, 0xf41b },
2904 { 0x14, 0xfb54 },
2905 { 0x18, 0xf5c7 },
2906 { 0x1f, 0x0000 },
2907
2908 { 0x1f, 0x0001 },
2909 { 0x17, 0x0cc0 },
2910 { 0x1f, 0x0000 }
2911 };
2912
2913 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2914
2915 rtl8169scd_hw_phy_config_quirk(tp);
2916 }
2917
2918 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2919 {
2920 static const struct phy_reg phy_reg_init[] = {
2921 { 0x1f, 0x0001 },
2922 { 0x04, 0x0000 },
2923 { 0x03, 0x00a1 },
2924 { 0x02, 0x0008 },
2925 { 0x01, 0x0120 },
2926 { 0x00, 0x1000 },
2927 { 0x04, 0x0800 },
2928 { 0x04, 0x9000 },
2929 { 0x03, 0x802f },
2930 { 0x02, 0x4f02 },
2931 { 0x01, 0x0409 },
2932 { 0x00, 0xf099 },
2933 { 0x04, 0x9800 },
2934 { 0x04, 0xa000 },
2935 { 0x03, 0xdf01 },
2936 { 0x02, 0xdf20 },
2937 { 0x01, 0xff95 },
2938 { 0x00, 0xba00 },
2939 { 0x04, 0xa800 },
2940 { 0x04, 0xf000 },
2941 { 0x03, 0xdf01 },
2942 { 0x02, 0xdf20 },
2943 { 0x01, 0x101a },
2944 { 0x00, 0xa0ff },
2945 { 0x04, 0xf800 },
2946 { 0x04, 0x0000 },
2947 { 0x1f, 0x0000 },
2948
2949 { 0x1f, 0x0001 },
2950 { 0x0b, 0x8480 },
2951 { 0x1f, 0x0000 },
2952
2953 { 0x1f, 0x0001 },
2954 { 0x18, 0x67c7 },
2955 { 0x04, 0x2000 },
2956 { 0x03, 0x002f },
2957 { 0x02, 0x4360 },
2958 { 0x01, 0x0109 },
2959 { 0x00, 0x3022 },
2960 { 0x04, 0x2800 },
2961 { 0x1f, 0x0000 },
2962
2963 { 0x1f, 0x0001 },
2964 { 0x17, 0x0cc0 },
2965 { 0x1f, 0x0000 }
2966 };
2967
2968 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2969 }
2970
2971 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2972 {
2973 static const struct phy_reg phy_reg_init[] = {
2974 { 0x10, 0xf41b },
2975 { 0x1f, 0x0000 }
2976 };
2977
2978 rtl_writephy(tp, 0x1f, 0x0001);
2979 rtl_patchphy(tp, 0x16, 1 << 0);
2980
2981 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2982 }
2983
2984 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2985 {
2986 static const struct phy_reg phy_reg_init[] = {
2987 { 0x1f, 0x0001 },
2988 { 0x10, 0xf41b },
2989 { 0x1f, 0x0000 }
2990 };
2991
2992 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2993 }
2994
2995 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2996 {
2997 static const struct phy_reg phy_reg_init[] = {
2998 { 0x1f, 0x0000 },
2999 { 0x1d, 0x0f00 },
3000 { 0x1f, 0x0002 },
3001 { 0x0c, 0x1ec8 },
3002 { 0x1f, 0x0000 }
3003 };
3004
3005 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3006 }
3007
3008 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
3009 {
3010 static const struct phy_reg phy_reg_init[] = {
3011 { 0x1f, 0x0001 },
3012 { 0x1d, 0x3d98 },
3013 { 0x1f, 0x0000 }
3014 };
3015
3016 rtl_writephy(tp, 0x1f, 0x0000);
3017 rtl_patchphy(tp, 0x14, 1 << 5);
3018 rtl_patchphy(tp, 0x0d, 1 << 5);
3019
3020 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3021 }
3022
3023 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
3024 {
3025 static const struct phy_reg phy_reg_init[] = {
3026 { 0x1f, 0x0001 },
3027 { 0x12, 0x2300 },
3028 { 0x1f, 0x0002 },
3029 { 0x00, 0x88d4 },
3030 { 0x01, 0x82b1 },
3031 { 0x03, 0x7002 },
3032 { 0x08, 0x9e30 },
3033 { 0x09, 0x01f0 },
3034 { 0x0a, 0x5500 },
3035 { 0x0c, 0x00c8 },
3036 { 0x1f, 0x0003 },
3037 { 0x12, 0xc096 },
3038 { 0x16, 0x000a },
3039 { 0x1f, 0x0000 },
3040 { 0x1f, 0x0000 },
3041 { 0x09, 0x2000 },
3042 { 0x09, 0x0000 }
3043 };
3044
3045 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3046
3047 rtl_patchphy(tp, 0x14, 1 << 5);
3048 rtl_patchphy(tp, 0x0d, 1 << 5);
3049 rtl_writephy(tp, 0x1f, 0x0000);
3050 }
3051
3052 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
3053 {
3054 static const struct phy_reg phy_reg_init[] = {
3055 { 0x1f, 0x0001 },
3056 { 0x12, 0x2300 },
3057 { 0x03, 0x802f },
3058 { 0x02, 0x4f02 },
3059 { 0x01, 0x0409 },
3060 { 0x00, 0xf099 },
3061 { 0x04, 0x9800 },
3062 { 0x04, 0x9000 },
3063 { 0x1d, 0x3d98 },
3064 { 0x1f, 0x0002 },
3065 { 0x0c, 0x7eb8 },
3066 { 0x06, 0x0761 },
3067 { 0x1f, 0x0003 },
3068 { 0x16, 0x0f0a },
3069 { 0x1f, 0x0000 }
3070 };
3071
3072 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3073
3074 rtl_patchphy(tp, 0x16, 1 << 0);
3075 rtl_patchphy(tp, 0x14, 1 << 5);
3076 rtl_patchphy(tp, 0x0d, 1 << 5);
3077 rtl_writephy(tp, 0x1f, 0x0000);
3078 }
3079
3080 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
3081 {
3082 static const struct phy_reg phy_reg_init[] = {
3083 { 0x1f, 0x0001 },
3084 { 0x12, 0x2300 },
3085 { 0x1d, 0x3d98 },
3086 { 0x1f, 0x0002 },
3087 { 0x0c, 0x7eb8 },
3088 { 0x06, 0x5461 },
3089 { 0x1f, 0x0003 },
3090 { 0x16, 0x0f0a },
3091 { 0x1f, 0x0000 }
3092 };
3093
3094 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3095
3096 rtl_patchphy(tp, 0x16, 1 << 0);
3097 rtl_patchphy(tp, 0x14, 1 << 5);
3098 rtl_patchphy(tp, 0x0d, 1 << 5);
3099 rtl_writephy(tp, 0x1f, 0x0000);
3100 }
3101
3102 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
3103 {
3104 rtl8168c_3_hw_phy_config(tp);
3105 }
3106
3107 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
3108 {
3109 static const struct phy_reg phy_reg_init_0[] = {
3110 /* Channel Estimation */
3111 { 0x1f, 0x0001 },
3112 { 0x06, 0x4064 },
3113 { 0x07, 0x2863 },
3114 { 0x08, 0x059c },
3115 { 0x09, 0x26b4 },
3116 { 0x0a, 0x6a19 },
3117 { 0x0b, 0xdcc8 },
3118 { 0x10, 0xf06d },
3119 { 0x14, 0x7f68 },
3120 { 0x18, 0x7fd9 },
3121 { 0x1c, 0xf0ff },
3122 { 0x1d, 0x3d9c },
3123 { 0x1f, 0x0003 },
3124 { 0x12, 0xf49f },
3125 { 0x13, 0x070b },
3126 { 0x1a, 0x05ad },
3127 { 0x14, 0x94c0 },
3128
3129 /*
3130 * Tx Error Issue
3131 * Enhance line driver power
3132 */
3133 { 0x1f, 0x0002 },
3134 { 0x06, 0x5561 },
3135 { 0x1f, 0x0005 },
3136 { 0x05, 0x8332 },
3137 { 0x06, 0x5561 },
3138
3139 /*
3140 * Can not link to 1Gbps with bad cable
3141 * Decrease SNR threshold form 21.07dB to 19.04dB
3142 */
3143 { 0x1f, 0x0001 },
3144 { 0x17, 0x0cc0 },
3145
3146 { 0x1f, 0x0000 },
3147 { 0x0d, 0xf880 }
3148 };
3149
3150 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3151
3152 /*
3153 * Rx Error Issue
3154 * Fine Tune Switching regulator parameter
3155 */
3156 rtl_writephy(tp, 0x1f, 0x0002);
3157 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
3158 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
3159
3160 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3161 static const struct phy_reg phy_reg_init[] = {
3162 { 0x1f, 0x0002 },
3163 { 0x05, 0x669a },
3164 { 0x1f, 0x0005 },
3165 { 0x05, 0x8330 },
3166 { 0x06, 0x669a },
3167 { 0x1f, 0x0002 }
3168 };
3169 int val;
3170
3171 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3172
3173 val = rtl_readphy(tp, 0x0d);
3174
3175 if ((val & 0x00ff) != 0x006c) {
3176 static const u32 set[] = {
3177 0x0065, 0x0066, 0x0067, 0x0068,
3178 0x0069, 0x006a, 0x006b, 0x006c
3179 };
3180 int i;
3181
3182 rtl_writephy(tp, 0x1f, 0x0002);
3183
3184 val &= 0xff00;
3185 for (i = 0; i < ARRAY_SIZE(set); i++)
3186 rtl_writephy(tp, 0x0d, val | set[i]);
3187 }
3188 } else {
3189 static const struct phy_reg phy_reg_init[] = {
3190 { 0x1f, 0x0002 },
3191 { 0x05, 0x6662 },
3192 { 0x1f, 0x0005 },
3193 { 0x05, 0x8330 },
3194 { 0x06, 0x6662 }
3195 };
3196
3197 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3198 }
3199
3200 /* RSET couple improve */
3201 rtl_writephy(tp, 0x1f, 0x0002);
3202 rtl_patchphy(tp, 0x0d, 0x0300);
3203 rtl_patchphy(tp, 0x0f, 0x0010);
3204
3205 /* Fine tune PLL performance */
3206 rtl_writephy(tp, 0x1f, 0x0002);
3207 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3208 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3209
3210 rtl_writephy(tp, 0x1f, 0x0005);
3211 rtl_writephy(tp, 0x05, 0x001b);
3212
3213 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
3214
3215 rtl_writephy(tp, 0x1f, 0x0000);
3216 }
3217
3218 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
3219 {
3220 static const struct phy_reg phy_reg_init_0[] = {
3221 /* Channel Estimation */
3222 { 0x1f, 0x0001 },
3223 { 0x06, 0x4064 },
3224 { 0x07, 0x2863 },
3225 { 0x08, 0x059c },
3226 { 0x09, 0x26b4 },
3227 { 0x0a, 0x6a19 },
3228 { 0x0b, 0xdcc8 },
3229 { 0x10, 0xf06d },
3230 { 0x14, 0x7f68 },
3231 { 0x18, 0x7fd9 },
3232 { 0x1c, 0xf0ff },
3233 { 0x1d, 0x3d9c },
3234 { 0x1f, 0x0003 },
3235 { 0x12, 0xf49f },
3236 { 0x13, 0x070b },
3237 { 0x1a, 0x05ad },
3238 { 0x14, 0x94c0 },
3239
3240 /*
3241 * Tx Error Issue
3242 * Enhance line driver power
3243 */
3244 { 0x1f, 0x0002 },
3245 { 0x06, 0x5561 },
3246 { 0x1f, 0x0005 },
3247 { 0x05, 0x8332 },
3248 { 0x06, 0x5561 },
3249
3250 /*
3251 * Can not link to 1Gbps with bad cable
3252 * Decrease SNR threshold form 21.07dB to 19.04dB
3253 */
3254 { 0x1f, 0x0001 },
3255 { 0x17, 0x0cc0 },
3256
3257 { 0x1f, 0x0000 },
3258 { 0x0d, 0xf880 }
3259 };
3260
3261 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3262
3263 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3264 static const struct phy_reg phy_reg_init[] = {
3265 { 0x1f, 0x0002 },
3266 { 0x05, 0x669a },
3267 { 0x1f, 0x0005 },
3268 { 0x05, 0x8330 },
3269 { 0x06, 0x669a },
3270
3271 { 0x1f, 0x0002 }
3272 };
3273 int val;
3274
3275 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3276
3277 val = rtl_readphy(tp, 0x0d);
3278 if ((val & 0x00ff) != 0x006c) {
3279 static const u32 set[] = {
3280 0x0065, 0x0066, 0x0067, 0x0068,
3281 0x0069, 0x006a, 0x006b, 0x006c
3282 };
3283 int i;
3284
3285 rtl_writephy(tp, 0x1f, 0x0002);
3286
3287 val &= 0xff00;
3288 for (i = 0; i < ARRAY_SIZE(set); i++)
3289 rtl_writephy(tp, 0x0d, val | set[i]);
3290 }
3291 } else {
3292 static const struct phy_reg phy_reg_init[] = {
3293 { 0x1f, 0x0002 },
3294 { 0x05, 0x2642 },
3295 { 0x1f, 0x0005 },
3296 { 0x05, 0x8330 },
3297 { 0x06, 0x2642 }
3298 };
3299
3300 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3301 }
3302
3303 /* Fine tune PLL performance */
3304 rtl_writephy(tp, 0x1f, 0x0002);
3305 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3306 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3307
3308 /* Switching regulator Slew rate */
3309 rtl_writephy(tp, 0x1f, 0x0002);
3310 rtl_patchphy(tp, 0x0f, 0x0017);
3311
3312 rtl_writephy(tp, 0x1f, 0x0005);
3313 rtl_writephy(tp, 0x05, 0x001b);
3314
3315 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3316
3317 rtl_writephy(tp, 0x1f, 0x0000);
3318 }
3319
3320 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3321 {
3322 static const struct phy_reg phy_reg_init[] = {
3323 { 0x1f, 0x0002 },
3324 { 0x10, 0x0008 },
3325 { 0x0d, 0x006c },
3326
3327 { 0x1f, 0x0000 },
3328 { 0x0d, 0xf880 },
3329
3330 { 0x1f, 0x0001 },
3331 { 0x17, 0x0cc0 },
3332
3333 { 0x1f, 0x0001 },
3334 { 0x0b, 0xa4d8 },
3335 { 0x09, 0x281c },
3336 { 0x07, 0x2883 },
3337 { 0x0a, 0x6b35 },
3338 { 0x1d, 0x3da4 },
3339 { 0x1c, 0xeffd },
3340 { 0x14, 0x7f52 },
3341 { 0x18, 0x7fc6 },
3342 { 0x08, 0x0601 },
3343 { 0x06, 0x4063 },
3344 { 0x10, 0xf074 },
3345 { 0x1f, 0x0003 },
3346 { 0x13, 0x0789 },
3347 { 0x12, 0xf4bd },
3348 { 0x1a, 0x04fd },
3349 { 0x14, 0x84b0 },
3350 { 0x1f, 0x0000 },
3351 { 0x00, 0x9200 },
3352
3353 { 0x1f, 0x0005 },
3354 { 0x01, 0x0340 },
3355 { 0x1f, 0x0001 },
3356 { 0x04, 0x4000 },
3357 { 0x03, 0x1d21 },
3358 { 0x02, 0x0c32 },
3359 { 0x01, 0x0200 },
3360 { 0x00, 0x5554 },
3361 { 0x04, 0x4800 },
3362 { 0x04, 0x4000 },
3363 { 0x04, 0xf000 },
3364 { 0x03, 0xdf01 },
3365 { 0x02, 0xdf20 },
3366 { 0x01, 0x101a },
3367 { 0x00, 0xa0ff },
3368 { 0x04, 0xf800 },
3369 { 0x04, 0xf000 },
3370 { 0x1f, 0x0000 },
3371
3372 { 0x1f, 0x0007 },
3373 { 0x1e, 0x0023 },
3374 { 0x16, 0x0000 },
3375 { 0x1f, 0x0000 }
3376 };
3377
3378 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3379 }
3380
3381 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3382 {
3383 static const struct phy_reg phy_reg_init[] = {
3384 { 0x1f, 0x0001 },
3385 { 0x17, 0x0cc0 },
3386
3387 { 0x1f, 0x0007 },
3388 { 0x1e, 0x002d },
3389 { 0x18, 0x0040 },
3390 { 0x1f, 0x0000 }
3391 };
3392
3393 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3394 rtl_patchphy(tp, 0x0d, 1 << 5);
3395 }
3396
3397 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3398 {
3399 static const struct phy_reg phy_reg_init[] = {
3400 /* Enable Delay cap */
3401 { 0x1f, 0x0005 },
3402 { 0x05, 0x8b80 },
3403 { 0x06, 0xc896 },
3404 { 0x1f, 0x0000 },
3405
3406 /* Channel estimation fine tune */
3407 { 0x1f, 0x0001 },
3408 { 0x0b, 0x6c20 },
3409 { 0x07, 0x2872 },
3410 { 0x1c, 0xefff },
3411 { 0x1f, 0x0003 },
3412 { 0x14, 0x6420 },
3413 { 0x1f, 0x0000 },
3414
3415 /* Update PFM & 10M TX idle timer */
3416 { 0x1f, 0x0007 },
3417 { 0x1e, 0x002f },
3418 { 0x15, 0x1919 },
3419 { 0x1f, 0x0000 },
3420
3421 { 0x1f, 0x0007 },
3422 { 0x1e, 0x00ac },
3423 { 0x18, 0x0006 },
3424 { 0x1f, 0x0000 }
3425 };
3426
3427 rtl_apply_firmware(tp);
3428
3429 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3430
3431 /* DCO enable for 10M IDLE Power */
3432 rtl_writephy(tp, 0x1f, 0x0007);
3433 rtl_writephy(tp, 0x1e, 0x0023);
3434 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3435 rtl_writephy(tp, 0x1f, 0x0000);
3436
3437 /* For impedance matching */
3438 rtl_writephy(tp, 0x1f, 0x0002);
3439 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3440 rtl_writephy(tp, 0x1f, 0x0000);
3441
3442 /* PHY auto speed down */
3443 rtl_writephy(tp, 0x1f, 0x0007);
3444 rtl_writephy(tp, 0x1e, 0x002d);
3445 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3446 rtl_writephy(tp, 0x1f, 0x0000);
3447 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3448
3449 rtl_writephy(tp, 0x1f, 0x0005);
3450 rtl_writephy(tp, 0x05, 0x8b86);
3451 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3452 rtl_writephy(tp, 0x1f, 0x0000);
3453
3454 rtl_writephy(tp, 0x1f, 0x0005);
3455 rtl_writephy(tp, 0x05, 0x8b85);
3456 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3457 rtl_writephy(tp, 0x1f, 0x0007);
3458 rtl_writephy(tp, 0x1e, 0x0020);
3459 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3460 rtl_writephy(tp, 0x1f, 0x0006);
3461 rtl_writephy(tp, 0x00, 0x5a00);
3462 rtl_writephy(tp, 0x1f, 0x0000);
3463 rtl_writephy(tp, 0x0d, 0x0007);
3464 rtl_writephy(tp, 0x0e, 0x003c);
3465 rtl_writephy(tp, 0x0d, 0x4007);
3466 rtl_writephy(tp, 0x0e, 0x0000);
3467 rtl_writephy(tp, 0x0d, 0x0000);
3468 }
3469
3470 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3471 {
3472 const u16 w[] = {
3473 addr[0] | (addr[1] << 8),
3474 addr[2] | (addr[3] << 8),
3475 addr[4] | (addr[5] << 8)
3476 };
3477 const struct exgmac_reg e[] = {
3478 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3479 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3480 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3481 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3482 };
3483
3484 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3485 }
3486
3487 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3488 {
3489 static const struct phy_reg phy_reg_init[] = {
3490 /* Enable Delay cap */
3491 { 0x1f, 0x0004 },
3492 { 0x1f, 0x0007 },
3493 { 0x1e, 0x00ac },
3494 { 0x18, 0x0006 },
3495 { 0x1f, 0x0002 },
3496 { 0x1f, 0x0000 },
3497 { 0x1f, 0x0000 },
3498
3499 /* Channel estimation fine tune */
3500 { 0x1f, 0x0003 },
3501 { 0x09, 0xa20f },
3502 { 0x1f, 0x0000 },
3503 { 0x1f, 0x0000 },
3504
3505 /* Green Setting */
3506 { 0x1f, 0x0005 },
3507 { 0x05, 0x8b5b },
3508 { 0x06, 0x9222 },
3509 { 0x05, 0x8b6d },
3510 { 0x06, 0x8000 },
3511 { 0x05, 0x8b76 },
3512 { 0x06, 0x8000 },
3513 { 0x1f, 0x0000 }
3514 };
3515
3516 rtl_apply_firmware(tp);
3517
3518 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3519
3520 /* For 4-corner performance improve */
3521 rtl_writephy(tp, 0x1f, 0x0005);
3522 rtl_writephy(tp, 0x05, 0x8b80);
3523 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3524 rtl_writephy(tp, 0x1f, 0x0000);
3525
3526 /* PHY auto speed down */
3527 rtl_writephy(tp, 0x1f, 0x0004);
3528 rtl_writephy(tp, 0x1f, 0x0007);
3529 rtl_writephy(tp, 0x1e, 0x002d);
3530 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3531 rtl_writephy(tp, 0x1f, 0x0002);
3532 rtl_writephy(tp, 0x1f, 0x0000);
3533 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3534
3535 /* improve 10M EEE waveform */
3536 rtl_writephy(tp, 0x1f, 0x0005);
3537 rtl_writephy(tp, 0x05, 0x8b86);
3538 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3539 rtl_writephy(tp, 0x1f, 0x0000);
3540
3541 /* Improve 2-pair detection performance */
3542 rtl_writephy(tp, 0x1f, 0x0005);
3543 rtl_writephy(tp, 0x05, 0x8b85);
3544 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3545 rtl_writephy(tp, 0x1f, 0x0000);
3546
3547 /* EEE setting */
3548 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
3549 rtl_writephy(tp, 0x1f, 0x0005);
3550 rtl_writephy(tp, 0x05, 0x8b85);
3551 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3552 rtl_writephy(tp, 0x1f, 0x0004);
3553 rtl_writephy(tp, 0x1f, 0x0007);
3554 rtl_writephy(tp, 0x1e, 0x0020);
3555 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3556 rtl_writephy(tp, 0x1f, 0x0002);
3557 rtl_writephy(tp, 0x1f, 0x0000);
3558 rtl_writephy(tp, 0x0d, 0x0007);
3559 rtl_writephy(tp, 0x0e, 0x003c);
3560 rtl_writephy(tp, 0x0d, 0x4007);
3561 rtl_writephy(tp, 0x0e, 0x0000);
3562 rtl_writephy(tp, 0x0d, 0x0000);
3563
3564 /* Green feature */
3565 rtl_writephy(tp, 0x1f, 0x0003);
3566 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3567 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3568 rtl_writephy(tp, 0x1f, 0x0000);
3569
3570 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3571 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3572 }
3573
3574 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3575 {
3576 /* For 4-corner performance improve */
3577 rtl_writephy(tp, 0x1f, 0x0005);
3578 rtl_writephy(tp, 0x05, 0x8b80);
3579 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3580 rtl_writephy(tp, 0x1f, 0x0000);
3581
3582 /* PHY auto speed down */
3583 rtl_writephy(tp, 0x1f, 0x0007);
3584 rtl_writephy(tp, 0x1e, 0x002d);
3585 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3586 rtl_writephy(tp, 0x1f, 0x0000);
3587 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3588
3589 /* Improve 10M EEE waveform */
3590 rtl_writephy(tp, 0x1f, 0x0005);
3591 rtl_writephy(tp, 0x05, 0x8b86);
3592 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3593 rtl_writephy(tp, 0x1f, 0x0000);
3594 }
3595
3596 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3597 {
3598 static const struct phy_reg phy_reg_init[] = {
3599 /* Channel estimation fine tune */
3600 { 0x1f, 0x0003 },
3601 { 0x09, 0xa20f },
3602 { 0x1f, 0x0000 },
3603
3604 /* Modify green table for giga & fnet */
3605 { 0x1f, 0x0005 },
3606 { 0x05, 0x8b55 },
3607 { 0x06, 0x0000 },
3608 { 0x05, 0x8b5e },
3609 { 0x06, 0x0000 },
3610 { 0x05, 0x8b67 },
3611 { 0x06, 0x0000 },
3612 { 0x05, 0x8b70 },
3613 { 0x06, 0x0000 },
3614 { 0x1f, 0x0000 },
3615 { 0x1f, 0x0007 },
3616 { 0x1e, 0x0078 },
3617 { 0x17, 0x0000 },
3618 { 0x19, 0x00fb },
3619 { 0x1f, 0x0000 },
3620
3621 /* Modify green table for 10M */
3622 { 0x1f, 0x0005 },
3623 { 0x05, 0x8b79 },
3624 { 0x06, 0xaa00 },
3625 { 0x1f, 0x0000 },
3626
3627 /* Disable hiimpedance detection (RTCT) */
3628 { 0x1f, 0x0003 },
3629 { 0x01, 0x328a },
3630 { 0x1f, 0x0000 }
3631 };
3632
3633 rtl_apply_firmware(tp);
3634
3635 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3636
3637 rtl8168f_hw_phy_config(tp);
3638
3639 /* Improve 2-pair detection performance */
3640 rtl_writephy(tp, 0x1f, 0x0005);
3641 rtl_writephy(tp, 0x05, 0x8b85);
3642 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3643 rtl_writephy(tp, 0x1f, 0x0000);
3644 }
3645
3646 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3647 {
3648 rtl_apply_firmware(tp);
3649
3650 rtl8168f_hw_phy_config(tp);
3651 }
3652
3653 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3654 {
3655 static const struct phy_reg phy_reg_init[] = {
3656 /* Channel estimation fine tune */
3657 { 0x1f, 0x0003 },
3658 { 0x09, 0xa20f },
3659 { 0x1f, 0x0000 },
3660
3661 /* Modify green table for giga & fnet */
3662 { 0x1f, 0x0005 },
3663 { 0x05, 0x8b55 },
3664 { 0x06, 0x0000 },
3665 { 0x05, 0x8b5e },
3666 { 0x06, 0x0000 },
3667 { 0x05, 0x8b67 },
3668 { 0x06, 0x0000 },
3669 { 0x05, 0x8b70 },
3670 { 0x06, 0x0000 },
3671 { 0x1f, 0x0000 },
3672 { 0x1f, 0x0007 },
3673 { 0x1e, 0x0078 },
3674 { 0x17, 0x0000 },
3675 { 0x19, 0x00aa },
3676 { 0x1f, 0x0000 },
3677
3678 /* Modify green table for 10M */
3679 { 0x1f, 0x0005 },
3680 { 0x05, 0x8b79 },
3681 { 0x06, 0xaa00 },
3682 { 0x1f, 0x0000 },
3683
3684 /* Disable hiimpedance detection (RTCT) */
3685 { 0x1f, 0x0003 },
3686 { 0x01, 0x328a },
3687 { 0x1f, 0x0000 }
3688 };
3689
3690
3691 rtl_apply_firmware(tp);
3692
3693 rtl8168f_hw_phy_config(tp);
3694
3695 /* Improve 2-pair detection performance */
3696 rtl_writephy(tp, 0x1f, 0x0005);
3697 rtl_writephy(tp, 0x05, 0x8b85);
3698 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3699 rtl_writephy(tp, 0x1f, 0x0000);
3700
3701 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3702
3703 /* Modify green table for giga */
3704 rtl_writephy(tp, 0x1f, 0x0005);
3705 rtl_writephy(tp, 0x05, 0x8b54);
3706 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3707 rtl_writephy(tp, 0x05, 0x8b5d);
3708 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3709 rtl_writephy(tp, 0x05, 0x8a7c);
3710 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3711 rtl_writephy(tp, 0x05, 0x8a7f);
3712 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3713 rtl_writephy(tp, 0x05, 0x8a82);
3714 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3715 rtl_writephy(tp, 0x05, 0x8a85);
3716 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3717 rtl_writephy(tp, 0x05, 0x8a88);
3718 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3719 rtl_writephy(tp, 0x1f, 0x0000);
3720
3721 /* uc same-seed solution */
3722 rtl_writephy(tp, 0x1f, 0x0005);
3723 rtl_writephy(tp, 0x05, 0x8b85);
3724 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3725 rtl_writephy(tp, 0x1f, 0x0000);
3726
3727 /* eee setting */
3728 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3729 rtl_writephy(tp, 0x1f, 0x0005);
3730 rtl_writephy(tp, 0x05, 0x8b85);
3731 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3732 rtl_writephy(tp, 0x1f, 0x0004);
3733 rtl_writephy(tp, 0x1f, 0x0007);
3734 rtl_writephy(tp, 0x1e, 0x0020);
3735 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3736 rtl_writephy(tp, 0x1f, 0x0000);
3737 rtl_writephy(tp, 0x0d, 0x0007);
3738 rtl_writephy(tp, 0x0e, 0x003c);
3739 rtl_writephy(tp, 0x0d, 0x4007);
3740 rtl_writephy(tp, 0x0e, 0x0000);
3741 rtl_writephy(tp, 0x0d, 0x0000);
3742
3743 /* Green feature */
3744 rtl_writephy(tp, 0x1f, 0x0003);
3745 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3746 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3747 rtl_writephy(tp, 0x1f, 0x0000);
3748 }
3749
3750 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3751 {
3752 rtl_apply_firmware(tp);
3753
3754 rtl_writephy(tp, 0x1f, 0x0a46);
3755 if (rtl_readphy(tp, 0x10) & 0x0100) {
3756 rtl_writephy(tp, 0x1f, 0x0bcc);
3757 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3758 } else {
3759 rtl_writephy(tp, 0x1f, 0x0bcc);
3760 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3761 }
3762
3763 rtl_writephy(tp, 0x1f, 0x0a46);
3764 if (rtl_readphy(tp, 0x13) & 0x0100) {
3765 rtl_writephy(tp, 0x1f, 0x0c41);
3766 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3767 } else {
3768 rtl_writephy(tp, 0x1f, 0x0c41);
3769 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3770 }
3771
3772 /* Enable PHY auto speed down */
3773 rtl_writephy(tp, 0x1f, 0x0a44);
3774 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3775
3776 rtl_writephy(tp, 0x1f, 0x0bcc);
3777 rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
3778 rtl_writephy(tp, 0x1f, 0x0a44);
3779 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3780 rtl_writephy(tp, 0x1f, 0x0a43);
3781 rtl_writephy(tp, 0x13, 0x8084);
3782 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3783 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3784
3785 /* EEE auto-fallback function */
3786 rtl_writephy(tp, 0x1f, 0x0a4b);
3787 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3788
3789 /* Enable UC LPF tune function */
3790 rtl_writephy(tp, 0x1f, 0x0a43);
3791 rtl_writephy(tp, 0x13, 0x8012);
3792 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3793
3794 rtl_writephy(tp, 0x1f, 0x0c42);
3795 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3796
3797 /* Improve SWR Efficiency */
3798 rtl_writephy(tp, 0x1f, 0x0bcd);
3799 rtl_writephy(tp, 0x14, 0x5065);
3800 rtl_writephy(tp, 0x14, 0xd065);
3801 rtl_writephy(tp, 0x1f, 0x0bc8);
3802 rtl_writephy(tp, 0x11, 0x5655);
3803 rtl_writephy(tp, 0x1f, 0x0bcd);
3804 rtl_writephy(tp, 0x14, 0x1065);
3805 rtl_writephy(tp, 0x14, 0x9065);
3806 rtl_writephy(tp, 0x14, 0x1065);
3807
3808 /* Check ALDPS bit, disable it if enabled */
3809 rtl_writephy(tp, 0x1f, 0x0a43);
3810 if (rtl_readphy(tp, 0x10) & 0x0004)
3811 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3812
3813 rtl_writephy(tp, 0x1f, 0x0000);
3814 }
3815
3816 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3817 {
3818 rtl_apply_firmware(tp);
3819 }
3820
3821 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3822 {
3823 u16 dout_tapbin;
3824 u32 data;
3825
3826 rtl_apply_firmware(tp);
3827
3828 /* CHN EST parameters adjust - giga master */
3829 rtl_writephy(tp, 0x1f, 0x0a43);
3830 rtl_writephy(tp, 0x13, 0x809b);
3831 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3832 rtl_writephy(tp, 0x13, 0x80a2);
3833 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3834 rtl_writephy(tp, 0x13, 0x80a4);
3835 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3836 rtl_writephy(tp, 0x13, 0x809c);
3837 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3838 rtl_writephy(tp, 0x1f, 0x0000);
3839
3840 /* CHN EST parameters adjust - giga slave */
3841 rtl_writephy(tp, 0x1f, 0x0a43);
3842 rtl_writephy(tp, 0x13, 0x80ad);
3843 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3844 rtl_writephy(tp, 0x13, 0x80b4);
3845 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3846 rtl_writephy(tp, 0x13, 0x80ac);
3847 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3848 rtl_writephy(tp, 0x1f, 0x0000);
3849
3850 /* CHN EST parameters adjust - fnet */
3851 rtl_writephy(tp, 0x1f, 0x0a43);
3852 rtl_writephy(tp, 0x13, 0x808e);
3853 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3854 rtl_writephy(tp, 0x13, 0x8090);
3855 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3856 rtl_writephy(tp, 0x13, 0x8092);
3857 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3858 rtl_writephy(tp, 0x1f, 0x0000);
3859
3860 /* enable R-tune & PGA-retune function */
3861 dout_tapbin = 0;
3862 rtl_writephy(tp, 0x1f, 0x0a46);
3863 data = rtl_readphy(tp, 0x13);
3864 data &= 3;
3865 data <<= 2;
3866 dout_tapbin |= data;
3867 data = rtl_readphy(tp, 0x12);
3868 data &= 0xc000;
3869 data >>= 14;
3870 dout_tapbin |= data;
3871 dout_tapbin = ~(dout_tapbin^0x08);
3872 dout_tapbin <<= 12;
3873 dout_tapbin &= 0xf000;
3874 rtl_writephy(tp, 0x1f, 0x0a43);
3875 rtl_writephy(tp, 0x13, 0x827a);
3876 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3877 rtl_writephy(tp, 0x13, 0x827b);
3878 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3879 rtl_writephy(tp, 0x13, 0x827c);
3880 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3881 rtl_writephy(tp, 0x13, 0x827d);
3882 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3883
3884 rtl_writephy(tp, 0x1f, 0x0a43);
3885 rtl_writephy(tp, 0x13, 0x0811);
3886 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3887 rtl_writephy(tp, 0x1f, 0x0a42);
3888 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3889 rtl_writephy(tp, 0x1f, 0x0000);
3890
3891 /* enable GPHY 10M */
3892 rtl_writephy(tp, 0x1f, 0x0a44);
3893 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3894 rtl_writephy(tp, 0x1f, 0x0000);
3895
3896 /* SAR ADC performance */
3897 rtl_writephy(tp, 0x1f, 0x0bca);
3898 rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3899 rtl_writephy(tp, 0x1f, 0x0000);
3900
3901 rtl_writephy(tp, 0x1f, 0x0a43);
3902 rtl_writephy(tp, 0x13, 0x803f);
3903 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3904 rtl_writephy(tp, 0x13, 0x8047);
3905 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3906 rtl_writephy(tp, 0x13, 0x804f);
3907 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3908 rtl_writephy(tp, 0x13, 0x8057);
3909 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3910 rtl_writephy(tp, 0x13, 0x805f);
3911 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3912 rtl_writephy(tp, 0x13, 0x8067);
3913 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3914 rtl_writephy(tp, 0x13, 0x806f);
3915 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3916 rtl_writephy(tp, 0x1f, 0x0000);
3917
3918 /* disable phy pfm mode */
3919 rtl_writephy(tp, 0x1f, 0x0a44);
3920 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3921 rtl_writephy(tp, 0x1f, 0x0000);
3922
3923 /* Check ALDPS bit, disable it if enabled */
3924 rtl_writephy(tp, 0x1f, 0x0a43);
3925 if (rtl_readphy(tp, 0x10) & 0x0004)
3926 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3927
3928 rtl_writephy(tp, 0x1f, 0x0000);
3929 }
3930
3931 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3932 {
3933 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3934 u16 rlen;
3935 u32 data;
3936
3937 rtl_apply_firmware(tp);
3938
3939 /* CHIN EST parameter update */
3940 rtl_writephy(tp, 0x1f, 0x0a43);
3941 rtl_writephy(tp, 0x13, 0x808a);
3942 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3943 rtl_writephy(tp, 0x1f, 0x0000);
3944
3945 /* enable R-tune & PGA-retune function */
3946 rtl_writephy(tp, 0x1f, 0x0a43);
3947 rtl_writephy(tp, 0x13, 0x0811);
3948 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3949 rtl_writephy(tp, 0x1f, 0x0a42);
3950 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3951 rtl_writephy(tp, 0x1f, 0x0000);
3952
3953 /* enable GPHY 10M */
3954 rtl_writephy(tp, 0x1f, 0x0a44);
3955 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3956 rtl_writephy(tp, 0x1f, 0x0000);
3957
3958 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3959 data = r8168_mac_ocp_read(tp, 0xdd02);
3960 ioffset_p3 = ((data & 0x80)>>7);
3961 ioffset_p3 <<= 3;
3962
3963 data = r8168_mac_ocp_read(tp, 0xdd00);
3964 ioffset_p3 |= ((data & (0xe000))>>13);
3965 ioffset_p2 = ((data & (0x1e00))>>9);
3966 ioffset_p1 = ((data & (0x01e0))>>5);
3967 ioffset_p0 = ((data & 0x0010)>>4);
3968 ioffset_p0 <<= 3;
3969 ioffset_p0 |= (data & (0x07));
3970 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3971
3972 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3973 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3974 rtl_writephy(tp, 0x1f, 0x0bcf);
3975 rtl_writephy(tp, 0x16, data);
3976 rtl_writephy(tp, 0x1f, 0x0000);
3977 }
3978
3979 /* Modify rlen (TX LPF corner frequency) level */
3980 rtl_writephy(tp, 0x1f, 0x0bcd);
3981 data = rtl_readphy(tp, 0x16);
3982 data &= 0x000f;
3983 rlen = 0;
3984 if (data > 3)
3985 rlen = data - 3;
3986 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3987 rtl_writephy(tp, 0x17, data);
3988 rtl_writephy(tp, 0x1f, 0x0bcd);
3989 rtl_writephy(tp, 0x1f, 0x0000);
3990
3991 /* disable phy pfm mode */
3992 rtl_writephy(tp, 0x1f, 0x0a44);
3993 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3994 rtl_writephy(tp, 0x1f, 0x0000);
3995
3996 /* Check ALDPS bit, disable it if enabled */
3997 rtl_writephy(tp, 0x1f, 0x0a43);
3998 if (rtl_readphy(tp, 0x10) & 0x0004)
3999 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4000
4001 rtl_writephy(tp, 0x1f, 0x0000);
4002 }
4003
4004 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
4005 {
4006 /* Enable PHY auto speed down */
4007 rtl_writephy(tp, 0x1f, 0x0a44);
4008 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
4009 rtl_writephy(tp, 0x1f, 0x0000);
4010
4011 /* patch 10M & ALDPS */
4012 rtl_writephy(tp, 0x1f, 0x0bcc);
4013 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4014 rtl_writephy(tp, 0x1f, 0x0a44);
4015 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4016 rtl_writephy(tp, 0x1f, 0x0a43);
4017 rtl_writephy(tp, 0x13, 0x8084);
4018 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4019 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4020 rtl_writephy(tp, 0x1f, 0x0000);
4021
4022 /* Enable EEE auto-fallback function */
4023 rtl_writephy(tp, 0x1f, 0x0a4b);
4024 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
4025 rtl_writephy(tp, 0x1f, 0x0000);
4026
4027 /* Enable UC LPF tune function */
4028 rtl_writephy(tp, 0x1f, 0x0a43);
4029 rtl_writephy(tp, 0x13, 0x8012);
4030 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4031 rtl_writephy(tp, 0x1f, 0x0000);
4032
4033 /* set rg_sel_sdm_rate */
4034 rtl_writephy(tp, 0x1f, 0x0c42);
4035 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4036 rtl_writephy(tp, 0x1f, 0x0000);
4037
4038 /* Check ALDPS bit, disable it if enabled */
4039 rtl_writephy(tp, 0x1f, 0x0a43);
4040 if (rtl_readphy(tp, 0x10) & 0x0004)
4041 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4042
4043 rtl_writephy(tp, 0x1f, 0x0000);
4044 }
4045
4046 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
4047 {
4048 /* patch 10M & ALDPS */
4049 rtl_writephy(tp, 0x1f, 0x0bcc);
4050 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4051 rtl_writephy(tp, 0x1f, 0x0a44);
4052 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4053 rtl_writephy(tp, 0x1f, 0x0a43);
4054 rtl_writephy(tp, 0x13, 0x8084);
4055 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4056 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4057 rtl_writephy(tp, 0x1f, 0x0000);
4058
4059 /* Enable UC LPF tune function */
4060 rtl_writephy(tp, 0x1f, 0x0a43);
4061 rtl_writephy(tp, 0x13, 0x8012);
4062 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4063 rtl_writephy(tp, 0x1f, 0x0000);
4064
4065 /* Set rg_sel_sdm_rate */
4066 rtl_writephy(tp, 0x1f, 0x0c42);
4067 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4068 rtl_writephy(tp, 0x1f, 0x0000);
4069
4070 /* Channel estimation parameters */
4071 rtl_writephy(tp, 0x1f, 0x0a43);
4072 rtl_writephy(tp, 0x13, 0x80f3);
4073 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
4074 rtl_writephy(tp, 0x13, 0x80f0);
4075 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
4076 rtl_writephy(tp, 0x13, 0x80ef);
4077 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
4078 rtl_writephy(tp, 0x13, 0x80f6);
4079 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
4080 rtl_writephy(tp, 0x13, 0x80ec);
4081 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
4082 rtl_writephy(tp, 0x13, 0x80ed);
4083 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4084 rtl_writephy(tp, 0x13, 0x80f2);
4085 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
4086 rtl_writephy(tp, 0x13, 0x80f4);
4087 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
4088 rtl_writephy(tp, 0x1f, 0x0a43);
4089 rtl_writephy(tp, 0x13, 0x8110);
4090 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
4091 rtl_writephy(tp, 0x13, 0x810f);
4092 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
4093 rtl_writephy(tp, 0x13, 0x8111);
4094 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
4095 rtl_writephy(tp, 0x13, 0x8113);
4096 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
4097 rtl_writephy(tp, 0x13, 0x8115);
4098 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
4099 rtl_writephy(tp, 0x13, 0x810e);
4100 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
4101 rtl_writephy(tp, 0x13, 0x810c);
4102 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4103 rtl_writephy(tp, 0x13, 0x810b);
4104 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
4105 rtl_writephy(tp, 0x1f, 0x0a43);
4106 rtl_writephy(tp, 0x13, 0x80d1);
4107 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
4108 rtl_writephy(tp, 0x13, 0x80cd);
4109 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
4110 rtl_writephy(tp, 0x13, 0x80d3);
4111 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
4112 rtl_writephy(tp, 0x13, 0x80d5);
4113 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
4114 rtl_writephy(tp, 0x13, 0x80d7);
4115 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
4116
4117 /* Force PWM-mode */
4118 rtl_writephy(tp, 0x1f, 0x0bcd);
4119 rtl_writephy(tp, 0x14, 0x5065);
4120 rtl_writephy(tp, 0x14, 0xd065);
4121 rtl_writephy(tp, 0x1f, 0x0bc8);
4122 rtl_writephy(tp, 0x12, 0x00ed);
4123 rtl_writephy(tp, 0x1f, 0x0bcd);
4124 rtl_writephy(tp, 0x14, 0x1065);
4125 rtl_writephy(tp, 0x14, 0x9065);
4126 rtl_writephy(tp, 0x14, 0x1065);
4127 rtl_writephy(tp, 0x1f, 0x0000);
4128
4129 /* Check ALDPS bit, disable it if enabled */
4130 rtl_writephy(tp, 0x1f, 0x0a43);
4131 if (rtl_readphy(tp, 0x10) & 0x0004)
4132 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4133
4134 rtl_writephy(tp, 0x1f, 0x0000);
4135 }
4136
4137 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
4138 {
4139 static const struct phy_reg phy_reg_init[] = {
4140 { 0x1f, 0x0003 },
4141 { 0x08, 0x441d },
4142 { 0x01, 0x9100 },
4143 { 0x1f, 0x0000 }
4144 };
4145
4146 rtl_writephy(tp, 0x1f, 0x0000);
4147 rtl_patchphy(tp, 0x11, 1 << 12);
4148 rtl_patchphy(tp, 0x19, 1 << 13);
4149 rtl_patchphy(tp, 0x10, 1 << 15);
4150
4151 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4152 }
4153
4154 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
4155 {
4156 static const struct phy_reg phy_reg_init[] = {
4157 { 0x1f, 0x0005 },
4158 { 0x1a, 0x0000 },
4159 { 0x1f, 0x0000 },
4160
4161 { 0x1f, 0x0004 },
4162 { 0x1c, 0x0000 },
4163 { 0x1f, 0x0000 },
4164
4165 { 0x1f, 0x0001 },
4166 { 0x15, 0x7701 },
4167 { 0x1f, 0x0000 }
4168 };
4169
4170 /* Disable ALDPS before ram code */
4171 rtl_writephy(tp, 0x1f, 0x0000);
4172 rtl_writephy(tp, 0x18, 0x0310);
4173 msleep(100);
4174
4175 rtl_apply_firmware(tp);
4176
4177 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4178 }
4179
4180 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
4181 {
4182 /* Disable ALDPS before setting firmware */
4183 rtl_writephy(tp, 0x1f, 0x0000);
4184 rtl_writephy(tp, 0x18, 0x0310);
4185 msleep(20);
4186
4187 rtl_apply_firmware(tp);
4188
4189 /* EEE setting */
4190 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4191 rtl_writephy(tp, 0x1f, 0x0004);
4192 rtl_writephy(tp, 0x10, 0x401f);
4193 rtl_writephy(tp, 0x19, 0x7030);
4194 rtl_writephy(tp, 0x1f, 0x0000);
4195 }
4196
4197 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
4198 {
4199 static const struct phy_reg phy_reg_init[] = {
4200 { 0x1f, 0x0004 },
4201 { 0x10, 0xc07f },
4202 { 0x19, 0x7030 },
4203 { 0x1f, 0x0000 }
4204 };
4205
4206 /* Disable ALDPS before ram code */
4207 rtl_writephy(tp, 0x1f, 0x0000);
4208 rtl_writephy(tp, 0x18, 0x0310);
4209 msleep(100);
4210
4211 rtl_apply_firmware(tp);
4212
4213 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4214 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4215
4216 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4217 }
4218
4219 static void rtl_hw_phy_config(struct net_device *dev)
4220 {
4221 struct rtl8169_private *tp = netdev_priv(dev);
4222
4223 rtl8169_print_mac_version(tp);
4224
4225 switch (tp->mac_version) {
4226 case RTL_GIGA_MAC_VER_01:
4227 break;
4228 case RTL_GIGA_MAC_VER_02:
4229 case RTL_GIGA_MAC_VER_03:
4230 rtl8169s_hw_phy_config(tp);
4231 break;
4232 case RTL_GIGA_MAC_VER_04:
4233 rtl8169sb_hw_phy_config(tp);
4234 break;
4235 case RTL_GIGA_MAC_VER_05:
4236 rtl8169scd_hw_phy_config(tp);
4237 break;
4238 case RTL_GIGA_MAC_VER_06:
4239 rtl8169sce_hw_phy_config(tp);
4240 break;
4241 case RTL_GIGA_MAC_VER_07:
4242 case RTL_GIGA_MAC_VER_08:
4243 case RTL_GIGA_MAC_VER_09:
4244 rtl8102e_hw_phy_config(tp);
4245 break;
4246 case RTL_GIGA_MAC_VER_11:
4247 rtl8168bb_hw_phy_config(tp);
4248 break;
4249 case RTL_GIGA_MAC_VER_12:
4250 rtl8168bef_hw_phy_config(tp);
4251 break;
4252 case RTL_GIGA_MAC_VER_17:
4253 rtl8168bef_hw_phy_config(tp);
4254 break;
4255 case RTL_GIGA_MAC_VER_18:
4256 rtl8168cp_1_hw_phy_config(tp);
4257 break;
4258 case RTL_GIGA_MAC_VER_19:
4259 rtl8168c_1_hw_phy_config(tp);
4260 break;
4261 case RTL_GIGA_MAC_VER_20:
4262 rtl8168c_2_hw_phy_config(tp);
4263 break;
4264 case RTL_GIGA_MAC_VER_21:
4265 rtl8168c_3_hw_phy_config(tp);
4266 break;
4267 case RTL_GIGA_MAC_VER_22:
4268 rtl8168c_4_hw_phy_config(tp);
4269 break;
4270 case RTL_GIGA_MAC_VER_23:
4271 case RTL_GIGA_MAC_VER_24:
4272 rtl8168cp_2_hw_phy_config(tp);
4273 break;
4274 case RTL_GIGA_MAC_VER_25:
4275 rtl8168d_1_hw_phy_config(tp);
4276 break;
4277 case RTL_GIGA_MAC_VER_26:
4278 rtl8168d_2_hw_phy_config(tp);
4279 break;
4280 case RTL_GIGA_MAC_VER_27:
4281 rtl8168d_3_hw_phy_config(tp);
4282 break;
4283 case RTL_GIGA_MAC_VER_28:
4284 rtl8168d_4_hw_phy_config(tp);
4285 break;
4286 case RTL_GIGA_MAC_VER_29:
4287 case RTL_GIGA_MAC_VER_30:
4288 rtl8105e_hw_phy_config(tp);
4289 break;
4290 case RTL_GIGA_MAC_VER_31:
4291 /* None. */
4292 break;
4293 case RTL_GIGA_MAC_VER_32:
4294 case RTL_GIGA_MAC_VER_33:
4295 rtl8168e_1_hw_phy_config(tp);
4296 break;
4297 case RTL_GIGA_MAC_VER_34:
4298 rtl8168e_2_hw_phy_config(tp);
4299 break;
4300 case RTL_GIGA_MAC_VER_35:
4301 rtl8168f_1_hw_phy_config(tp);
4302 break;
4303 case RTL_GIGA_MAC_VER_36:
4304 rtl8168f_2_hw_phy_config(tp);
4305 break;
4306
4307 case RTL_GIGA_MAC_VER_37:
4308 rtl8402_hw_phy_config(tp);
4309 break;
4310
4311 case RTL_GIGA_MAC_VER_38:
4312 rtl8411_hw_phy_config(tp);
4313 break;
4314
4315 case RTL_GIGA_MAC_VER_39:
4316 rtl8106e_hw_phy_config(tp);
4317 break;
4318
4319 case RTL_GIGA_MAC_VER_40:
4320 rtl8168g_1_hw_phy_config(tp);
4321 break;
4322 case RTL_GIGA_MAC_VER_42:
4323 case RTL_GIGA_MAC_VER_43:
4324 case RTL_GIGA_MAC_VER_44:
4325 rtl8168g_2_hw_phy_config(tp);
4326 break;
4327 case RTL_GIGA_MAC_VER_45:
4328 case RTL_GIGA_MAC_VER_47:
4329 rtl8168h_1_hw_phy_config(tp);
4330 break;
4331 case RTL_GIGA_MAC_VER_46:
4332 case RTL_GIGA_MAC_VER_48:
4333 rtl8168h_2_hw_phy_config(tp);
4334 break;
4335
4336 case RTL_GIGA_MAC_VER_49:
4337 rtl8168ep_1_hw_phy_config(tp);
4338 break;
4339 case RTL_GIGA_MAC_VER_50:
4340 case RTL_GIGA_MAC_VER_51:
4341 rtl8168ep_2_hw_phy_config(tp);
4342 break;
4343
4344 case RTL_GIGA_MAC_VER_41:
4345 default:
4346 break;
4347 }
4348 }
4349
4350 static void rtl_phy_work(struct rtl8169_private *tp)
4351 {
4352 struct timer_list *timer = &tp->timer;
4353 void __iomem *ioaddr = tp->mmio_addr;
4354 unsigned long timeout = RTL8169_PHY_TIMEOUT;
4355
4356 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
4357
4358 if (tp->phy_reset_pending(tp)) {
4359 /*
4360 * A busy loop could burn quite a few cycles on nowadays CPU.
4361 * Let's delay the execution of the timer for a few ticks.
4362 */
4363 timeout = HZ/10;
4364 goto out_mod_timer;
4365 }
4366
4367 if (tp->link_ok(ioaddr))
4368 return;
4369
4370 netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
4371
4372 tp->phy_reset_enable(tp);
4373
4374 out_mod_timer:
4375 mod_timer(timer, jiffies + timeout);
4376 }
4377
4378 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4379 {
4380 if (!test_and_set_bit(flag, tp->wk.flags))
4381 schedule_work(&tp->wk.work);
4382 }
4383
4384 static void rtl8169_phy_timer(unsigned long __opaque)
4385 {
4386 struct net_device *dev = (struct net_device *)__opaque;
4387 struct rtl8169_private *tp = netdev_priv(dev);
4388
4389 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
4390 }
4391
4392 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
4393 void __iomem *ioaddr)
4394 {
4395 iounmap(ioaddr);
4396 pci_release_regions(pdev);
4397 pci_clear_mwi(pdev);
4398 pci_disable_device(pdev);
4399 free_netdev(dev);
4400 }
4401
4402 DECLARE_RTL_COND(rtl_phy_reset_cond)
4403 {
4404 return tp->phy_reset_pending(tp);
4405 }
4406
4407 static void rtl8169_phy_reset(struct net_device *dev,
4408 struct rtl8169_private *tp)
4409 {
4410 tp->phy_reset_enable(tp);
4411 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
4412 }
4413
4414 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4415 {
4416 void __iomem *ioaddr = tp->mmio_addr;
4417
4418 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4419 (RTL_R8(PHYstatus) & TBI_Enable);
4420 }
4421
4422 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4423 {
4424 void __iomem *ioaddr = tp->mmio_addr;
4425
4426 rtl_hw_phy_config(dev);
4427
4428 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4429 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4430 RTL_W8(0x82, 0x01);
4431 }
4432
4433 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4434
4435 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4436 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4437
4438 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4439 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4440 RTL_W8(0x82, 0x01);
4441 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4442 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4443 }
4444
4445 rtl8169_phy_reset(dev, tp);
4446
4447 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4448 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4449 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4450 (tp->mii.supports_gmii ?
4451 ADVERTISED_1000baseT_Half |
4452 ADVERTISED_1000baseT_Full : 0));
4453
4454 if (rtl_tbi_enabled(tp))
4455 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4456 }
4457
4458 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4459 {
4460 void __iomem *ioaddr = tp->mmio_addr;
4461
4462 rtl_lock_work(tp);
4463
4464 RTL_W8(Cfg9346, Cfg9346_Unlock);
4465
4466 RTL_W32(MAC4, addr[4] | addr[5] << 8);
4467 RTL_R32(MAC4);
4468
4469 RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4470 RTL_R32(MAC0);
4471
4472 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4473 rtl_rar_exgmac_set(tp, addr);
4474
4475 RTL_W8(Cfg9346, Cfg9346_Lock);
4476
4477 rtl_unlock_work(tp);
4478 }
4479
4480 static int rtl_set_mac_address(struct net_device *dev, void *p)
4481 {
4482 struct rtl8169_private *tp = netdev_priv(dev);
4483 struct device *d = &tp->pci_dev->dev;
4484 struct sockaddr *addr = p;
4485
4486 if (!is_valid_ether_addr(addr->sa_data))
4487 return -EADDRNOTAVAIL;
4488
4489 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4490
4491 pm_runtime_get_noresume(d);
4492
4493 if (pm_runtime_active(d))
4494 rtl_rar_set(tp, dev->dev_addr);
4495
4496 pm_runtime_put_noidle(d);
4497
4498 return 0;
4499 }
4500
4501 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4502 {
4503 struct rtl8169_private *tp = netdev_priv(dev);
4504 struct mii_ioctl_data *data = if_mii(ifr);
4505
4506 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
4507 }
4508
4509 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
4510 struct mii_ioctl_data *data, int cmd)
4511 {
4512 switch (cmd) {
4513 case SIOCGMIIPHY:
4514 data->phy_id = 32; /* Internal PHY */
4515 return 0;
4516
4517 case SIOCGMIIREG:
4518 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
4519 return 0;
4520
4521 case SIOCSMIIREG:
4522 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
4523 return 0;
4524 }
4525 return -EOPNOTSUPP;
4526 }
4527
4528 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
4529 {
4530 return -EOPNOTSUPP;
4531 }
4532
4533 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
4534 {
4535 if (tp->features & RTL_FEATURE_MSI) {
4536 pci_disable_msi(pdev);
4537 tp->features &= ~RTL_FEATURE_MSI;
4538 }
4539 }
4540
4541 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4542 {
4543 struct mdio_ops *ops = &tp->mdio_ops;
4544
4545 switch (tp->mac_version) {
4546 case RTL_GIGA_MAC_VER_27:
4547 ops->write = r8168dp_1_mdio_write;
4548 ops->read = r8168dp_1_mdio_read;
4549 break;
4550 case RTL_GIGA_MAC_VER_28:
4551 case RTL_GIGA_MAC_VER_31:
4552 ops->write = r8168dp_2_mdio_write;
4553 ops->read = r8168dp_2_mdio_read;
4554 break;
4555 case RTL_GIGA_MAC_VER_40:
4556 case RTL_GIGA_MAC_VER_41:
4557 case RTL_GIGA_MAC_VER_42:
4558 case RTL_GIGA_MAC_VER_43:
4559 case RTL_GIGA_MAC_VER_44:
4560 case RTL_GIGA_MAC_VER_45:
4561 case RTL_GIGA_MAC_VER_46:
4562 case RTL_GIGA_MAC_VER_47:
4563 case RTL_GIGA_MAC_VER_48:
4564 case RTL_GIGA_MAC_VER_49:
4565 case RTL_GIGA_MAC_VER_50:
4566 case RTL_GIGA_MAC_VER_51:
4567 ops->write = r8168g_mdio_write;
4568 ops->read = r8168g_mdio_read;
4569 break;
4570 default:
4571 ops->write = r8169_mdio_write;
4572 ops->read = r8169_mdio_read;
4573 break;
4574 }
4575 }
4576
4577 static void rtl_speed_down(struct rtl8169_private *tp)
4578 {
4579 u32 adv;
4580 int lpa;
4581
4582 rtl_writephy(tp, 0x1f, 0x0000);
4583 lpa = rtl_readphy(tp, MII_LPA);
4584
4585 if (lpa & (LPA_10HALF | LPA_10FULL))
4586 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
4587 else if (lpa & (LPA_100HALF | LPA_100FULL))
4588 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4589 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4590 else
4591 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4592 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4593 (tp->mii.supports_gmii ?
4594 ADVERTISED_1000baseT_Half |
4595 ADVERTISED_1000baseT_Full : 0);
4596
4597 rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4598 adv);
4599 }
4600
4601 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4602 {
4603 void __iomem *ioaddr = tp->mmio_addr;
4604
4605 switch (tp->mac_version) {
4606 case RTL_GIGA_MAC_VER_25:
4607 case RTL_GIGA_MAC_VER_26:
4608 case RTL_GIGA_MAC_VER_29:
4609 case RTL_GIGA_MAC_VER_30:
4610 case RTL_GIGA_MAC_VER_32:
4611 case RTL_GIGA_MAC_VER_33:
4612 case RTL_GIGA_MAC_VER_34:
4613 case RTL_GIGA_MAC_VER_37:
4614 case RTL_GIGA_MAC_VER_38:
4615 case RTL_GIGA_MAC_VER_39:
4616 case RTL_GIGA_MAC_VER_40:
4617 case RTL_GIGA_MAC_VER_41:
4618 case RTL_GIGA_MAC_VER_42:
4619 case RTL_GIGA_MAC_VER_43:
4620 case RTL_GIGA_MAC_VER_44:
4621 case RTL_GIGA_MAC_VER_45:
4622 case RTL_GIGA_MAC_VER_46:
4623 case RTL_GIGA_MAC_VER_47:
4624 case RTL_GIGA_MAC_VER_48:
4625 case RTL_GIGA_MAC_VER_49:
4626 case RTL_GIGA_MAC_VER_50:
4627 case RTL_GIGA_MAC_VER_51:
4628 RTL_W32(RxConfig, RTL_R32(RxConfig) |
4629 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4630 break;
4631 default:
4632 break;
4633 }
4634 }
4635
4636 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4637 {
4638 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
4639 return false;
4640
4641 rtl_speed_down(tp);
4642 rtl_wol_suspend_quirk(tp);
4643
4644 return true;
4645 }
4646
4647 static void r810x_phy_power_down(struct rtl8169_private *tp)
4648 {
4649 rtl_writephy(tp, 0x1f, 0x0000);
4650 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4651 }
4652
4653 static void r810x_phy_power_up(struct rtl8169_private *tp)
4654 {
4655 rtl_writephy(tp, 0x1f, 0x0000);
4656 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4657 }
4658
4659 static void r810x_pll_power_down(struct rtl8169_private *tp)
4660 {
4661 void __iomem *ioaddr = tp->mmio_addr;
4662
4663 if (rtl_wol_pll_power_down(tp))
4664 return;
4665
4666 r810x_phy_power_down(tp);
4667
4668 switch (tp->mac_version) {
4669 case RTL_GIGA_MAC_VER_07:
4670 case RTL_GIGA_MAC_VER_08:
4671 case RTL_GIGA_MAC_VER_09:
4672 case RTL_GIGA_MAC_VER_10:
4673 case RTL_GIGA_MAC_VER_13:
4674 case RTL_GIGA_MAC_VER_16:
4675 break;
4676 default:
4677 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4678 break;
4679 }
4680 }
4681
4682 static void r810x_pll_power_up(struct rtl8169_private *tp)
4683 {
4684 void __iomem *ioaddr = tp->mmio_addr;
4685
4686 r810x_phy_power_up(tp);
4687
4688 switch (tp->mac_version) {
4689 case RTL_GIGA_MAC_VER_07:
4690 case RTL_GIGA_MAC_VER_08:
4691 case RTL_GIGA_MAC_VER_09:
4692 case RTL_GIGA_MAC_VER_10:
4693 case RTL_GIGA_MAC_VER_13:
4694 case RTL_GIGA_MAC_VER_16:
4695 break;
4696 case RTL_GIGA_MAC_VER_47:
4697 case RTL_GIGA_MAC_VER_48:
4698 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4699 break;
4700 default:
4701 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4702 break;
4703 }
4704 }
4705
4706 static void r8168_phy_power_up(struct rtl8169_private *tp)
4707 {
4708 rtl_writephy(tp, 0x1f, 0x0000);
4709 switch (tp->mac_version) {
4710 case RTL_GIGA_MAC_VER_11:
4711 case RTL_GIGA_MAC_VER_12:
4712 case RTL_GIGA_MAC_VER_17:
4713 case RTL_GIGA_MAC_VER_18:
4714 case RTL_GIGA_MAC_VER_19:
4715 case RTL_GIGA_MAC_VER_20:
4716 case RTL_GIGA_MAC_VER_21:
4717 case RTL_GIGA_MAC_VER_22:
4718 case RTL_GIGA_MAC_VER_23:
4719 case RTL_GIGA_MAC_VER_24:
4720 case RTL_GIGA_MAC_VER_25:
4721 case RTL_GIGA_MAC_VER_26:
4722 case RTL_GIGA_MAC_VER_27:
4723 case RTL_GIGA_MAC_VER_28:
4724 case RTL_GIGA_MAC_VER_31:
4725 rtl_writephy(tp, 0x0e, 0x0000);
4726 break;
4727 default:
4728 break;
4729 }
4730 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4731 }
4732
4733 static void r8168_phy_power_down(struct rtl8169_private *tp)
4734 {
4735 rtl_writephy(tp, 0x1f, 0x0000);
4736 switch (tp->mac_version) {
4737 case RTL_GIGA_MAC_VER_32:
4738 case RTL_GIGA_MAC_VER_33:
4739 case RTL_GIGA_MAC_VER_40:
4740 case RTL_GIGA_MAC_VER_41:
4741 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4742 break;
4743
4744 case RTL_GIGA_MAC_VER_11:
4745 case RTL_GIGA_MAC_VER_12:
4746 case RTL_GIGA_MAC_VER_17:
4747 case RTL_GIGA_MAC_VER_18:
4748 case RTL_GIGA_MAC_VER_19:
4749 case RTL_GIGA_MAC_VER_20:
4750 case RTL_GIGA_MAC_VER_21:
4751 case RTL_GIGA_MAC_VER_22:
4752 case RTL_GIGA_MAC_VER_23:
4753 case RTL_GIGA_MAC_VER_24:
4754 case RTL_GIGA_MAC_VER_25:
4755 case RTL_GIGA_MAC_VER_26:
4756 case RTL_GIGA_MAC_VER_27:
4757 case RTL_GIGA_MAC_VER_28:
4758 case RTL_GIGA_MAC_VER_31:
4759 rtl_writephy(tp, 0x0e, 0x0200);
4760 default:
4761 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4762 break;
4763 }
4764 }
4765
4766 static void r8168_pll_power_down(struct rtl8169_private *tp)
4767 {
4768 void __iomem *ioaddr = tp->mmio_addr;
4769
4770 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4771 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4772 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
4773 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
4774 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
4775 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
4776 r8168_check_dash(tp)) {
4777 return;
4778 }
4779
4780 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4781 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
4782 (RTL_R16(CPlusCmd) & ASF)) {
4783 return;
4784 }
4785
4786 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4787 tp->mac_version == RTL_GIGA_MAC_VER_33)
4788 rtl_ephy_write(tp, 0x19, 0xff64);
4789
4790 if (rtl_wol_pll_power_down(tp))
4791 return;
4792
4793 r8168_phy_power_down(tp);
4794
4795 switch (tp->mac_version) {
4796 case RTL_GIGA_MAC_VER_25:
4797 case RTL_GIGA_MAC_VER_26:
4798 case RTL_GIGA_MAC_VER_27:
4799 case RTL_GIGA_MAC_VER_28:
4800 case RTL_GIGA_MAC_VER_31:
4801 case RTL_GIGA_MAC_VER_32:
4802 case RTL_GIGA_MAC_VER_33:
4803 case RTL_GIGA_MAC_VER_44:
4804 case RTL_GIGA_MAC_VER_45:
4805 case RTL_GIGA_MAC_VER_46:
4806 case RTL_GIGA_MAC_VER_50:
4807 case RTL_GIGA_MAC_VER_51:
4808 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4809 break;
4810 case RTL_GIGA_MAC_VER_40:
4811 case RTL_GIGA_MAC_VER_41:
4812 case RTL_GIGA_MAC_VER_49:
4813 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4814 0xfc000000, ERIAR_EXGMAC);
4815 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4816 break;
4817 }
4818 }
4819
4820 static void r8168_pll_power_up(struct rtl8169_private *tp)
4821 {
4822 void __iomem *ioaddr = tp->mmio_addr;
4823
4824 switch (tp->mac_version) {
4825 case RTL_GIGA_MAC_VER_25:
4826 case RTL_GIGA_MAC_VER_26:
4827 case RTL_GIGA_MAC_VER_27:
4828 case RTL_GIGA_MAC_VER_28:
4829 case RTL_GIGA_MAC_VER_31:
4830 case RTL_GIGA_MAC_VER_32:
4831 case RTL_GIGA_MAC_VER_33:
4832 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4833 break;
4834 case RTL_GIGA_MAC_VER_44:
4835 case RTL_GIGA_MAC_VER_45:
4836 case RTL_GIGA_MAC_VER_46:
4837 case RTL_GIGA_MAC_VER_50:
4838 case RTL_GIGA_MAC_VER_51:
4839 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4840 break;
4841 case RTL_GIGA_MAC_VER_40:
4842 case RTL_GIGA_MAC_VER_41:
4843 case RTL_GIGA_MAC_VER_49:
4844 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4845 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4846 0x00000000, ERIAR_EXGMAC);
4847 break;
4848 }
4849
4850 r8168_phy_power_up(tp);
4851 }
4852
4853 static void rtl_generic_op(struct rtl8169_private *tp,
4854 void (*op)(struct rtl8169_private *))
4855 {
4856 if (op)
4857 op(tp);
4858 }
4859
4860 static void rtl_pll_power_down(struct rtl8169_private *tp)
4861 {
4862 rtl_generic_op(tp, tp->pll_power_ops.down);
4863 }
4864
4865 static void rtl_pll_power_up(struct rtl8169_private *tp)
4866 {
4867 rtl_generic_op(tp, tp->pll_power_ops.up);
4868 }
4869
4870 static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
4871 {
4872 struct pll_power_ops *ops = &tp->pll_power_ops;
4873
4874 switch (tp->mac_version) {
4875 case RTL_GIGA_MAC_VER_07:
4876 case RTL_GIGA_MAC_VER_08:
4877 case RTL_GIGA_MAC_VER_09:
4878 case RTL_GIGA_MAC_VER_10:
4879 case RTL_GIGA_MAC_VER_16:
4880 case RTL_GIGA_MAC_VER_29:
4881 case RTL_GIGA_MAC_VER_30:
4882 case RTL_GIGA_MAC_VER_37:
4883 case RTL_GIGA_MAC_VER_39:
4884 case RTL_GIGA_MAC_VER_43:
4885 case RTL_GIGA_MAC_VER_47:
4886 case RTL_GIGA_MAC_VER_48:
4887 ops->down = r810x_pll_power_down;
4888 ops->up = r810x_pll_power_up;
4889 break;
4890
4891 case RTL_GIGA_MAC_VER_11:
4892 case RTL_GIGA_MAC_VER_12:
4893 case RTL_GIGA_MAC_VER_17:
4894 case RTL_GIGA_MAC_VER_18:
4895 case RTL_GIGA_MAC_VER_19:
4896 case RTL_GIGA_MAC_VER_20:
4897 case RTL_GIGA_MAC_VER_21:
4898 case RTL_GIGA_MAC_VER_22:
4899 case RTL_GIGA_MAC_VER_23:
4900 case RTL_GIGA_MAC_VER_24:
4901 case RTL_GIGA_MAC_VER_25:
4902 case RTL_GIGA_MAC_VER_26:
4903 case RTL_GIGA_MAC_VER_27:
4904 case RTL_GIGA_MAC_VER_28:
4905 case RTL_GIGA_MAC_VER_31:
4906 case RTL_GIGA_MAC_VER_32:
4907 case RTL_GIGA_MAC_VER_33:
4908 case RTL_GIGA_MAC_VER_34:
4909 case RTL_GIGA_MAC_VER_35:
4910 case RTL_GIGA_MAC_VER_36:
4911 case RTL_GIGA_MAC_VER_38:
4912 case RTL_GIGA_MAC_VER_40:
4913 case RTL_GIGA_MAC_VER_41:
4914 case RTL_GIGA_MAC_VER_42:
4915 case RTL_GIGA_MAC_VER_44:
4916 case RTL_GIGA_MAC_VER_45:
4917 case RTL_GIGA_MAC_VER_46:
4918 case RTL_GIGA_MAC_VER_49:
4919 case RTL_GIGA_MAC_VER_50:
4920 case RTL_GIGA_MAC_VER_51:
4921 ops->down = r8168_pll_power_down;
4922 ops->up = r8168_pll_power_up;
4923 break;
4924
4925 default:
4926 ops->down = NULL;
4927 ops->up = NULL;
4928 break;
4929 }
4930 }
4931
4932 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4933 {
4934 void __iomem *ioaddr = tp->mmio_addr;
4935
4936 switch (tp->mac_version) {
4937 case RTL_GIGA_MAC_VER_01:
4938 case RTL_GIGA_MAC_VER_02:
4939 case RTL_GIGA_MAC_VER_03:
4940 case RTL_GIGA_MAC_VER_04:
4941 case RTL_GIGA_MAC_VER_05:
4942 case RTL_GIGA_MAC_VER_06:
4943 case RTL_GIGA_MAC_VER_10:
4944 case RTL_GIGA_MAC_VER_11:
4945 case RTL_GIGA_MAC_VER_12:
4946 case RTL_GIGA_MAC_VER_13:
4947 case RTL_GIGA_MAC_VER_14:
4948 case RTL_GIGA_MAC_VER_15:
4949 case RTL_GIGA_MAC_VER_16:
4950 case RTL_GIGA_MAC_VER_17:
4951 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4952 break;
4953 case RTL_GIGA_MAC_VER_18:
4954 case RTL_GIGA_MAC_VER_19:
4955 case RTL_GIGA_MAC_VER_20:
4956 case RTL_GIGA_MAC_VER_21:
4957 case RTL_GIGA_MAC_VER_22:
4958 case RTL_GIGA_MAC_VER_23:
4959 case RTL_GIGA_MAC_VER_24:
4960 case RTL_GIGA_MAC_VER_34:
4961 case RTL_GIGA_MAC_VER_35:
4962 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4963 break;
4964 case RTL_GIGA_MAC_VER_40:
4965 case RTL_GIGA_MAC_VER_41:
4966 case RTL_GIGA_MAC_VER_42:
4967 case RTL_GIGA_MAC_VER_43:
4968 case RTL_GIGA_MAC_VER_44:
4969 case RTL_GIGA_MAC_VER_45:
4970 case RTL_GIGA_MAC_VER_46:
4971 case RTL_GIGA_MAC_VER_47:
4972 case RTL_GIGA_MAC_VER_48:
4973 case RTL_GIGA_MAC_VER_49:
4974 case RTL_GIGA_MAC_VER_50:
4975 case RTL_GIGA_MAC_VER_51:
4976 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4977 break;
4978 default:
4979 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4980 break;
4981 }
4982 }
4983
4984 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4985 {
4986 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4987 }
4988
4989 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4990 {
4991 void __iomem *ioaddr = tp->mmio_addr;
4992
4993 RTL_W8(Cfg9346, Cfg9346_Unlock);
4994 rtl_generic_op(tp, tp->jumbo_ops.enable);
4995 RTL_W8(Cfg9346, Cfg9346_Lock);
4996 }
4997
4998 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4999 {
5000 void __iomem *ioaddr = tp->mmio_addr;
5001
5002 RTL_W8(Cfg9346, Cfg9346_Unlock);
5003 rtl_generic_op(tp, tp->jumbo_ops.disable);
5004 RTL_W8(Cfg9346, Cfg9346_Lock);
5005 }
5006
5007 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
5008 {
5009 void __iomem *ioaddr = tp->mmio_addr;
5010
5011 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5012 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
5013 rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
5014 }
5015
5016 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
5017 {
5018 void __iomem *ioaddr = tp->mmio_addr;
5019
5020 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5021 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
5022 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5023 }
5024
5025 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
5026 {
5027 void __iomem *ioaddr = tp->mmio_addr;
5028
5029 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5030 }
5031
5032 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
5033 {
5034 void __iomem *ioaddr = tp->mmio_addr;
5035
5036 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5037 }
5038
5039 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
5040 {
5041 void __iomem *ioaddr = tp->mmio_addr;
5042
5043 RTL_W8(MaxTxPacketSize, 0x3f);
5044 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5045 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
5046 rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
5047 }
5048
5049 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
5050 {
5051 void __iomem *ioaddr = tp->mmio_addr;
5052
5053 RTL_W8(MaxTxPacketSize, 0x0c);
5054 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5055 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
5056 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5057 }
5058
5059 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
5060 {
5061 rtl_tx_performance_tweak(tp->pci_dev,
5062 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
5063 }
5064
5065 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
5066 {
5067 rtl_tx_performance_tweak(tp->pci_dev,
5068 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
5069 }
5070
5071 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
5072 {
5073 void __iomem *ioaddr = tp->mmio_addr;
5074
5075 r8168b_0_hw_jumbo_enable(tp);
5076
5077 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
5078 }
5079
5080 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
5081 {
5082 void __iomem *ioaddr = tp->mmio_addr;
5083
5084 r8168b_0_hw_jumbo_disable(tp);
5085
5086 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5087 }
5088
5089 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
5090 {
5091 struct jumbo_ops *ops = &tp->jumbo_ops;
5092
5093 switch (tp->mac_version) {
5094 case RTL_GIGA_MAC_VER_11:
5095 ops->disable = r8168b_0_hw_jumbo_disable;
5096 ops->enable = r8168b_0_hw_jumbo_enable;
5097 break;
5098 case RTL_GIGA_MAC_VER_12:
5099 case RTL_GIGA_MAC_VER_17:
5100 ops->disable = r8168b_1_hw_jumbo_disable;
5101 ops->enable = r8168b_1_hw_jumbo_enable;
5102 break;
5103 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
5104 case RTL_GIGA_MAC_VER_19:
5105 case RTL_GIGA_MAC_VER_20:
5106 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
5107 case RTL_GIGA_MAC_VER_22:
5108 case RTL_GIGA_MAC_VER_23:
5109 case RTL_GIGA_MAC_VER_24:
5110 case RTL_GIGA_MAC_VER_25:
5111 case RTL_GIGA_MAC_VER_26:
5112 ops->disable = r8168c_hw_jumbo_disable;
5113 ops->enable = r8168c_hw_jumbo_enable;
5114 break;
5115 case RTL_GIGA_MAC_VER_27:
5116 case RTL_GIGA_MAC_VER_28:
5117 ops->disable = r8168dp_hw_jumbo_disable;
5118 ops->enable = r8168dp_hw_jumbo_enable;
5119 break;
5120 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
5121 case RTL_GIGA_MAC_VER_32:
5122 case RTL_GIGA_MAC_VER_33:
5123 case RTL_GIGA_MAC_VER_34:
5124 ops->disable = r8168e_hw_jumbo_disable;
5125 ops->enable = r8168e_hw_jumbo_enable;
5126 break;
5127
5128 /*
5129 * No action needed for jumbo frames with 8169.
5130 * No jumbo for 810x at all.
5131 */
5132 case RTL_GIGA_MAC_VER_40:
5133 case RTL_GIGA_MAC_VER_41:
5134 case RTL_GIGA_MAC_VER_42:
5135 case RTL_GIGA_MAC_VER_43:
5136 case RTL_GIGA_MAC_VER_44:
5137 case RTL_GIGA_MAC_VER_45:
5138 case RTL_GIGA_MAC_VER_46:
5139 case RTL_GIGA_MAC_VER_47:
5140 case RTL_GIGA_MAC_VER_48:
5141 case RTL_GIGA_MAC_VER_49:
5142 case RTL_GIGA_MAC_VER_50:
5143 case RTL_GIGA_MAC_VER_51:
5144 default:
5145 ops->disable = NULL;
5146 ops->enable = NULL;
5147 break;
5148 }
5149 }
5150
5151 DECLARE_RTL_COND(rtl_chipcmd_cond)
5152 {
5153 void __iomem *ioaddr = tp->mmio_addr;
5154
5155 return RTL_R8(ChipCmd) & CmdReset;
5156 }
5157
5158 static void rtl_hw_reset(struct rtl8169_private *tp)
5159 {
5160 void __iomem *ioaddr = tp->mmio_addr;
5161
5162 RTL_W8(ChipCmd, CmdReset);
5163
5164 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
5165 }
5166
5167 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
5168 {
5169 struct rtl_fw *rtl_fw;
5170 const char *name;
5171 int rc = -ENOMEM;
5172
5173 name = rtl_lookup_firmware_name(tp);
5174 if (!name)
5175 goto out_no_firmware;
5176
5177 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
5178 if (!rtl_fw)
5179 goto err_warn;
5180
5181 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
5182 if (rc < 0)
5183 goto err_free;
5184
5185 rc = rtl_check_firmware(tp, rtl_fw);
5186 if (rc < 0)
5187 goto err_release_firmware;
5188
5189 tp->rtl_fw = rtl_fw;
5190 out:
5191 return;
5192
5193 err_release_firmware:
5194 release_firmware(rtl_fw->fw);
5195 err_free:
5196 kfree(rtl_fw);
5197 err_warn:
5198 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
5199 name, rc);
5200 out_no_firmware:
5201 tp->rtl_fw = NULL;
5202 goto out;
5203 }
5204
5205 static void rtl_request_firmware(struct rtl8169_private *tp)
5206 {
5207 if (IS_ERR(tp->rtl_fw))
5208 rtl_request_uncached_firmware(tp);
5209 }
5210
5211 static void rtl_rx_close(struct rtl8169_private *tp)
5212 {
5213 void __iomem *ioaddr = tp->mmio_addr;
5214
5215 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
5216 }
5217
5218 DECLARE_RTL_COND(rtl_npq_cond)
5219 {
5220 void __iomem *ioaddr = tp->mmio_addr;
5221
5222 return RTL_R8(TxPoll) & NPQ;
5223 }
5224
5225 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
5226 {
5227 void __iomem *ioaddr = tp->mmio_addr;
5228
5229 return RTL_R32(TxConfig) & TXCFG_EMPTY;
5230 }
5231
5232 static void rtl8169_hw_reset(struct rtl8169_private *tp)
5233 {
5234 void __iomem *ioaddr = tp->mmio_addr;
5235
5236 /* Disable interrupts */
5237 rtl8169_irq_mask_and_ack(tp);
5238
5239 rtl_rx_close(tp);
5240
5241 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
5242 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
5243 tp->mac_version == RTL_GIGA_MAC_VER_31) {
5244 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
5245 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
5246 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
5247 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
5248 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
5249 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
5250 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
5251 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
5252 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
5253 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
5254 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
5255 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
5256 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
5257 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
5258 tp->mac_version == RTL_GIGA_MAC_VER_48 ||
5259 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
5260 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
5261 tp->mac_version == RTL_GIGA_MAC_VER_51) {
5262 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5263 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
5264 } else {
5265 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5266 udelay(100);
5267 }
5268
5269 rtl_hw_reset(tp);
5270 }
5271
5272 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
5273 {
5274 void __iomem *ioaddr = tp->mmio_addr;
5275
5276 /* Set DMA burst size and Interframe Gap Time */
5277 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
5278 (InterFrameGap << TxInterFrameGapShift));
5279 }
5280
5281 static void rtl_hw_start(struct net_device *dev)
5282 {
5283 struct rtl8169_private *tp = netdev_priv(dev);
5284
5285 tp->hw_start(dev);
5286
5287 rtl_irq_enable_all(tp);
5288 }
5289
5290 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
5291 void __iomem *ioaddr)
5292 {
5293 /*
5294 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
5295 * register to be written before TxDescAddrLow to work.
5296 * Switching from MMIO to I/O access fixes the issue as well.
5297 */
5298 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
5299 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
5300 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
5301 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
5302 }
5303
5304 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
5305 {
5306 u16 cmd;
5307
5308 cmd = RTL_R16(CPlusCmd);
5309 RTL_W16(CPlusCmd, cmd);
5310 return cmd;
5311 }
5312
5313 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
5314 {
5315 /* Low hurts. Let's disable the filtering. */
5316 RTL_W16(RxMaxSize, rx_buf_sz + 1);
5317 }
5318
5319 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
5320 {
5321 static const struct rtl_cfg2_info {
5322 u32 mac_version;
5323 u32 clk;
5324 u32 val;
5325 } cfg2_info [] = {
5326 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
5327 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
5328 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
5329 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
5330 };
5331 const struct rtl_cfg2_info *p = cfg2_info;
5332 unsigned int i;
5333 u32 clk;
5334
5335 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
5336 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
5337 if ((p->mac_version == mac_version) && (p->clk == clk)) {
5338 RTL_W32(0x7c, p->val);
5339 break;
5340 }
5341 }
5342 }
5343
5344 static void rtl_set_rx_mode(struct net_device *dev)
5345 {
5346 struct rtl8169_private *tp = netdev_priv(dev);
5347 void __iomem *ioaddr = tp->mmio_addr;
5348 u32 mc_filter[2]; /* Multicast hash filter */
5349 int rx_mode;
5350 u32 tmp = 0;
5351
5352 if (dev->flags & IFF_PROMISC) {
5353 /* Unconditionally log net taps. */
5354 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5355 rx_mode =
5356 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5357 AcceptAllPhys;
5358 mc_filter[1] = mc_filter[0] = 0xffffffff;
5359 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5360 (dev->flags & IFF_ALLMULTI)) {
5361 /* Too many to filter perfectly -- accept all multicasts. */
5362 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5363 mc_filter[1] = mc_filter[0] = 0xffffffff;
5364 } else {
5365 struct netdev_hw_addr *ha;
5366
5367 rx_mode = AcceptBroadcast | AcceptMyPhys;
5368 mc_filter[1] = mc_filter[0] = 0;
5369 netdev_for_each_mc_addr(ha, dev) {
5370 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5371 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5372 rx_mode |= AcceptMulticast;
5373 }
5374 }
5375
5376 if (dev->features & NETIF_F_RXALL)
5377 rx_mode |= (AcceptErr | AcceptRunt);
5378
5379 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
5380
5381 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5382 u32 data = mc_filter[0];
5383
5384 mc_filter[0] = swab32(mc_filter[1]);
5385 mc_filter[1] = swab32(data);
5386 }
5387
5388 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
5389 mc_filter[1] = mc_filter[0] = 0xffffffff;
5390
5391 RTL_W32(MAR0 + 4, mc_filter[1]);
5392 RTL_W32(MAR0 + 0, mc_filter[0]);
5393
5394 RTL_W32(RxConfig, tmp);
5395 }
5396
5397 static void rtl_hw_start_8169(struct net_device *dev)
5398 {
5399 struct rtl8169_private *tp = netdev_priv(dev);
5400 void __iomem *ioaddr = tp->mmio_addr;
5401 struct pci_dev *pdev = tp->pci_dev;
5402
5403 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
5404 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
5405 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
5406 }
5407
5408 RTL_W8(Cfg9346, Cfg9346_Unlock);
5409 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5410 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5411 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5412 tp->mac_version == RTL_GIGA_MAC_VER_04)
5413 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5414
5415 rtl_init_rxcfg(tp);
5416
5417 RTL_W8(EarlyTxThres, NoEarlyTx);
5418
5419 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5420
5421 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5422 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5423 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5424 tp->mac_version == RTL_GIGA_MAC_VER_04)
5425 rtl_set_rx_tx_config_registers(tp);
5426
5427 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
5428
5429 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5430 tp->mac_version == RTL_GIGA_MAC_VER_03) {
5431 dprintk("Set MAC Reg C+CR Offset 0xe0. "
5432 "Bit-3 and bit-14 MUST be 1\n");
5433 tp->cp_cmd |= (1 << 14);
5434 }
5435
5436 RTL_W16(CPlusCmd, tp->cp_cmd);
5437
5438 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
5439
5440 /*
5441 * Undocumented corner. Supposedly:
5442 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
5443 */
5444 RTL_W16(IntrMitigate, 0x0000);
5445
5446 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5447
5448 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
5449 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
5450 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
5451 tp->mac_version != RTL_GIGA_MAC_VER_04) {
5452 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5453 rtl_set_rx_tx_config_registers(tp);
5454 }
5455
5456 RTL_W8(Cfg9346, Cfg9346_Lock);
5457
5458 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5459 RTL_R8(IntrMask);
5460
5461 RTL_W32(RxMissed, 0);
5462
5463 rtl_set_rx_mode(dev);
5464
5465 /* no early-rx interrupts */
5466 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5467 }
5468
5469 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
5470 {
5471 if (tp->csi_ops.write)
5472 tp->csi_ops.write(tp, addr, value);
5473 }
5474
5475 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
5476 {
5477 return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
5478 }
5479
5480 static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
5481 {
5482 u32 csi;
5483
5484 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
5485 rtl_csi_write(tp, 0x070c, csi | bits);
5486 }
5487
5488 static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
5489 {
5490 rtl_csi_access_enable(tp, 0x17000000);
5491 }
5492
5493 static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
5494 {
5495 rtl_csi_access_enable(tp, 0x27000000);
5496 }
5497
5498 DECLARE_RTL_COND(rtl_csiar_cond)
5499 {
5500 void __iomem *ioaddr = tp->mmio_addr;
5501
5502 return RTL_R32(CSIAR) & CSIAR_FLAG;
5503 }
5504
5505 static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
5506 {
5507 void __iomem *ioaddr = tp->mmio_addr;
5508
5509 RTL_W32(CSIDR, value);
5510 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5511 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5512
5513 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5514 }
5515
5516 static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
5517 {
5518 void __iomem *ioaddr = tp->mmio_addr;
5519
5520 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
5521 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5522
5523 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5524 RTL_R32(CSIDR) : ~0;
5525 }
5526
5527 static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
5528 {
5529 void __iomem *ioaddr = tp->mmio_addr;
5530
5531 RTL_W32(CSIDR, value);
5532 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5533 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5534 CSIAR_FUNC_NIC);
5535
5536 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5537 }
5538
5539 static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
5540 {
5541 void __iomem *ioaddr = tp->mmio_addr;
5542
5543 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
5544 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5545
5546 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5547 RTL_R32(CSIDR) : ~0;
5548 }
5549
5550 static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
5551 {
5552 void __iomem *ioaddr = tp->mmio_addr;
5553
5554 RTL_W32(CSIDR, value);
5555 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5556 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5557 CSIAR_FUNC_NIC2);
5558
5559 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5560 }
5561
5562 static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
5563 {
5564 void __iomem *ioaddr = tp->mmio_addr;
5565
5566 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
5567 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5568
5569 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5570 RTL_R32(CSIDR) : ~0;
5571 }
5572
5573 static void rtl_init_csi_ops(struct rtl8169_private *tp)
5574 {
5575 struct csi_ops *ops = &tp->csi_ops;
5576
5577 switch (tp->mac_version) {
5578 case RTL_GIGA_MAC_VER_01:
5579 case RTL_GIGA_MAC_VER_02:
5580 case RTL_GIGA_MAC_VER_03:
5581 case RTL_GIGA_MAC_VER_04:
5582 case RTL_GIGA_MAC_VER_05:
5583 case RTL_GIGA_MAC_VER_06:
5584 case RTL_GIGA_MAC_VER_10:
5585 case RTL_GIGA_MAC_VER_11:
5586 case RTL_GIGA_MAC_VER_12:
5587 case RTL_GIGA_MAC_VER_13:
5588 case RTL_GIGA_MAC_VER_14:
5589 case RTL_GIGA_MAC_VER_15:
5590 case RTL_GIGA_MAC_VER_16:
5591 case RTL_GIGA_MAC_VER_17:
5592 ops->write = NULL;
5593 ops->read = NULL;
5594 break;
5595
5596 case RTL_GIGA_MAC_VER_37:
5597 case RTL_GIGA_MAC_VER_38:
5598 ops->write = r8402_csi_write;
5599 ops->read = r8402_csi_read;
5600 break;
5601
5602 case RTL_GIGA_MAC_VER_44:
5603 ops->write = r8411_csi_write;
5604 ops->read = r8411_csi_read;
5605 break;
5606
5607 default:
5608 ops->write = r8169_csi_write;
5609 ops->read = r8169_csi_read;
5610 break;
5611 }
5612 }
5613
5614 struct ephy_info {
5615 unsigned int offset;
5616 u16 mask;
5617 u16 bits;
5618 };
5619
5620 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
5621 int len)
5622 {
5623 u16 w;
5624
5625 while (len-- > 0) {
5626 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
5627 rtl_ephy_write(tp, e->offset, w);
5628 e++;
5629 }
5630 }
5631
5632 static void rtl_disable_clock_request(struct pci_dev *pdev)
5633 {
5634 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
5635 PCI_EXP_LNKCTL_CLKREQ_EN);
5636 }
5637
5638 static void rtl_enable_clock_request(struct pci_dev *pdev)
5639 {
5640 pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
5641 PCI_EXP_LNKCTL_CLKREQ_EN);
5642 }
5643
5644 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
5645 {
5646 void __iomem *ioaddr = tp->mmio_addr;
5647 u8 data;
5648
5649 data = RTL_R8(Config3);
5650
5651 if (enable)
5652 data |= Rdy_to_L23;
5653 else
5654 data &= ~Rdy_to_L23;
5655
5656 RTL_W8(Config3, data);
5657 }
5658
5659 #define R8168_CPCMD_QUIRK_MASK (\
5660 EnableBist | \
5661 Mac_dbgo_oe | \
5662 Force_half_dup | \
5663 Force_rxflow_en | \
5664 Force_txflow_en | \
5665 Cxpl_dbg_sel | \
5666 ASF | \
5667 PktCntrDisable | \
5668 Mac_dbgo_sel)
5669
5670 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
5671 {
5672 void __iomem *ioaddr = tp->mmio_addr;
5673 struct pci_dev *pdev = tp->pci_dev;
5674
5675 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5676
5677 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5678
5679 if (tp->dev->mtu <= ETH_DATA_LEN) {
5680 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
5681 PCI_EXP_DEVCTL_NOSNOOP_EN);
5682 }
5683 }
5684
5685 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
5686 {
5687 void __iomem *ioaddr = tp->mmio_addr;
5688
5689 rtl_hw_start_8168bb(tp);
5690
5691 RTL_W8(MaxTxPacketSize, TxPacketMax);
5692
5693 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5694 }
5695
5696 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
5697 {
5698 void __iomem *ioaddr = tp->mmio_addr;
5699 struct pci_dev *pdev = tp->pci_dev;
5700
5701 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
5702
5703 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5704
5705 if (tp->dev->mtu <= ETH_DATA_LEN)
5706 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5707
5708 rtl_disable_clock_request(pdev);
5709
5710 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5711 }
5712
5713 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
5714 {
5715 static const struct ephy_info e_info_8168cp[] = {
5716 { 0x01, 0, 0x0001 },
5717 { 0x02, 0x0800, 0x1000 },
5718 { 0x03, 0, 0x0042 },
5719 { 0x06, 0x0080, 0x0000 },
5720 { 0x07, 0, 0x2000 }
5721 };
5722
5723 rtl_csi_access_enable_2(tp);
5724
5725 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
5726
5727 __rtl_hw_start_8168cp(tp);
5728 }
5729
5730 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
5731 {
5732 void __iomem *ioaddr = tp->mmio_addr;
5733 struct pci_dev *pdev = tp->pci_dev;
5734
5735 rtl_csi_access_enable_2(tp);
5736
5737 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5738
5739 if (tp->dev->mtu <= ETH_DATA_LEN)
5740 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5741
5742 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5743 }
5744
5745 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
5746 {
5747 void __iomem *ioaddr = tp->mmio_addr;
5748 struct pci_dev *pdev = tp->pci_dev;
5749
5750 rtl_csi_access_enable_2(tp);
5751
5752 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5753
5754 /* Magic. */
5755 RTL_W8(DBG_REG, 0x20);
5756
5757 RTL_W8(MaxTxPacketSize, TxPacketMax);
5758
5759 if (tp->dev->mtu <= ETH_DATA_LEN)
5760 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5761
5762 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5763 }
5764
5765 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
5766 {
5767 void __iomem *ioaddr = tp->mmio_addr;
5768 static const struct ephy_info e_info_8168c_1[] = {
5769 { 0x02, 0x0800, 0x1000 },
5770 { 0x03, 0, 0x0002 },
5771 { 0x06, 0x0080, 0x0000 }
5772 };
5773
5774 rtl_csi_access_enable_2(tp);
5775
5776 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
5777
5778 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
5779
5780 __rtl_hw_start_8168cp(tp);
5781 }
5782
5783 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
5784 {
5785 static const struct ephy_info e_info_8168c_2[] = {
5786 { 0x01, 0, 0x0001 },
5787 { 0x03, 0x0400, 0x0220 }
5788 };
5789
5790 rtl_csi_access_enable_2(tp);
5791
5792 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
5793
5794 __rtl_hw_start_8168cp(tp);
5795 }
5796
5797 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
5798 {
5799 rtl_hw_start_8168c_2(tp);
5800 }
5801
5802 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
5803 {
5804 rtl_csi_access_enable_2(tp);
5805
5806 __rtl_hw_start_8168cp(tp);
5807 }
5808
5809 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5810 {
5811 void __iomem *ioaddr = tp->mmio_addr;
5812 struct pci_dev *pdev = tp->pci_dev;
5813
5814 rtl_csi_access_enable_2(tp);
5815
5816 rtl_disable_clock_request(pdev);
5817
5818 RTL_W8(MaxTxPacketSize, TxPacketMax);
5819
5820 if (tp->dev->mtu <= ETH_DATA_LEN)
5821 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5822
5823 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5824 }
5825
5826 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
5827 {
5828 void __iomem *ioaddr = tp->mmio_addr;
5829 struct pci_dev *pdev = tp->pci_dev;
5830
5831 rtl_csi_access_enable_1(tp);
5832
5833 if (tp->dev->mtu <= ETH_DATA_LEN)
5834 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5835
5836 RTL_W8(MaxTxPacketSize, TxPacketMax);
5837
5838 rtl_disable_clock_request(pdev);
5839 }
5840
5841 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
5842 {
5843 void __iomem *ioaddr = tp->mmio_addr;
5844 struct pci_dev *pdev = tp->pci_dev;
5845 static const struct ephy_info e_info_8168d_4[] = {
5846 { 0x0b, 0x0000, 0x0048 },
5847 { 0x19, 0x0020, 0x0050 },
5848 { 0x0c, 0x0100, 0x0020 }
5849 };
5850
5851 rtl_csi_access_enable_1(tp);
5852
5853 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5854
5855 RTL_W8(MaxTxPacketSize, TxPacketMax);
5856
5857 rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
5858
5859 rtl_enable_clock_request(pdev);
5860 }
5861
5862 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5863 {
5864 void __iomem *ioaddr = tp->mmio_addr;
5865 struct pci_dev *pdev = tp->pci_dev;
5866 static const struct ephy_info e_info_8168e_1[] = {
5867 { 0x00, 0x0200, 0x0100 },
5868 { 0x00, 0x0000, 0x0004 },
5869 { 0x06, 0x0002, 0x0001 },
5870 { 0x06, 0x0000, 0x0030 },
5871 { 0x07, 0x0000, 0x2000 },
5872 { 0x00, 0x0000, 0x0020 },
5873 { 0x03, 0x5800, 0x2000 },
5874 { 0x03, 0x0000, 0x0001 },
5875 { 0x01, 0x0800, 0x1000 },
5876 { 0x07, 0x0000, 0x4000 },
5877 { 0x1e, 0x0000, 0x2000 },
5878 { 0x19, 0xffff, 0xfe6c },
5879 { 0x0a, 0x0000, 0x0040 }
5880 };
5881
5882 rtl_csi_access_enable_2(tp);
5883
5884 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5885
5886 if (tp->dev->mtu <= ETH_DATA_LEN)
5887 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5888
5889 RTL_W8(MaxTxPacketSize, TxPacketMax);
5890
5891 rtl_disable_clock_request(pdev);
5892
5893 /* Reset tx FIFO pointer */
5894 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5895 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
5896
5897 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5898 }
5899
5900 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5901 {
5902 void __iomem *ioaddr = tp->mmio_addr;
5903 struct pci_dev *pdev = tp->pci_dev;
5904 static const struct ephy_info e_info_8168e_2[] = {
5905 { 0x09, 0x0000, 0x0080 },
5906 { 0x19, 0x0000, 0x0224 }
5907 };
5908
5909 rtl_csi_access_enable_1(tp);
5910
5911 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5912
5913 if (tp->dev->mtu <= ETH_DATA_LEN)
5914 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5915
5916 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5917 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5918 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5919 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5920 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5921 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5922 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5923 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5924
5925 RTL_W8(MaxTxPacketSize, EarlySize);
5926
5927 rtl_disable_clock_request(pdev);
5928
5929 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5930 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5931
5932 /* Adjust EEE LED frequency */
5933 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5934
5935 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5936 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5937 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5938 }
5939
5940 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5941 {
5942 void __iomem *ioaddr = tp->mmio_addr;
5943 struct pci_dev *pdev = tp->pci_dev;
5944
5945 rtl_csi_access_enable_2(tp);
5946
5947 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5948
5949 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5950 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5951 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5952 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5953 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5954 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5955 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5956 rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5957 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5958 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5959
5960 RTL_W8(MaxTxPacketSize, EarlySize);
5961
5962 rtl_disable_clock_request(pdev);
5963
5964 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5965 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5966 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5967 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5968 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5969 }
5970
5971 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5972 {
5973 void __iomem *ioaddr = tp->mmio_addr;
5974 static const struct ephy_info e_info_8168f_1[] = {
5975 { 0x06, 0x00c0, 0x0020 },
5976 { 0x08, 0x0001, 0x0002 },
5977 { 0x09, 0x0000, 0x0080 },
5978 { 0x19, 0x0000, 0x0224 }
5979 };
5980
5981 rtl_hw_start_8168f(tp);
5982
5983 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5984
5985 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5986
5987 /* Adjust EEE LED frequency */
5988 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5989 }
5990
5991 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5992 {
5993 static const struct ephy_info e_info_8168f_1[] = {
5994 { 0x06, 0x00c0, 0x0020 },
5995 { 0x0f, 0xffff, 0x5200 },
5996 { 0x1e, 0x0000, 0x4000 },
5997 { 0x19, 0x0000, 0x0224 }
5998 };
5999
6000 rtl_hw_start_8168f(tp);
6001 rtl_pcie_state_l2l3_enable(tp, false);
6002
6003 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
6004
6005 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
6006 }
6007
6008 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
6009 {
6010 void __iomem *ioaddr = tp->mmio_addr;
6011 struct pci_dev *pdev = tp->pci_dev;
6012
6013 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6014
6015 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
6016 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6017 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6018 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6019
6020 rtl_csi_access_enable_1(tp);
6021
6022 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6023
6024 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6025 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6026 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
6027
6028 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6029 RTL_W8(MaxTxPacketSize, EarlySize);
6030
6031 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6032 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6033
6034 /* Adjust EEE LED frequency */
6035 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6036
6037 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6038 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6039
6040 rtl_pcie_state_l2l3_enable(tp, false);
6041 }
6042
6043 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
6044 {
6045 void __iomem *ioaddr = tp->mmio_addr;
6046 static const struct ephy_info e_info_8168g_1[] = {
6047 { 0x00, 0x0000, 0x0008 },
6048 { 0x0c, 0x37d0, 0x0820 },
6049 { 0x1e, 0x0000, 0x0001 },
6050 { 0x19, 0x8000, 0x0000 }
6051 };
6052
6053 rtl_hw_start_8168g(tp);
6054
6055 /* disable aspm and clock request before access ephy */
6056 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6057 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6058 rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
6059 }
6060
6061 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
6062 {
6063 void __iomem *ioaddr = tp->mmio_addr;
6064 static const struct ephy_info e_info_8168g_2[] = {
6065 { 0x00, 0x0000, 0x0008 },
6066 { 0x0c, 0x3df0, 0x0200 },
6067 { 0x19, 0xffff, 0xfc00 },
6068 { 0x1e, 0xffff, 0x20eb }
6069 };
6070
6071 rtl_hw_start_8168g(tp);
6072
6073 /* disable aspm and clock request before access ephy */
6074 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6075 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6076 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
6077 }
6078
6079 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
6080 {
6081 void __iomem *ioaddr = tp->mmio_addr;
6082 static const struct ephy_info e_info_8411_2[] = {
6083 { 0x00, 0x0000, 0x0008 },
6084 { 0x0c, 0x3df0, 0x0200 },
6085 { 0x0f, 0xffff, 0x5200 },
6086 { 0x19, 0x0020, 0x0000 },
6087 { 0x1e, 0x0000, 0x2000 }
6088 };
6089
6090 rtl_hw_start_8168g(tp);
6091
6092 /* disable aspm and clock request before access ephy */
6093 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6094 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6095 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
6096 }
6097
6098 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
6099 {
6100 void __iomem *ioaddr = tp->mmio_addr;
6101 struct pci_dev *pdev = tp->pci_dev;
6102 int rg_saw_cnt;
6103 u32 data;
6104 static const struct ephy_info e_info_8168h_1[] = {
6105 { 0x1e, 0x0800, 0x0001 },
6106 { 0x1d, 0x0000, 0x0800 },
6107 { 0x05, 0xffff, 0x2089 },
6108 { 0x06, 0xffff, 0x5881 },
6109 { 0x04, 0xffff, 0x154a },
6110 { 0x01, 0xffff, 0x068b }
6111 };
6112
6113 /* disable aspm and clock request before access ephy */
6114 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6115 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6116 rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
6117
6118 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6119
6120 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6121 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6122 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6123 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6124
6125 rtl_csi_access_enable_1(tp);
6126
6127 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6128
6129 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6130 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6131
6132 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
6133
6134 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
6135
6136 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6137
6138 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6139 RTL_W8(MaxTxPacketSize, EarlySize);
6140
6141 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6142 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6143
6144 /* Adjust EEE LED frequency */
6145 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6146
6147 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6148 RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6149
6150 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6151
6152 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6153
6154 rtl_pcie_state_l2l3_enable(tp, false);
6155
6156 rtl_writephy(tp, 0x1f, 0x0c42);
6157 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
6158 rtl_writephy(tp, 0x1f, 0x0000);
6159 if (rg_saw_cnt > 0) {
6160 u16 sw_cnt_1ms_ini;
6161
6162 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
6163 sw_cnt_1ms_ini &= 0x0fff;
6164 data = r8168_mac_ocp_read(tp, 0xd412);
6165 data &= ~0x0fff;
6166 data |= sw_cnt_1ms_ini;
6167 r8168_mac_ocp_write(tp, 0xd412, data);
6168 }
6169
6170 data = r8168_mac_ocp_read(tp, 0xe056);
6171 data &= ~0xf0;
6172 data |= 0x70;
6173 r8168_mac_ocp_write(tp, 0xe056, data);
6174
6175 data = r8168_mac_ocp_read(tp, 0xe052);
6176 data &= ~0x6000;
6177 data |= 0x8008;
6178 r8168_mac_ocp_write(tp, 0xe052, data);
6179
6180 data = r8168_mac_ocp_read(tp, 0xe0d6);
6181 data &= ~0x01ff;
6182 data |= 0x017f;
6183 r8168_mac_ocp_write(tp, 0xe0d6, data);
6184
6185 data = r8168_mac_ocp_read(tp, 0xd420);
6186 data &= ~0x0fff;
6187 data |= 0x047f;
6188 r8168_mac_ocp_write(tp, 0xd420, data);
6189
6190 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
6191 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
6192 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
6193 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
6194 }
6195
6196 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
6197 {
6198 void __iomem *ioaddr = tp->mmio_addr;
6199 struct pci_dev *pdev = tp->pci_dev;
6200
6201 rtl8168ep_stop_cmac(tp);
6202
6203 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6204
6205 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6206 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
6207 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
6208 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6209
6210 rtl_csi_access_enable_1(tp);
6211
6212 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6213
6214 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6215 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6216
6217 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
6218
6219 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6220
6221 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6222 RTL_W8(MaxTxPacketSize, EarlySize);
6223
6224 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6225 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6226
6227 /* Adjust EEE LED frequency */
6228 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6229
6230 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6231
6232 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6233
6234 rtl_pcie_state_l2l3_enable(tp, false);
6235 }
6236
6237 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
6238 {
6239 void __iomem *ioaddr = tp->mmio_addr;
6240 static const struct ephy_info e_info_8168ep_1[] = {
6241 { 0x00, 0xffff, 0x10ab },
6242 { 0x06, 0xffff, 0xf030 },
6243 { 0x08, 0xffff, 0x2006 },
6244 { 0x0d, 0xffff, 0x1666 },
6245 { 0x0c, 0x3ff0, 0x0000 }
6246 };
6247
6248 /* disable aspm and clock request before access ephy */
6249 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6250 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6251 rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
6252
6253 rtl_hw_start_8168ep(tp);
6254 }
6255
6256 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
6257 {
6258 void __iomem *ioaddr = tp->mmio_addr;
6259 static const struct ephy_info e_info_8168ep_2[] = {
6260 { 0x00, 0xffff, 0x10a3 },
6261 { 0x19, 0xffff, 0xfc00 },
6262 { 0x1e, 0xffff, 0x20ea }
6263 };
6264
6265 /* disable aspm and clock request before access ephy */
6266 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6267 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6268 rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
6269
6270 rtl_hw_start_8168ep(tp);
6271
6272 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6273 RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6274 }
6275
6276 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
6277 {
6278 void __iomem *ioaddr = tp->mmio_addr;
6279 u32 data;
6280 static const struct ephy_info e_info_8168ep_3[] = {
6281 { 0x00, 0xffff, 0x10a3 },
6282 { 0x19, 0xffff, 0x7c00 },
6283 { 0x1e, 0xffff, 0x20eb },
6284 { 0x0d, 0xffff, 0x1666 }
6285 };
6286
6287 /* disable aspm and clock request before access ephy */
6288 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6289 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6290 rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
6291
6292 rtl_hw_start_8168ep(tp);
6293
6294 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6295 RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6296
6297 data = r8168_mac_ocp_read(tp, 0xd3e2);
6298 data &= 0xf000;
6299 data |= 0x0271;
6300 r8168_mac_ocp_write(tp, 0xd3e2, data);
6301
6302 data = r8168_mac_ocp_read(tp, 0xd3e4);
6303 data &= 0xff00;
6304 r8168_mac_ocp_write(tp, 0xd3e4, data);
6305
6306 data = r8168_mac_ocp_read(tp, 0xe860);
6307 data |= 0x0080;
6308 r8168_mac_ocp_write(tp, 0xe860, data);
6309 }
6310
6311 static void rtl_hw_start_8168(struct net_device *dev)
6312 {
6313 struct rtl8169_private *tp = netdev_priv(dev);
6314 void __iomem *ioaddr = tp->mmio_addr;
6315
6316 RTL_W8(Cfg9346, Cfg9346_Unlock);
6317
6318 RTL_W8(MaxTxPacketSize, TxPacketMax);
6319
6320 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6321
6322 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
6323
6324 RTL_W16(CPlusCmd, tp->cp_cmd);
6325
6326 RTL_W16(IntrMitigate, 0x5151);
6327
6328 /* Work around for RxFIFO overflow. */
6329 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
6330 tp->event_slow |= RxFIFOOver | PCSTimeout;
6331 tp->event_slow &= ~RxOverflow;
6332 }
6333
6334 rtl_set_rx_tx_desc_registers(tp, ioaddr);
6335
6336 rtl_set_rx_tx_config_registers(tp);
6337
6338 RTL_R8(IntrMask);
6339
6340 switch (tp->mac_version) {
6341 case RTL_GIGA_MAC_VER_11:
6342 rtl_hw_start_8168bb(tp);
6343 break;
6344
6345 case RTL_GIGA_MAC_VER_12:
6346 case RTL_GIGA_MAC_VER_17:
6347 rtl_hw_start_8168bef(tp);
6348 break;
6349
6350 case RTL_GIGA_MAC_VER_18:
6351 rtl_hw_start_8168cp_1(tp);
6352 break;
6353
6354 case RTL_GIGA_MAC_VER_19:
6355 rtl_hw_start_8168c_1(tp);
6356 break;
6357
6358 case RTL_GIGA_MAC_VER_20:
6359 rtl_hw_start_8168c_2(tp);
6360 break;
6361
6362 case RTL_GIGA_MAC_VER_21:
6363 rtl_hw_start_8168c_3(tp);
6364 break;
6365
6366 case RTL_GIGA_MAC_VER_22:
6367 rtl_hw_start_8168c_4(tp);
6368 break;
6369
6370 case RTL_GIGA_MAC_VER_23:
6371 rtl_hw_start_8168cp_2(tp);
6372 break;
6373
6374 case RTL_GIGA_MAC_VER_24:
6375 rtl_hw_start_8168cp_3(tp);
6376 break;
6377
6378 case RTL_GIGA_MAC_VER_25:
6379 case RTL_GIGA_MAC_VER_26:
6380 case RTL_GIGA_MAC_VER_27:
6381 rtl_hw_start_8168d(tp);
6382 break;
6383
6384 case RTL_GIGA_MAC_VER_28:
6385 rtl_hw_start_8168d_4(tp);
6386 break;
6387
6388 case RTL_GIGA_MAC_VER_31:
6389 rtl_hw_start_8168dp(tp);
6390 break;
6391
6392 case RTL_GIGA_MAC_VER_32:
6393 case RTL_GIGA_MAC_VER_33:
6394 rtl_hw_start_8168e_1(tp);
6395 break;
6396 case RTL_GIGA_MAC_VER_34:
6397 rtl_hw_start_8168e_2(tp);
6398 break;
6399
6400 case RTL_GIGA_MAC_VER_35:
6401 case RTL_GIGA_MAC_VER_36:
6402 rtl_hw_start_8168f_1(tp);
6403 break;
6404
6405 case RTL_GIGA_MAC_VER_38:
6406 rtl_hw_start_8411(tp);
6407 break;
6408
6409 case RTL_GIGA_MAC_VER_40:
6410 case RTL_GIGA_MAC_VER_41:
6411 rtl_hw_start_8168g_1(tp);
6412 break;
6413 case RTL_GIGA_MAC_VER_42:
6414 rtl_hw_start_8168g_2(tp);
6415 break;
6416
6417 case RTL_GIGA_MAC_VER_44:
6418 rtl_hw_start_8411_2(tp);
6419 break;
6420
6421 case RTL_GIGA_MAC_VER_45:
6422 case RTL_GIGA_MAC_VER_46:
6423 rtl_hw_start_8168h_1(tp);
6424 break;
6425
6426 case RTL_GIGA_MAC_VER_49:
6427 rtl_hw_start_8168ep_1(tp);
6428 break;
6429
6430 case RTL_GIGA_MAC_VER_50:
6431 rtl_hw_start_8168ep_2(tp);
6432 break;
6433
6434 case RTL_GIGA_MAC_VER_51:
6435 rtl_hw_start_8168ep_3(tp);
6436 break;
6437
6438 default:
6439 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
6440 dev->name, tp->mac_version);
6441 break;
6442 }
6443
6444 RTL_W8(Cfg9346, Cfg9346_Lock);
6445
6446 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6447
6448 rtl_set_rx_mode(dev);
6449
6450 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6451 }
6452
6453 #define R810X_CPCMD_QUIRK_MASK (\
6454 EnableBist | \
6455 Mac_dbgo_oe | \
6456 Force_half_dup | \
6457 Force_rxflow_en | \
6458 Force_txflow_en | \
6459 Cxpl_dbg_sel | \
6460 ASF | \
6461 PktCntrDisable | \
6462 Mac_dbgo_sel)
6463
6464 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
6465 {
6466 void __iomem *ioaddr = tp->mmio_addr;
6467 struct pci_dev *pdev = tp->pci_dev;
6468 static const struct ephy_info e_info_8102e_1[] = {
6469 { 0x01, 0, 0x6e65 },
6470 { 0x02, 0, 0x091f },
6471 { 0x03, 0, 0xc2f9 },
6472 { 0x06, 0, 0xafb5 },
6473 { 0x07, 0, 0x0e00 },
6474 { 0x19, 0, 0xec80 },
6475 { 0x01, 0, 0x2e65 },
6476 { 0x01, 0, 0x6e65 }
6477 };
6478 u8 cfg1;
6479
6480 rtl_csi_access_enable_2(tp);
6481
6482 RTL_W8(DBG_REG, FIX_NAK_1);
6483
6484 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6485
6486 RTL_W8(Config1,
6487 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
6488 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6489
6490 cfg1 = RTL_R8(Config1);
6491 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
6492 RTL_W8(Config1, cfg1 & ~LEDS0);
6493
6494 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
6495 }
6496
6497 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
6498 {
6499 void __iomem *ioaddr = tp->mmio_addr;
6500 struct pci_dev *pdev = tp->pci_dev;
6501
6502 rtl_csi_access_enable_2(tp);
6503
6504 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6505
6506 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
6507 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6508 }
6509
6510 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
6511 {
6512 rtl_hw_start_8102e_2(tp);
6513
6514 rtl_ephy_write(tp, 0x03, 0xc2f9);
6515 }
6516
6517 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
6518 {
6519 void __iomem *ioaddr = tp->mmio_addr;
6520 static const struct ephy_info e_info_8105e_1[] = {
6521 { 0x07, 0, 0x4000 },
6522 { 0x19, 0, 0x0200 },
6523 { 0x19, 0, 0x0020 },
6524 { 0x1e, 0, 0x2000 },
6525 { 0x03, 0, 0x0001 },
6526 { 0x19, 0, 0x0100 },
6527 { 0x19, 0, 0x0004 },
6528 { 0x0a, 0, 0x0020 }
6529 };
6530
6531 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6532 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6533
6534 /* Disable Early Tally Counter */
6535 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
6536
6537 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6538 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
6539
6540 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
6541
6542 rtl_pcie_state_l2l3_enable(tp, false);
6543 }
6544
6545 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
6546 {
6547 rtl_hw_start_8105e_1(tp);
6548 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
6549 }
6550
6551 static void rtl_hw_start_8402(struct rtl8169_private *tp)
6552 {
6553 void __iomem *ioaddr = tp->mmio_addr;
6554 static const struct ephy_info e_info_8402[] = {
6555 { 0x19, 0xffff, 0xff64 },
6556 { 0x1e, 0, 0x4000 }
6557 };
6558
6559 rtl_csi_access_enable_2(tp);
6560
6561 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6562 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6563
6564 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6565 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6566
6567 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
6568
6569 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
6570
6571 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
6572 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
6573 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6574 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6575 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6576 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6577 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
6578
6579 rtl_pcie_state_l2l3_enable(tp, false);
6580 }
6581
6582 static void rtl_hw_start_8106(struct rtl8169_private *tp)
6583 {
6584 void __iomem *ioaddr = tp->mmio_addr;
6585
6586 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6587 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6588
6589 RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
6590 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6591 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6592
6593 rtl_pcie_state_l2l3_enable(tp, false);
6594 }
6595
6596 static void rtl_hw_start_8101(struct net_device *dev)
6597 {
6598 struct rtl8169_private *tp = netdev_priv(dev);
6599 void __iomem *ioaddr = tp->mmio_addr;
6600 struct pci_dev *pdev = tp->pci_dev;
6601
6602 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
6603 tp->event_slow &= ~RxFIFOOver;
6604
6605 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
6606 tp->mac_version == RTL_GIGA_MAC_VER_16)
6607 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
6608 PCI_EXP_DEVCTL_NOSNOOP_EN);
6609
6610 RTL_W8(Cfg9346, Cfg9346_Unlock);
6611
6612 RTL_W8(MaxTxPacketSize, TxPacketMax);
6613
6614 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6615
6616 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
6617 RTL_W16(CPlusCmd, tp->cp_cmd);
6618
6619 rtl_set_rx_tx_desc_registers(tp, ioaddr);
6620
6621 rtl_set_rx_tx_config_registers(tp);
6622
6623 switch (tp->mac_version) {
6624 case RTL_GIGA_MAC_VER_07:
6625 rtl_hw_start_8102e_1(tp);
6626 break;
6627
6628 case RTL_GIGA_MAC_VER_08:
6629 rtl_hw_start_8102e_3(tp);
6630 break;
6631
6632 case RTL_GIGA_MAC_VER_09:
6633 rtl_hw_start_8102e_2(tp);
6634 break;
6635
6636 case RTL_GIGA_MAC_VER_29:
6637 rtl_hw_start_8105e_1(tp);
6638 break;
6639 case RTL_GIGA_MAC_VER_30:
6640 rtl_hw_start_8105e_2(tp);
6641 break;
6642
6643 case RTL_GIGA_MAC_VER_37:
6644 rtl_hw_start_8402(tp);
6645 break;
6646
6647 case RTL_GIGA_MAC_VER_39:
6648 rtl_hw_start_8106(tp);
6649 break;
6650 case RTL_GIGA_MAC_VER_43:
6651 rtl_hw_start_8168g_2(tp);
6652 break;
6653 case RTL_GIGA_MAC_VER_47:
6654 case RTL_GIGA_MAC_VER_48:
6655 rtl_hw_start_8168h_1(tp);
6656 break;
6657 }
6658
6659 RTL_W8(Cfg9346, Cfg9346_Lock);
6660
6661 RTL_W16(IntrMitigate, 0x0000);
6662
6663 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6664
6665 rtl_set_rx_mode(dev);
6666
6667 RTL_R8(IntrMask);
6668
6669 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6670 }
6671
6672 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
6673 {
6674 struct rtl8169_private *tp = netdev_priv(dev);
6675
6676 if (new_mtu < ETH_ZLEN ||
6677 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
6678 return -EINVAL;
6679
6680 if (new_mtu > ETH_DATA_LEN)
6681 rtl_hw_jumbo_enable(tp);
6682 else
6683 rtl_hw_jumbo_disable(tp);
6684
6685 dev->mtu = new_mtu;
6686 netdev_update_features(dev);
6687
6688 return 0;
6689 }
6690
6691 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
6692 {
6693 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
6694 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
6695 }
6696
6697 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
6698 void **data_buff, struct RxDesc *desc)
6699 {
6700 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
6701 DMA_FROM_DEVICE);
6702
6703 kfree(*data_buff);
6704 *data_buff = NULL;
6705 rtl8169_make_unusable_by_asic(desc);
6706 }
6707
6708 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
6709 {
6710 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
6711
6712 /* Force memory writes to complete before releasing descriptor */
6713 dma_wmb();
6714
6715 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
6716 }
6717
6718 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
6719 u32 rx_buf_sz)
6720 {
6721 desc->addr = cpu_to_le64(mapping);
6722 rtl8169_mark_to_asic(desc, rx_buf_sz);
6723 }
6724
6725 static inline void *rtl8169_align(void *data)
6726 {
6727 return (void *)ALIGN((long)data, 16);
6728 }
6729
6730 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
6731 struct RxDesc *desc)
6732 {
6733 void *data;
6734 dma_addr_t mapping;
6735 struct device *d = &tp->pci_dev->dev;
6736 struct net_device *dev = tp->dev;
6737 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
6738
6739 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
6740 if (!data)
6741 return NULL;
6742
6743 if (rtl8169_align(data) != data) {
6744 kfree(data);
6745 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
6746 if (!data)
6747 return NULL;
6748 }
6749
6750 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
6751 DMA_FROM_DEVICE);
6752 if (unlikely(dma_mapping_error(d, mapping))) {
6753 if (net_ratelimit())
6754 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
6755 goto err_out;
6756 }
6757
6758 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6759 return data;
6760
6761 err_out:
6762 kfree(data);
6763 return NULL;
6764 }
6765
6766 static void rtl8169_rx_clear(struct rtl8169_private *tp)
6767 {
6768 unsigned int i;
6769
6770 for (i = 0; i < NUM_RX_DESC; i++) {
6771 if (tp->Rx_databuff[i]) {
6772 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
6773 tp->RxDescArray + i);
6774 }
6775 }
6776 }
6777
6778 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
6779 {
6780 desc->opts1 |= cpu_to_le32(RingEnd);
6781 }
6782
6783 static int rtl8169_rx_fill(struct rtl8169_private *tp)
6784 {
6785 unsigned int i;
6786
6787 for (i = 0; i < NUM_RX_DESC; i++) {
6788 void *data;
6789
6790 if (tp->Rx_databuff[i])
6791 continue;
6792
6793 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6794 if (!data) {
6795 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
6796 goto err_out;
6797 }
6798 tp->Rx_databuff[i] = data;
6799 }
6800
6801 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
6802 return 0;
6803
6804 err_out:
6805 rtl8169_rx_clear(tp);
6806 return -ENOMEM;
6807 }
6808
6809 static int rtl8169_init_ring(struct net_device *dev)
6810 {
6811 struct rtl8169_private *tp = netdev_priv(dev);
6812
6813 rtl8169_init_ring_indexes(tp);
6814
6815 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6816 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
6817
6818 return rtl8169_rx_fill(tp);
6819 }
6820
6821 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
6822 struct TxDesc *desc)
6823 {
6824 unsigned int len = tx_skb->len;
6825
6826 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
6827
6828 desc->opts1 = 0x00;
6829 desc->opts2 = 0x00;
6830 desc->addr = 0x00;
6831 tx_skb->len = 0;
6832 }
6833
6834 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
6835 unsigned int n)
6836 {
6837 unsigned int i;
6838
6839 for (i = 0; i < n; i++) {
6840 unsigned int entry = (start + i) % NUM_TX_DESC;
6841 struct ring_info *tx_skb = tp->tx_skb + entry;
6842 unsigned int len = tx_skb->len;
6843
6844 if (len) {
6845 struct sk_buff *skb = tx_skb->skb;
6846
6847 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
6848 tp->TxDescArray + entry);
6849 if (skb) {
6850 tp->dev->stats.tx_dropped++;
6851 dev_kfree_skb_any(skb);
6852 tx_skb->skb = NULL;
6853 }
6854 }
6855 }
6856 }
6857
6858 static void rtl8169_tx_clear(struct rtl8169_private *tp)
6859 {
6860 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
6861 tp->cur_tx = tp->dirty_tx = 0;
6862 }
6863
6864 static void rtl_reset_work(struct rtl8169_private *tp)
6865 {
6866 struct net_device *dev = tp->dev;
6867 int i;
6868
6869 napi_disable(&tp->napi);
6870 netif_stop_queue(dev);
6871 synchronize_sched();
6872
6873 rtl8169_hw_reset(tp);
6874
6875 for (i = 0; i < NUM_RX_DESC; i++)
6876 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
6877
6878 rtl8169_tx_clear(tp);
6879 rtl8169_init_ring_indexes(tp);
6880
6881 napi_enable(&tp->napi);
6882 rtl_hw_start(dev);
6883 netif_wake_queue(dev);
6884 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
6885 }
6886
6887 static void rtl8169_tx_timeout(struct net_device *dev)
6888 {
6889 struct rtl8169_private *tp = netdev_priv(dev);
6890
6891 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6892 }
6893
6894 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
6895 u32 *opts)
6896 {
6897 struct skb_shared_info *info = skb_shinfo(skb);
6898 unsigned int cur_frag, entry;
6899 struct TxDesc *uninitialized_var(txd);
6900 struct device *d = &tp->pci_dev->dev;
6901
6902 entry = tp->cur_tx;
6903 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
6904 const skb_frag_t *frag = info->frags + cur_frag;
6905 dma_addr_t mapping;
6906 u32 status, len;
6907 void *addr;
6908
6909 entry = (entry + 1) % NUM_TX_DESC;
6910
6911 txd = tp->TxDescArray + entry;
6912 len = skb_frag_size(frag);
6913 addr = skb_frag_address(frag);
6914 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
6915 if (unlikely(dma_mapping_error(d, mapping))) {
6916 if (net_ratelimit())
6917 netif_err(tp, drv, tp->dev,
6918 "Failed to map TX fragments DMA!\n");
6919 goto err_out;
6920 }
6921
6922 /* Anti gcc 2.95.3 bugware (sic) */
6923 status = opts[0] | len |
6924 (RingEnd * !((entry + 1) % NUM_TX_DESC));
6925
6926 txd->opts1 = cpu_to_le32(status);
6927 txd->opts2 = cpu_to_le32(opts[1]);
6928 txd->addr = cpu_to_le64(mapping);
6929
6930 tp->tx_skb[entry].len = len;
6931 }
6932
6933 if (cur_frag) {
6934 tp->tx_skb[entry].skb = skb;
6935 txd->opts1 |= cpu_to_le32(LastFrag);
6936 }
6937
6938 return cur_frag;
6939
6940 err_out:
6941 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6942 return -EIO;
6943 }
6944
6945 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6946 {
6947 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6948 }
6949
6950 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6951 struct net_device *dev);
6952 /* r8169_csum_workaround()
6953 * The hw limites the value the transport offset. When the offset is out of the
6954 * range, calculate the checksum by sw.
6955 */
6956 static void r8169_csum_workaround(struct rtl8169_private *tp,
6957 struct sk_buff *skb)
6958 {
6959 if (skb_shinfo(skb)->gso_size) {
6960 netdev_features_t features = tp->dev->features;
6961 struct sk_buff *segs, *nskb;
6962
6963 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6964 segs = skb_gso_segment(skb, features);
6965 if (IS_ERR(segs) || !segs)
6966 goto drop;
6967
6968 do {
6969 nskb = segs;
6970 segs = segs->next;
6971 nskb->next = NULL;
6972 rtl8169_start_xmit(nskb, tp->dev);
6973 } while (segs);
6974
6975 dev_consume_skb_any(skb);
6976 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6977 if (skb_checksum_help(skb) < 0)
6978 goto drop;
6979
6980 rtl8169_start_xmit(skb, tp->dev);
6981 } else {
6982 struct net_device_stats *stats;
6983
6984 drop:
6985 stats = &tp->dev->stats;
6986 stats->tx_dropped++;
6987 dev_kfree_skb_any(skb);
6988 }
6989 }
6990
6991 /* msdn_giant_send_check()
6992 * According to the document of microsoft, the TCP Pseudo Header excludes the
6993 * packet length for IPv6 TCP large packets.
6994 */
6995 static int msdn_giant_send_check(struct sk_buff *skb)
6996 {
6997 const struct ipv6hdr *ipv6h;
6998 struct tcphdr *th;
6999 int ret;
7000
7001 ret = skb_cow_head(skb, 0);
7002 if (ret)
7003 return ret;
7004
7005 ipv6h = ipv6_hdr(skb);
7006 th = tcp_hdr(skb);
7007
7008 th->check = 0;
7009 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
7010
7011 return ret;
7012 }
7013
7014 static inline __be16 get_protocol(struct sk_buff *skb)
7015 {
7016 __be16 protocol;
7017
7018 if (skb->protocol == htons(ETH_P_8021Q))
7019 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
7020 else
7021 protocol = skb->protocol;
7022
7023 return protocol;
7024 }
7025
7026 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
7027 struct sk_buff *skb, u32 *opts)
7028 {
7029 u32 mss = skb_shinfo(skb)->gso_size;
7030
7031 if (mss) {
7032 opts[0] |= TD_LSO;
7033 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
7034 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7035 const struct iphdr *ip = ip_hdr(skb);
7036
7037 if (ip->protocol == IPPROTO_TCP)
7038 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
7039 else if (ip->protocol == IPPROTO_UDP)
7040 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
7041 else
7042 WARN_ON_ONCE(1);
7043 }
7044
7045 return true;
7046 }
7047
7048 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
7049 struct sk_buff *skb, u32 *opts)
7050 {
7051 u32 transport_offset = (u32)skb_transport_offset(skb);
7052 u32 mss = skb_shinfo(skb)->gso_size;
7053
7054 if (mss) {
7055 if (transport_offset > GTTCPHO_MAX) {
7056 netif_warn(tp, tx_err, tp->dev,
7057 "Invalid transport offset 0x%x for TSO\n",
7058 transport_offset);
7059 return false;
7060 }
7061
7062 switch (get_protocol(skb)) {
7063 case htons(ETH_P_IP):
7064 opts[0] |= TD1_GTSENV4;
7065 break;
7066
7067 case htons(ETH_P_IPV6):
7068 if (msdn_giant_send_check(skb))
7069 return false;
7070
7071 opts[0] |= TD1_GTSENV6;
7072 break;
7073
7074 default:
7075 WARN_ON_ONCE(1);
7076 break;
7077 }
7078
7079 opts[0] |= transport_offset << GTTCPHO_SHIFT;
7080 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
7081 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7082 u8 ip_protocol;
7083
7084 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
7085 return !(skb_checksum_help(skb) || eth_skb_pad(skb));
7086
7087 if (transport_offset > TCPHO_MAX) {
7088 netif_warn(tp, tx_err, tp->dev,
7089 "Invalid transport offset 0x%x\n",
7090 transport_offset);
7091 return false;
7092 }
7093
7094 switch (get_protocol(skb)) {
7095 case htons(ETH_P_IP):
7096 opts[1] |= TD1_IPv4_CS;
7097 ip_protocol = ip_hdr(skb)->protocol;
7098 break;
7099
7100 case htons(ETH_P_IPV6):
7101 opts[1] |= TD1_IPv6_CS;
7102 ip_protocol = ipv6_hdr(skb)->nexthdr;
7103 break;
7104
7105 default:
7106 ip_protocol = IPPROTO_RAW;
7107 break;
7108 }
7109
7110 if (ip_protocol == IPPROTO_TCP)
7111 opts[1] |= TD1_TCP_CS;
7112 else if (ip_protocol == IPPROTO_UDP)
7113 opts[1] |= TD1_UDP_CS;
7114 else
7115 WARN_ON_ONCE(1);
7116
7117 opts[1] |= transport_offset << TCPHO_SHIFT;
7118 } else {
7119 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
7120 return !eth_skb_pad(skb);
7121 }
7122
7123 return true;
7124 }
7125
7126 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
7127 struct net_device *dev)
7128 {
7129 struct rtl8169_private *tp = netdev_priv(dev);
7130 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
7131 struct TxDesc *txd = tp->TxDescArray + entry;
7132 void __iomem *ioaddr = tp->mmio_addr;
7133 struct device *d = &tp->pci_dev->dev;
7134 dma_addr_t mapping;
7135 u32 status, len;
7136 u32 opts[2];
7137 int frags;
7138
7139 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
7140 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
7141 goto err_stop_0;
7142 }
7143
7144 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
7145 goto err_stop_0;
7146
7147 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
7148 opts[0] = DescOwn;
7149
7150 if (!tp->tso_csum(tp, skb, opts)) {
7151 r8169_csum_workaround(tp, skb);
7152 return NETDEV_TX_OK;
7153 }
7154
7155 len = skb_headlen(skb);
7156 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
7157 if (unlikely(dma_mapping_error(d, mapping))) {
7158 if (net_ratelimit())
7159 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
7160 goto err_dma_0;
7161 }
7162
7163 tp->tx_skb[entry].len = len;
7164 txd->addr = cpu_to_le64(mapping);
7165
7166 frags = rtl8169_xmit_frags(tp, skb, opts);
7167 if (frags < 0)
7168 goto err_dma_1;
7169 else if (frags)
7170 opts[0] |= FirstFrag;
7171 else {
7172 opts[0] |= FirstFrag | LastFrag;
7173 tp->tx_skb[entry].skb = skb;
7174 }
7175
7176 txd->opts2 = cpu_to_le32(opts[1]);
7177
7178 skb_tx_timestamp(skb);
7179
7180 /* Force memory writes to complete before releasing descriptor */
7181 dma_wmb();
7182
7183 /* Anti gcc 2.95.3 bugware (sic) */
7184 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
7185 txd->opts1 = cpu_to_le32(status);
7186
7187 /* Force all memory writes to complete before notifying device */
7188 wmb();
7189
7190 tp->cur_tx += frags + 1;
7191
7192 RTL_W8(TxPoll, NPQ);
7193
7194 mmiowb();
7195
7196 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7197 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
7198 * not miss a ring update when it notices a stopped queue.
7199 */
7200 smp_wmb();
7201 netif_stop_queue(dev);
7202 /* Sync with rtl_tx:
7203 * - publish queue status and cur_tx ring index (write barrier)
7204 * - refresh dirty_tx ring index (read barrier).
7205 * May the current thread have a pessimistic view of the ring
7206 * status and forget to wake up queue, a racing rtl_tx thread
7207 * can't.
7208 */
7209 smp_mb();
7210 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
7211 netif_wake_queue(dev);
7212 }
7213
7214 return NETDEV_TX_OK;
7215
7216 err_dma_1:
7217 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
7218 err_dma_0:
7219 dev_kfree_skb_any(skb);
7220 dev->stats.tx_dropped++;
7221 return NETDEV_TX_OK;
7222
7223 err_stop_0:
7224 netif_stop_queue(dev);
7225 dev->stats.tx_dropped++;
7226 return NETDEV_TX_BUSY;
7227 }
7228
7229 static void rtl8169_pcierr_interrupt(struct net_device *dev)
7230 {
7231 struct rtl8169_private *tp = netdev_priv(dev);
7232 struct pci_dev *pdev = tp->pci_dev;
7233 u16 pci_status, pci_cmd;
7234
7235 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
7236 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
7237
7238 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
7239 pci_cmd, pci_status);
7240
7241 /*
7242 * The recovery sequence below admits a very elaborated explanation:
7243 * - it seems to work;
7244 * - I did not see what else could be done;
7245 * - it makes iop3xx happy.
7246 *
7247 * Feel free to adjust to your needs.
7248 */
7249 if (pdev->broken_parity_status)
7250 pci_cmd &= ~PCI_COMMAND_PARITY;
7251 else
7252 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
7253
7254 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
7255
7256 pci_write_config_word(pdev, PCI_STATUS,
7257 pci_status & (PCI_STATUS_DETECTED_PARITY |
7258 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
7259 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
7260
7261 /* The infamous DAC f*ckup only happens at boot time */
7262 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
7263 void __iomem *ioaddr = tp->mmio_addr;
7264
7265 netif_info(tp, intr, dev, "disabling PCI DAC\n");
7266 tp->cp_cmd &= ~PCIDAC;
7267 RTL_W16(CPlusCmd, tp->cp_cmd);
7268 dev->features &= ~NETIF_F_HIGHDMA;
7269 }
7270
7271 rtl8169_hw_reset(tp);
7272
7273 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7274 }
7275
7276 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
7277 {
7278 unsigned int dirty_tx, tx_left;
7279
7280 dirty_tx = tp->dirty_tx;
7281 smp_rmb();
7282 tx_left = tp->cur_tx - dirty_tx;
7283
7284 while (tx_left > 0) {
7285 unsigned int entry = dirty_tx % NUM_TX_DESC;
7286 struct ring_info *tx_skb = tp->tx_skb + entry;
7287 u32 status;
7288
7289 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
7290 if (status & DescOwn)
7291 break;
7292
7293 /* This barrier is needed to keep us from reading
7294 * any other fields out of the Tx descriptor until
7295 * we know the status of DescOwn
7296 */
7297 dma_rmb();
7298
7299 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
7300 tp->TxDescArray + entry);
7301 if (status & LastFrag) {
7302 u64_stats_update_begin(&tp->tx_stats.syncp);
7303 tp->tx_stats.packets++;
7304 tp->tx_stats.bytes += tx_skb->skb->len;
7305 u64_stats_update_end(&tp->tx_stats.syncp);
7306 dev_kfree_skb_any(tx_skb->skb);
7307 tx_skb->skb = NULL;
7308 }
7309 dirty_tx++;
7310 tx_left--;
7311 }
7312
7313 if (tp->dirty_tx != dirty_tx) {
7314 tp->dirty_tx = dirty_tx;
7315 /* Sync with rtl8169_start_xmit:
7316 * - publish dirty_tx ring index (write barrier)
7317 * - refresh cur_tx ring index and queue status (read barrier)
7318 * May the current thread miss the stopped queue condition,
7319 * a racing xmit thread can only have a right view of the
7320 * ring status.
7321 */
7322 smp_mb();
7323 if (netif_queue_stopped(dev) &&
7324 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7325 netif_wake_queue(dev);
7326 }
7327 /*
7328 * 8168 hack: TxPoll requests are lost when the Tx packets are
7329 * too close. Let's kick an extra TxPoll request when a burst
7330 * of start_xmit activity is detected (if it is not detected,
7331 * it is slow enough). -- FR
7332 */
7333 if (tp->cur_tx != dirty_tx) {
7334 void __iomem *ioaddr = tp->mmio_addr;
7335
7336 RTL_W8(TxPoll, NPQ);
7337 }
7338 }
7339 }
7340
7341 static inline int rtl8169_fragmented_frame(u32 status)
7342 {
7343 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
7344 }
7345
7346 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
7347 {
7348 u32 status = opts1 & RxProtoMask;
7349
7350 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
7351 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
7352 skb->ip_summed = CHECKSUM_UNNECESSARY;
7353 else
7354 skb_checksum_none_assert(skb);
7355 }
7356
7357 static struct sk_buff *rtl8169_try_rx_copy(void *data,
7358 struct rtl8169_private *tp,
7359 int pkt_size,
7360 dma_addr_t addr)
7361 {
7362 struct sk_buff *skb;
7363 struct device *d = &tp->pci_dev->dev;
7364
7365 data = rtl8169_align(data);
7366 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
7367 prefetch(data);
7368 skb = napi_alloc_skb(&tp->napi, pkt_size);
7369 if (skb)
7370 memcpy(skb->data, data, pkt_size);
7371 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
7372
7373 return skb;
7374 }
7375
7376 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
7377 {
7378 unsigned int cur_rx, rx_left;
7379 unsigned int count;
7380
7381 cur_rx = tp->cur_rx;
7382
7383 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
7384 unsigned int entry = cur_rx % NUM_RX_DESC;
7385 struct RxDesc *desc = tp->RxDescArray + entry;
7386 u32 status;
7387
7388 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
7389 if (status & DescOwn)
7390 break;
7391
7392 /* This barrier is needed to keep us from reading
7393 * any other fields out of the Rx descriptor until
7394 * we know the status of DescOwn
7395 */
7396 dma_rmb();
7397
7398 if (unlikely(status & RxRES)) {
7399 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
7400 status);
7401 dev->stats.rx_errors++;
7402 if (status & (RxRWT | RxRUNT))
7403 dev->stats.rx_length_errors++;
7404 if (status & RxCRC)
7405 dev->stats.rx_crc_errors++;
7406 if (status & RxFOVF) {
7407 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7408 dev->stats.rx_fifo_errors++;
7409 }
7410 if ((status & (RxRUNT | RxCRC)) &&
7411 !(status & (RxRWT | RxFOVF)) &&
7412 (dev->features & NETIF_F_RXALL))
7413 goto process_pkt;
7414 } else {
7415 struct sk_buff *skb;
7416 dma_addr_t addr;
7417 int pkt_size;
7418
7419 process_pkt:
7420 addr = le64_to_cpu(desc->addr);
7421 if (likely(!(dev->features & NETIF_F_RXFCS)))
7422 pkt_size = (status & 0x00003fff) - 4;
7423 else
7424 pkt_size = status & 0x00003fff;
7425
7426 /*
7427 * The driver does not support incoming fragmented
7428 * frames. They are seen as a symptom of over-mtu
7429 * sized frames.
7430 */
7431 if (unlikely(rtl8169_fragmented_frame(status))) {
7432 dev->stats.rx_dropped++;
7433 dev->stats.rx_length_errors++;
7434 goto release_descriptor;
7435 }
7436
7437 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
7438 tp, pkt_size, addr);
7439 if (!skb) {
7440 dev->stats.rx_dropped++;
7441 goto release_descriptor;
7442 }
7443
7444 rtl8169_rx_csum(skb, status);
7445 skb_put(skb, pkt_size);
7446 skb->protocol = eth_type_trans(skb, dev);
7447
7448 rtl8169_rx_vlan_tag(desc, skb);
7449
7450 if (skb->pkt_type == PACKET_MULTICAST)
7451 dev->stats.multicast++;
7452
7453 napi_gro_receive(&tp->napi, skb);
7454
7455 u64_stats_update_begin(&tp->rx_stats.syncp);
7456 tp->rx_stats.packets++;
7457 tp->rx_stats.bytes += pkt_size;
7458 u64_stats_update_end(&tp->rx_stats.syncp);
7459 }
7460 release_descriptor:
7461 desc->opts2 = 0;
7462 rtl8169_mark_to_asic(desc, rx_buf_sz);
7463 }
7464
7465 count = cur_rx - tp->cur_rx;
7466 tp->cur_rx = cur_rx;
7467
7468 return count;
7469 }
7470
7471 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
7472 {
7473 struct net_device *dev = dev_instance;
7474 struct rtl8169_private *tp = netdev_priv(dev);
7475 int handled = 0;
7476 u16 status;
7477
7478 status = rtl_get_events(tp);
7479 if (status && status != 0xffff) {
7480 status &= RTL_EVENT_NAPI | tp->event_slow;
7481 if (status) {
7482 handled = 1;
7483
7484 rtl_irq_disable(tp);
7485 napi_schedule(&tp->napi);
7486 }
7487 }
7488 return IRQ_RETVAL(handled);
7489 }
7490
7491 /*
7492 * Workqueue context.
7493 */
7494 static void rtl_slow_event_work(struct rtl8169_private *tp)
7495 {
7496 struct net_device *dev = tp->dev;
7497 u16 status;
7498
7499 status = rtl_get_events(tp) & tp->event_slow;
7500 rtl_ack_events(tp, status);
7501
7502 if (unlikely(status & RxFIFOOver)) {
7503 switch (tp->mac_version) {
7504 /* Work around for rx fifo overflow */
7505 case RTL_GIGA_MAC_VER_11:
7506 netif_stop_queue(dev);
7507 /* XXX - Hack alert. See rtl_task(). */
7508 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
7509 default:
7510 break;
7511 }
7512 }
7513
7514 if (unlikely(status & SYSErr))
7515 rtl8169_pcierr_interrupt(dev);
7516
7517 if (status & LinkChg)
7518 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
7519
7520 rtl_irq_enable_all(tp);
7521 }
7522
7523 static void rtl_task(struct work_struct *work)
7524 {
7525 static const struct {
7526 int bitnr;
7527 void (*action)(struct rtl8169_private *);
7528 } rtl_work[] = {
7529 /* XXX - keep rtl_slow_event_work() as first element. */
7530 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
7531 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
7532 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
7533 };
7534 struct rtl8169_private *tp =
7535 container_of(work, struct rtl8169_private, wk.work);
7536 struct net_device *dev = tp->dev;
7537 int i;
7538
7539 rtl_lock_work(tp);
7540
7541 if (!netif_running(dev) ||
7542 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
7543 goto out_unlock;
7544
7545 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
7546 bool pending;
7547
7548 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
7549 if (pending)
7550 rtl_work[i].action(tp);
7551 }
7552
7553 out_unlock:
7554 rtl_unlock_work(tp);
7555 }
7556
7557 static int rtl8169_poll(struct napi_struct *napi, int budget)
7558 {
7559 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
7560 struct net_device *dev = tp->dev;
7561 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
7562 int work_done= 0;
7563 u16 status;
7564
7565 status = rtl_get_events(tp);
7566 rtl_ack_events(tp, status & ~tp->event_slow);
7567
7568 if (status & RTL_EVENT_NAPI_RX)
7569 work_done = rtl_rx(dev, tp, (u32) budget);
7570
7571 if (status & RTL_EVENT_NAPI_TX)
7572 rtl_tx(dev, tp);
7573
7574 if (status & tp->event_slow) {
7575 enable_mask &= ~tp->event_slow;
7576
7577 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
7578 }
7579
7580 if (work_done < budget) {
7581 napi_complete(napi);
7582
7583 rtl_irq_enable(tp, enable_mask);
7584 mmiowb();
7585 }
7586
7587 return work_done;
7588 }
7589
7590 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
7591 {
7592 struct rtl8169_private *tp = netdev_priv(dev);
7593
7594 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
7595 return;
7596
7597 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
7598 RTL_W32(RxMissed, 0);
7599 }
7600
7601 static void rtl8169_down(struct net_device *dev)
7602 {
7603 struct rtl8169_private *tp = netdev_priv(dev);
7604 void __iomem *ioaddr = tp->mmio_addr;
7605
7606 del_timer_sync(&tp->timer);
7607
7608 napi_disable(&tp->napi);
7609 netif_stop_queue(dev);
7610
7611 rtl8169_hw_reset(tp);
7612 /*
7613 * At this point device interrupts can not be enabled in any function,
7614 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
7615 * and napi is disabled (rtl8169_poll).
7616 */
7617 rtl8169_rx_missed(dev, ioaddr);
7618
7619 /* Give a racing hard_start_xmit a few cycles to complete. */
7620 synchronize_sched();
7621
7622 rtl8169_tx_clear(tp);
7623
7624 rtl8169_rx_clear(tp);
7625
7626 rtl_pll_power_down(tp);
7627 }
7628
7629 static int rtl8169_close(struct net_device *dev)
7630 {
7631 struct rtl8169_private *tp = netdev_priv(dev);
7632 struct pci_dev *pdev = tp->pci_dev;
7633
7634 pm_runtime_get_sync(&pdev->dev);
7635
7636 /* Update counters before going down */
7637 rtl8169_update_counters(dev);
7638
7639 rtl_lock_work(tp);
7640 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7641
7642 rtl8169_down(dev);
7643 rtl_unlock_work(tp);
7644
7645 cancel_work_sync(&tp->wk.work);
7646
7647 free_irq(pdev->irq, dev);
7648
7649 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7650 tp->RxPhyAddr);
7651 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7652 tp->TxPhyAddr);
7653 tp->TxDescArray = NULL;
7654 tp->RxDescArray = NULL;
7655
7656 pm_runtime_put_sync(&pdev->dev);
7657
7658 return 0;
7659 }
7660
7661 #ifdef CONFIG_NET_POLL_CONTROLLER
7662 static void rtl8169_netpoll(struct net_device *dev)
7663 {
7664 struct rtl8169_private *tp = netdev_priv(dev);
7665
7666 rtl8169_interrupt(tp->pci_dev->irq, dev);
7667 }
7668 #endif
7669
7670 static int rtl_open(struct net_device *dev)
7671 {
7672 struct rtl8169_private *tp = netdev_priv(dev);
7673 void __iomem *ioaddr = tp->mmio_addr;
7674 struct pci_dev *pdev = tp->pci_dev;
7675 int retval = -ENOMEM;
7676
7677 pm_runtime_get_sync(&pdev->dev);
7678
7679 /*
7680 * Rx and Tx descriptors needs 256 bytes alignment.
7681 * dma_alloc_coherent provides more.
7682 */
7683 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
7684 &tp->TxPhyAddr, GFP_KERNEL);
7685 if (!tp->TxDescArray)
7686 goto err_pm_runtime_put;
7687
7688 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
7689 &tp->RxPhyAddr, GFP_KERNEL);
7690 if (!tp->RxDescArray)
7691 goto err_free_tx_0;
7692
7693 retval = rtl8169_init_ring(dev);
7694 if (retval < 0)
7695 goto err_free_rx_1;
7696
7697 INIT_WORK(&tp->wk.work, rtl_task);
7698
7699 smp_mb();
7700
7701 rtl_request_firmware(tp);
7702
7703 retval = request_irq(pdev->irq, rtl8169_interrupt,
7704 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
7705 dev->name, dev);
7706 if (retval < 0)
7707 goto err_release_fw_2;
7708
7709 rtl_lock_work(tp);
7710
7711 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7712
7713 napi_enable(&tp->napi);
7714
7715 rtl8169_init_phy(dev, tp);
7716
7717 __rtl8169_set_features(dev, dev->features);
7718
7719 rtl_pll_power_up(tp);
7720
7721 rtl_hw_start(dev);
7722
7723 if (!rtl8169_init_counter_offsets(dev))
7724 netif_warn(tp, hw, dev, "counter reset/update failed\n");
7725
7726 netif_start_queue(dev);
7727
7728 rtl_unlock_work(tp);
7729
7730 tp->saved_wolopts = 0;
7731 pm_runtime_put_noidle(&pdev->dev);
7732
7733 rtl8169_check_link_status(dev, tp, ioaddr);
7734 out:
7735 return retval;
7736
7737 err_release_fw_2:
7738 rtl_release_firmware(tp);
7739 rtl8169_rx_clear(tp);
7740 err_free_rx_1:
7741 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7742 tp->RxPhyAddr);
7743 tp->RxDescArray = NULL;
7744 err_free_tx_0:
7745 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7746 tp->TxPhyAddr);
7747 tp->TxDescArray = NULL;
7748 err_pm_runtime_put:
7749 pm_runtime_put_noidle(&pdev->dev);
7750 goto out;
7751 }
7752
7753 static struct rtnl_link_stats64 *
7754 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
7755 {
7756 struct rtl8169_private *tp = netdev_priv(dev);
7757 void __iomem *ioaddr = tp->mmio_addr;
7758 struct pci_dev *pdev = tp->pci_dev;
7759 struct rtl8169_counters *counters = tp->counters;
7760 unsigned int start;
7761
7762 pm_runtime_get_noresume(&pdev->dev);
7763
7764 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
7765 rtl8169_rx_missed(dev, ioaddr);
7766
7767 do {
7768 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
7769 stats->rx_packets = tp->rx_stats.packets;
7770 stats->rx_bytes = tp->rx_stats.bytes;
7771 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
7772
7773 do {
7774 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
7775 stats->tx_packets = tp->tx_stats.packets;
7776 stats->tx_bytes = tp->tx_stats.bytes;
7777 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
7778
7779 stats->rx_dropped = dev->stats.rx_dropped;
7780 stats->tx_dropped = dev->stats.tx_dropped;
7781 stats->rx_length_errors = dev->stats.rx_length_errors;
7782 stats->rx_errors = dev->stats.rx_errors;
7783 stats->rx_crc_errors = dev->stats.rx_crc_errors;
7784 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
7785 stats->rx_missed_errors = dev->stats.rx_missed_errors;
7786 stats->multicast = dev->stats.multicast;
7787
7788 /*
7789 * Fetch additonal counter values missing in stats collected by driver
7790 * from tally counters.
7791 */
7792 if (pm_runtime_active(&pdev->dev))
7793 rtl8169_update_counters(dev);
7794
7795 /*
7796 * Subtract values fetched during initalization.
7797 * See rtl8169_init_counter_offsets for a description why we do that.
7798 */
7799 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
7800 le64_to_cpu(tp->tc_offset.tx_errors);
7801 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
7802 le32_to_cpu(tp->tc_offset.tx_multi_collision);
7803 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
7804 le16_to_cpu(tp->tc_offset.tx_aborted);
7805
7806 pm_runtime_put_noidle(&pdev->dev);
7807
7808 return stats;
7809 }
7810
7811 static void rtl8169_net_suspend(struct net_device *dev)
7812 {
7813 struct rtl8169_private *tp = netdev_priv(dev);
7814
7815 if (!netif_running(dev))
7816 return;
7817
7818 netif_device_detach(dev);
7819 netif_stop_queue(dev);
7820
7821 rtl_lock_work(tp);
7822 napi_disable(&tp->napi);
7823 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7824 rtl_unlock_work(tp);
7825
7826 rtl_pll_power_down(tp);
7827 }
7828
7829 #ifdef CONFIG_PM
7830
7831 static int rtl8169_suspend(struct device *device)
7832 {
7833 struct pci_dev *pdev = to_pci_dev(device);
7834 struct net_device *dev = pci_get_drvdata(pdev);
7835
7836 rtl8169_net_suspend(dev);
7837
7838 return 0;
7839 }
7840
7841 static void __rtl8169_resume(struct net_device *dev)
7842 {
7843 struct rtl8169_private *tp = netdev_priv(dev);
7844
7845 netif_device_attach(dev);
7846
7847 rtl_pll_power_up(tp);
7848
7849 rtl_lock_work(tp);
7850 napi_enable(&tp->napi);
7851 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7852 rtl_unlock_work(tp);
7853
7854 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7855 }
7856
7857 static int rtl8169_resume(struct device *device)
7858 {
7859 struct pci_dev *pdev = to_pci_dev(device);
7860 struct net_device *dev = pci_get_drvdata(pdev);
7861 struct rtl8169_private *tp = netdev_priv(dev);
7862
7863 rtl8169_init_phy(dev, tp);
7864
7865 if (netif_running(dev))
7866 __rtl8169_resume(dev);
7867
7868 return 0;
7869 }
7870
7871 static int rtl8169_runtime_suspend(struct device *device)
7872 {
7873 struct pci_dev *pdev = to_pci_dev(device);
7874 struct net_device *dev = pci_get_drvdata(pdev);
7875 struct rtl8169_private *tp = netdev_priv(dev);
7876
7877 if (!tp->TxDescArray)
7878 return 0;
7879
7880 rtl_lock_work(tp);
7881 tp->saved_wolopts = __rtl8169_get_wol(tp);
7882 __rtl8169_set_wol(tp, WAKE_ANY);
7883 rtl_unlock_work(tp);
7884
7885 rtl8169_net_suspend(dev);
7886
7887 /* Update counters before going runtime suspend */
7888 rtl8169_rx_missed(dev, tp->mmio_addr);
7889 rtl8169_update_counters(dev);
7890
7891 return 0;
7892 }
7893
7894 static int rtl8169_runtime_resume(struct device *device)
7895 {
7896 struct pci_dev *pdev = to_pci_dev(device);
7897 struct net_device *dev = pci_get_drvdata(pdev);
7898 struct rtl8169_private *tp = netdev_priv(dev);
7899 rtl_rar_set(tp, dev->dev_addr);
7900
7901 if (!tp->TxDescArray)
7902 return 0;
7903
7904 rtl_lock_work(tp);
7905 __rtl8169_set_wol(tp, tp->saved_wolopts);
7906 tp->saved_wolopts = 0;
7907 rtl_unlock_work(tp);
7908
7909 rtl8169_init_phy(dev, tp);
7910
7911 __rtl8169_resume(dev);
7912
7913 return 0;
7914 }
7915
7916 static int rtl8169_runtime_idle(struct device *device)
7917 {
7918 struct pci_dev *pdev = to_pci_dev(device);
7919 struct net_device *dev = pci_get_drvdata(pdev);
7920 struct rtl8169_private *tp = netdev_priv(dev);
7921
7922 return tp->TxDescArray ? -EBUSY : 0;
7923 }
7924
7925 static const struct dev_pm_ops rtl8169_pm_ops = {
7926 .suspend = rtl8169_suspend,
7927 .resume = rtl8169_resume,
7928 .freeze = rtl8169_suspend,
7929 .thaw = rtl8169_resume,
7930 .poweroff = rtl8169_suspend,
7931 .restore = rtl8169_resume,
7932 .runtime_suspend = rtl8169_runtime_suspend,
7933 .runtime_resume = rtl8169_runtime_resume,
7934 .runtime_idle = rtl8169_runtime_idle,
7935 };
7936
7937 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
7938
7939 #else /* !CONFIG_PM */
7940
7941 #define RTL8169_PM_OPS NULL
7942
7943 #endif /* !CONFIG_PM */
7944
7945 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7946 {
7947 void __iomem *ioaddr = tp->mmio_addr;
7948
7949 /* WoL fails with 8168b when the receiver is disabled. */
7950 switch (tp->mac_version) {
7951 case RTL_GIGA_MAC_VER_11:
7952 case RTL_GIGA_MAC_VER_12:
7953 case RTL_GIGA_MAC_VER_17:
7954 pci_clear_master(tp->pci_dev);
7955
7956 RTL_W8(ChipCmd, CmdRxEnb);
7957 /* PCI commit */
7958 RTL_R8(ChipCmd);
7959 break;
7960 default:
7961 break;
7962 }
7963 }
7964
7965 static void rtl_shutdown(struct pci_dev *pdev)
7966 {
7967 struct net_device *dev = pci_get_drvdata(pdev);
7968 struct rtl8169_private *tp = netdev_priv(dev);
7969 struct device *d = &pdev->dev;
7970
7971 pm_runtime_get_sync(d);
7972
7973 rtl8169_net_suspend(dev);
7974
7975 /* Restore original MAC address */
7976 rtl_rar_set(tp, dev->perm_addr);
7977
7978 rtl8169_hw_reset(tp);
7979
7980 if (system_state == SYSTEM_POWER_OFF) {
7981 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
7982 rtl_wol_suspend_quirk(tp);
7983 rtl_wol_shutdown_quirk(tp);
7984 }
7985
7986 pci_wake_from_d3(pdev, true);
7987 pci_set_power_state(pdev, PCI_D3hot);
7988 }
7989
7990 pm_runtime_put_noidle(d);
7991 }
7992
7993 static void rtl_remove_one(struct pci_dev *pdev)
7994 {
7995 struct net_device *dev = pci_get_drvdata(pdev);
7996 struct rtl8169_private *tp = netdev_priv(dev);
7997
7998 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
7999 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
8000 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
8001 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8002 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8003 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
8004 r8168_check_dash(tp)) {
8005 rtl8168_driver_stop(tp);
8006 }
8007
8008 netif_napi_del(&tp->napi);
8009
8010 unregister_netdev(dev);
8011
8012 dma_free_coherent(&tp->pci_dev->dev, sizeof(*tp->counters),
8013 tp->counters, tp->counters_phys_addr);
8014
8015 rtl_release_firmware(tp);
8016
8017 if (pci_dev_run_wake(pdev))
8018 pm_runtime_get_noresume(&pdev->dev);
8019
8020 /* restore original MAC address */
8021 rtl_rar_set(tp, dev->perm_addr);
8022
8023 rtl_disable_msi(pdev, tp);
8024 rtl8169_release_board(pdev, dev, tp->mmio_addr);
8025 }
8026
8027 static const struct net_device_ops rtl_netdev_ops = {
8028 .ndo_open = rtl_open,
8029 .ndo_stop = rtl8169_close,
8030 .ndo_get_stats64 = rtl8169_get_stats64,
8031 .ndo_start_xmit = rtl8169_start_xmit,
8032 .ndo_tx_timeout = rtl8169_tx_timeout,
8033 .ndo_validate_addr = eth_validate_addr,
8034 .ndo_change_mtu = rtl8169_change_mtu,
8035 .ndo_fix_features = rtl8169_fix_features,
8036 .ndo_set_features = rtl8169_set_features,
8037 .ndo_set_mac_address = rtl_set_mac_address,
8038 .ndo_do_ioctl = rtl8169_ioctl,
8039 .ndo_set_rx_mode = rtl_set_rx_mode,
8040 #ifdef CONFIG_NET_POLL_CONTROLLER
8041 .ndo_poll_controller = rtl8169_netpoll,
8042 #endif
8043
8044 };
8045
8046 static const struct rtl_cfg_info {
8047 void (*hw_start)(struct net_device *);
8048 unsigned int region;
8049 unsigned int align;
8050 u16 event_slow;
8051 unsigned features;
8052 u8 default_ver;
8053 } rtl_cfg_infos [] = {
8054 [RTL_CFG_0] = {
8055 .hw_start = rtl_hw_start_8169,
8056 .region = 1,
8057 .align = 0,
8058 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
8059 .features = RTL_FEATURE_GMII,
8060 .default_ver = RTL_GIGA_MAC_VER_01,
8061 },
8062 [RTL_CFG_1] = {
8063 .hw_start = rtl_hw_start_8168,
8064 .region = 2,
8065 .align = 8,
8066 .event_slow = SYSErr | LinkChg | RxOverflow,
8067 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
8068 .default_ver = RTL_GIGA_MAC_VER_11,
8069 },
8070 [RTL_CFG_2] = {
8071 .hw_start = rtl_hw_start_8101,
8072 .region = 2,
8073 .align = 8,
8074 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
8075 PCSTimeout,
8076 .features = RTL_FEATURE_MSI,
8077 .default_ver = RTL_GIGA_MAC_VER_13,
8078 }
8079 };
8080
8081 /* Cfg9346_Unlock assumed. */
8082 static unsigned rtl_try_msi(struct rtl8169_private *tp,
8083 const struct rtl_cfg_info *cfg)
8084 {
8085 void __iomem *ioaddr = tp->mmio_addr;
8086 unsigned msi = 0;
8087 u8 cfg2;
8088
8089 cfg2 = RTL_R8(Config2) & ~MSIEnable;
8090 if (cfg->features & RTL_FEATURE_MSI) {
8091 if (pci_enable_msi(tp->pci_dev)) {
8092 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
8093 } else {
8094 cfg2 |= MSIEnable;
8095 msi = RTL_FEATURE_MSI;
8096 }
8097 }
8098 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
8099 RTL_W8(Config2, cfg2);
8100 return msi;
8101 }
8102
8103 DECLARE_RTL_COND(rtl_link_list_ready_cond)
8104 {
8105 void __iomem *ioaddr = tp->mmio_addr;
8106
8107 return RTL_R8(MCU) & LINK_LIST_RDY;
8108 }
8109
8110 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
8111 {
8112 void __iomem *ioaddr = tp->mmio_addr;
8113
8114 return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
8115 }
8116
8117 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
8118 {
8119 void __iomem *ioaddr = tp->mmio_addr;
8120 u32 data;
8121
8122 tp->ocp_base = OCP_STD_PHY_BASE;
8123
8124 RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
8125
8126 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
8127 return;
8128
8129 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
8130 return;
8131
8132 RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
8133 msleep(1);
8134 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
8135
8136 data = r8168_mac_ocp_read(tp, 0xe8de);
8137 data &= ~(1 << 14);
8138 r8168_mac_ocp_write(tp, 0xe8de, data);
8139
8140 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8141 return;
8142
8143 data = r8168_mac_ocp_read(tp, 0xe8de);
8144 data |= (1 << 15);
8145 r8168_mac_ocp_write(tp, 0xe8de, data);
8146
8147 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8148 return;
8149 }
8150
8151 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
8152 {
8153 rtl8168ep_stop_cmac(tp);
8154 rtl_hw_init_8168g(tp);
8155 }
8156
8157 static void rtl_hw_initialize(struct rtl8169_private *tp)
8158 {
8159 switch (tp->mac_version) {
8160 case RTL_GIGA_MAC_VER_40:
8161 case RTL_GIGA_MAC_VER_41:
8162 case RTL_GIGA_MAC_VER_42:
8163 case RTL_GIGA_MAC_VER_43:
8164 case RTL_GIGA_MAC_VER_44:
8165 case RTL_GIGA_MAC_VER_45:
8166 case RTL_GIGA_MAC_VER_46:
8167 case RTL_GIGA_MAC_VER_47:
8168 case RTL_GIGA_MAC_VER_48:
8169 rtl_hw_init_8168g(tp);
8170 break;
8171 case RTL_GIGA_MAC_VER_49:
8172 case RTL_GIGA_MAC_VER_50:
8173 case RTL_GIGA_MAC_VER_51:
8174 rtl_hw_init_8168ep(tp);
8175 break;
8176 default:
8177 break;
8178 }
8179 }
8180
8181 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8182 {
8183 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
8184 const unsigned int region = cfg->region;
8185 struct rtl8169_private *tp;
8186 struct mii_if_info *mii;
8187 struct net_device *dev;
8188 void __iomem *ioaddr;
8189 int chipset, i;
8190 int rc;
8191
8192 if (netif_msg_drv(&debug)) {
8193 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
8194 MODULENAME, RTL8169_VERSION);
8195 }
8196
8197 dev = alloc_etherdev(sizeof (*tp));
8198 if (!dev) {
8199 rc = -ENOMEM;
8200 goto out;
8201 }
8202
8203 SET_NETDEV_DEV(dev, &pdev->dev);
8204 dev->netdev_ops = &rtl_netdev_ops;
8205 tp = netdev_priv(dev);
8206 tp->dev = dev;
8207 tp->pci_dev = pdev;
8208 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
8209
8210 mii = &tp->mii;
8211 mii->dev = dev;
8212 mii->mdio_read = rtl_mdio_read;
8213 mii->mdio_write = rtl_mdio_write;
8214 mii->phy_id_mask = 0x1f;
8215 mii->reg_num_mask = 0x1f;
8216 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
8217
8218 /* disable ASPM completely as that cause random device stop working
8219 * problems as well as full system hangs for some PCIe devices users */
8220 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
8221 PCIE_LINK_STATE_CLKPM);
8222
8223 /* enable device (incl. PCI PM wakeup and hotplug setup) */
8224 rc = pci_enable_device(pdev);
8225 if (rc < 0) {
8226 netif_err(tp, probe, dev, "enable failure\n");
8227 goto err_out_free_dev_1;
8228 }
8229
8230 if (pci_set_mwi(pdev) < 0)
8231 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
8232
8233 /* make sure PCI base addr 1 is MMIO */
8234 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
8235 netif_err(tp, probe, dev,
8236 "region #%d not an MMIO resource, aborting\n",
8237 region);
8238 rc = -ENODEV;
8239 goto err_out_mwi_2;
8240 }
8241
8242 /* check for weird/broken PCI region reporting */
8243 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
8244 netif_err(tp, probe, dev,
8245 "Invalid PCI region size(s), aborting\n");
8246 rc = -ENODEV;
8247 goto err_out_mwi_2;
8248 }
8249
8250 rc = pci_request_regions(pdev, MODULENAME);
8251 if (rc < 0) {
8252 netif_err(tp, probe, dev, "could not request regions\n");
8253 goto err_out_mwi_2;
8254 }
8255
8256 /* ioremap MMIO region */
8257 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
8258 if (!ioaddr) {
8259 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
8260 rc = -EIO;
8261 goto err_out_free_res_3;
8262 }
8263 tp->mmio_addr = ioaddr;
8264
8265 if (!pci_is_pcie(pdev))
8266 netif_info(tp, probe, dev, "not PCI Express\n");
8267
8268 /* Identify chip attached to board */
8269 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
8270
8271 tp->cp_cmd = 0;
8272
8273 if ((sizeof(dma_addr_t) > 4) &&
8274 (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) &&
8275 tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
8276 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
8277
8278 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
8279 if (!pci_is_pcie(pdev))
8280 tp->cp_cmd |= PCIDAC;
8281 dev->features |= NETIF_F_HIGHDMA;
8282 } else {
8283 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8284 if (rc < 0) {
8285 netif_err(tp, probe, dev, "DMA configuration failed\n");
8286 goto err_out_unmap_4;
8287 }
8288 }
8289
8290 rtl_init_rxcfg(tp);
8291
8292 rtl_irq_disable(tp);
8293
8294 rtl_hw_initialize(tp);
8295
8296 rtl_hw_reset(tp);
8297
8298 rtl_ack_events(tp, 0xffff);
8299
8300 pci_set_master(pdev);
8301
8302 rtl_init_mdio_ops(tp);
8303 rtl_init_pll_power_ops(tp);
8304 rtl_init_jumbo_ops(tp);
8305 rtl_init_csi_ops(tp);
8306
8307 rtl8169_print_mac_version(tp);
8308
8309 chipset = tp->mac_version;
8310 tp->txd_version = rtl_chip_infos[chipset].txd_version;
8311
8312 RTL_W8(Cfg9346, Cfg9346_Unlock);
8313 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
8314 RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus));
8315 switch (tp->mac_version) {
8316 case RTL_GIGA_MAC_VER_34:
8317 case RTL_GIGA_MAC_VER_35:
8318 case RTL_GIGA_MAC_VER_36:
8319 case RTL_GIGA_MAC_VER_37:
8320 case RTL_GIGA_MAC_VER_38:
8321 case RTL_GIGA_MAC_VER_40:
8322 case RTL_GIGA_MAC_VER_41:
8323 case RTL_GIGA_MAC_VER_42:
8324 case RTL_GIGA_MAC_VER_43:
8325 case RTL_GIGA_MAC_VER_44:
8326 case RTL_GIGA_MAC_VER_45:
8327 case RTL_GIGA_MAC_VER_46:
8328 case RTL_GIGA_MAC_VER_47:
8329 case RTL_GIGA_MAC_VER_48:
8330 case RTL_GIGA_MAC_VER_49:
8331 case RTL_GIGA_MAC_VER_50:
8332 case RTL_GIGA_MAC_VER_51:
8333 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
8334 tp->features |= RTL_FEATURE_WOL;
8335 if ((RTL_R8(Config3) & LinkUp) != 0)
8336 tp->features |= RTL_FEATURE_WOL;
8337 break;
8338 default:
8339 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
8340 tp->features |= RTL_FEATURE_WOL;
8341 break;
8342 }
8343 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
8344 tp->features |= RTL_FEATURE_WOL;
8345 tp->features |= rtl_try_msi(tp, cfg);
8346 RTL_W8(Cfg9346, Cfg9346_Lock);
8347
8348 if (rtl_tbi_enabled(tp)) {
8349 tp->set_speed = rtl8169_set_speed_tbi;
8350 tp->get_settings = rtl8169_gset_tbi;
8351 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
8352 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
8353 tp->link_ok = rtl8169_tbi_link_ok;
8354 tp->do_ioctl = rtl_tbi_ioctl;
8355 } else {
8356 tp->set_speed = rtl8169_set_speed_xmii;
8357 tp->get_settings = rtl8169_gset_xmii;
8358 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
8359 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
8360 tp->link_ok = rtl8169_xmii_link_ok;
8361 tp->do_ioctl = rtl_xmii_ioctl;
8362 }
8363
8364 mutex_init(&tp->wk.mutex);
8365 u64_stats_init(&tp->rx_stats.syncp);
8366 u64_stats_init(&tp->tx_stats.syncp);
8367
8368 /* Get MAC address */
8369 if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
8370 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
8371 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
8372 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
8373 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
8374 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
8375 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
8376 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
8377 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
8378 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
8379 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
8380 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
8381 tp->mac_version == RTL_GIGA_MAC_VER_48 ||
8382 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8383 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8384 tp->mac_version == RTL_GIGA_MAC_VER_51) {
8385 u16 mac_addr[3];
8386
8387 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
8388 *(u16 *)&mac_addr[2] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
8389
8390 if (is_valid_ether_addr((u8 *)mac_addr))
8391 rtl_rar_set(tp, (u8 *)mac_addr);
8392 }
8393 for (i = 0; i < ETH_ALEN; i++)
8394 dev->dev_addr[i] = RTL_R8(MAC0 + i);
8395
8396 dev->ethtool_ops = &rtl8169_ethtool_ops;
8397 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
8398
8399 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
8400
8401 /* don't enable SG, IP_CSUM and TSO by default - it might not work
8402 * properly for all devices */
8403 dev->features |= NETIF_F_RXCSUM |
8404 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
8405
8406 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8407 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
8408 NETIF_F_HW_VLAN_CTAG_RX;
8409 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8410 NETIF_F_HIGHDMA;
8411
8412 tp->cp_cmd |= RxChkSum | RxVlan;
8413
8414 /*
8415 * Pretend we are using VLANs; This bypasses a nasty bug where
8416 * Interrupts stop flowing on high load on 8110SCd controllers.
8417 */
8418 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
8419 /* Disallow toggling */
8420 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
8421
8422 if (tp->txd_version == RTL_TD_0)
8423 tp->tso_csum = rtl8169_tso_csum_v1;
8424 else if (tp->txd_version == RTL_TD_1) {
8425 tp->tso_csum = rtl8169_tso_csum_v2;
8426 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
8427 } else
8428 WARN_ON_ONCE(1);
8429
8430 dev->hw_features |= NETIF_F_RXALL;
8431 dev->hw_features |= NETIF_F_RXFCS;
8432
8433 tp->hw_start = cfg->hw_start;
8434 tp->event_slow = cfg->event_slow;
8435
8436 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
8437 ~(RxBOVF | RxFOVF) : ~0;
8438
8439 init_timer(&tp->timer);
8440 tp->timer.data = (unsigned long) dev;
8441 tp->timer.function = rtl8169_phy_timer;
8442
8443 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
8444
8445 tp->counters = dma_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
8446 &tp->counters_phys_addr, GFP_KERNEL);
8447 if (!tp->counters) {
8448 rc = -ENOMEM;
8449 goto err_out_msi_5;
8450 }
8451
8452 rc = register_netdev(dev);
8453 if (rc < 0)
8454 goto err_out_cnt_6;
8455
8456 pci_set_drvdata(pdev, dev);
8457
8458 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
8459 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
8460 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
8461 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
8462 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
8463 "tx checksumming: %s]\n",
8464 rtl_chip_infos[chipset].jumbo_max,
8465 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
8466 }
8467
8468 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
8469 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
8470 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
8471 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8472 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8473 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
8474 r8168_check_dash(tp)) {
8475 rtl8168_driver_start(tp);
8476 }
8477
8478 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
8479
8480 if (pci_dev_run_wake(pdev))
8481 pm_runtime_put_noidle(&pdev->dev);
8482
8483 netif_carrier_off(dev);
8484
8485 out:
8486 return rc;
8487
8488 err_out_cnt_6:
8489 dma_free_coherent(&pdev->dev, sizeof(*tp->counters), tp->counters,
8490 tp->counters_phys_addr);
8491 err_out_msi_5:
8492 netif_napi_del(&tp->napi);
8493 rtl_disable_msi(pdev, tp);
8494 err_out_unmap_4:
8495 iounmap(ioaddr);
8496 err_out_free_res_3:
8497 pci_release_regions(pdev);
8498 err_out_mwi_2:
8499 pci_clear_mwi(pdev);
8500 pci_disable_device(pdev);
8501 err_out_free_dev_1:
8502 free_netdev(dev);
8503 goto out;
8504 }
8505
8506 static struct pci_driver rtl8169_pci_driver = {
8507 .name = MODULENAME,
8508 .id_table = rtl8169_pci_tbl,
8509 .probe = rtl_init_one,
8510 .remove = rtl_remove_one,
8511 .shutdown = rtl_shutdown,
8512 .driver.pm = RTL8169_PM_OPS,
8513 };
8514
8515 module_pci_driver(rtl8169_pci_driver);
CRIS linux kernel tree