drivers/net/ethernet/stmicro/stmmac/dwmac4.h

   1 /*
   2  * DWMAC4 Header file.
   3  *
   4  * Copyright (C) 2015  STMicroelectronics Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * Author: Alexandre Torgue <alexandre.torgue@st.com>
  11  */
  12
  13 #ifndef __DWMAC4_H__
  14 #define __DWMAC4_H__
  15
  16 #include "common.h"
  17
  18 /*  MAC registers */
  19 #define GMAC_CONFIG                     0x00000000
  20 #define GMAC_PACKET_FILTER              0x00000008
  21 #define GMAC_HASH_TAB_0_31              0x00000010
  22 #define GMAC_HASH_TAB_32_63             0x00000014
  23 #define GMAC_RX_FLOW_CTRL               0x00000090
  24 #define GMAC_QX_TX_FLOW_CTRL(x)         (0x70 + x * 4)
  25 #define GMAC_INT_STATUS                 0x000000b0
  26 #define GMAC_INT_EN                     0x000000b4
  27 #define GMAC_PCS_BASE                   0x000000e0
  28 #define GMAC_PHYIF_CONTROL_STATUS       0x000000f8
  29 #define GMAC_PMT                        0x000000c0
  30 #define GMAC_VERSION                    0x00000110
  31 #define GMAC_DEBUG                      0x00000114
  32 #define GMAC_HW_FEATURE0                0x0000011c
  33 #define GMAC_HW_FEATURE1                0x00000120
  34 #define GMAC_HW_FEATURE2                0x00000124
  35 #define GMAC_MDIO_ADDR                  0x00000200
  36 #define GMAC_MDIO_DATA                  0x00000204
  37 #define GMAC_ADDR_HIGH(reg)             (0x300 + reg * 8)
  38 #define GMAC_ADDR_LOW(reg)              (0x304 + reg * 8)
  39
  40 /* MAC Packet Filtering */
  41 #define GMAC_PACKET_FILTER_PR           BIT(0)
  42 #define GMAC_PACKET_FILTER_HMC          BIT(2)
  43 #define GMAC_PACKET_FILTER_PM           BIT(4)
  44
  45 #define GMAC_MAX_PERFECT_ADDRESSES      128
  46
  47 /* MAC Flow Control RX */
  48 #define GMAC_RX_FLOW_CTRL_RFE           BIT(0)
  49
  50 /* MAC Flow Control TX */
  51 #define GMAC_TX_FLOW_CTRL_TFE           BIT(1)
  52 #define GMAC_TX_FLOW_CTRL_PT_SHIFT      16
  53
  54 /*  MAC Interrupt bitmap*/
  55 #define GMAC_INT_RGSMIIS                BIT(0)
  56 #define GMAC_INT_PCS_LINK               BIT(1)
  57 #define GMAC_INT_PCS_ANE                BIT(2)
  58 #define GMAC_INT_PCS_PHYIS              BIT(3)
  59 #define GMAC_INT_PMT_EN                 BIT(4)
  60 #define GMAC_INT_LPI_EN                 BIT(5)
  61
  62 #define GMAC_PCS_IRQ_DEFAULT    (GMAC_INT_RGSMIIS | GMAC_INT_PCS_LINK | \
  63                                  GMAC_INT_PCS_ANE)
  64
  65 #define GMAC_INT_DEFAULT_MASK   GMAC_INT_PMT_EN
  66
  67 enum dwmac4_irq_status {
  68         time_stamp_irq = 0x00001000,
  69         mmc_rx_csum_offload_irq = 0x00000800,
  70         mmc_tx_irq = 0x00000400,
  71         mmc_rx_irq = 0x00000200,
  72         mmc_irq = 0x00000100,
  73         pmt_irq = 0x00000010,
  74 };
  75
  76 /* MAC PMT bitmap */
  77 enum power_event {
  78         pointer_reset = 0x80000000,
  79         global_unicast = 0x00000200,
  80         wake_up_rx_frame = 0x00000040,
  81         magic_frame = 0x00000020,
  82         wake_up_frame_en = 0x00000004,
  83         magic_pkt_en = 0x00000002,
  84         power_down = 0x00000001,
  85 };
  86
  87 /* MAC Debug bitmap */
  88 #define GMAC_DEBUG_TFCSTS_MASK          GENMASK(18, 17)
  89 #define GMAC_DEBUG_TFCSTS_SHIFT         17
  90 #define GMAC_DEBUG_TFCSTS_IDLE          0
  91 #define GMAC_DEBUG_TFCSTS_WAIT          1
  92 #define GMAC_DEBUG_TFCSTS_GEN_PAUSE     2
  93 #define GMAC_DEBUG_TFCSTS_XFER          3
  94 #define GMAC_DEBUG_TPESTS               BIT(16)
  95 #define GMAC_DEBUG_RFCFCSTS_MASK        GENMASK(2, 1)
  96 #define GMAC_DEBUG_RFCFCSTS_SHIFT       1
  97 #define GMAC_DEBUG_RPESTS               BIT(0)
  98
  99 /* MAC config */
 100 #define GMAC_CONFIG_IPC                 BIT(27)
 101 #define GMAC_CONFIG_2K                  BIT(22)
 102 #define GMAC_CONFIG_ACS                 BIT(20)
 103 #define GMAC_CONFIG_BE                  BIT(18)
 104 #define GMAC_CONFIG_JD                  BIT(17)
 105 #define GMAC_CONFIG_JE                  BIT(16)
 106 #define GMAC_CONFIG_PS                  BIT(15)
 107 #define GMAC_CONFIG_FES                 BIT(14)
 108 #define GMAC_CONFIG_DM                  BIT(13)
 109 #define GMAC_CONFIG_DCRS                BIT(9)
 110 #define GMAC_CONFIG_TE                  BIT(1)
 111 #define GMAC_CONFIG_RE                  BIT(0)
 112
 113 /* MAC HW features0 bitmap */
 114 #define GMAC_HW_FEAT_ADDMAC             BIT(18)
 115 #define GMAC_HW_FEAT_RXCOESEL           BIT(16)
 116 #define GMAC_HW_FEAT_TXCOSEL            BIT(14)
 117 #define GMAC_HW_FEAT_EEESEL             BIT(13)
 118 #define GMAC_HW_FEAT_TSSEL              BIT(12)
 119 #define GMAC_HW_FEAT_MMCSEL             BIT(8)
 120 #define GMAC_HW_FEAT_MGKSEL             BIT(7)
 121 #define GMAC_HW_FEAT_RWKSEL             BIT(6)
 122 #define GMAC_HW_FEAT_SMASEL             BIT(5)
 123 #define GMAC_HW_FEAT_VLHASH             BIT(4)
 124 #define GMAC_HW_FEAT_PCSSEL             BIT(3)
 125 #define GMAC_HW_FEAT_HDSEL              BIT(2)
 126 #define GMAC_HW_FEAT_GMIISEL            BIT(1)
 127 #define GMAC_HW_FEAT_MIISEL             BIT(0)
 128
 129 /* MAC HW features1 bitmap */
 130 #define GMAC_HW_FEAT_AVSEL              BIT(20)
 131 #define GMAC_HW_TSOEN                   BIT(18)
 132
 133 /* MAC HW features2 bitmap */
 134 #define GMAC_HW_FEAT_TXCHCNT            GENMASK(21, 18)
 135 #define GMAC_HW_FEAT_RXCHCNT            GENMASK(15, 12)
 136
 137 /* MAC HW ADDR regs */
 138 #define GMAC_HI_DCS                     GENMASK(18, 16)
 139 #define GMAC_HI_DCS_SHIFT               16
 140 #define GMAC_HI_REG_AE                  BIT(31)
 141
 142 /*  MTL registers */
 143 #define MTL_INT_STATUS                  0x00000c20
 144 #define MTL_INT_Q0                      BIT(0)
 145
 146 #define MTL_CHAN_BASE_ADDR              0x00000d00
 147 #define MTL_CHAN_BASE_OFFSET            0x40
 148 #define MTL_CHANX_BASE_ADDR(x)          (MTL_CHAN_BASE_ADDR + \
 149                                         (x * MTL_CHAN_BASE_OFFSET))
 150
 151 #define MTL_CHAN_TX_OP_MODE(x)          MTL_CHANX_BASE_ADDR(x)
 152 #define MTL_CHAN_TX_DEBUG(x)            (MTL_CHANX_BASE_ADDR(x) + 0x8)
 153 #define MTL_CHAN_INT_CTRL(x)            (MTL_CHANX_BASE_ADDR(x) + 0x2c)
 154 #define MTL_CHAN_RX_OP_MODE(x)          (MTL_CHANX_BASE_ADDR(x) + 0x30)
 155 #define MTL_CHAN_RX_DEBUG(x)            (MTL_CHANX_BASE_ADDR(x) + 0x38)
 156
 157 #define MTL_OP_MODE_RSF                 BIT(5)
 158 #define MTL_OP_MODE_TSF                 BIT(1)
 159
 160 #define MTL_OP_MODE_TTC_MASK            0x70
 161 #define MTL_OP_MODE_TTC_SHIFT           4
 162
 163 #define MTL_OP_MODE_TTC_32              0
 164 #define MTL_OP_MODE_TTC_64              (1 << MTL_OP_MODE_TTC_SHIFT)
 165 #define MTL_OP_MODE_TTC_96              (2 << MTL_OP_MODE_TTC_SHIFT)
 166 #define MTL_OP_MODE_TTC_128             (3 << MTL_OP_MODE_TTC_SHIFT)
 167 #define MTL_OP_MODE_TTC_192             (4 << MTL_OP_MODE_TTC_SHIFT)
 168 #define MTL_OP_MODE_TTC_256             (5 << MTL_OP_MODE_TTC_SHIFT)
 169 #define MTL_OP_MODE_TTC_384             (6 << MTL_OP_MODE_TTC_SHIFT)
 170 #define MTL_OP_MODE_TTC_512             (7 << MTL_OP_MODE_TTC_SHIFT)
 171
 172 #define MTL_OP_MODE_RTC_MASK            0x18
 173 #define MTL_OP_MODE_RTC_SHIFT           3
 174
 175 #define MTL_OP_MODE_RTC_32              (1 << MTL_OP_MODE_RTC_SHIFT)
 176 #define MTL_OP_MODE_RTC_64              0
 177 #define MTL_OP_MODE_RTC_96              (2 << MTL_OP_MODE_RTC_SHIFT)
 178 #define MTL_OP_MODE_RTC_128             (3 << MTL_OP_MODE_RTC_SHIFT)
 179
 180 /*  MTL debug */
 181 #define MTL_DEBUG_TXSTSFSTS             BIT(5)
 182 #define MTL_DEBUG_TXFSTS                BIT(4)
 183 #define MTL_DEBUG_TWCSTS                BIT(3)
 184
 185 /* MTL debug: Tx FIFO Read Controller Status */
 186 #define MTL_DEBUG_TRCSTS_MASK           GENMASK(2, 1)
 187 #define MTL_DEBUG_TRCSTS_SHIFT          1
 188 #define MTL_DEBUG_TRCSTS_IDLE           0
 189 #define MTL_DEBUG_TRCSTS_READ           1
 190 #define MTL_DEBUG_TRCSTS_TXW            2
 191 #define MTL_DEBUG_TRCSTS_WRITE          3
 192 #define MTL_DEBUG_TXPAUSED              BIT(0)
 193
 194 /* MAC debug: GMII or MII Transmit Protocol Engine Status */
 195 #define MTL_DEBUG_RXFSTS_MASK           GENMASK(5, 4)
 196 #define MTL_DEBUG_RXFSTS_SHIFT          4
 197 #define MTL_DEBUG_RXFSTS_EMPTY          0
 198 #define MTL_DEBUG_RXFSTS_BT             1
 199 #define MTL_DEBUG_RXFSTS_AT             2
 200 #define MTL_DEBUG_RXFSTS_FULL           3
 201 #define MTL_DEBUG_RRCSTS_MASK           GENMASK(2, 1)
 202 #define MTL_DEBUG_RRCSTS_SHIFT          1
 203 #define MTL_DEBUG_RRCSTS_IDLE           0
 204 #define MTL_DEBUG_RRCSTS_RDATA          1
 205 #define MTL_DEBUG_RRCSTS_RSTAT          2
 206 #define MTL_DEBUG_RRCSTS_FLUSH          3
 207 #define MTL_DEBUG_RWCSTS                BIT(0)
 208
 209 /*  MTL interrupt */
 210 #define MTL_RX_OVERFLOW_INT_EN          BIT(24)
 211 #define MTL_RX_OVERFLOW_INT             BIT(16)
 212
 213 /* Default operating mode of the MAC */
 214 #define GMAC_CORE_INIT (GMAC_CONFIG_JD | GMAC_CONFIG_PS | GMAC_CONFIG_ACS | \
 215                         GMAC_CONFIG_BE | GMAC_CONFIG_DCRS)
 216
 217 /* To dump the core regs excluding  the Address Registers */
 218 #define GMAC_REG_NUM    132
 219
 220 /*  MTL debug */
 221 #define MTL_DEBUG_TXSTSFSTS             BIT(5)
 222 #define MTL_DEBUG_TXFSTS                BIT(4)
 223 #define MTL_DEBUG_TWCSTS                BIT(3)
 224
 225 /* MTL debug: Tx FIFO Read Controller Status */
 226 #define MTL_DEBUG_TRCSTS_MASK           GENMASK(2, 1)
 227 #define MTL_DEBUG_TRCSTS_SHIFT          1
 228 #define MTL_DEBUG_TRCSTS_IDLE           0
 229 #define MTL_DEBUG_TRCSTS_READ           1
 230 #define MTL_DEBUG_TRCSTS_TXW            2
 231 #define MTL_DEBUG_TRCSTS_WRITE          3
 232 #define MTL_DEBUG_TXPAUSED              BIT(0)
 233
 234 /* MAC debug: GMII or MII Transmit Protocol Engine Status */
 235 #define MTL_DEBUG_RXFSTS_MASK           GENMASK(5, 4)
 236 #define MTL_DEBUG_RXFSTS_SHIFT          4
 237 #define MTL_DEBUG_RXFSTS_EMPTY          0
 238 #define MTL_DEBUG_RXFSTS_BT             1
 239 #define MTL_DEBUG_RXFSTS_AT             2
 240 #define MTL_DEBUG_RXFSTS_FULL           3
 241 #define MTL_DEBUG_RRCSTS_MASK           GENMASK(2, 1)
 242 #define MTL_DEBUG_RRCSTS_SHIFT          1
 243 #define MTL_DEBUG_RRCSTS_IDLE           0
 244 #define MTL_DEBUG_RRCSTS_RDATA          1
 245 #define MTL_DEBUG_RRCSTS_RSTAT          2
 246 #define MTL_DEBUG_RRCSTS_FLUSH          3
 247 #define MTL_DEBUG_RWCSTS                BIT(0)
 248
 249 /* SGMII/RGMII status register */
 250 #define GMAC_PHYIF_CTRLSTATUS_TC                BIT(0)
 251 #define GMAC_PHYIF_CTRLSTATUS_LUD               BIT(1)
 252 #define GMAC_PHYIF_CTRLSTATUS_SMIDRXS           BIT(4)
 253 #define GMAC_PHYIF_CTRLSTATUS_LNKMOD            BIT(16)
 254 #define GMAC_PHYIF_CTRLSTATUS_SPEED             GENMASK(18, 17)
 255 #define GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT       17
 256 #define GMAC_PHYIF_CTRLSTATUS_LNKSTS            BIT(19)
 257 #define GMAC_PHYIF_CTRLSTATUS_JABTO             BIT(20)
 258 #define GMAC_PHYIF_CTRLSTATUS_FALSECARDET       BIT(21)
 259 /* LNKMOD */
 260 #define GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK       0x1
 261 /* LNKSPEED */
 262 #define GMAC_PHYIF_CTRLSTATUS_SPEED_125         0x2
 263 #define GMAC_PHYIF_CTRLSTATUS_SPEED_25          0x1
 264 #define GMAC_PHYIF_CTRLSTATUS_SPEED_2_5         0x0
 265
 266 extern const struct stmmac_dma_ops dwmac4_dma_ops;
 267 extern const struct stmmac_dma_ops dwmac410_dma_ops;
 268 #endif /* __DWMAC4_H__ */