drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c

   1 /*******************************************************************************
   2   Copyright (C) 2007-2009  STMicroelectronics Ltd
   3
   4   This program is free software; you can redistribute it and/or modify it
   5   under the terms and conditions of the GNU General Public License,
   6   version 2, as published by the Free Software Foundation.
   7
   8   This program is distributed in the hope it will be useful, but WITHOUT
   9   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11   more details.
  12
  13   You should have received a copy of the GNU General Public License along with
  14   this program; if not, write to the Free Software Foundation, Inc.,
  15   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  16
  17   The full GNU General Public License is included in this distribution in
  18   the file called "COPYING".
  19
  20   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  21 *******************************************************************************/
  22
  23 #include <linux/io.h>
  24 #include "common.h"
  25 #include "dwmac_dma.h"
  26
  27 #define GMAC_HI_REG_AE          0x80000000
  28
  29 int dwmac_dma_reset(void __iomem *ioaddr)
  30 {
  31         u32 value = readl(ioaddr + DMA_BUS_MODE);
  32         int limit;
  33
  34         /* DMA SW reset */
  35         value |= DMA_BUS_MODE_SFT_RESET;
  36         writel(value, ioaddr + DMA_BUS_MODE);
  37         limit = 10;
  38         while (limit--) {
  39                 if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET))
  40                         break;
  41                 mdelay(10);
  42         }
  43
  44         if (limit < 0)
  45                 return -EBUSY;
  46
  47         return 0;
  48 }
  49
  50 /* CSR1 enables the transmit DMA to check for new descriptor */
  51 void dwmac_enable_dma_transmission(void __iomem *ioaddr)
  52 {
  53         writel(1, ioaddr + DMA_XMT_POLL_DEMAND);
  54 }
  55
  56 void dwmac_enable_dma_irq(void __iomem *ioaddr)
  57 {
  58         writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
  59 }
  60
  61 void dwmac_disable_dma_irq(void __iomem *ioaddr)
  62 {
  63         writel(0, ioaddr + DMA_INTR_ENA);
  64 }
  65
  66 void dwmac_dma_start_tx(void __iomem *ioaddr)
  67 {
  68         u32 value = readl(ioaddr + DMA_CONTROL);
  69         value |= DMA_CONTROL_ST;
  70         writel(value, ioaddr + DMA_CONTROL);
  71 }
  72
  73 void dwmac_dma_stop_tx(void __iomem *ioaddr)
  74 {
  75         u32 value = readl(ioaddr + DMA_CONTROL);
  76         value &= ~DMA_CONTROL_ST;
  77         writel(value, ioaddr + DMA_CONTROL);
  78 }
  79
  80 void dwmac_dma_start_rx(void __iomem *ioaddr)
  81 {
  82         u32 value = readl(ioaddr + DMA_CONTROL);
  83         value |= DMA_CONTROL_SR;
  84         writel(value, ioaddr + DMA_CONTROL);
  85 }
  86
  87 void dwmac_dma_stop_rx(void __iomem *ioaddr)
  88 {
  89         u32 value = readl(ioaddr + DMA_CONTROL);
  90         value &= ~DMA_CONTROL_SR;
  91         writel(value, ioaddr + DMA_CONTROL);
  92 }
  93
  94 #ifdef DWMAC_DMA_DEBUG
  95 static void show_tx_process_state(unsigned int status)
  96 {
  97         unsigned int state;
  98         state = (status & DMA_STATUS_TS_MASK) >> DMA_STATUS_TS_SHIFT;
  99
 100         switch (state) {
 101         case 0:
 102                 pr_debug("- TX (Stopped): Reset or Stop command\n");
 103                 break;
 104         case 1:
 105                 pr_debug("- TX (Running):Fetching the Tx desc\n");
 106                 break;
 107         case 2:
 108                 pr_debug("- TX (Running): Waiting for end of tx\n");
 109                 break;
 110         case 3:
 111                 pr_debug("- TX (Running): Reading the data "
 112                        "and queuing the data into the Tx buf\n");
 113                 break;
 114         case 6:
 115                 pr_debug("- TX (Suspended): Tx Buff Underflow "
 116                        "or an unavailable Transmit descriptor\n");
 117                 break;
 118         case 7:
 119                 pr_debug("- TX (Running): Closing Tx descriptor\n");
 120                 break;
 121         default:
 122                 break;
 123         }
 124 }
 125
 126 static void show_rx_process_state(unsigned int status)
 127 {
 128         unsigned int state;
 129         state = (status & DMA_STATUS_RS_MASK) >> DMA_STATUS_RS_SHIFT;
 130
 131         switch (state) {
 132         case 0:
 133                 pr_debug("- RX (Stopped): Reset or Stop command\n");
 134                 break;
 135         case 1:
 136                 pr_debug("- RX (Running): Fetching the Rx desc\n");
 137                 break;
 138         case 2:
 139                 pr_debug("- RX (Running):Checking for end of pkt\n");
 140                 break;
 141         case 3:
 142                 pr_debug("- RX (Running): Waiting for Rx pkt\n");
 143                 break;
 144         case 4:
 145                 pr_debug("- RX (Suspended): Unavailable Rx buf\n");
 146                 break;
 147         case 5:
 148                 pr_debug("- RX (Running): Closing Rx descriptor\n");
 149                 break;
 150         case 6:
 151                 pr_debug("- RX(Running): Flushing the current frame"
 152                        " from the Rx buf\n");
 153                 break;
 154         case 7:
 155                 pr_debug("- RX (Running): Queuing the Rx frame"
 156                        " from the Rx buf into memory\n");
 157                 break;
 158         default:
 159                 break;
 160         }
 161 }
 162 #endif
 163
 164 int dwmac_dma_interrupt(void __iomem *ioaddr,
 165                         struct stmmac_extra_stats *x)
 166 {
 167         int ret = 0;
 168         /* read the status register (CSR5) */
 169         u32 intr_status = readl(ioaddr + DMA_STATUS);
 170
 171 #ifdef DWMAC_DMA_DEBUG
 172         /* Enable it to monitor DMA rx/tx status in case of critical problems */
 173         pr_debug("%s: [CSR5: 0x%08x]\n", __func__, intr_status);
 174         show_tx_process_state(intr_status);
 175         show_rx_process_state(intr_status);
 176 #endif
 177         /* ABNORMAL interrupts */
 178         if (unlikely(intr_status & DMA_STATUS_AIS)) {
 179                 if (unlikely(intr_status & DMA_STATUS_UNF)) {
 180                         ret = tx_hard_error_bump_tc;
 181                         x->tx_undeflow_irq++;
 182                 }
 183                 if (unlikely(intr_status & DMA_STATUS_TJT))
 184                         x->tx_jabber_irq++;
 185
 186                 if (unlikely(intr_status & DMA_STATUS_OVF))
 187                         x->rx_overflow_irq++;
 188
 189                 if (unlikely(intr_status & DMA_STATUS_RU))
 190                         x->rx_buf_unav_irq++;
 191                 if (unlikely(intr_status & DMA_STATUS_RPS))
 192                         x->rx_process_stopped_irq++;
 193                 if (unlikely(intr_status & DMA_STATUS_RWT))
 194                         x->rx_watchdog_irq++;
 195                 if (unlikely(intr_status & DMA_STATUS_ETI))
 196                         x->tx_early_irq++;
 197                 if (unlikely(intr_status & DMA_STATUS_TPS)) {
 198                         x->tx_process_stopped_irq++;
 199                         ret = tx_hard_error;
 200                 }
 201                 if (unlikely(intr_status & DMA_STATUS_FBI)) {
 202                         x->fatal_bus_error_irq++;
 203                         ret = tx_hard_error;
 204                 }
 205         }
 206         /* TX/RX NORMAL interrupts */
 207         if (likely(intr_status & DMA_STATUS_NIS)) {
 208                 x->normal_irq_n++;
 209                 if (likely(intr_status & DMA_STATUS_RI)) {
 210                         u32 value = readl(ioaddr + DMA_INTR_ENA);
 211                         /* to schedule NAPI on real RIE event. */
 212                         if (likely(value & DMA_INTR_ENA_RIE)) {
 213                                 x->rx_normal_irq_n++;
 214                                 ret |= handle_rx;
 215                         }
 216                 }
 217                 if (likely(intr_status & DMA_STATUS_TI)) {
 218                         x->tx_normal_irq_n++;
 219                         ret |= handle_tx;
 220                 }
 221                 if (unlikely(intr_status & DMA_STATUS_ERI))
 222                         x->rx_early_irq++;
 223         }
 224         /* Optional hardware blocks, interrupts should be disabled */
 225         if (unlikely(intr_status &
 226                      (DMA_STATUS_GPI | DMA_STATUS_GMI | DMA_STATUS_GLI)))
 227                 pr_warn("%s: unexpected status %08x\n", __func__, intr_status);
 228
 229         /* Clear the interrupt by writing a logic 1 to the CSR5[15-0] */
 230         writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS);
 231
 232         return ret;
 233 }
 234
 235 void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr)
 236 {
 237         u32 csr6 = readl(ioaddr + DMA_CONTROL);
 238         writel((csr6 | DMA_CONTROL_FTF), ioaddr + DMA_CONTROL);
 239
 240         do {} while ((readl(ioaddr + DMA_CONTROL) & DMA_CONTROL_FTF));
 241 }
 242
 243 void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
 244                          unsigned int high, unsigned int low)
 245 {
 246         unsigned long data;
 247
 248         data = (addr[5] << 8) | addr[4];
 249         /* For MAC Addr registers se have to set the Address Enable (AE)
 250          * bit that has no effect on the High Reg 0 where the bit 31 (MO)
 251          * is RO.
 252          */
 253         writel(data | GMAC_HI_REG_AE, ioaddr + high);
 254         data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
 255         writel(data, ioaddr + low);
 256 }
 257
 258 /* Enable disable MAC RX/TX */
 259 void stmmac_set_mac(void __iomem *ioaddr, bool enable)
 260 {
 261         u32 value = readl(ioaddr + MAC_CTRL_REG);
 262
 263         if (enable)
 264                 value |= MAC_RNABLE_RX | MAC_ENABLE_TX;
 265         else
 266                 value &= ~(MAC_ENABLE_TX | MAC_RNABLE_RX);
 267
 268         writel(value, ioaddr + MAC_CTRL_REG);
 269 }
 270
 271 void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
 272                          unsigned int high, unsigned int low)
 273 {
 274         unsigned int hi_addr, lo_addr;
 275
 276         /* Read the MAC address from the hardware */
 277         hi_addr = readl(ioaddr + high);
 278         lo_addr = readl(ioaddr + low);
 279
 280         /* Extract the MAC address from the high and low words */
 281         addr[0] = lo_addr & 0xff;
 282         addr[1] = (lo_addr >> 8) & 0xff;
 283         addr[2] = (lo_addr >> 16) & 0xff;
 284         addr[3] = (lo_addr >> 24) & 0xff;
 285         addr[4] = hi_addr & 0xff;
 286         addr[5] = (hi_addr >> 8) & 0xff;
 287 }
 288