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Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[cris-mirror.git] / drivers / net / ethernet / stmicro / stmmac / stmmac_ethtool.c
blob1e06173fc9d733d63c1e5ccbbc12c03506d0a44c
1 /*******************************************************************************
2 STMMAC Ethtool support
3
4 Copyright (C) 2007-2009 STMicroelectronics Ltd
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
23 *******************************************************************************/
24
25 #include <linux/etherdevice.h>
26 #include <linux/ethtool.h>
27 #include <linux/interrupt.h>
28 #include <linux/mii.h>
29 #include <linux/phy.h>
30 #include <linux/net_tstamp.h>
31 #include <asm/io.h>
32
33 #include "stmmac.h"
34 #include "dwmac_dma.h"
35
36 #define REG_SPACE_SIZE 0x1054
37 #define MAC100_ETHTOOL_NAME "st_mac100"
38 #define GMAC_ETHTOOL_NAME "st_gmac"
39
40 struct stmmac_stats {
41 char stat_string[ETH_GSTRING_LEN];
42 int sizeof_stat;
43 int stat_offset;
44 };
45
46 #define STMMAC_STAT(m) \
47 { #m, FIELD_SIZEOF(struct stmmac_extra_stats, m), \
48 offsetof(struct stmmac_priv, xstats.m)}
49
50 static const struct stmmac_stats stmmac_gstrings_stats[] = {
51 /* Transmit errors */
52 STMMAC_STAT(tx_underflow),
53 STMMAC_STAT(tx_carrier),
54 STMMAC_STAT(tx_losscarrier),
55 STMMAC_STAT(vlan_tag),
56 STMMAC_STAT(tx_deferred),
57 STMMAC_STAT(tx_vlan),
58 STMMAC_STAT(tx_jabber),
59 STMMAC_STAT(tx_frame_flushed),
60 STMMAC_STAT(tx_payload_error),
61 STMMAC_STAT(tx_ip_header_error),
62 /* Receive errors */
63 STMMAC_STAT(rx_desc),
64 STMMAC_STAT(sa_filter_fail),
65 STMMAC_STAT(overflow_error),
66 STMMAC_STAT(ipc_csum_error),
67 STMMAC_STAT(rx_collision),
68 STMMAC_STAT(rx_crc),
69 STMMAC_STAT(dribbling_bit),
70 STMMAC_STAT(rx_length),
71 STMMAC_STAT(rx_mii),
72 STMMAC_STAT(rx_multicast),
73 STMMAC_STAT(rx_gmac_overflow),
74 STMMAC_STAT(rx_watchdog),
75 STMMAC_STAT(da_rx_filter_fail),
76 STMMAC_STAT(sa_rx_filter_fail),
77 STMMAC_STAT(rx_missed_cntr),
78 STMMAC_STAT(rx_overflow_cntr),
79 STMMAC_STAT(rx_vlan),
80 /* Tx/Rx IRQ error info */
81 STMMAC_STAT(tx_undeflow_irq),
82 STMMAC_STAT(tx_process_stopped_irq),
83 STMMAC_STAT(tx_jabber_irq),
84 STMMAC_STAT(rx_overflow_irq),
85 STMMAC_STAT(rx_buf_unav_irq),
86 STMMAC_STAT(rx_process_stopped_irq),
87 STMMAC_STAT(rx_watchdog_irq),
88 STMMAC_STAT(tx_early_irq),
89 STMMAC_STAT(fatal_bus_error_irq),
90 /* Tx/Rx IRQ Events */
91 STMMAC_STAT(rx_early_irq),
92 STMMAC_STAT(threshold),
93 STMMAC_STAT(tx_pkt_n),
94 STMMAC_STAT(rx_pkt_n),
95 STMMAC_STAT(normal_irq_n),
96 STMMAC_STAT(rx_normal_irq_n),
97 STMMAC_STAT(napi_poll),
98 STMMAC_STAT(tx_normal_irq_n),
99 STMMAC_STAT(tx_clean),
100 STMMAC_STAT(tx_set_ic_bit),
101 STMMAC_STAT(irq_receive_pmt_irq_n),
102 /* MMC info */
103 STMMAC_STAT(mmc_tx_irq_n),
104 STMMAC_STAT(mmc_rx_irq_n),
105 STMMAC_STAT(mmc_rx_csum_offload_irq_n),
106 /* EEE */
107 STMMAC_STAT(irq_tx_path_in_lpi_mode_n),
108 STMMAC_STAT(irq_tx_path_exit_lpi_mode_n),
109 STMMAC_STAT(irq_rx_path_in_lpi_mode_n),
110 STMMAC_STAT(irq_rx_path_exit_lpi_mode_n),
111 STMMAC_STAT(phy_eee_wakeup_error_n),
112 /* Extended RDES status */
113 STMMAC_STAT(ip_hdr_err),
114 STMMAC_STAT(ip_payload_err),
115 STMMAC_STAT(ip_csum_bypassed),
116 STMMAC_STAT(ipv4_pkt_rcvd),
117 STMMAC_STAT(ipv6_pkt_rcvd),
118 STMMAC_STAT(rx_msg_type_ext_no_ptp),
119 STMMAC_STAT(rx_msg_type_sync),
120 STMMAC_STAT(rx_msg_type_follow_up),
121 STMMAC_STAT(rx_msg_type_delay_req),
122 STMMAC_STAT(rx_msg_type_delay_resp),
123 STMMAC_STAT(rx_msg_type_pdelay_req),
124 STMMAC_STAT(rx_msg_type_pdelay_resp),
125 STMMAC_STAT(rx_msg_type_pdelay_follow_up),
126 STMMAC_STAT(ptp_frame_type),
127 STMMAC_STAT(ptp_ver),
128 STMMAC_STAT(timestamp_dropped),
129 STMMAC_STAT(av_pkt_rcvd),
130 STMMAC_STAT(av_tagged_pkt_rcvd),
131 STMMAC_STAT(vlan_tag_priority_val),
132 STMMAC_STAT(l3_filter_match),
133 STMMAC_STAT(l4_filter_match),
134 STMMAC_STAT(l3_l4_filter_no_match),
135 /* PCS */
136 STMMAC_STAT(irq_pcs_ane_n),
137 STMMAC_STAT(irq_pcs_link_n),
138 STMMAC_STAT(irq_rgmii_n),
139 /* DEBUG */
140 STMMAC_STAT(mtl_tx_status_fifo_full),
141 STMMAC_STAT(mtl_tx_fifo_not_empty),
142 STMMAC_STAT(mmtl_fifo_ctrl),
143 STMMAC_STAT(mtl_tx_fifo_read_ctrl_write),
144 STMMAC_STAT(mtl_tx_fifo_read_ctrl_wait),
145 STMMAC_STAT(mtl_tx_fifo_read_ctrl_read),
146 STMMAC_STAT(mtl_tx_fifo_read_ctrl_idle),
147 STMMAC_STAT(mac_tx_in_pause),
148 STMMAC_STAT(mac_tx_frame_ctrl_xfer),
149 STMMAC_STAT(mac_tx_frame_ctrl_idle),
150 STMMAC_STAT(mac_tx_frame_ctrl_wait),
151 STMMAC_STAT(mac_tx_frame_ctrl_pause),
152 STMMAC_STAT(mac_gmii_tx_proto_engine),
153 STMMAC_STAT(mtl_rx_fifo_fill_level_full),
154 STMMAC_STAT(mtl_rx_fifo_fill_above_thresh),
155 STMMAC_STAT(mtl_rx_fifo_fill_below_thresh),
156 STMMAC_STAT(mtl_rx_fifo_fill_level_empty),
157 STMMAC_STAT(mtl_rx_fifo_read_ctrl_flush),
158 STMMAC_STAT(mtl_rx_fifo_read_ctrl_read_data),
159 STMMAC_STAT(mtl_rx_fifo_read_ctrl_status),
160 STMMAC_STAT(mtl_rx_fifo_read_ctrl_idle),
161 STMMAC_STAT(mtl_rx_fifo_ctrl_active),
162 STMMAC_STAT(mac_rx_frame_ctrl_fifo),
163 STMMAC_STAT(mac_gmii_rx_proto_engine),
164 /* TSO */
165 STMMAC_STAT(tx_tso_frames),
166 STMMAC_STAT(tx_tso_nfrags),
167 };
168 #define STMMAC_STATS_LEN ARRAY_SIZE(stmmac_gstrings_stats)
169
170 /* HW MAC Management counters (if supported) */
171 #define STMMAC_MMC_STAT(m) \
172 { #m, FIELD_SIZEOF(struct stmmac_counters, m), \
173 offsetof(struct stmmac_priv, mmc.m)}
174
175 static const struct stmmac_stats stmmac_mmc[] = {
176 STMMAC_MMC_STAT(mmc_tx_octetcount_gb),
177 STMMAC_MMC_STAT(mmc_tx_framecount_gb),
178 STMMAC_MMC_STAT(mmc_tx_broadcastframe_g),
179 STMMAC_MMC_STAT(mmc_tx_multicastframe_g),
180 STMMAC_MMC_STAT(mmc_tx_64_octets_gb),
181 STMMAC_MMC_STAT(mmc_tx_65_to_127_octets_gb),
182 STMMAC_MMC_STAT(mmc_tx_128_to_255_octets_gb),
183 STMMAC_MMC_STAT(mmc_tx_256_to_511_octets_gb),
184 STMMAC_MMC_STAT(mmc_tx_512_to_1023_octets_gb),
185 STMMAC_MMC_STAT(mmc_tx_1024_to_max_octets_gb),
186 STMMAC_MMC_STAT(mmc_tx_unicast_gb),
187 STMMAC_MMC_STAT(mmc_tx_multicast_gb),
188 STMMAC_MMC_STAT(mmc_tx_broadcast_gb),
189 STMMAC_MMC_STAT(mmc_tx_underflow_error),
190 STMMAC_MMC_STAT(mmc_tx_singlecol_g),
191 STMMAC_MMC_STAT(mmc_tx_multicol_g),
192 STMMAC_MMC_STAT(mmc_tx_deferred),
193 STMMAC_MMC_STAT(mmc_tx_latecol),
194 STMMAC_MMC_STAT(mmc_tx_exesscol),
195 STMMAC_MMC_STAT(mmc_tx_carrier_error),
196 STMMAC_MMC_STAT(mmc_tx_octetcount_g),
197 STMMAC_MMC_STAT(mmc_tx_framecount_g),
198 STMMAC_MMC_STAT(mmc_tx_excessdef),
199 STMMAC_MMC_STAT(mmc_tx_pause_frame),
200 STMMAC_MMC_STAT(mmc_tx_vlan_frame_g),
201 STMMAC_MMC_STAT(mmc_rx_framecount_gb),
202 STMMAC_MMC_STAT(mmc_rx_octetcount_gb),
203 STMMAC_MMC_STAT(mmc_rx_octetcount_g),
204 STMMAC_MMC_STAT(mmc_rx_broadcastframe_g),
205 STMMAC_MMC_STAT(mmc_rx_multicastframe_g),
206 STMMAC_MMC_STAT(mmc_rx_crc_error),
207 STMMAC_MMC_STAT(mmc_rx_align_error),
208 STMMAC_MMC_STAT(mmc_rx_run_error),
209 STMMAC_MMC_STAT(mmc_rx_jabber_error),
210 STMMAC_MMC_STAT(mmc_rx_undersize_g),
211 STMMAC_MMC_STAT(mmc_rx_oversize_g),
212 STMMAC_MMC_STAT(mmc_rx_64_octets_gb),
213 STMMAC_MMC_STAT(mmc_rx_65_to_127_octets_gb),
214 STMMAC_MMC_STAT(mmc_rx_128_to_255_octets_gb),
215 STMMAC_MMC_STAT(mmc_rx_256_to_511_octets_gb),
216 STMMAC_MMC_STAT(mmc_rx_512_to_1023_octets_gb),
217 STMMAC_MMC_STAT(mmc_rx_1024_to_max_octets_gb),
218 STMMAC_MMC_STAT(mmc_rx_unicast_g),
219 STMMAC_MMC_STAT(mmc_rx_length_error),
220 STMMAC_MMC_STAT(mmc_rx_autofrangetype),
221 STMMAC_MMC_STAT(mmc_rx_pause_frames),
222 STMMAC_MMC_STAT(mmc_rx_fifo_overflow),
223 STMMAC_MMC_STAT(mmc_rx_vlan_frames_gb),
224 STMMAC_MMC_STAT(mmc_rx_watchdog_error),
225 STMMAC_MMC_STAT(mmc_rx_ipc_intr_mask),
226 STMMAC_MMC_STAT(mmc_rx_ipc_intr),
227 STMMAC_MMC_STAT(mmc_rx_ipv4_gd),
228 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr),
229 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay),
230 STMMAC_MMC_STAT(mmc_rx_ipv4_frag),
231 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl),
232 STMMAC_MMC_STAT(mmc_rx_ipv4_gd_octets),
233 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr_octets),
234 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay_octets),
235 STMMAC_MMC_STAT(mmc_rx_ipv4_frag_octets),
236 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl_octets),
237 STMMAC_MMC_STAT(mmc_rx_ipv6_gd_octets),
238 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr_octets),
239 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay_octets),
240 STMMAC_MMC_STAT(mmc_rx_ipv6_gd),
241 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr),
242 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay),
243 STMMAC_MMC_STAT(mmc_rx_udp_gd),
244 STMMAC_MMC_STAT(mmc_rx_udp_err),
245 STMMAC_MMC_STAT(mmc_rx_tcp_gd),
246 STMMAC_MMC_STAT(mmc_rx_tcp_err),
247 STMMAC_MMC_STAT(mmc_rx_icmp_gd),
248 STMMAC_MMC_STAT(mmc_rx_icmp_err),
249 STMMAC_MMC_STAT(mmc_rx_udp_gd_octets),
250 STMMAC_MMC_STAT(mmc_rx_udp_err_octets),
251 STMMAC_MMC_STAT(mmc_rx_tcp_gd_octets),
252 STMMAC_MMC_STAT(mmc_rx_tcp_err_octets),
253 STMMAC_MMC_STAT(mmc_rx_icmp_gd_octets),
254 STMMAC_MMC_STAT(mmc_rx_icmp_err_octets),
255 };
256 #define STMMAC_MMC_STATS_LEN ARRAY_SIZE(stmmac_mmc)
257
258 static void stmmac_ethtool_getdrvinfo(struct net_device *dev,
259 struct ethtool_drvinfo *info)
260 {
261 struct stmmac_priv *priv = netdev_priv(dev);
262
263 if (priv->plat->has_gmac)
264 strlcpy(info->driver, GMAC_ETHTOOL_NAME, sizeof(info->driver));
265 else
266 strlcpy(info->driver, MAC100_ETHTOOL_NAME,
267 sizeof(info->driver));
268
269 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
270 }
271
272 static int stmmac_ethtool_getsettings(struct net_device *dev,
273 struct ethtool_cmd *cmd)
274 {
275 struct stmmac_priv *priv = netdev_priv(dev);
276 struct phy_device *phy = priv->phydev;
277 int rc;
278
279 if (priv->hw->pcs & STMMAC_PCS_RGMII ||
280 priv->hw->pcs & STMMAC_PCS_SGMII) {
281 struct rgmii_adv adv;
282
283 if (!priv->xstats.pcs_link) {
284 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
285 cmd->duplex = DUPLEX_UNKNOWN;
286 return 0;
287 }
288 cmd->duplex = priv->xstats.pcs_duplex;
289
290 ethtool_cmd_speed_set(cmd, priv->xstats.pcs_speed);
291
292 /* Get and convert ADV/LP_ADV from the HW AN registers */
293 if (!priv->hw->mac->pcs_get_adv_lp)
294 return -EOPNOTSUPP; /* should never happen indeed */
295
296 priv->hw->mac->pcs_get_adv_lp(priv->ioaddr, &adv);
297
298 /* Encoding of PSE bits is defined in 802.3z, 37.2.1.4 */
299
300 if (adv.pause & STMMAC_PCS_PAUSE)
301 cmd->advertising |= ADVERTISED_Pause;
302 if (adv.pause & STMMAC_PCS_ASYM_PAUSE)
303 cmd->advertising |= ADVERTISED_Asym_Pause;
304 if (adv.lp_pause & STMMAC_PCS_PAUSE)
305 cmd->lp_advertising |= ADVERTISED_Pause;
306 if (adv.lp_pause & STMMAC_PCS_ASYM_PAUSE)
307 cmd->lp_advertising |= ADVERTISED_Asym_Pause;
308
309 /* Reg49[3] always set because ANE is always supported */
310 cmd->autoneg = ADVERTISED_Autoneg;
311 cmd->supported |= SUPPORTED_Autoneg;
312 cmd->advertising |= ADVERTISED_Autoneg;
313 cmd->lp_advertising |= ADVERTISED_Autoneg;
314
315 if (adv.duplex) {
316 cmd->supported |= (SUPPORTED_1000baseT_Full |
317 SUPPORTED_100baseT_Full |
318 SUPPORTED_10baseT_Full);
319 cmd->advertising |= (ADVERTISED_1000baseT_Full |
320 ADVERTISED_100baseT_Full |
321 ADVERTISED_10baseT_Full);
322 } else {
323 cmd->supported |= (SUPPORTED_1000baseT_Half |
324 SUPPORTED_100baseT_Half |
325 SUPPORTED_10baseT_Half);
326 cmd->advertising |= (ADVERTISED_1000baseT_Half |
327 ADVERTISED_100baseT_Half |
328 ADVERTISED_10baseT_Half);
329 }
330 if (adv.lp_duplex)
331 cmd->lp_advertising |= (ADVERTISED_1000baseT_Full |
332 ADVERTISED_100baseT_Full |
333 ADVERTISED_10baseT_Full);
334 else
335 cmd->lp_advertising |= (ADVERTISED_1000baseT_Half |
336 ADVERTISED_100baseT_Half |
337 ADVERTISED_10baseT_Half);
338 cmd->port = PORT_OTHER;
339
340 return 0;
341 }
342
343 if (phy == NULL) {
344 pr_err("%s: %s: PHY is not registered\n",
345 __func__, dev->name);
346 return -ENODEV;
347 }
348 if (!netif_running(dev)) {
349 pr_err("%s: interface is disabled: we cannot track "
350 "link speed / duplex setting\n", dev->name);
351 return -EBUSY;
352 }
353 cmd->transceiver = XCVR_INTERNAL;
354 rc = phy_ethtool_gset(phy, cmd);
355 return rc;
356 }
357
358 static int stmmac_ethtool_setsettings(struct net_device *dev,
359 struct ethtool_cmd *cmd)
360 {
361 struct stmmac_priv *priv = netdev_priv(dev);
362 struct phy_device *phy = priv->phydev;
363 int rc;
364
365 if (priv->hw->pcs & STMMAC_PCS_RGMII ||
366 priv->hw->pcs & STMMAC_PCS_SGMII) {
367 u32 mask = ADVERTISED_Autoneg | ADVERTISED_Pause;
368
369 /* Only support ANE */
370 if (cmd->autoneg != AUTONEG_ENABLE)
371 return -EINVAL;
372
373 mask &= (ADVERTISED_1000baseT_Half |
374 ADVERTISED_1000baseT_Full |
375 ADVERTISED_100baseT_Half |
376 ADVERTISED_100baseT_Full |
377 ADVERTISED_10baseT_Half |
378 ADVERTISED_10baseT_Full);
379
380 spin_lock(&priv->lock);
381
382 if (priv->hw->mac->pcs_ctrl_ane)
383 priv->hw->mac->pcs_ctrl_ane(priv->ioaddr, 1,
384 priv->hw->ps, 0);
385
386 spin_unlock(&priv->lock);
387
388 return 0;
389 }
390
391 spin_lock(&priv->lock);
392 rc = phy_ethtool_sset(phy, cmd);
393 spin_unlock(&priv->lock);
394
395 return rc;
396 }
397
398 static u32 stmmac_ethtool_getmsglevel(struct net_device *dev)
399 {
400 struct stmmac_priv *priv = netdev_priv(dev);
401 return priv->msg_enable;
402 }
403
404 static void stmmac_ethtool_setmsglevel(struct net_device *dev, u32 level)
405 {
406 struct stmmac_priv *priv = netdev_priv(dev);
407 priv->msg_enable = level;
408
409 }
410
411 static int stmmac_check_if_running(struct net_device *dev)
412 {
413 if (!netif_running(dev))
414 return -EBUSY;
415 return 0;
416 }
417
418 static int stmmac_ethtool_get_regs_len(struct net_device *dev)
419 {
420 return REG_SPACE_SIZE;
421 }
422
423 static void stmmac_ethtool_gregs(struct net_device *dev,
424 struct ethtool_regs *regs, void *space)
425 {
426 int i;
427 u32 *reg_space = (u32 *) space;
428
429 struct stmmac_priv *priv = netdev_priv(dev);
430
431 memset(reg_space, 0x0, REG_SPACE_SIZE);
432
433 if (!priv->plat->has_gmac) {
434 /* MAC registers */
435 for (i = 0; i < 12; i++)
436 reg_space[i] = readl(priv->ioaddr + (i * 4));
437 /* DMA registers */
438 for (i = 0; i < 9; i++)
439 reg_space[i + 12] =
440 readl(priv->ioaddr + (DMA_BUS_MODE + (i * 4)));
441 reg_space[22] = readl(priv->ioaddr + DMA_CUR_TX_BUF_ADDR);
442 reg_space[23] = readl(priv->ioaddr + DMA_CUR_RX_BUF_ADDR);
443 } else {
444 /* MAC registers */
445 for (i = 0; i < 55; i++)
446 reg_space[i] = readl(priv->ioaddr + (i * 4));
447 /* DMA registers */
448 for (i = 0; i < 22; i++)
449 reg_space[i + 55] =
450 readl(priv->ioaddr + (DMA_BUS_MODE + (i * 4)));
451 }
452 }
453
454 static void
455 stmmac_get_pauseparam(struct net_device *netdev,
456 struct ethtool_pauseparam *pause)
457 {
458 struct stmmac_priv *priv = netdev_priv(netdev);
459
460 pause->rx_pause = 0;
461 pause->tx_pause = 0;
462
463 if (priv->hw->pcs && priv->hw->mac->pcs_get_adv_lp) {
464 struct rgmii_adv adv_lp;
465
466 pause->autoneg = 1;
467 priv->hw->mac->pcs_get_adv_lp(priv->ioaddr, &adv_lp);
468 if (!adv_lp.pause)
469 return;
470 } else {
471 if (!(priv->phydev->supported & SUPPORTED_Pause) ||
472 !(priv->phydev->supported & SUPPORTED_Asym_Pause))
473 return;
474 }
475
476 pause->autoneg = priv->phydev->autoneg;
477
478 if (priv->flow_ctrl & FLOW_RX)
479 pause->rx_pause = 1;
480 if (priv->flow_ctrl & FLOW_TX)
481 pause->tx_pause = 1;
482
483 }
484
485 static int
486 stmmac_set_pauseparam(struct net_device *netdev,
487 struct ethtool_pauseparam *pause)
488 {
489 struct stmmac_priv *priv = netdev_priv(netdev);
490 struct phy_device *phy = priv->phydev;
491 int new_pause = FLOW_OFF;
492
493 if (priv->hw->pcs && priv->hw->mac->pcs_get_adv_lp) {
494 struct rgmii_adv adv_lp;
495
496 pause->autoneg = 1;
497 priv->hw->mac->pcs_get_adv_lp(priv->ioaddr, &adv_lp);
498 if (!adv_lp.pause)
499 return -EOPNOTSUPP;
500 } else {
501 if (!(phy->supported & SUPPORTED_Pause) ||
502 !(phy->supported & SUPPORTED_Asym_Pause))
503 return -EOPNOTSUPP;
504 }
505
506 if (pause->rx_pause)
507 new_pause |= FLOW_RX;
508 if (pause->tx_pause)
509 new_pause |= FLOW_TX;
510
511 priv->flow_ctrl = new_pause;
512 phy->autoneg = pause->autoneg;
513
514 if (phy->autoneg) {
515 if (netif_running(netdev))
516 return phy_start_aneg(phy);
517 }
518
519 priv->hw->mac->flow_ctrl(priv->hw, phy->duplex, priv->flow_ctrl,
520 priv->pause);
521 return 0;
522 }
523
524 static void stmmac_get_ethtool_stats(struct net_device *dev,
525 struct ethtool_stats *dummy, u64 *data)
526 {
527 struct stmmac_priv *priv = netdev_priv(dev);
528 int i, j = 0;
529
530 /* Update the DMA HW counters for dwmac10/100 */
531 if (priv->hw->dma->dma_diagnostic_fr)
532 priv->hw->dma->dma_diagnostic_fr(&dev->stats,
533 (void *) &priv->xstats,
534 priv->ioaddr);
535 else {
536 /* If supported, for new GMAC chips expose the MMC counters */
537 if (priv->dma_cap.rmon) {
538 dwmac_mmc_read(priv->mmcaddr, &priv->mmc);
539
540 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) {
541 char *p;
542 p = (char *)priv + stmmac_mmc[i].stat_offset;
543
544 data[j++] = (stmmac_mmc[i].sizeof_stat ==
545 sizeof(u64)) ? (*(u64 *)p) :
546 (*(u32 *)p);
547 }
548 }
549 if (priv->eee_enabled) {
550 int val = phy_get_eee_err(priv->phydev);
551 if (val)
552 priv->xstats.phy_eee_wakeup_error_n = val;
553 }
554
555 if ((priv->hw->mac->debug) &&
556 (priv->synopsys_id >= DWMAC_CORE_3_50))
557 priv->hw->mac->debug(priv->ioaddr,
558 (void *)&priv->xstats);
559 }
560 for (i = 0; i < STMMAC_STATS_LEN; i++) {
561 char *p = (char *)priv + stmmac_gstrings_stats[i].stat_offset;
562 data[j++] = (stmmac_gstrings_stats[i].sizeof_stat ==
563 sizeof(u64)) ? (*(u64 *)p) : (*(u32 *)p);
564 }
565 }
566
567 static int stmmac_get_sset_count(struct net_device *netdev, int sset)
568 {
569 struct stmmac_priv *priv = netdev_priv(netdev);
570 int len;
571
572 switch (sset) {
573 case ETH_SS_STATS:
574 len = STMMAC_STATS_LEN;
575
576 if (priv->dma_cap.rmon)
577 len += STMMAC_MMC_STATS_LEN;
578
579 return len;
580 default:
581 return -EOPNOTSUPP;
582 }
583 }
584
585 static void stmmac_get_strings(struct net_device *dev, u32 stringset, u8 *data)
586 {
587 int i;
588 u8 *p = data;
589 struct stmmac_priv *priv = netdev_priv(dev);
590
591 switch (stringset) {
592 case ETH_SS_STATS:
593 if (priv->dma_cap.rmon)
594 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) {
595 memcpy(p, stmmac_mmc[i].stat_string,
596 ETH_GSTRING_LEN);
597 p += ETH_GSTRING_LEN;
598 }
599 for (i = 0; i < STMMAC_STATS_LEN; i++) {
600 memcpy(p, stmmac_gstrings_stats[i].stat_string,
601 ETH_GSTRING_LEN);
602 p += ETH_GSTRING_LEN;
603 }
604 break;
605 default:
606 WARN_ON(1);
607 break;
608 }
609 }
610
611 /* Currently only support WOL through Magic packet. */
612 static void stmmac_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
613 {
614 struct stmmac_priv *priv = netdev_priv(dev);
615
616 spin_lock_irq(&priv->lock);
617 if (device_can_wakeup(priv->device)) {
618 wol->supported = WAKE_MAGIC | WAKE_UCAST;
619 wol->wolopts = priv->wolopts;
620 }
621 spin_unlock_irq(&priv->lock);
622 }
623
624 static int stmmac_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
625 {
626 struct stmmac_priv *priv = netdev_priv(dev);
627 u32 support = WAKE_MAGIC | WAKE_UCAST;
628
629 /* By default almost all GMAC devices support the WoL via
630 * magic frame but we can disable it if the HW capability
631 * register shows no support for pmt_magic_frame. */
632 if ((priv->hw_cap_support) && (!priv->dma_cap.pmt_magic_frame))
633 wol->wolopts &= ~WAKE_MAGIC;
634
635 if (!device_can_wakeup(priv->device))
636 return -EINVAL;
637
638 if (wol->wolopts & ~support)
639 return -EINVAL;
640
641 if (wol->wolopts) {
642 pr_info("stmmac: wakeup enable\n");
643 device_set_wakeup_enable(priv->device, 1);
644 enable_irq_wake(priv->wol_irq);
645 } else {
646 device_set_wakeup_enable(priv->device, 0);
647 disable_irq_wake(priv->wol_irq);
648 }
649
650 spin_lock_irq(&priv->lock);
651 priv->wolopts = wol->wolopts;
652 spin_unlock_irq(&priv->lock);
653
654 return 0;
655 }
656
657 static int stmmac_ethtool_op_get_eee(struct net_device *dev,
658 struct ethtool_eee *edata)
659 {
660 struct stmmac_priv *priv = netdev_priv(dev);
661
662 if (!priv->dma_cap.eee)
663 return -EOPNOTSUPP;
664
665 edata->eee_enabled = priv->eee_enabled;
666 edata->eee_active = priv->eee_active;
667 edata->tx_lpi_timer = priv->tx_lpi_timer;
668
669 return phy_ethtool_get_eee(priv->phydev, edata);
670 }
671
672 static int stmmac_ethtool_op_set_eee(struct net_device *dev,
673 struct ethtool_eee *edata)
674 {
675 struct stmmac_priv *priv = netdev_priv(dev);
676
677 priv->eee_enabled = edata->eee_enabled;
678
679 if (!priv->eee_enabled)
680 stmmac_disable_eee_mode(priv);
681 else {
682 /* We are asking for enabling the EEE but it is safe
683 * to verify all by invoking the eee_init function.
684 * In case of failure it will return an error.
685 */
686 priv->eee_enabled = stmmac_eee_init(priv);
687 if (!priv->eee_enabled)
688 return -EOPNOTSUPP;
689
690 /* Do not change tx_lpi_timer in case of failure */
691 priv->tx_lpi_timer = edata->tx_lpi_timer;
692 }
693
694 return phy_ethtool_set_eee(priv->phydev, edata);
695 }
696
697 static u32 stmmac_usec2riwt(u32 usec, struct stmmac_priv *priv)
698 {
699 unsigned long clk = clk_get_rate(priv->stmmac_clk);
700
701 if (!clk)
702 return 0;
703
704 return (usec * (clk / 1000000)) / 256;
705 }
706
707 static u32 stmmac_riwt2usec(u32 riwt, struct stmmac_priv *priv)
708 {
709 unsigned long clk = clk_get_rate(priv->stmmac_clk);
710
711 if (!clk)
712 return 0;
713
714 return (riwt * 256) / (clk / 1000000);
715 }
716
717 static int stmmac_get_coalesce(struct net_device *dev,
718 struct ethtool_coalesce *ec)
719 {
720 struct stmmac_priv *priv = netdev_priv(dev);
721
722 ec->tx_coalesce_usecs = priv->tx_coal_timer;
723 ec->tx_max_coalesced_frames = priv->tx_coal_frames;
724
725 if (priv->use_riwt)
726 ec->rx_coalesce_usecs = stmmac_riwt2usec(priv->rx_riwt, priv);
727
728 return 0;
729 }
730
731 static int stmmac_set_coalesce(struct net_device *dev,
732 struct ethtool_coalesce *ec)
733 {
734 struct stmmac_priv *priv = netdev_priv(dev);
735 unsigned int rx_riwt;
736
737 /* Check not supported parameters */
738 if ((ec->rx_max_coalesced_frames) || (ec->rx_coalesce_usecs_irq) ||
739 (ec->rx_max_coalesced_frames_irq) || (ec->tx_coalesce_usecs_irq) ||
740 (ec->use_adaptive_rx_coalesce) || (ec->use_adaptive_tx_coalesce) ||
741 (ec->pkt_rate_low) || (ec->rx_coalesce_usecs_low) ||
742 (ec->rx_max_coalesced_frames_low) || (ec->tx_coalesce_usecs_high) ||
743 (ec->tx_max_coalesced_frames_low) || (ec->pkt_rate_high) ||
744 (ec->tx_coalesce_usecs_low) || (ec->rx_coalesce_usecs_high) ||
745 (ec->rx_max_coalesced_frames_high) ||
746 (ec->tx_max_coalesced_frames_irq) ||
747 (ec->stats_block_coalesce_usecs) ||
748 (ec->tx_max_coalesced_frames_high) || (ec->rate_sample_interval))
749 return -EOPNOTSUPP;
750
751 if (ec->rx_coalesce_usecs == 0)
752 return -EINVAL;
753
754 if ((ec->tx_coalesce_usecs == 0) &&
755 (ec->tx_max_coalesced_frames == 0))
756 return -EINVAL;
757
758 if ((ec->tx_coalesce_usecs > STMMAC_MAX_COAL_TX_TICK) ||
759 (ec->tx_max_coalesced_frames > STMMAC_TX_MAX_FRAMES))
760 return -EINVAL;
761
762 rx_riwt = stmmac_usec2riwt(ec->rx_coalesce_usecs, priv);
763
764 if ((rx_riwt > MAX_DMA_RIWT) || (rx_riwt < MIN_DMA_RIWT))
765 return -EINVAL;
766 else if (!priv->use_riwt)
767 return -EOPNOTSUPP;
768
769 /* Only copy relevant parameters, ignore all others. */
770 priv->tx_coal_frames = ec->tx_max_coalesced_frames;
771 priv->tx_coal_timer = ec->tx_coalesce_usecs;
772 priv->rx_riwt = rx_riwt;
773 priv->hw->dma->rx_watchdog(priv->ioaddr, priv->rx_riwt);
774
775 return 0;
776 }
777
778 static int stmmac_get_ts_info(struct net_device *dev,
779 struct ethtool_ts_info *info)
780 {
781 struct stmmac_priv *priv = netdev_priv(dev);
782
783 if ((priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) {
784
785 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
786 SOF_TIMESTAMPING_TX_HARDWARE |
787 SOF_TIMESTAMPING_RX_SOFTWARE |
788 SOF_TIMESTAMPING_RX_HARDWARE |
789 SOF_TIMESTAMPING_SOFTWARE |
790 SOF_TIMESTAMPING_RAW_HARDWARE;
791
792 if (priv->ptp_clock)
793 info->phc_index = ptp_clock_index(priv->ptp_clock);
794
795 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
796
797 info->rx_filters = ((1 << HWTSTAMP_FILTER_NONE) |
798 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
799 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
800 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
801 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
802 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
803 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
804 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) |
805 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) |
806 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) |
807 (1 << HWTSTAMP_FILTER_ALL));
808 return 0;
809 } else
810 return ethtool_op_get_ts_info(dev, info);
811 }
812
813 static int stmmac_get_tunable(struct net_device *dev,
814 const struct ethtool_tunable *tuna, void *data)
815 {
816 struct stmmac_priv *priv = netdev_priv(dev);
817 int ret = 0;
818
819 switch (tuna->id) {
820 case ETHTOOL_RX_COPYBREAK:
821 *(u32 *)data = priv->rx_copybreak;
822 break;
823 default:
824 ret = -EINVAL;
825 break;
826 }
827
828 return ret;
829 }
830
831 static int stmmac_set_tunable(struct net_device *dev,
832 const struct ethtool_tunable *tuna,
833 const void *data)
834 {
835 struct stmmac_priv *priv = netdev_priv(dev);
836 int ret = 0;
837
838 switch (tuna->id) {
839 case ETHTOOL_RX_COPYBREAK:
840 priv->rx_copybreak = *(u32 *)data;
841 break;
842 default:
843 ret = -EINVAL;
844 break;
845 }
846
847 return ret;
848 }
849
850 static const struct ethtool_ops stmmac_ethtool_ops = {
851 .begin = stmmac_check_if_running,
852 .get_drvinfo = stmmac_ethtool_getdrvinfo,
853 .get_settings = stmmac_ethtool_getsettings,
854 .set_settings = stmmac_ethtool_setsettings,
855 .get_msglevel = stmmac_ethtool_getmsglevel,
856 .set_msglevel = stmmac_ethtool_setmsglevel,
857 .get_regs = stmmac_ethtool_gregs,
858 .get_regs_len = stmmac_ethtool_get_regs_len,
859 .get_link = ethtool_op_get_link,
860 .get_pauseparam = stmmac_get_pauseparam,
861 .set_pauseparam = stmmac_set_pauseparam,
862 .get_ethtool_stats = stmmac_get_ethtool_stats,
863 .get_strings = stmmac_get_strings,
864 .get_wol = stmmac_get_wol,
865 .set_wol = stmmac_set_wol,
866 .get_eee = stmmac_ethtool_op_get_eee,
867 .set_eee = stmmac_ethtool_op_set_eee,
868 .get_sset_count = stmmac_get_sset_count,
869 .get_ts_info = stmmac_get_ts_info,
870 .get_coalesce = stmmac_get_coalesce,
871 .set_coalesce = stmmac_set_coalesce,
872 .get_tunable = stmmac_get_tunable,
873 .set_tunable = stmmac_set_tunable,
874 };
875
876 void stmmac_set_ethtool_ops(struct net_device *netdev)
877 {
878 netdev->ethtool_ops = &stmmac_ethtool_ops;
879 }
CRIS linux kernel tree