drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c

   1 /*******************************************************************************
   2   STMMAC Ethernet Driver -- MDIO bus implementation
   3   Provides Bus interface for MII registers
   4
   5   Copyright (C) 2007-2009  STMicroelectronics Ltd
   6
   7   This program is free software; you can redistribute it and/or modify it
   8   under the terms and conditions of the GNU General Public License,
   9   version 2, as published by the Free Software Foundation.
  10
  11   This program is distributed in the hope it will be useful, but WITHOUT
  12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14   more details.
  15
  16   You should have received a copy of the GNU General Public License along with
  17   this program; if not, write to the Free Software Foundation, Inc.,
  18   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19
  20   The full GNU General Public License is included in this distribution in
  21   the file called "COPYING".
  22
  23   Author: Carl Shaw <carl.shaw@st.com>
  24   Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  25 *******************************************************************************/
  26
  27 #include <linux/mii.h>
  28 #include <linux/phy.h>
  29 #include <linux/slab.h>
  30 #include <linux/of.h>
  31 #include <linux/of_gpio.h>
  32 #include <linux/of_mdio.h>
  33 #include <asm/io.h>
  34
  35 #include "stmmac.h"
  36
  37 #define MII_BUSY 0x00000001
  38 #define MII_WRITE 0x00000002
  39
  40 /* GMAC4 defines */
  41 #define MII_GMAC4_GOC_SHIFT             2
  42 #define MII_GMAC4_WRITE                 (1 << MII_GMAC4_GOC_SHIFT)
  43 #define MII_GMAC4_READ                  (3 << MII_GMAC4_GOC_SHIFT)
  44
  45 #define MII_PHY_ADDR_GMAC4_SHIFT        21
  46 #define MII_PHY_ADDR_GMAC4_MASK         GENMASK(25, 21)
  47 #define MII_PHY_REG_GMAC4_SHIFT         16
  48 #define MII_PHY_REG_GMAC4_MASK          GENMASK(20, 16)
  49 #define MII_CSR_CLK_GMAC4_SHIFT         8
  50 #define MII_CSR_CLK_GMAC4_MASK          GENMASK(11, 8)
  51
  52 static int stmmac_mdio_busy_wait(void __iomem *ioaddr, unsigned int mii_addr)
  53 {
  54         unsigned long curr;
  55         unsigned long finish = jiffies + 3 * HZ;
  56
  57         do {
  58                 curr = jiffies;
  59                 if (readl(ioaddr + mii_addr) & MII_BUSY)
  60                         cpu_relax();
  61                 else
  62                         return 0;
  63         } while (!time_after_eq(curr, finish));
  64
  65         return -EBUSY;
  66 }
  67
  68 /**
  69  * stmmac_mdio_read
  70  * @bus: points to the mii_bus structure
  71  * @phyaddr: MII addr reg bits 15-11
  72  * @phyreg: MII addr reg bits 10-6
  73  * Description: it reads data from the MII register from within the phy device.
  74  * For the 7111 GMAC, we must set the bit 0 in the MII address register while
  75  * accessing the PHY registers.
  76  * Fortunately, it seems this has no drawback for the 7109 MAC.
  77  */
  78 static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
  79 {
  80         struct net_device *ndev = bus->priv;
  81         struct stmmac_priv *priv = netdev_priv(ndev);
  82         unsigned int mii_address = priv->hw->mii.addr;
  83         unsigned int mii_data = priv->hw->mii.data;
  84
  85         int data;
  86         u16 regValue = (((phyaddr << 11) & (0x0000F800)) |
  87                         ((phyreg << 6) & (0x000007C0)));
  88         regValue |= MII_BUSY | ((priv->clk_csr & 0xF) << 2);
  89
  90         if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))
  91                 return -EBUSY;
  92
  93         writel(regValue, priv->ioaddr + mii_address);
  94
  95         if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))
  96                 return -EBUSY;
  97
  98         /* Read the data from the MII data register */
  99         data = (int)readl(priv->ioaddr + mii_data);
 100
 101         return data;
 102 }
 103
 104 /**
 105  * stmmac_mdio_write
 106  * @bus: points to the mii_bus structure
 107  * @phyaddr: MII addr reg bits 15-11
 108  * @phyreg: MII addr reg bits 10-6
 109  * @phydata: phy data
 110  * Description: it writes the data into the MII register from within the device.
 111  */
 112 static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
 113                              u16 phydata)
 114 {
 115         struct net_device *ndev = bus->priv;
 116         struct stmmac_priv *priv = netdev_priv(ndev);
 117         unsigned int mii_address = priv->hw->mii.addr;
 118         unsigned int mii_data = priv->hw->mii.data;
 119
 120         u16 value =
 121             (((phyaddr << 11) & (0x0000F800)) | ((phyreg << 6) & (0x000007C0)))
 122             | MII_WRITE;
 123
 124         value |= MII_BUSY | ((priv->clk_csr & 0xF) << 2);
 125
 126         /* Wait until any existing MII operation is complete */
 127         if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))
 128                 return -EBUSY;
 129
 130         /* Set the MII address register to write */
 131         writel(phydata, priv->ioaddr + mii_data);
 132         writel(value, priv->ioaddr + mii_address);
 133
 134         /* Wait until any existing MII operation is complete */
 135         return stmmac_mdio_busy_wait(priv->ioaddr, mii_address);
 136 }
 137
 138 /**
 139  * stmmac_mdio_read_gmac4
 140  * @bus: points to the mii_bus structure
 141  * @phyaddr: MII addr reg bits 25-21
 142  * @phyreg: MII addr reg bits 20-16
 143  * Description: it reads data from the MII register of GMAC4 from within
 144  * the phy device.
 145  */
 146 static int stmmac_mdio_read_gmac4(struct mii_bus *bus, int phyaddr, int phyreg)
 147 {
 148         struct net_device *ndev = bus->priv;
 149         struct stmmac_priv *priv = netdev_priv(ndev);
 150         unsigned int mii_address = priv->hw->mii.addr;
 151         unsigned int mii_data = priv->hw->mii.data;
 152         int data;
 153         u32 value = (((phyaddr << MII_PHY_ADDR_GMAC4_SHIFT) &
 154                      (MII_PHY_ADDR_GMAC4_MASK)) |
 155                      ((phyreg << MII_PHY_REG_GMAC4_SHIFT) &
 156                      (MII_PHY_REG_GMAC4_MASK))) | MII_GMAC4_READ;
 157
 158         value |= MII_BUSY | ((priv->clk_csr & MII_CSR_CLK_GMAC4_MASK)
 159                  << MII_CSR_CLK_GMAC4_SHIFT);
 160
 161         if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))
 162                 return -EBUSY;
 163
 164         writel(value, priv->ioaddr + mii_address);
 165
 166         if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))
 167                 return -EBUSY;
 168
 169         /* Read the data from the MII data register */
 170         data = (int)readl(priv->ioaddr + mii_data);
 171
 172         return data;
 173 }
 174
 175 /**
 176  * stmmac_mdio_write_gmac4
 177  * @bus: points to the mii_bus structure
 178  * @phyaddr: MII addr reg bits 25-21
 179  * @phyreg: MII addr reg bits 20-16
 180  * @phydata: phy data
 181  * Description: it writes the data into the MII register of GMAC4 from within
 182  * the device.
 183  */
 184 static int stmmac_mdio_write_gmac4(struct mii_bus *bus, int phyaddr, int phyreg,
 185                                    u16 phydata)
 186 {
 187         struct net_device *ndev = bus->priv;
 188         struct stmmac_priv *priv = netdev_priv(ndev);
 189         unsigned int mii_address = priv->hw->mii.addr;
 190         unsigned int mii_data = priv->hw->mii.data;
 191
 192         u32 value = (((phyaddr << MII_PHY_ADDR_GMAC4_SHIFT) &
 193                      (MII_PHY_ADDR_GMAC4_MASK)) |
 194                      ((phyreg << MII_PHY_REG_GMAC4_SHIFT) &
 195                      (MII_PHY_REG_GMAC4_MASK))) | MII_GMAC4_WRITE;
 196
 197         value |= MII_BUSY | ((priv->clk_csr & MII_CSR_CLK_GMAC4_MASK)
 198                  << MII_CSR_CLK_GMAC4_SHIFT);
 199
 200         /* Wait until any existing MII operation is complete */
 201         if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))
 202                 return -EBUSY;
 203
 204         /* Set the MII address register to write */
 205         writel(phydata, priv->ioaddr + mii_data);
 206         writel(value, priv->ioaddr + mii_address);
 207
 208         /* Wait until any existing MII operation is complete */
 209         return stmmac_mdio_busy_wait(priv->ioaddr, mii_address);
 210 }
 211
 212 /**
 213  * stmmac_mdio_reset
 214  * @bus: points to the mii_bus structure
 215  * Description: reset the MII bus
 216  */
 217 int stmmac_mdio_reset(struct mii_bus *bus)
 218 {
 219 #if defined(CONFIG_STMMAC_PLATFORM)
 220         struct net_device *ndev = bus->priv;
 221         struct stmmac_priv *priv = netdev_priv(ndev);
 222         unsigned int mii_address = priv->hw->mii.addr;
 223         struct stmmac_mdio_bus_data *data = priv->plat->mdio_bus_data;
 224
 225 #ifdef CONFIG_OF
 226         if (priv->device->of_node) {
 227
 228                 if (data->reset_gpio < 0) {
 229                         struct device_node *np = priv->device->of_node;
 230                         if (!np)
 231                                 return 0;
 232
 233                         data->reset_gpio = of_get_named_gpio(np,
 234                                                 "snps,reset-gpio", 0);
 235                         if (data->reset_gpio < 0)
 236                                 return 0;
 237
 238                         data->active_low = of_property_read_bool(np,
 239                                                 "snps,reset-active-low");
 240                         of_property_read_u32_array(np,
 241                                 "snps,reset-delays-us", data->delays, 3);
 242
 243                         if (gpio_request(data->reset_gpio, "mdio-reset"))
 244                                 return 0;
 245                 }
 246
 247                 gpio_direction_output(data->reset_gpio,
 248                                       data->active_low ? 1 : 0);
 249                 if (data->delays[0])
 250                         msleep(DIV_ROUND_UP(data->delays[0], 1000));
 251
 252                 gpio_set_value(data->reset_gpio, data->active_low ? 0 : 1);
 253                 if (data->delays[1])
 254                         msleep(DIV_ROUND_UP(data->delays[1], 1000));
 255
 256                 gpio_set_value(data->reset_gpio, data->active_low ? 1 : 0);
 257                 if (data->delays[2])
 258                         msleep(DIV_ROUND_UP(data->delays[2], 1000));
 259         }
 260 #endif
 261
 262         if (data->phy_reset) {
 263                 pr_debug("stmmac_mdio_reset: calling phy_reset\n");
 264                 data->phy_reset(priv->plat->bsp_priv);
 265         }
 266
 267         /* This is a workaround for problems with the STE101P PHY.
 268          * It doesn't complete its reset until at least one clock cycle
 269          * on MDC, so perform a dummy mdio read. To be upadted for GMAC4
 270          * if needed.
 271          */
 272         if (!priv->plat->has_gmac4)
 273                 writel(0, priv->ioaddr + mii_address);
 274 #endif
 275         return 0;
 276 }
 277
 278 /**
 279  * stmmac_mdio_register
 280  * @ndev: net device structure
 281  * Description: it registers the MII bus
 282  */
 283 int stmmac_mdio_register(struct net_device *ndev)
 284 {
 285         int err = 0;
 286         struct mii_bus *new_bus;
 287         struct stmmac_priv *priv = netdev_priv(ndev);
 288         struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data;
 289         struct device_node *mdio_node = priv->plat->mdio_node;
 290         int addr, found;
 291
 292         if (!mdio_bus_data)
 293                 return 0;
 294
 295         new_bus = mdiobus_alloc();
 296         if (new_bus == NULL)
 297                 return -ENOMEM;
 298
 299         if (mdio_bus_data->irqs)
 300                 memcpy(new_bus->irq, mdio_bus_data->irqs, sizeof(new_bus->irq));
 301
 302 #ifdef CONFIG_OF
 303         if (priv->device->of_node)
 304                 mdio_bus_data->reset_gpio = -1;
 305 #endif
 306
 307         new_bus->name = "stmmac";
 308         if (priv->plat->has_gmac4) {
 309                 new_bus->read = &stmmac_mdio_read_gmac4;
 310                 new_bus->write = &stmmac_mdio_write_gmac4;
 311         } else {
 312                 new_bus->read = &stmmac_mdio_read;
 313                 new_bus->write = &stmmac_mdio_write;
 314         }
 315
 316         new_bus->reset = &stmmac_mdio_reset;
 317         snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s-%x",
 318                  new_bus->name, priv->plat->bus_id);
 319         new_bus->priv = ndev;
 320         new_bus->phy_mask = mdio_bus_data->phy_mask;
 321         new_bus->parent = priv->device;
 322
 323         if (mdio_node)
 324                 err = of_mdiobus_register(new_bus, mdio_node);
 325         else
 326                 err = mdiobus_register(new_bus);
 327         if (err != 0) {
 328                 pr_err("%s: Cannot register as MDIO bus\n", new_bus->name);
 329                 goto bus_register_fail;
 330         }
 331
 332         if (priv->plat->phy_node || mdio_node)
 333                 goto bus_register_done;
 334
 335         found = 0;
 336         for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
 337                 struct phy_device *phydev = mdiobus_get_phy(new_bus, addr);
 338                 if (phydev) {
 339                         int act = 0;
 340                         char irq_num[4];
 341                         char *irq_str;
 342
 343                         /*
 344                          * If an IRQ was provided to be assigned after
 345                          * the bus probe, do it here.
 346                          */
 347                         if ((mdio_bus_data->irqs == NULL) &&
 348                             (mdio_bus_data->probed_phy_irq > 0)) {
 349                                 new_bus->irq[addr] =
 350                                         mdio_bus_data->probed_phy_irq;
 351                                 phydev->irq = mdio_bus_data->probed_phy_irq;
 352                         }
 353
 354                         /*
 355                          * If we're going to bind the MAC to this PHY bus,
 356                          * and no PHY number was provided to the MAC,
 357                          * use the one probed here.
 358                          */
 359                         if (priv->plat->phy_addr == -1)
 360                                 priv->plat->phy_addr = addr;
 361
 362                         act = (priv->plat->phy_addr == addr);
 363                         switch (phydev->irq) {
 364                         case PHY_POLL:
 365                                 irq_str = "POLL";
 366                                 break;
 367                         case PHY_IGNORE_INTERRUPT:
 368                                 irq_str = "IGNORE";
 369                                 break;
 370                         default:
 371                                 sprintf(irq_num, "%d", phydev->irq);
 372                                 irq_str = irq_num;
 373                                 break;
 374                         }
 375                         pr_info("%s: PHY ID %08x at %d IRQ %s (%s)%s\n",
 376                                 ndev->name, phydev->phy_id, addr,
 377                                 irq_str, phydev_name(phydev),
 378                                 act ? " active" : "");
 379                         found = 1;
 380                 }
 381         }
 382
 383         if (!found && !mdio_node) {
 384                 pr_warn("%s: No PHY found\n", ndev->name);
 385                 mdiobus_unregister(new_bus);
 386                 mdiobus_free(new_bus);
 387                 return -ENODEV;
 388         }
 389
 390 bus_register_done:
 391         priv->mii = new_bus;
 392
 393         return 0;
 394
 395 bus_register_fail:
 396         mdiobus_free(new_bus);
 397         return err;
 398 }
 399
 400 /**
 401  * stmmac_mdio_unregister
 402  * @ndev: net device structure
 403  * Description: it unregisters the MII bus
 404  */
 405 int stmmac_mdio_unregister(struct net_device *ndev)
 406 {
 407         struct stmmac_priv *priv = netdev_priv(ndev);
 408
 409         if (!priv->mii)
 410                 return 0;
 411
 412         mdiobus_unregister(priv->mii);
 413         priv->mii->priv = NULL;
 414         mdiobus_free(priv->mii);
 415         priv->mii = NULL;
 416
 417         return 0;
 418 }