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Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[cris-mirror.git] / drivers / net / ethernet / wiznet / w5100.c
blob37ab46cdbec4b9059bd3eec7eb1e148eaa3cb3dd
1 /*
2 * Ethernet driver for the WIZnet W5100 chip.
3 *
4 * Copyright (C) 2006-2008 WIZnet Co.,Ltd.
5 * Copyright (C) 2012 Mike Sinkovsky <msink@permonline.ru>
6 *
7 * Licensed under the GPL-2 or later.
8 */
9
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/kconfig.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/platform_device.h>
16 #include <linux/platform_data/wiznet.h>
17 #include <linux/ethtool.h>
18 #include <linux/skbuff.h>
19 #include <linux/types.h>
20 #include <linux/errno.h>
21 #include <linux/delay.h>
22 #include <linux/slab.h>
23 #include <linux/spinlock.h>
24 #include <linux/io.h>
25 #include <linux/ioport.h>
26 #include <linux/interrupt.h>
27 #include <linux/irq.h>
28 #include <linux/gpio.h>
29
30 #include "w5100.h"
31
32 #define DRV_NAME "w5100"
33 #define DRV_VERSION "2012-04-04"
34
35 MODULE_DESCRIPTION("WIZnet W5100 Ethernet driver v"DRV_VERSION);
36 MODULE_AUTHOR("Mike Sinkovsky <msink@permonline.ru>");
37 MODULE_ALIAS("platform:"DRV_NAME);
38 MODULE_LICENSE("GPL");
39
40 /*
41 * W5100/W5200/W5500 common registers
42 */
43 #define W5100_COMMON_REGS 0x0000
44 #define W5100_MR 0x0000 /* Mode Register */
45 #define MR_RST 0x80 /* S/W reset */
46 #define MR_PB 0x10 /* Ping block */
47 #define MR_AI 0x02 /* Address Auto-Increment */
48 #define MR_IND 0x01 /* Indirect mode */
49 #define W5100_SHAR 0x0009 /* Source MAC address */
50 #define W5100_IR 0x0015 /* Interrupt Register */
51 #define W5100_COMMON_REGS_LEN 0x0040
52
53 #define W5100_Sn_MR 0x0000 /* Sn Mode Register */
54 #define W5100_Sn_CR 0x0001 /* Sn Command Register */
55 #define W5100_Sn_IR 0x0002 /* Sn Interrupt Register */
56 #define W5100_Sn_SR 0x0003 /* Sn Status Register */
57 #define W5100_Sn_TX_FSR 0x0020 /* Sn Transmit free memory size */
58 #define W5100_Sn_TX_RD 0x0022 /* Sn Transmit memory read pointer */
59 #define W5100_Sn_TX_WR 0x0024 /* Sn Transmit memory write pointer */
60 #define W5100_Sn_RX_RSR 0x0026 /* Sn Receive free memory size */
61 #define W5100_Sn_RX_RD 0x0028 /* Sn Receive memory read pointer */
62
63 #define S0_REGS(priv) ((priv)->s0_regs)
64
65 #define W5100_S0_MR(priv) (S0_REGS(priv) + W5100_Sn_MR)
66 #define S0_MR_MACRAW 0x04 /* MAC RAW mode */
67 #define S0_MR_MF 0x40 /* MAC Filter for W5100 and W5200 */
68 #define W5500_S0_MR_MF 0x80 /* MAC Filter for W5500 */
69 #define W5100_S0_CR(priv) (S0_REGS(priv) + W5100_Sn_CR)
70 #define S0_CR_OPEN 0x01 /* OPEN command */
71 #define S0_CR_CLOSE 0x10 /* CLOSE command */
72 #define S0_CR_SEND 0x20 /* SEND command */
73 #define S0_CR_RECV 0x40 /* RECV command */
74 #define W5100_S0_IR(priv) (S0_REGS(priv) + W5100_Sn_IR)
75 #define S0_IR_SENDOK 0x10 /* complete sending */
76 #define S0_IR_RECV 0x04 /* receiving data */
77 #define W5100_S0_SR(priv) (S0_REGS(priv) + W5100_Sn_SR)
78 #define S0_SR_MACRAW 0x42 /* mac raw mode */
79 #define W5100_S0_TX_FSR(priv) (S0_REGS(priv) + W5100_Sn_TX_FSR)
80 #define W5100_S0_TX_RD(priv) (S0_REGS(priv) + W5100_Sn_TX_RD)
81 #define W5100_S0_TX_WR(priv) (S0_REGS(priv) + W5100_Sn_TX_WR)
82 #define W5100_S0_RX_RSR(priv) (S0_REGS(priv) + W5100_Sn_RX_RSR)
83 #define W5100_S0_RX_RD(priv) (S0_REGS(priv) + W5100_Sn_RX_RD)
84
85 #define W5100_S0_REGS_LEN 0x0040
86
87 /*
88 * W5100 and W5200 common registers
89 */
90 #define W5100_IMR 0x0016 /* Interrupt Mask Register */
91 #define IR_S0 0x01 /* S0 interrupt */
92 #define W5100_RTR 0x0017 /* Retry Time-value Register */
93 #define RTR_DEFAULT 2000 /* =0x07d0 (2000) */
94
95 /*
96 * W5100 specific register and memory
97 */
98 #define W5100_RMSR 0x001a /* Receive Memory Size */
99 #define W5100_TMSR 0x001b /* Transmit Memory Size */
100
101 #define W5100_S0_REGS 0x0400
102
103 #define W5100_TX_MEM_START 0x4000
104 #define W5100_TX_MEM_SIZE 0x2000
105 #define W5100_RX_MEM_START 0x6000
106 #define W5100_RX_MEM_SIZE 0x2000
107
108 /*
109 * W5200 specific register and memory
110 */
111 #define W5200_S0_REGS 0x4000
112
113 #define W5200_Sn_RXMEM_SIZE(n) (0x401e + (n) * 0x0100) /* Sn RX Memory Size */
114 #define W5200_Sn_TXMEM_SIZE(n) (0x401f + (n) * 0x0100) /* Sn TX Memory Size */
115
116 #define W5200_TX_MEM_START 0x8000
117 #define W5200_TX_MEM_SIZE 0x4000
118 #define W5200_RX_MEM_START 0xc000
119 #define W5200_RX_MEM_SIZE 0x4000
120
121 /*
122 * W5500 specific register and memory
123 *
124 * W5500 register and memory are organized by multiple blocks. Each one is
125 * selected by 16bits offset address and 5bits block select bits. So we
126 * encode it into 32bits address. (lower 16bits is offset address and
127 * upper 16bits is block select bits)
128 */
129 #define W5500_SIMR 0x0018 /* Socket Interrupt Mask Register */
130 #define W5500_RTR 0x0019 /* Retry Time-value Register */
131
132 #define W5500_S0_REGS 0x10000
133
134 #define W5500_Sn_RXMEM_SIZE(n) \
135 (0x1001e + (n) * 0x40000) /* Sn RX Memory Size */
136 #define W5500_Sn_TXMEM_SIZE(n) \
137 (0x1001f + (n) * 0x40000) /* Sn TX Memory Size */
138
139 #define W5500_TX_MEM_START 0x20000
140 #define W5500_TX_MEM_SIZE 0x04000
141 #define W5500_RX_MEM_START 0x30000
142 #define W5500_RX_MEM_SIZE 0x04000
143
144 /*
145 * Device driver private data structure
146 */
147
148 struct w5100_priv {
149 const struct w5100_ops *ops;
150
151 /* Socket 0 register offset address */
152 u32 s0_regs;
153 /* Socket 0 TX buffer offset address and size */
154 u32 s0_tx_buf;
155 u16 s0_tx_buf_size;
156 /* Socket 0 RX buffer offset address and size */
157 u32 s0_rx_buf;
158 u16 s0_rx_buf_size;
159
160 int irq;
161 int link_irq;
162 int link_gpio;
163
164 struct napi_struct napi;
165 struct net_device *ndev;
166 bool promisc;
167 u32 msg_enable;
168
169 struct workqueue_struct *xfer_wq;
170 struct work_struct rx_work;
171 struct sk_buff *tx_skb;
172 struct work_struct tx_work;
173 struct work_struct setrx_work;
174 struct work_struct restart_work;
175 };
176
177 /************************************************************************
178 *
179 * Lowlevel I/O functions
180 *
181 ***********************************************************************/
182
183 struct w5100_mmio_priv {
184 void __iomem *base;
185 /* Serialize access in indirect address mode */
186 spinlock_t reg_lock;
187 };
188
189 static inline struct w5100_mmio_priv *w5100_mmio_priv(struct net_device *dev)
190 {
191 return w5100_ops_priv(dev);
192 }
193
194 static inline void __iomem *w5100_mmio(struct net_device *ndev)
195 {
196 struct w5100_mmio_priv *mmio_priv = w5100_mmio_priv(ndev);
197
198 return mmio_priv->base;
199 }
200
201 /*
202 * In direct address mode host system can directly access W5100 registers
203 * after mapping to Memory-Mapped I/O space.
204 *
205 * 0x8000 bytes are required for memory space.
206 */
207 static inline int w5100_read_direct(struct net_device *ndev, u32 addr)
208 {
209 return ioread8(w5100_mmio(ndev) + (addr << CONFIG_WIZNET_BUS_SHIFT));
210 }
211
212 static inline int __w5100_write_direct(struct net_device *ndev, u32 addr,
213 u8 data)
214 {
215 iowrite8(data, w5100_mmio(ndev) + (addr << CONFIG_WIZNET_BUS_SHIFT));
216
217 return 0;
218 }
219
220 static inline int w5100_write_direct(struct net_device *ndev, u32 addr, u8 data)
221 {
222 __w5100_write_direct(ndev, addr, data);
223 mmiowb();
224
225 return 0;
226 }
227
228 static int w5100_read16_direct(struct net_device *ndev, u32 addr)
229 {
230 u16 data;
231 data = w5100_read_direct(ndev, addr) << 8;
232 data |= w5100_read_direct(ndev, addr + 1);
233 return data;
234 }
235
236 static int w5100_write16_direct(struct net_device *ndev, u32 addr, u16 data)
237 {
238 __w5100_write_direct(ndev, addr, data >> 8);
239 __w5100_write_direct(ndev, addr + 1, data);
240 mmiowb();
241
242 return 0;
243 }
244
245 static int w5100_readbulk_direct(struct net_device *ndev, u32 addr, u8 *buf,
246 int len)
247 {
248 int i;
249
250 for (i = 0; i < len; i++, addr++)
251 *buf++ = w5100_read_direct(ndev, addr);
252
253 return 0;
254 }
255
256 static int w5100_writebulk_direct(struct net_device *ndev, u32 addr,
257 const u8 *buf, int len)
258 {
259 int i;
260
261 for (i = 0; i < len; i++, addr++)
262 __w5100_write_direct(ndev, addr, *buf++);
263
264 mmiowb();
265
266 return 0;
267 }
268
269 static int w5100_mmio_init(struct net_device *ndev)
270 {
271 struct platform_device *pdev = to_platform_device(ndev->dev.parent);
272 struct w5100_priv *priv = netdev_priv(ndev);
273 struct w5100_mmio_priv *mmio_priv = w5100_mmio_priv(ndev);
274 struct resource *mem;
275
276 spin_lock_init(&mmio_priv->reg_lock);
277
278 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
279 mmio_priv->base = devm_ioremap_resource(&pdev->dev, mem);
280 if (IS_ERR(mmio_priv->base))
281 return PTR_ERR(mmio_priv->base);
282
283 netdev_info(ndev, "at 0x%llx irq %d\n", (u64)mem->start, priv->irq);
284
285 return 0;
286 }
287
288 static const struct w5100_ops w5100_mmio_direct_ops = {
289 .chip_id = W5100,
290 .read = w5100_read_direct,
291 .write = w5100_write_direct,
292 .read16 = w5100_read16_direct,
293 .write16 = w5100_write16_direct,
294 .readbulk = w5100_readbulk_direct,
295 .writebulk = w5100_writebulk_direct,
296 .init = w5100_mmio_init,
297 };
298
299 /*
300 * In indirect address mode host system indirectly accesses registers by
301 * using Indirect Mode Address Register (IDM_AR) and Indirect Mode Data
302 * Register (IDM_DR), which are directly mapped to Memory-Mapped I/O space.
303 * Mode Register (MR) is directly accessible.
304 *
305 * Only 0x04 bytes are required for memory space.
306 */
307 #define W5100_IDM_AR 0x01 /* Indirect Mode Address Register */
308 #define W5100_IDM_DR 0x03 /* Indirect Mode Data Register */
309
310 static int w5100_read_indirect(struct net_device *ndev, u32 addr)
311 {
312 struct w5100_mmio_priv *mmio_priv = w5100_mmio_priv(ndev);
313 unsigned long flags;
314 u8 data;
315
316 spin_lock_irqsave(&mmio_priv->reg_lock, flags);
317 w5100_write16_direct(ndev, W5100_IDM_AR, addr);
318 data = w5100_read_direct(ndev, W5100_IDM_DR);
319 spin_unlock_irqrestore(&mmio_priv->reg_lock, flags);
320
321 return data;
322 }
323
324 static int w5100_write_indirect(struct net_device *ndev, u32 addr, u8 data)
325 {
326 struct w5100_mmio_priv *mmio_priv = w5100_mmio_priv(ndev);
327 unsigned long flags;
328
329 spin_lock_irqsave(&mmio_priv->reg_lock, flags);
330 w5100_write16_direct(ndev, W5100_IDM_AR, addr);
331 w5100_write_direct(ndev, W5100_IDM_DR, data);
332 spin_unlock_irqrestore(&mmio_priv->reg_lock, flags);
333
334 return 0;
335 }
336
337 static int w5100_read16_indirect(struct net_device *ndev, u32 addr)
338 {
339 struct w5100_mmio_priv *mmio_priv = w5100_mmio_priv(ndev);
340 unsigned long flags;
341 u16 data;
342
343 spin_lock_irqsave(&mmio_priv->reg_lock, flags);
344 w5100_write16_direct(ndev, W5100_IDM_AR, addr);
345 data = w5100_read_direct(ndev, W5100_IDM_DR) << 8;
346 data |= w5100_read_direct(ndev, W5100_IDM_DR);
347 spin_unlock_irqrestore(&mmio_priv->reg_lock, flags);
348
349 return data;
350 }
351
352 static int w5100_write16_indirect(struct net_device *ndev, u32 addr, u16 data)
353 {
354 struct w5100_mmio_priv *mmio_priv = w5100_mmio_priv(ndev);
355 unsigned long flags;
356
357 spin_lock_irqsave(&mmio_priv->reg_lock, flags);
358 w5100_write16_direct(ndev, W5100_IDM_AR, addr);
359 __w5100_write_direct(ndev, W5100_IDM_DR, data >> 8);
360 w5100_write_direct(ndev, W5100_IDM_DR, data);
361 spin_unlock_irqrestore(&mmio_priv->reg_lock, flags);
362
363 return 0;
364 }
365
366 static int w5100_readbulk_indirect(struct net_device *ndev, u32 addr, u8 *buf,
367 int len)
368 {
369 struct w5100_mmio_priv *mmio_priv = w5100_mmio_priv(ndev);
370 unsigned long flags;
371 int i;
372
373 spin_lock_irqsave(&mmio_priv->reg_lock, flags);
374 w5100_write16_direct(ndev, W5100_IDM_AR, addr);
375
376 for (i = 0; i < len; i++)
377 *buf++ = w5100_read_direct(ndev, W5100_IDM_DR);
378
379 mmiowb();
380 spin_unlock_irqrestore(&mmio_priv->reg_lock, flags);
381
382 return 0;
383 }
384
385 static int w5100_writebulk_indirect(struct net_device *ndev, u32 addr,
386 const u8 *buf, int len)
387 {
388 struct w5100_mmio_priv *mmio_priv = w5100_mmio_priv(ndev);
389 unsigned long flags;
390 int i;
391
392 spin_lock_irqsave(&mmio_priv->reg_lock, flags);
393 w5100_write16_direct(ndev, W5100_IDM_AR, addr);
394
395 for (i = 0; i < len; i++)
396 __w5100_write_direct(ndev, W5100_IDM_DR, *buf++);
397
398 mmiowb();
399 spin_unlock_irqrestore(&mmio_priv->reg_lock, flags);
400
401 return 0;
402 }
403
404 static int w5100_reset_indirect(struct net_device *ndev)
405 {
406 w5100_write_direct(ndev, W5100_MR, MR_RST);
407 mdelay(5);
408 w5100_write_direct(ndev, W5100_MR, MR_PB | MR_AI | MR_IND);
409
410 return 0;
411 }
412
413 static const struct w5100_ops w5100_mmio_indirect_ops = {
414 .chip_id = W5100,
415 .read = w5100_read_indirect,
416 .write = w5100_write_indirect,
417 .read16 = w5100_read16_indirect,
418 .write16 = w5100_write16_indirect,
419 .readbulk = w5100_readbulk_indirect,
420 .writebulk = w5100_writebulk_indirect,
421 .init = w5100_mmio_init,
422 .reset = w5100_reset_indirect,
423 };
424
425 #if defined(CONFIG_WIZNET_BUS_DIRECT)
426
427 static int w5100_read(struct w5100_priv *priv, u32 addr)
428 {
429 return w5100_read_direct(priv->ndev, addr);
430 }
431
432 static int w5100_write(struct w5100_priv *priv, u32 addr, u8 data)
433 {
434 return w5100_write_direct(priv->ndev, addr, data);
435 }
436
437 static int w5100_read16(struct w5100_priv *priv, u32 addr)
438 {
439 return w5100_read16_direct(priv->ndev, addr);
440 }
441
442 static int w5100_write16(struct w5100_priv *priv, u32 addr, u16 data)
443 {
444 return w5100_write16_direct(priv->ndev, addr, data);
445 }
446
447 static int w5100_readbulk(struct w5100_priv *priv, u32 addr, u8 *buf, int len)
448 {
449 return w5100_readbulk_direct(priv->ndev, addr, buf, len);
450 }
451
452 static int w5100_writebulk(struct w5100_priv *priv, u32 addr, const u8 *buf,
453 int len)
454 {
455 return w5100_writebulk_direct(priv->ndev, addr, buf, len);
456 }
457
458 #elif defined(CONFIG_WIZNET_BUS_INDIRECT)
459
460 static int w5100_read(struct w5100_priv *priv, u32 addr)
461 {
462 return w5100_read_indirect(priv->ndev, addr);
463 }
464
465 static int w5100_write(struct w5100_priv *priv, u32 addr, u8 data)
466 {
467 return w5100_write_indirect(priv->ndev, addr, data);
468 }
469
470 static int w5100_read16(struct w5100_priv *priv, u32 addr)
471 {
472 return w5100_read16_indirect(priv->ndev, addr);
473 }
474
475 static int w5100_write16(struct w5100_priv *priv, u32 addr, u16 data)
476 {
477 return w5100_write16_indirect(priv->ndev, addr, data);
478 }
479
480 static int w5100_readbulk(struct w5100_priv *priv, u32 addr, u8 *buf, int len)
481 {
482 return w5100_readbulk_indirect(priv->ndev, addr, buf, len);
483 }
484
485 static int w5100_writebulk(struct w5100_priv *priv, u32 addr, const u8 *buf,
486 int len)
487 {
488 return w5100_writebulk_indirect(priv->ndev, addr, buf, len);
489 }
490
491 #else /* CONFIG_WIZNET_BUS_ANY */
492
493 static int w5100_read(struct w5100_priv *priv, u32 addr)
494 {
495 return priv->ops->read(priv->ndev, addr);
496 }
497
498 static int w5100_write(struct w5100_priv *priv, u32 addr, u8 data)
499 {
500 return priv->ops->write(priv->ndev, addr, data);
501 }
502
503 static int w5100_read16(struct w5100_priv *priv, u32 addr)
504 {
505 return priv->ops->read16(priv->ndev, addr);
506 }
507
508 static int w5100_write16(struct w5100_priv *priv, u32 addr, u16 data)
509 {
510 return priv->ops->write16(priv->ndev, addr, data);
511 }
512
513 static int w5100_readbulk(struct w5100_priv *priv, u32 addr, u8 *buf, int len)
514 {
515 return priv->ops->readbulk(priv->ndev, addr, buf, len);
516 }
517
518 static int w5100_writebulk(struct w5100_priv *priv, u32 addr, const u8 *buf,
519 int len)
520 {
521 return priv->ops->writebulk(priv->ndev, addr, buf, len);
522 }
523
524 #endif
525
526 static int w5100_readbuf(struct w5100_priv *priv, u16 offset, u8 *buf, int len)
527 {
528 u32 addr;
529 int remain = 0;
530 int ret;
531 const u32 mem_start = priv->s0_rx_buf;
532 const u16 mem_size = priv->s0_rx_buf_size;
533
534 offset %= mem_size;
535 addr = mem_start + offset;
536
537 if (offset + len > mem_size) {
538 remain = (offset + len) % mem_size;
539 len = mem_size - offset;
540 }
541
542 ret = w5100_readbulk(priv, addr, buf, len);
543 if (ret || !remain)
544 return ret;
545
546 return w5100_readbulk(priv, mem_start, buf + len, remain);
547 }
548
549 static int w5100_writebuf(struct w5100_priv *priv, u16 offset, const u8 *buf,
550 int len)
551 {
552 u32 addr;
553 int ret;
554 int remain = 0;
555 const u32 mem_start = priv->s0_tx_buf;
556 const u16 mem_size = priv->s0_tx_buf_size;
557
558 offset %= mem_size;
559 addr = mem_start + offset;
560
561 if (offset + len > mem_size) {
562 remain = (offset + len) % mem_size;
563 len = mem_size - offset;
564 }
565
566 ret = w5100_writebulk(priv, addr, buf, len);
567 if (ret || !remain)
568 return ret;
569
570 return w5100_writebulk(priv, mem_start, buf + len, remain);
571 }
572
573 static int w5100_reset(struct w5100_priv *priv)
574 {
575 if (priv->ops->reset)
576 return priv->ops->reset(priv->ndev);
577
578 w5100_write(priv, W5100_MR, MR_RST);
579 mdelay(5);
580 w5100_write(priv, W5100_MR, MR_PB);
581
582 return 0;
583 }
584
585 static int w5100_command(struct w5100_priv *priv, u16 cmd)
586 {
587 unsigned long timeout;
588
589 w5100_write(priv, W5100_S0_CR(priv), cmd);
590
591 timeout = jiffies + msecs_to_jiffies(100);
592
593 while (w5100_read(priv, W5100_S0_CR(priv)) != 0) {
594 if (time_after(jiffies, timeout))
595 return -EIO;
596 cpu_relax();
597 }
598
599 return 0;
600 }
601
602 static void w5100_write_macaddr(struct w5100_priv *priv)
603 {
604 struct net_device *ndev = priv->ndev;
605
606 w5100_writebulk(priv, W5100_SHAR, ndev->dev_addr, ETH_ALEN);
607 }
608
609 static void w5100_socket_intr_mask(struct w5100_priv *priv, u8 mask)
610 {
611 u32 imr;
612
613 if (priv->ops->chip_id == W5500)
614 imr = W5500_SIMR;
615 else
616 imr = W5100_IMR;
617
618 w5100_write(priv, imr, mask);
619 }
620
621 static void w5100_enable_intr(struct w5100_priv *priv)
622 {
623 w5100_socket_intr_mask(priv, IR_S0);
624 }
625
626 static void w5100_disable_intr(struct w5100_priv *priv)
627 {
628 w5100_socket_intr_mask(priv, 0);
629 }
630
631 static void w5100_memory_configure(struct w5100_priv *priv)
632 {
633 /* Configure 16K of internal memory
634 * as 8K RX buffer and 8K TX buffer
635 */
636 w5100_write(priv, W5100_RMSR, 0x03);
637 w5100_write(priv, W5100_TMSR, 0x03);
638 }
639
640 static void w5200_memory_configure(struct w5100_priv *priv)
641 {
642 int i;
643
644 /* Configure internal RX memory as 16K RX buffer and
645 * internal TX memory as 16K TX buffer
646 */
647 w5100_write(priv, W5200_Sn_RXMEM_SIZE(0), 0x10);
648 w5100_write(priv, W5200_Sn_TXMEM_SIZE(0), 0x10);
649
650 for (i = 1; i < 8; i++) {
651 w5100_write(priv, W5200_Sn_RXMEM_SIZE(i), 0);
652 w5100_write(priv, W5200_Sn_TXMEM_SIZE(i), 0);
653 }
654 }
655
656 static void w5500_memory_configure(struct w5100_priv *priv)
657 {
658 int i;
659
660 /* Configure internal RX memory as 16K RX buffer and
661 * internal TX memory as 16K TX buffer
662 */
663 w5100_write(priv, W5500_Sn_RXMEM_SIZE(0), 0x10);
664 w5100_write(priv, W5500_Sn_TXMEM_SIZE(0), 0x10);
665
666 for (i = 1; i < 8; i++) {
667 w5100_write(priv, W5500_Sn_RXMEM_SIZE(i), 0);
668 w5100_write(priv, W5500_Sn_TXMEM_SIZE(i), 0);
669 }
670 }
671
672 static int w5100_hw_reset(struct w5100_priv *priv)
673 {
674 u32 rtr;
675
676 w5100_reset(priv);
677
678 w5100_disable_intr(priv);
679 w5100_write_macaddr(priv);
680
681 switch (priv->ops->chip_id) {
682 case W5100:
683 w5100_memory_configure(priv);
684 rtr = W5100_RTR;
685 break;
686 case W5200:
687 w5200_memory_configure(priv);
688 rtr = W5100_RTR;
689 break;
690 case W5500:
691 w5500_memory_configure(priv);
692 rtr = W5500_RTR;
693 break;
694 default:
695 return -EINVAL;
696 }
697
698 if (w5100_read16(priv, rtr) != RTR_DEFAULT)
699 return -ENODEV;
700
701 return 0;
702 }
703
704 static void w5100_hw_start(struct w5100_priv *priv)
705 {
706 u8 mode = S0_MR_MACRAW;
707
708 if (!priv->promisc) {
709 if (priv->ops->chip_id == W5500)
710 mode |= W5500_S0_MR_MF;
711 else
712 mode |= S0_MR_MF;
713 }
714
715 w5100_write(priv, W5100_S0_MR(priv), mode);
716 w5100_command(priv, S0_CR_OPEN);
717 w5100_enable_intr(priv);
718 }
719
720 static void w5100_hw_close(struct w5100_priv *priv)
721 {
722 w5100_disable_intr(priv);
723 w5100_command(priv, S0_CR_CLOSE);
724 }
725
726 /***********************************************************************
727 *
728 * Device driver functions / callbacks
729 *
730 ***********************************************************************/
731
732 static void w5100_get_drvinfo(struct net_device *ndev,
733 struct ethtool_drvinfo *info)
734 {
735 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
736 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
737 strlcpy(info->bus_info, dev_name(ndev->dev.parent),
738 sizeof(info->bus_info));
739 }
740
741 static u32 w5100_get_link(struct net_device *ndev)
742 {
743 struct w5100_priv *priv = netdev_priv(ndev);
744
745 if (gpio_is_valid(priv->link_gpio))
746 return !!gpio_get_value(priv->link_gpio);
747
748 return 1;
749 }
750
751 static u32 w5100_get_msglevel(struct net_device *ndev)
752 {
753 struct w5100_priv *priv = netdev_priv(ndev);
754
755 return priv->msg_enable;
756 }
757
758 static void w5100_set_msglevel(struct net_device *ndev, u32 value)
759 {
760 struct w5100_priv *priv = netdev_priv(ndev);
761
762 priv->msg_enable = value;
763 }
764
765 static int w5100_get_regs_len(struct net_device *ndev)
766 {
767 return W5100_COMMON_REGS_LEN + W5100_S0_REGS_LEN;
768 }
769
770 static void w5100_get_regs(struct net_device *ndev,
771 struct ethtool_regs *regs, void *buf)
772 {
773 struct w5100_priv *priv = netdev_priv(ndev);
774
775 regs->version = 1;
776 w5100_readbulk(priv, W5100_COMMON_REGS, buf, W5100_COMMON_REGS_LEN);
777 buf += W5100_COMMON_REGS_LEN;
778 w5100_readbulk(priv, S0_REGS(priv), buf, W5100_S0_REGS_LEN);
779 }
780
781 static void w5100_restart(struct net_device *ndev)
782 {
783 struct w5100_priv *priv = netdev_priv(ndev);
784
785 netif_stop_queue(ndev);
786 w5100_hw_reset(priv);
787 w5100_hw_start(priv);
788 ndev->stats.tx_errors++;
789 netif_trans_update(ndev);
790 netif_wake_queue(ndev);
791 }
792
793 static void w5100_restart_work(struct work_struct *work)
794 {
795 struct w5100_priv *priv = container_of(work, struct w5100_priv,
796 restart_work);
797
798 w5100_restart(priv->ndev);
799 }
800
801 static void w5100_tx_timeout(struct net_device *ndev)
802 {
803 struct w5100_priv *priv = netdev_priv(ndev);
804
805 if (priv->ops->may_sleep)
806 schedule_work(&priv->restart_work);
807 else
808 w5100_restart(ndev);
809 }
810
811 static void w5100_tx_skb(struct net_device *ndev, struct sk_buff *skb)
812 {
813 struct w5100_priv *priv = netdev_priv(ndev);
814 u16 offset;
815
816 offset = w5100_read16(priv, W5100_S0_TX_WR(priv));
817 w5100_writebuf(priv, offset, skb->data, skb->len);
818 w5100_write16(priv, W5100_S0_TX_WR(priv), offset + skb->len);
819 ndev->stats.tx_bytes += skb->len;
820 ndev->stats.tx_packets++;
821 dev_kfree_skb(skb);
822
823 w5100_command(priv, S0_CR_SEND);
824 }
825
826 static void w5100_tx_work(struct work_struct *work)
827 {
828 struct w5100_priv *priv = container_of(work, struct w5100_priv,
829 tx_work);
830 struct sk_buff *skb = priv->tx_skb;
831
832 priv->tx_skb = NULL;
833
834 if (WARN_ON(!skb))
835 return;
836 w5100_tx_skb(priv->ndev, skb);
837 }
838
839 static int w5100_start_tx(struct sk_buff *skb, struct net_device *ndev)
840 {
841 struct w5100_priv *priv = netdev_priv(ndev);
842
843 netif_stop_queue(ndev);
844
845 if (priv->ops->may_sleep) {
846 WARN_ON(priv->tx_skb);
847 priv->tx_skb = skb;
848 queue_work(priv->xfer_wq, &priv->tx_work);
849 } else {
850 w5100_tx_skb(ndev, skb);
851 }
852
853 return NETDEV_TX_OK;
854 }
855
856 static struct sk_buff *w5100_rx_skb(struct net_device *ndev)
857 {
858 struct w5100_priv *priv = netdev_priv(ndev);
859 struct sk_buff *skb;
860 u16 rx_len;
861 u16 offset;
862 u8 header[2];
863 u16 rx_buf_len = w5100_read16(priv, W5100_S0_RX_RSR(priv));
864
865 if (rx_buf_len == 0)
866 return NULL;
867
868 offset = w5100_read16(priv, W5100_S0_RX_RD(priv));
869 w5100_readbuf(priv, offset, header, 2);
870 rx_len = get_unaligned_be16(header) - 2;
871
872 skb = netdev_alloc_skb_ip_align(ndev, rx_len);
873 if (unlikely(!skb)) {
874 w5100_write16(priv, W5100_S0_RX_RD(priv), offset + rx_buf_len);
875 w5100_command(priv, S0_CR_RECV);
876 ndev->stats.rx_dropped++;
877 return NULL;
878 }
879
880 skb_put(skb, rx_len);
881 w5100_readbuf(priv, offset + 2, skb->data, rx_len);
882 w5100_write16(priv, W5100_S0_RX_RD(priv), offset + 2 + rx_len);
883 w5100_command(priv, S0_CR_RECV);
884 skb->protocol = eth_type_trans(skb, ndev);
885
886 ndev->stats.rx_packets++;
887 ndev->stats.rx_bytes += rx_len;
888
889 return skb;
890 }
891
892 static void w5100_rx_work(struct work_struct *work)
893 {
894 struct w5100_priv *priv = container_of(work, struct w5100_priv,
895 rx_work);
896 struct sk_buff *skb;
897
898 while ((skb = w5100_rx_skb(priv->ndev)))
899 netif_rx_ni(skb);
900
901 w5100_enable_intr(priv);
902 }
903
904 static int w5100_napi_poll(struct napi_struct *napi, int budget)
905 {
906 struct w5100_priv *priv = container_of(napi, struct w5100_priv, napi);
907 int rx_count;
908
909 for (rx_count = 0; rx_count < budget; rx_count++) {
910 struct sk_buff *skb = w5100_rx_skb(priv->ndev);
911
912 if (skb)
913 netif_receive_skb(skb);
914 else
915 break;
916 }
917
918 if (rx_count < budget) {
919 napi_complete(napi);
920 w5100_enable_intr(priv);
921 }
922
923 return rx_count;
924 }
925
926 static irqreturn_t w5100_interrupt(int irq, void *ndev_instance)
927 {
928 struct net_device *ndev = ndev_instance;
929 struct w5100_priv *priv = netdev_priv(ndev);
930
931 int ir = w5100_read(priv, W5100_S0_IR(priv));
932 if (!ir)
933 return IRQ_NONE;
934 w5100_write(priv, W5100_S0_IR(priv), ir);
935
936 if (ir & S0_IR_SENDOK) {
937 netif_dbg(priv, tx_done, ndev, "tx done\n");
938 netif_wake_queue(ndev);
939 }
940
941 if (ir & S0_IR_RECV) {
942 w5100_disable_intr(priv);
943
944 if (priv->ops->may_sleep)
945 queue_work(priv->xfer_wq, &priv->rx_work);
946 else if (napi_schedule_prep(&priv->napi))
947 __napi_schedule(&priv->napi);
948 }
949
950 return IRQ_HANDLED;
951 }
952
953 static irqreturn_t w5100_detect_link(int irq, void *ndev_instance)
954 {
955 struct net_device *ndev = ndev_instance;
956 struct w5100_priv *priv = netdev_priv(ndev);
957
958 if (netif_running(ndev)) {
959 if (gpio_get_value(priv->link_gpio) != 0) {
960 netif_info(priv, link, ndev, "link is up\n");
961 netif_carrier_on(ndev);
962 } else {
963 netif_info(priv, link, ndev, "link is down\n");
964 netif_carrier_off(ndev);
965 }
966 }
967
968 return IRQ_HANDLED;
969 }
970
971 static void w5100_setrx_work(struct work_struct *work)
972 {
973 struct w5100_priv *priv = container_of(work, struct w5100_priv,
974 setrx_work);
975
976 w5100_hw_start(priv);
977 }
978
979 static void w5100_set_rx_mode(struct net_device *ndev)
980 {
981 struct w5100_priv *priv = netdev_priv(ndev);
982 bool set_promisc = (ndev->flags & IFF_PROMISC) != 0;
983
984 if (priv->promisc != set_promisc) {
985 priv->promisc = set_promisc;
986
987 if (priv->ops->may_sleep)
988 schedule_work(&priv->setrx_work);
989 else
990 w5100_hw_start(priv);
991 }
992 }
993
994 static int w5100_set_macaddr(struct net_device *ndev, void *addr)
995 {
996 struct w5100_priv *priv = netdev_priv(ndev);
997 struct sockaddr *sock_addr = addr;
998
999 if (!is_valid_ether_addr(sock_addr->sa_data))
1000 return -EADDRNOTAVAIL;
1001 memcpy(ndev->dev_addr, sock_addr->sa_data, ETH_ALEN);
1002 w5100_write_macaddr(priv);
1003 return 0;
1004 }
1005
1006 static int w5100_open(struct net_device *ndev)
1007 {
1008 struct w5100_priv *priv = netdev_priv(ndev);
1009
1010 netif_info(priv, ifup, ndev, "enabling\n");
1011 w5100_hw_start(priv);
1012 napi_enable(&priv->napi);
1013 netif_start_queue(ndev);
1014 if (!gpio_is_valid(priv->link_gpio) ||
1015 gpio_get_value(priv->link_gpio) != 0)
1016 netif_carrier_on(ndev);
1017 return 0;
1018 }
1019
1020 static int w5100_stop(struct net_device *ndev)
1021 {
1022 struct w5100_priv *priv = netdev_priv(ndev);
1023
1024 netif_info(priv, ifdown, ndev, "shutting down\n");
1025 w5100_hw_close(priv);
1026 netif_carrier_off(ndev);
1027 netif_stop_queue(ndev);
1028 napi_disable(&priv->napi);
1029 return 0;
1030 }
1031
1032 static const struct ethtool_ops w5100_ethtool_ops = {
1033 .get_drvinfo = w5100_get_drvinfo,
1034 .get_msglevel = w5100_get_msglevel,
1035 .set_msglevel = w5100_set_msglevel,
1036 .get_link = w5100_get_link,
1037 .get_regs_len = w5100_get_regs_len,
1038 .get_regs = w5100_get_regs,
1039 };
1040
1041 static const struct net_device_ops w5100_netdev_ops = {
1042 .ndo_open = w5100_open,
1043 .ndo_stop = w5100_stop,
1044 .ndo_start_xmit = w5100_start_tx,
1045 .ndo_tx_timeout = w5100_tx_timeout,
1046 .ndo_set_rx_mode = w5100_set_rx_mode,
1047 .ndo_set_mac_address = w5100_set_macaddr,
1048 .ndo_validate_addr = eth_validate_addr,
1049 .ndo_change_mtu = eth_change_mtu,
1050 };
1051
1052 static int w5100_mmio_probe(struct platform_device *pdev)
1053 {
1054 struct wiznet_platform_data *data = dev_get_platdata(&pdev->dev);
1055 const void *mac_addr = NULL;
1056 struct resource *mem;
1057 const struct w5100_ops *ops;
1058 int irq;
1059
1060 if (data && is_valid_ether_addr(data->mac_addr))
1061 mac_addr = data->mac_addr;
1062
1063 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1064 if (resource_size(mem) < W5100_BUS_DIRECT_SIZE)
1065 ops = &w5100_mmio_indirect_ops;
1066 else
1067 ops = &w5100_mmio_direct_ops;
1068
1069 irq = platform_get_irq(pdev, 0);
1070 if (irq < 0)
1071 return irq;
1072
1073 return w5100_probe(&pdev->dev, ops, sizeof(struct w5100_mmio_priv),
1074 mac_addr, irq, data ? data->link_gpio : -EINVAL);
1075 }
1076
1077 static int w5100_mmio_remove(struct platform_device *pdev)
1078 {
1079 return w5100_remove(&pdev->dev);
1080 }
1081
1082 void *w5100_ops_priv(const struct net_device *ndev)
1083 {
1084 return netdev_priv(ndev) +
1085 ALIGN(sizeof(struct w5100_priv), NETDEV_ALIGN);
1086 }
1087 EXPORT_SYMBOL_GPL(w5100_ops_priv);
1088
1089 int w5100_probe(struct device *dev, const struct w5100_ops *ops,
1090 int sizeof_ops_priv, const void *mac_addr, int irq,
1091 int link_gpio)
1092 {
1093 struct w5100_priv *priv;
1094 struct net_device *ndev;
1095 int err;
1096 size_t alloc_size;
1097
1098 alloc_size = sizeof(*priv);
1099 if (sizeof_ops_priv) {
1100 alloc_size = ALIGN(alloc_size, NETDEV_ALIGN);
1101 alloc_size += sizeof_ops_priv;
1102 }
1103 alloc_size += NETDEV_ALIGN - 1;
1104
1105 ndev = alloc_etherdev(alloc_size);
1106 if (!ndev)
1107 return -ENOMEM;
1108 SET_NETDEV_DEV(ndev, dev);
1109 dev_set_drvdata(dev, ndev);
1110 priv = netdev_priv(ndev);
1111
1112 switch (ops->chip_id) {
1113 case W5100:
1114 priv->s0_regs = W5100_S0_REGS;
1115 priv->s0_tx_buf = W5100_TX_MEM_START;
1116 priv->s0_tx_buf_size = W5100_TX_MEM_SIZE;
1117 priv->s0_rx_buf = W5100_RX_MEM_START;
1118 priv->s0_rx_buf_size = W5100_RX_MEM_SIZE;
1119 break;
1120 case W5200:
1121 priv->s0_regs = W5200_S0_REGS;
1122 priv->s0_tx_buf = W5200_TX_MEM_START;
1123 priv->s0_tx_buf_size = W5200_TX_MEM_SIZE;
1124 priv->s0_rx_buf = W5200_RX_MEM_START;
1125 priv->s0_rx_buf_size = W5200_RX_MEM_SIZE;
1126 break;
1127 case W5500:
1128 priv->s0_regs = W5500_S0_REGS;
1129 priv->s0_tx_buf = W5500_TX_MEM_START;
1130 priv->s0_tx_buf_size = W5500_TX_MEM_SIZE;
1131 priv->s0_rx_buf = W5500_RX_MEM_START;
1132 priv->s0_rx_buf_size = W5500_RX_MEM_SIZE;
1133 break;
1134 default:
1135 err = -EINVAL;
1136 goto err_register;
1137 }
1138
1139 priv->ndev = ndev;
1140 priv->ops = ops;
1141 priv->irq = irq;
1142 priv->link_gpio = link_gpio;
1143
1144 ndev->netdev_ops = &w5100_netdev_ops;
1145 ndev->ethtool_ops = &w5100_ethtool_ops;
1146 netif_napi_add(ndev, &priv->napi, w5100_napi_poll, 16);
1147
1148 /* This chip doesn't support VLAN packets with normal MTU,
1149 * so disable VLAN for this device.
1150 */
1151 ndev->features |= NETIF_F_VLAN_CHALLENGED;
1152
1153 err = register_netdev(ndev);
1154 if (err < 0)
1155 goto err_register;
1156
1157 priv->xfer_wq = alloc_workqueue(netdev_name(ndev), WQ_MEM_RECLAIM, 0);
1158 if (!priv->xfer_wq) {
1159 err = -ENOMEM;
1160 goto err_wq;
1161 }
1162
1163 INIT_WORK(&priv->rx_work, w5100_rx_work);
1164 INIT_WORK(&priv->tx_work, w5100_tx_work);
1165 INIT_WORK(&priv->setrx_work, w5100_setrx_work);
1166 INIT_WORK(&priv->restart_work, w5100_restart_work);
1167
1168 if (mac_addr)
1169 memcpy(ndev->dev_addr, mac_addr, ETH_ALEN);
1170 else
1171 eth_hw_addr_random(ndev);
1172
1173 if (priv->ops->init) {
1174 err = priv->ops->init(priv->ndev);
1175 if (err)
1176 goto err_hw;
1177 }
1178
1179 err = w5100_hw_reset(priv);
1180 if (err)
1181 goto err_hw;
1182
1183 if (ops->may_sleep) {
1184 err = request_threaded_irq(priv->irq, NULL, w5100_interrupt,
1185 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1186 netdev_name(ndev), ndev);
1187 } else {
1188 err = request_irq(priv->irq, w5100_interrupt,
1189 IRQF_TRIGGER_LOW, netdev_name(ndev), ndev);
1190 }
1191 if (err)
1192 goto err_hw;
1193
1194 if (gpio_is_valid(priv->link_gpio)) {
1195 char *link_name = devm_kzalloc(dev, 16, GFP_KERNEL);
1196
1197 if (!link_name) {
1198 err = -ENOMEM;
1199 goto err_gpio;
1200 }
1201 snprintf(link_name, 16, "%s-link", netdev_name(ndev));
1202 priv->link_irq = gpio_to_irq(priv->link_gpio);
1203 if (request_any_context_irq(priv->link_irq, w5100_detect_link,
1204 IRQF_TRIGGER_RISING |
1205 IRQF_TRIGGER_FALLING,
1206 link_name, priv->ndev) < 0)
1207 priv->link_gpio = -EINVAL;
1208 }
1209
1210 return 0;
1211
1212 err_gpio:
1213 free_irq(priv->irq, ndev);
1214 err_hw:
1215 destroy_workqueue(priv->xfer_wq);
1216 err_wq:
1217 unregister_netdev(ndev);
1218 err_register:
1219 free_netdev(ndev);
1220 return err;
1221 }
1222 EXPORT_SYMBOL_GPL(w5100_probe);
1223
1224 int w5100_remove(struct device *dev)
1225 {
1226 struct net_device *ndev = dev_get_drvdata(dev);
1227 struct w5100_priv *priv = netdev_priv(ndev);
1228
1229 w5100_hw_reset(priv);
1230 free_irq(priv->irq, ndev);
1231 if (gpio_is_valid(priv->link_gpio))
1232 free_irq(priv->link_irq, ndev);
1233
1234 flush_work(&priv->setrx_work);
1235 flush_work(&priv->restart_work);
1236 destroy_workqueue(priv->xfer_wq);
1237
1238 unregister_netdev(ndev);
1239 free_netdev(ndev);
1240 return 0;
1241 }
1242 EXPORT_SYMBOL_GPL(w5100_remove);
1243
1244 #ifdef CONFIG_PM_SLEEP
1245 static int w5100_suspend(struct device *dev)
1246 {
1247 struct net_device *ndev = dev_get_drvdata(dev);
1248 struct w5100_priv *priv = netdev_priv(ndev);
1249
1250 if (netif_running(ndev)) {
1251 netif_carrier_off(ndev);
1252 netif_device_detach(ndev);
1253
1254 w5100_hw_close(priv);
1255 }
1256 return 0;
1257 }
1258
1259 static int w5100_resume(struct device *dev)
1260 {
1261 struct net_device *ndev = dev_get_drvdata(dev);
1262 struct w5100_priv *priv = netdev_priv(ndev);
1263
1264 if (netif_running(ndev)) {
1265 w5100_hw_reset(priv);
1266 w5100_hw_start(priv);
1267
1268 netif_device_attach(ndev);
1269 if (!gpio_is_valid(priv->link_gpio) ||
1270 gpio_get_value(priv->link_gpio) != 0)
1271 netif_carrier_on(ndev);
1272 }
1273 return 0;
1274 }
1275 #endif /* CONFIG_PM_SLEEP */
1276
1277 SIMPLE_DEV_PM_OPS(w5100_pm_ops, w5100_suspend, w5100_resume);
1278 EXPORT_SYMBOL_GPL(w5100_pm_ops);
1279
1280 static struct platform_driver w5100_mmio_driver = {
1281 .driver = {
1282 .name = DRV_NAME,
1283 .pm = &w5100_pm_ops,
1284 },
1285 .probe = w5100_mmio_probe,
1286 .remove = w5100_mmio_remove,
1287 };
1288 module_platform_driver(w5100_mmio_driver);
CRIS linux kernel tree