drivers/spi/spi-pxa2xx-dma.c

   1 /*
   2  * PXA2xx SPI DMA engine support.
   3  *
   4  * Copyright (C) 2013, Intel Corporation
   5  * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/device.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/dmaengine.h>
  15 #include <linux/pxa2xx_ssp.h>
  16 #include <linux/scatterlist.h>
  17 #include <linux/sizes.h>
  18 #include <linux/spi/spi.h>
  19 #include <linux/spi/pxa2xx_spi.h>
  20
  21 #include "spi-pxa2xx.h"
  22
  23 static void pxa2xx_spi_dma_transfer_complete(struct driver_data *drv_data,
  24                                              bool error)
  25 {
  26         struct spi_message *msg = drv_data->cur_msg;
  27
  28         /*
  29          * It is possible that one CPU is handling ROR interrupt and other
  30          * just gets DMA completion. Calling pump_transfers() twice for the
  31          * same transfer leads to problems thus we prevent concurrent calls
  32          * by using ->dma_running.
  33          */
  34         if (atomic_dec_and_test(&drv_data->dma_running)) {
  35                 /*
  36                  * If the other CPU is still handling the ROR interrupt we
  37                  * might not know about the error yet. So we re-check the
  38                  * ROR bit here before we clear the status register.
  39                  */
  40                 if (!error) {
  41                         u32 status = pxa2xx_spi_read(drv_data, SSSR)
  42                                      & drv_data->mask_sr;
  43                         error = status & SSSR_ROR;
  44                 }
  45
  46                 /* Clear status & disable interrupts */
  47                 pxa2xx_spi_write(drv_data, SSCR1,
  48                                  pxa2xx_spi_read(drv_data, SSCR1)
  49                                  & ~drv_data->dma_cr1);
  50                 write_SSSR_CS(drv_data, drv_data->clear_sr);
  51                 if (!pxa25x_ssp_comp(drv_data))
  52                         pxa2xx_spi_write(drv_data, SSTO, 0);
  53
  54                 if (!error) {
  55                         msg->actual_length += drv_data->len;
  56                         msg->state = pxa2xx_spi_next_transfer(drv_data);
  57                 } else {
  58                         /* In case we got an error we disable the SSP now */
  59                         pxa2xx_spi_write(drv_data, SSCR0,
  60                                          pxa2xx_spi_read(drv_data, SSCR0)
  61                                          & ~SSCR0_SSE);
  62
  63                         msg->state = ERROR_STATE;
  64                 }
  65
  66                 tasklet_schedule(&drv_data->pump_transfers);
  67         }
  68 }
  69
  70 static void pxa2xx_spi_dma_callback(void *data)
  71 {
  72         pxa2xx_spi_dma_transfer_complete(data, false);
  73 }
  74
  75 static struct dma_async_tx_descriptor *
  76 pxa2xx_spi_dma_prepare_one(struct driver_data *drv_data,
  77                            enum dma_transfer_direction dir)
  78 {
  79         struct chip_data *chip = drv_data->cur_chip;
  80         struct spi_transfer *xfer = drv_data->cur_transfer;
  81         enum dma_slave_buswidth width;
  82         struct dma_slave_config cfg;
  83         struct dma_chan *chan;
  84         struct sg_table *sgt;
  85         int ret;
  86
  87         switch (drv_data->n_bytes) {
  88         case 1:
  89                 width = DMA_SLAVE_BUSWIDTH_1_BYTE;
  90                 break;
  91         case 2:
  92                 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
  93                 break;
  94         default:
  95                 width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  96                 break;
  97         }
  98
  99         memset(&cfg, 0, sizeof(cfg));
 100         cfg.direction = dir;
 101
 102         if (dir == DMA_MEM_TO_DEV) {
 103                 cfg.dst_addr = drv_data->ssdr_physical;
 104                 cfg.dst_addr_width = width;
 105                 cfg.dst_maxburst = chip->dma_burst_size;
 106
 107                 sgt = &xfer->tx_sg;
 108                 chan = drv_data->master->dma_tx;
 109         } else {
 110                 cfg.src_addr = drv_data->ssdr_physical;
 111                 cfg.src_addr_width = width;
 112                 cfg.src_maxburst = chip->dma_burst_size;
 113
 114                 sgt = &xfer->rx_sg;
 115                 chan = drv_data->master->dma_rx;
 116         }
 117
 118         ret = dmaengine_slave_config(chan, &cfg);
 119         if (ret) {
 120                 dev_warn(&drv_data->pdev->dev, "DMA slave config failed\n");
 121                 return NULL;
 122         }
 123
 124         return dmaengine_prep_slave_sg(chan, sgt->sgl, sgt->nents, dir,
 125                                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 126 }
 127
 128 irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data)
 129 {
 130         u32 status;
 131
 132         status = pxa2xx_spi_read(drv_data, SSSR) & drv_data->mask_sr;
 133         if (status & SSSR_ROR) {
 134                 dev_err(&drv_data->pdev->dev, "FIFO overrun\n");
 135
 136                 dmaengine_terminate_async(drv_data->master->dma_rx);
 137                 dmaengine_terminate_async(drv_data->master->dma_tx);
 138
 139                 pxa2xx_spi_dma_transfer_complete(drv_data, true);
 140                 return IRQ_HANDLED;
 141         }
 142
 143         return IRQ_NONE;
 144 }
 145
 146 int pxa2xx_spi_dma_prepare(struct driver_data *drv_data, u32 dma_burst)
 147 {
 148         struct dma_async_tx_descriptor *tx_desc, *rx_desc;
 149         int err = 0;
 150
 151         tx_desc = pxa2xx_spi_dma_prepare_one(drv_data, DMA_MEM_TO_DEV);
 152         if (!tx_desc) {
 153                 dev_err(&drv_data->pdev->dev,
 154                         "failed to get DMA TX descriptor\n");
 155                 err = -EBUSY;
 156                 goto err_tx;
 157         }
 158
 159         rx_desc = pxa2xx_spi_dma_prepare_one(drv_data, DMA_DEV_TO_MEM);
 160         if (!rx_desc) {
 161                 dev_err(&drv_data->pdev->dev,
 162                         "failed to get DMA RX descriptor\n");
 163                 err = -EBUSY;
 164                 goto err_rx;
 165         }
 166
 167         /* We are ready when RX completes */
 168         rx_desc->callback = pxa2xx_spi_dma_callback;
 169         rx_desc->callback_param = drv_data;
 170
 171         dmaengine_submit(rx_desc);
 172         dmaengine_submit(tx_desc);
 173         return 0;
 174
 175 err_rx:
 176         dmaengine_terminate_async(drv_data->master->dma_tx);
 177 err_tx:
 178         return err;
 179 }
 180
 181 void pxa2xx_spi_dma_start(struct driver_data *drv_data)
 182 {
 183         dma_async_issue_pending(drv_data->master->dma_rx);
 184         dma_async_issue_pending(drv_data->master->dma_tx);
 185
 186         atomic_set(&drv_data->dma_running, 1);
 187 }
 188
 189 int pxa2xx_spi_dma_setup(struct driver_data *drv_data)
 190 {
 191         struct pxa2xx_spi_master *pdata = drv_data->master_info;
 192         struct device *dev = &drv_data->pdev->dev;
 193         struct spi_master *master = drv_data->master;
 194         dma_cap_mask_t mask;
 195
 196         dma_cap_zero(mask);
 197         dma_cap_set(DMA_SLAVE, mask);
 198
 199         master->dma_tx = dma_request_slave_channel_compat(mask,
 200                                 pdata->dma_filter, pdata->tx_param, dev, "tx");
 201         if (!master->dma_tx)
 202                 return -ENODEV;
 203
 204         master->dma_rx = dma_request_slave_channel_compat(mask,
 205                                 pdata->dma_filter, pdata->rx_param, dev, "rx");
 206         if (!master->dma_rx) {
 207                 dma_release_channel(master->dma_tx);
 208                 master->dma_tx = NULL;
 209                 return -ENODEV;
 210         }
 211
 212         return 0;
 213 }
 214
 215 void pxa2xx_spi_dma_release(struct driver_data *drv_data)
 216 {
 217         struct spi_master *master = drv_data->master;
 218
 219         if (master->dma_rx) {
 220                 dmaengine_terminate_sync(master->dma_rx);
 221                 dma_release_channel(master->dma_rx);
 222                 master->dma_rx = NULL;
 223         }
 224         if (master->dma_tx) {
 225                 dmaengine_terminate_sync(master->dma_tx);
 226                 dma_release_channel(master->dma_tx);
 227                 master->dma_tx = NULL;
 228         }
 229 }
 230
 231 int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
 232                                            struct spi_device *spi,
 233                                            u8 bits_per_word, u32 *burst_code,
 234                                            u32 *threshold)
 235 {
 236         struct pxa2xx_spi_chip *chip_info = spi->controller_data;
 237
 238         /*
 239          * If the DMA burst size is given in chip_info we use that,
 240          * otherwise we use the default. Also we use the default FIFO
 241          * thresholds for now.
 242          */
 243         *burst_code = chip_info ? chip_info->dma_burst_size : 1;
 244         *threshold = SSCR1_RxTresh(RX_THRESH_DFLT)
 245                    | SSCR1_TxTresh(TX_THRESH_DFLT);
 246
 247         return 0;
 248 }