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Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[cris-mirror.git] / include / uapi / linux / perf_event.h
blobc66a485a24ac81e324ea53ea17b405a3c73b520a
1 /*
2 * Performance events:
3 *
4 * Copyright (C) 2008-2009, Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2011, Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2008-2011, Red Hat, Inc., Peter Zijlstra
7 *
8 * Data type definitions, declarations, prototypes.
9 *
10 * Started by: Thomas Gleixner and Ingo Molnar
11 *
12 * For licencing details see kernel-base/COPYING
13 */
14 #ifndef _UAPI_LINUX_PERF_EVENT_H
15 #define _UAPI_LINUX_PERF_EVENT_H
16
17 #include <linux/types.h>
18 #include <linux/ioctl.h>
19 #include <asm/byteorder.h>
20
21 /*
22 * User-space ABI bits:
23 */
24
25 /*
26 * attr.type
27 */
28 enum perf_type_id {
29 PERF_TYPE_HARDWARE = 0,
30 PERF_TYPE_SOFTWARE = 1,
31 PERF_TYPE_TRACEPOINT = 2,
32 PERF_TYPE_HW_CACHE = 3,
33 PERF_TYPE_RAW = 4,
34 PERF_TYPE_BREAKPOINT = 5,
35
36 PERF_TYPE_MAX, /* non-ABI */
37 };
38
39 /*
40 * Generalized performance event event_id types, used by the
41 * attr.event_id parameter of the sys_perf_event_open()
42 * syscall:
43 */
44 enum perf_hw_id {
45 /*
46 * Common hardware events, generalized by the kernel:
47 */
48 PERF_COUNT_HW_CPU_CYCLES = 0,
49 PERF_COUNT_HW_INSTRUCTIONS = 1,
50 PERF_COUNT_HW_CACHE_REFERENCES = 2,
51 PERF_COUNT_HW_CACHE_MISSES = 3,
52 PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4,
53 PERF_COUNT_HW_BRANCH_MISSES = 5,
54 PERF_COUNT_HW_BUS_CYCLES = 6,
55 PERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7,
56 PERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8,
57 PERF_COUNT_HW_REF_CPU_CYCLES = 9,
58
59 PERF_COUNT_HW_MAX, /* non-ABI */
60 };
61
62 /*
63 * Generalized hardware cache events:
64 *
65 * { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x
66 * { read, write, prefetch } x
67 * { accesses, misses }
68 */
69 enum perf_hw_cache_id {
70 PERF_COUNT_HW_CACHE_L1D = 0,
71 PERF_COUNT_HW_CACHE_L1I = 1,
72 PERF_COUNT_HW_CACHE_LL = 2,
73 PERF_COUNT_HW_CACHE_DTLB = 3,
74 PERF_COUNT_HW_CACHE_ITLB = 4,
75 PERF_COUNT_HW_CACHE_BPU = 5,
76 PERF_COUNT_HW_CACHE_NODE = 6,
77
78 PERF_COUNT_HW_CACHE_MAX, /* non-ABI */
79 };
80
81 enum perf_hw_cache_op_id {
82 PERF_COUNT_HW_CACHE_OP_READ = 0,
83 PERF_COUNT_HW_CACHE_OP_WRITE = 1,
84 PERF_COUNT_HW_CACHE_OP_PREFETCH = 2,
85
86 PERF_COUNT_HW_CACHE_OP_MAX, /* non-ABI */
87 };
88
89 enum perf_hw_cache_op_result_id {
90 PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0,
91 PERF_COUNT_HW_CACHE_RESULT_MISS = 1,
92
93 PERF_COUNT_HW_CACHE_RESULT_MAX, /* non-ABI */
94 };
95
96 /*
97 * Special "software" events provided by the kernel, even if the hardware
98 * does not support performance events. These events measure various
99 * physical and sw events of the kernel (and allow the profiling of them as
100 * well):
101 */
102 enum perf_sw_ids {
103 PERF_COUNT_SW_CPU_CLOCK = 0,
104 PERF_COUNT_SW_TASK_CLOCK = 1,
105 PERF_COUNT_SW_PAGE_FAULTS = 2,
106 PERF_COUNT_SW_CONTEXT_SWITCHES = 3,
107 PERF_COUNT_SW_CPU_MIGRATIONS = 4,
108 PERF_COUNT_SW_PAGE_FAULTS_MIN = 5,
109 PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6,
110 PERF_COUNT_SW_ALIGNMENT_FAULTS = 7,
111 PERF_COUNT_SW_EMULATION_FAULTS = 8,
112 PERF_COUNT_SW_DUMMY = 9,
113 PERF_COUNT_SW_BPF_OUTPUT = 10,
114
115 PERF_COUNT_SW_MAX, /* non-ABI */
116 };
117
118 /*
119 * Bits that can be set in attr.sample_type to request information
120 * in the overflow packets.
121 */
122 enum perf_event_sample_format {
123 PERF_SAMPLE_IP = 1U << 0,
124 PERF_SAMPLE_TID = 1U << 1,
125 PERF_SAMPLE_TIME = 1U << 2,
126 PERF_SAMPLE_ADDR = 1U << 3,
127 PERF_SAMPLE_READ = 1U << 4,
128 PERF_SAMPLE_CALLCHAIN = 1U << 5,
129 PERF_SAMPLE_ID = 1U << 6,
130 PERF_SAMPLE_CPU = 1U << 7,
131 PERF_SAMPLE_PERIOD = 1U << 8,
132 PERF_SAMPLE_STREAM_ID = 1U << 9,
133 PERF_SAMPLE_RAW = 1U << 10,
134 PERF_SAMPLE_BRANCH_STACK = 1U << 11,
135 PERF_SAMPLE_REGS_USER = 1U << 12,
136 PERF_SAMPLE_STACK_USER = 1U << 13,
137 PERF_SAMPLE_WEIGHT = 1U << 14,
138 PERF_SAMPLE_DATA_SRC = 1U << 15,
139 PERF_SAMPLE_IDENTIFIER = 1U << 16,
140 PERF_SAMPLE_TRANSACTION = 1U << 17,
141 PERF_SAMPLE_REGS_INTR = 1U << 18,
142
143 PERF_SAMPLE_MAX = 1U << 19, /* non-ABI */
144 };
145
146 /*
147 * values to program into branch_sample_type when PERF_SAMPLE_BRANCH is set
148 *
149 * If the user does not pass priv level information via branch_sample_type,
150 * the kernel uses the event's priv level. Branch and event priv levels do
151 * not have to match. Branch priv level is checked for permissions.
152 *
153 * The branch types can be combined, however BRANCH_ANY covers all types
154 * of branches and therefore it supersedes all the other types.
155 */
156 enum perf_branch_sample_type_shift {
157 PERF_SAMPLE_BRANCH_USER_SHIFT = 0, /* user branches */
158 PERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1, /* kernel branches */
159 PERF_SAMPLE_BRANCH_HV_SHIFT = 2, /* hypervisor branches */
160
161 PERF_SAMPLE_BRANCH_ANY_SHIFT = 3, /* any branch types */
162 PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4, /* any call branch */
163 PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5, /* any return branch */
164 PERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6, /* indirect calls */
165 PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7, /* transaction aborts */
166 PERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8, /* in transaction */
167 PERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9, /* not in transaction */
168 PERF_SAMPLE_BRANCH_COND_SHIFT = 10, /* conditional branches */
169
170 PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11, /* call/ret stack */
171 PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12, /* indirect jumps */
172 PERF_SAMPLE_BRANCH_CALL_SHIFT = 13, /* direct call */
173
174 PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT = 14, /* no flags */
175 PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT = 15, /* no cycles */
176
177 PERF_SAMPLE_BRANCH_MAX_SHIFT /* non-ABI */
178 };
179
180 enum perf_branch_sample_type {
181 PERF_SAMPLE_BRANCH_USER = 1U << PERF_SAMPLE_BRANCH_USER_SHIFT,
182 PERF_SAMPLE_BRANCH_KERNEL = 1U << PERF_SAMPLE_BRANCH_KERNEL_SHIFT,
183 PERF_SAMPLE_BRANCH_HV = 1U << PERF_SAMPLE_BRANCH_HV_SHIFT,
184
185 PERF_SAMPLE_BRANCH_ANY = 1U << PERF_SAMPLE_BRANCH_ANY_SHIFT,
186 PERF_SAMPLE_BRANCH_ANY_CALL = 1U << PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT,
187 PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT,
188 PERF_SAMPLE_BRANCH_IND_CALL = 1U << PERF_SAMPLE_BRANCH_IND_CALL_SHIFT,
189 PERF_SAMPLE_BRANCH_ABORT_TX = 1U << PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT,
190 PERF_SAMPLE_BRANCH_IN_TX = 1U << PERF_SAMPLE_BRANCH_IN_TX_SHIFT,
191 PERF_SAMPLE_BRANCH_NO_TX = 1U << PERF_SAMPLE_BRANCH_NO_TX_SHIFT,
192 PERF_SAMPLE_BRANCH_COND = 1U << PERF_SAMPLE_BRANCH_COND_SHIFT,
193
194 PERF_SAMPLE_BRANCH_CALL_STACK = 1U << PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT,
195 PERF_SAMPLE_BRANCH_IND_JUMP = 1U << PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT,
196 PERF_SAMPLE_BRANCH_CALL = 1U << PERF_SAMPLE_BRANCH_CALL_SHIFT,
197
198 PERF_SAMPLE_BRANCH_NO_FLAGS = 1U << PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT,
199 PERF_SAMPLE_BRANCH_NO_CYCLES = 1U << PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT,
200
201 PERF_SAMPLE_BRANCH_MAX = 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT,
202 };
203
204 #define PERF_SAMPLE_BRANCH_PLM_ALL \
205 (PERF_SAMPLE_BRANCH_USER|\
206 PERF_SAMPLE_BRANCH_KERNEL|\
207 PERF_SAMPLE_BRANCH_HV)
208
209 /*
210 * Values to determine ABI of the registers dump.
211 */
212 enum perf_sample_regs_abi {
213 PERF_SAMPLE_REGS_ABI_NONE = 0,
214 PERF_SAMPLE_REGS_ABI_32 = 1,
215 PERF_SAMPLE_REGS_ABI_64 = 2,
216 };
217
218 /*
219 * Values for the memory transaction event qualifier, mostly for
220 * abort events. Multiple bits can be set.
221 */
222 enum {
223 PERF_TXN_ELISION = (1 << 0), /* From elision */
224 PERF_TXN_TRANSACTION = (1 << 1), /* From transaction */
225 PERF_TXN_SYNC = (1 << 2), /* Instruction is related */
226 PERF_TXN_ASYNC = (1 << 3), /* Instruction not related */
227 PERF_TXN_RETRY = (1 << 4), /* Retry possible */
228 PERF_TXN_CONFLICT = (1 << 5), /* Conflict abort */
229 PERF_TXN_CAPACITY_WRITE = (1 << 6), /* Capacity write abort */
230 PERF_TXN_CAPACITY_READ = (1 << 7), /* Capacity read abort */
231
232 PERF_TXN_MAX = (1 << 8), /* non-ABI */
233
234 /* bits 32..63 are reserved for the abort code */
235
236 PERF_TXN_ABORT_MASK = (0xffffffffULL << 32),
237 PERF_TXN_ABORT_SHIFT = 32,
238 };
239
240 /*
241 * The format of the data returned by read() on a perf event fd,
242 * as specified by attr.read_format:
243 *
244 * struct read_format {
245 * { u64 value;
246 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED
247 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING
248 * { u64 id; } && PERF_FORMAT_ID
249 * } && !PERF_FORMAT_GROUP
250 *
251 * { u64 nr;
252 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED
253 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING
254 * { u64 value;
255 * { u64 id; } && PERF_FORMAT_ID
256 * } cntr[nr];
257 * } && PERF_FORMAT_GROUP
258 * };
259 */
260 enum perf_event_read_format {
261 PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0,
262 PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1,
263 PERF_FORMAT_ID = 1U << 2,
264 PERF_FORMAT_GROUP = 1U << 3,
265
266 PERF_FORMAT_MAX = 1U << 4, /* non-ABI */
267 };
268
269 #define PERF_ATTR_SIZE_VER0 64 /* sizeof first published struct */
270 #define PERF_ATTR_SIZE_VER1 72 /* add: config2 */
271 #define PERF_ATTR_SIZE_VER2 80 /* add: branch_sample_type */
272 #define PERF_ATTR_SIZE_VER3 96 /* add: sample_regs_user */
273 /* add: sample_stack_user */
274 #define PERF_ATTR_SIZE_VER4 104 /* add: sample_regs_intr */
275 #define PERF_ATTR_SIZE_VER5 112 /* add: aux_watermark */
276
277 /*
278 * Hardware event_id to monitor via a performance monitoring event:
279 *
280 * @sample_max_stack: Max number of frame pointers in a callchain,
281 * should be < /proc/sys/kernel/perf_event_max_stack
282 */
283 struct perf_event_attr {
284
285 /*
286 * Major type: hardware/software/tracepoint/etc.
287 */
288 __u32 type;
289
290 /*
291 * Size of the attr structure, for fwd/bwd compat.
292 */
293 __u32 size;
294
295 /*
296 * Type specific configuration information.
297 */
298 __u64 config;
299
300 union {
301 __u64 sample_period;
302 __u64 sample_freq;
303 };
304
305 __u64 sample_type;
306 __u64 read_format;
307
308 __u64 disabled : 1, /* off by default */
309 inherit : 1, /* children inherit it */
310 pinned : 1, /* must always be on PMU */
311 exclusive : 1, /* only group on PMU */
312 exclude_user : 1, /* don't count user */
313 exclude_kernel : 1, /* ditto kernel */
314 exclude_hv : 1, /* ditto hypervisor */
315 exclude_idle : 1, /* don't count when idle */
316 mmap : 1, /* include mmap data */
317 comm : 1, /* include comm data */
318 freq : 1, /* use freq, not period */
319 inherit_stat : 1, /* per task counts */
320 enable_on_exec : 1, /* next exec enables */
321 task : 1, /* trace fork/exit */
322 watermark : 1, /* wakeup_watermark */
323 /*
324 * precise_ip:
325 *
326 * 0 - SAMPLE_IP can have arbitrary skid
327 * 1 - SAMPLE_IP must have constant skid
328 * 2 - SAMPLE_IP requested to have 0 skid
329 * 3 - SAMPLE_IP must have 0 skid
330 *
331 * See also PERF_RECORD_MISC_EXACT_IP
332 */
333 precise_ip : 2, /* skid constraint */
334 mmap_data : 1, /* non-exec mmap data */
335 sample_id_all : 1, /* sample_type all events */
336
337 exclude_host : 1, /* don't count in host */
338 exclude_guest : 1, /* don't count in guest */
339
340 exclude_callchain_kernel : 1, /* exclude kernel callchains */
341 exclude_callchain_user : 1, /* exclude user callchains */
342 mmap2 : 1, /* include mmap with inode data */
343 comm_exec : 1, /* flag comm events that are due to an exec */
344 use_clockid : 1, /* use @clockid for time fields */
345 context_switch : 1, /* context switch data */
346 write_backward : 1, /* Write ring buffer from end to beginning */
347 __reserved_1 : 36;
348
349 union {
350 __u32 wakeup_events; /* wakeup every n events */
351 __u32 wakeup_watermark; /* bytes before wakeup */
352 };
353
354 __u32 bp_type;
355 union {
356 __u64 bp_addr;
357 __u64 config1; /* extension of config */
358 };
359 union {
360 __u64 bp_len;
361 __u64 config2; /* extension of config1 */
362 };
363 __u64 branch_sample_type; /* enum perf_branch_sample_type */
364
365 /*
366 * Defines set of user regs to dump on samples.
367 * See asm/perf_regs.h for details.
368 */
369 __u64 sample_regs_user;
370
371 /*
372 * Defines size of the user stack to dump on samples.
373 */
374 __u32 sample_stack_user;
375
376 __s32 clockid;
377 /*
378 * Defines set of regs to dump for each sample
379 * state captured on:
380 * - precise = 0: PMU interrupt
381 * - precise > 0: sampled instruction
382 *
383 * See asm/perf_regs.h for details.
384 */
385 __u64 sample_regs_intr;
386
387 /*
388 * Wakeup watermark for AUX area
389 */
390 __u32 aux_watermark;
391 __u16 sample_max_stack;
392 __u16 __reserved_2; /* align to __u64 */
393 };
394
395 #define perf_flags(attr) (*(&(attr)->read_format + 1))
396
397 /*
398 * Ioctls that can be done on a perf event fd:
399 */
400 #define PERF_EVENT_IOC_ENABLE _IO ('$', 0)
401 #define PERF_EVENT_IOC_DISABLE _IO ('$', 1)
402 #define PERF_EVENT_IOC_REFRESH _IO ('$', 2)
403 #define PERF_EVENT_IOC_RESET _IO ('$', 3)
404 #define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64)
405 #define PERF_EVENT_IOC_SET_OUTPUT _IO ('$', 5)
406 #define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *)
407 #define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *)
408 #define PERF_EVENT_IOC_SET_BPF _IOW('$', 8, __u32)
409 #define PERF_EVENT_IOC_PAUSE_OUTPUT _IOW('$', 9, __u32)
410
411 enum perf_event_ioc_flags {
412 PERF_IOC_FLAG_GROUP = 1U << 0,
413 };
414
415 /*
416 * Structure of the page that can be mapped via mmap
417 */
418 struct perf_event_mmap_page {
419 __u32 version; /* version number of this structure */
420 __u32 compat_version; /* lowest version this is compat with */
421
422 /*
423 * Bits needed to read the hw events in user-space.
424 *
425 * u32 seq, time_mult, time_shift, index, width;
426 * u64 count, enabled, running;
427 * u64 cyc, time_offset;
428 * s64 pmc = 0;
429 *
430 * do {
431 * seq = pc->lock;
432 * barrier()
433 *
434 * enabled = pc->time_enabled;
435 * running = pc->time_running;
436 *
437 * if (pc->cap_usr_time && enabled != running) {
438 * cyc = rdtsc();
439 * time_offset = pc->time_offset;
440 * time_mult = pc->time_mult;
441 * time_shift = pc->time_shift;
442 * }
443 *
444 * index = pc->index;
445 * count = pc->offset;
446 * if (pc->cap_user_rdpmc && index) {
447 * width = pc->pmc_width;
448 * pmc = rdpmc(index - 1);
449 * }
450 *
451 * barrier();
452 * } while (pc->lock != seq);
453 *
454 * NOTE: for obvious reason this only works on self-monitoring
455 * processes.
456 */
457 __u32 lock; /* seqlock for synchronization */
458 __u32 index; /* hardware event identifier */
459 __s64 offset; /* add to hardware event value */
460 __u64 time_enabled; /* time event active */
461 __u64 time_running; /* time event on cpu */
462 union {
463 __u64 capabilities;
464 struct {
465 __u64 cap_bit0 : 1, /* Always 0, deprecated, see commit 860f085b74e9 */
466 cap_bit0_is_deprecated : 1, /* Always 1, signals that bit 0 is zero */
467
468 cap_user_rdpmc : 1, /* The RDPMC instruction can be used to read counts */
469 cap_user_time : 1, /* The time_* fields are used */
470 cap_user_time_zero : 1, /* The time_zero field is used */
471 cap_____res : 59;
472 };
473 };
474
475 /*
476 * If cap_user_rdpmc this field provides the bit-width of the value
477 * read using the rdpmc() or equivalent instruction. This can be used
478 * to sign extend the result like:
479 *
480 * pmc <<= 64 - width;
481 * pmc >>= 64 - width; // signed shift right
482 * count += pmc;
483 */
484 __u16 pmc_width;
485
486 /*
487 * If cap_usr_time the below fields can be used to compute the time
488 * delta since time_enabled (in ns) using rdtsc or similar.
489 *
490 * u64 quot, rem;
491 * u64 delta;
492 *
493 * quot = (cyc >> time_shift);
494 * rem = cyc & (((u64)1 << time_shift) - 1);
495 * delta = time_offset + quot * time_mult +
496 * ((rem * time_mult) >> time_shift);
497 *
498 * Where time_offset,time_mult,time_shift and cyc are read in the
499 * seqcount loop described above. This delta can then be added to
500 * enabled and possible running (if index), improving the scaling:
501 *
502 * enabled += delta;
503 * if (index)
504 * running += delta;
505 *
506 * quot = count / running;
507 * rem = count % running;
508 * count = quot * enabled + (rem * enabled) / running;
509 */
510 __u16 time_shift;
511 __u32 time_mult;
512 __u64 time_offset;
513 /*
514 * If cap_usr_time_zero, the hardware clock (e.g. TSC) can be calculated
515 * from sample timestamps.
516 *
517 * time = timestamp - time_zero;
518 * quot = time / time_mult;
519 * rem = time % time_mult;
520 * cyc = (quot << time_shift) + (rem << time_shift) / time_mult;
521 *
522 * And vice versa:
523 *
524 * quot = cyc >> time_shift;
525 * rem = cyc & (((u64)1 << time_shift) - 1);
526 * timestamp = time_zero + quot * time_mult +
527 * ((rem * time_mult) >> time_shift);
528 */
529 __u64 time_zero;
530 __u32 size; /* Header size up to __reserved[] fields. */
531
532 /*
533 * Hole for extension of the self monitor capabilities
534 */
535
536 __u8 __reserved[118*8+4]; /* align to 1k. */
537
538 /*
539 * Control data for the mmap() data buffer.
540 *
541 * User-space reading the @data_head value should issue an smp_rmb(),
542 * after reading this value.
543 *
544 * When the mapping is PROT_WRITE the @data_tail value should be
545 * written by userspace to reflect the last read data, after issueing
546 * an smp_mb() to separate the data read from the ->data_tail store.
547 * In this case the kernel will not over-write unread data.
548 *
549 * See perf_output_put_handle() for the data ordering.
550 *
551 * data_{offset,size} indicate the location and size of the perf record
552 * buffer within the mmapped area.
553 */
554 __u64 data_head; /* head in the data section */
555 __u64 data_tail; /* user-space written tail */
556 __u64 data_offset; /* where the buffer starts */
557 __u64 data_size; /* data buffer size */
558
559 /*
560 * AUX area is defined by aux_{offset,size} fields that should be set
561 * by the userspace, so that
562 *
563 * aux_offset >= data_offset + data_size
564 *
565 * prior to mmap()ing it. Size of the mmap()ed area should be aux_size.
566 *
567 * Ring buffer pointers aux_{head,tail} have the same semantics as
568 * data_{head,tail} and same ordering rules apply.
569 */
570 __u64 aux_head;
571 __u64 aux_tail;
572 __u64 aux_offset;
573 __u64 aux_size;
574 };
575
576 #define PERF_RECORD_MISC_CPUMODE_MASK (7 << 0)
577 #define PERF_RECORD_MISC_CPUMODE_UNKNOWN (0 << 0)
578 #define PERF_RECORD_MISC_KERNEL (1 << 0)
579 #define PERF_RECORD_MISC_USER (2 << 0)
580 #define PERF_RECORD_MISC_HYPERVISOR (3 << 0)
581 #define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0)
582 #define PERF_RECORD_MISC_GUEST_USER (5 << 0)
583
584 /*
585 * Indicates that /proc/PID/maps parsing are truncated by time out.
586 */
587 #define PERF_RECORD_MISC_PROC_MAP_PARSE_TIMEOUT (1 << 12)
588 /*
589 * PERF_RECORD_MISC_MMAP_DATA and PERF_RECORD_MISC_COMM_EXEC are used on
590 * different events so can reuse the same bit position.
591 * Ditto PERF_RECORD_MISC_SWITCH_OUT.
592 */
593 #define PERF_RECORD_MISC_MMAP_DATA (1 << 13)
594 #define PERF_RECORD_MISC_COMM_EXEC (1 << 13)
595 #define PERF_RECORD_MISC_SWITCH_OUT (1 << 13)
596 /*
597 * Indicates that the content of PERF_SAMPLE_IP points to
598 * the actual instruction that triggered the event. See also
599 * perf_event_attr::precise_ip.
600 */
601 #define PERF_RECORD_MISC_EXACT_IP (1 << 14)
602 /*
603 * Reserve the last bit to indicate some extended misc field
604 */
605 #define PERF_RECORD_MISC_EXT_RESERVED (1 << 15)
606
607 struct perf_event_header {
608 __u32 type;
609 __u16 misc;
610 __u16 size;
611 };
612
613 enum perf_event_type {
614
615 /*
616 * If perf_event_attr.sample_id_all is set then all event types will
617 * have the sample_type selected fields related to where/when
618 * (identity) an event took place (TID, TIME, ID, STREAM_ID, CPU,
619 * IDENTIFIER) described in PERF_RECORD_SAMPLE below, it will be stashed
620 * just after the perf_event_header and the fields already present for
621 * the existing fields, i.e. at the end of the payload. That way a newer
622 * perf.data file will be supported by older perf tools, with these new
623 * optional fields being ignored.
624 *
625 * struct sample_id {
626 * { u32 pid, tid; } && PERF_SAMPLE_TID
627 * { u64 time; } && PERF_SAMPLE_TIME
628 * { u64 id; } && PERF_SAMPLE_ID
629 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID
630 * { u32 cpu, res; } && PERF_SAMPLE_CPU
631 * { u64 id; } && PERF_SAMPLE_IDENTIFIER
632 * } && perf_event_attr::sample_id_all
633 *
634 * Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. The
635 * advantage of PERF_SAMPLE_IDENTIFIER is that its position is fixed
636 * relative to header.size.
637 */
638
639 /*
640 * The MMAP events record the PROT_EXEC mappings so that we can
641 * correlate userspace IPs to code. They have the following structure:
642 *
643 * struct {
644 * struct perf_event_header header;
645 *
646 * u32 pid, tid;
647 * u64 addr;
648 * u64 len;
649 * u64 pgoff;
650 * char filename[];
651 * struct sample_id sample_id;
652 * };
653 */
654 PERF_RECORD_MMAP = 1,
655
656 /*
657 * struct {
658 * struct perf_event_header header;
659 * u64 id;
660 * u64 lost;
661 * struct sample_id sample_id;
662 * };
663 */
664 PERF_RECORD_LOST = 2,
665
666 /*
667 * struct {
668 * struct perf_event_header header;
669 *
670 * u32 pid, tid;
671 * char comm[];
672 * struct sample_id sample_id;
673 * };
674 */
675 PERF_RECORD_COMM = 3,
676
677 /*
678 * struct {
679 * struct perf_event_header header;
680 * u32 pid, ppid;
681 * u32 tid, ptid;
682 * u64 time;
683 * struct sample_id sample_id;
684 * };
685 */
686 PERF_RECORD_EXIT = 4,
687
688 /*
689 * struct {
690 * struct perf_event_header header;
691 * u64 time;
692 * u64 id;
693 * u64 stream_id;
694 * struct sample_id sample_id;
695 * };
696 */
697 PERF_RECORD_THROTTLE = 5,
698 PERF_RECORD_UNTHROTTLE = 6,
699
700 /*
701 * struct {
702 * struct perf_event_header header;
703 * u32 pid, ppid;
704 * u32 tid, ptid;
705 * u64 time;
706 * struct sample_id sample_id;
707 * };
708 */
709 PERF_RECORD_FORK = 7,
710
711 /*
712 * struct {
713 * struct perf_event_header header;
714 * u32 pid, tid;
715 *
716 * struct read_format values;
717 * struct sample_id sample_id;
718 * };
719 */
720 PERF_RECORD_READ = 8,
721
722 /*
723 * struct {
724 * struct perf_event_header header;
725 *
726 * #
727 * # Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID.
728 * # The advantage of PERF_SAMPLE_IDENTIFIER is that its position
729 * # is fixed relative to header.
730 * #
731 *
732 * { u64 id; } && PERF_SAMPLE_IDENTIFIER
733 * { u64 ip; } && PERF_SAMPLE_IP
734 * { u32 pid, tid; } && PERF_SAMPLE_TID
735 * { u64 time; } && PERF_SAMPLE_TIME
736 * { u64 addr; } && PERF_SAMPLE_ADDR
737 * { u64 id; } && PERF_SAMPLE_ID
738 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID
739 * { u32 cpu, res; } && PERF_SAMPLE_CPU
740 * { u64 period; } && PERF_SAMPLE_PERIOD
741 *
742 * { struct read_format values; } && PERF_SAMPLE_READ
743 *
744 * { u64 nr,
745 * u64 ips[nr]; } && PERF_SAMPLE_CALLCHAIN
746 *
747 * #
748 * # The RAW record below is opaque data wrt the ABI
749 * #
750 * # That is, the ABI doesn't make any promises wrt to
751 * # the stability of its content, it may vary depending
752 * # on event, hardware, kernel version and phase of
753 * # the moon.
754 * #
755 * # In other words, PERF_SAMPLE_RAW contents are not an ABI.
756 * #
757 *
758 * { u32 size;
759 * char data[size];}&& PERF_SAMPLE_RAW
760 *
761 * { u64 nr;
762 * { u64 from, to, flags } lbr[nr];} && PERF_SAMPLE_BRANCH_STACK
763 *
764 * { u64 abi; # enum perf_sample_regs_abi
765 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER
766 *
767 * { u64 size;
768 * char data[size];
769 * u64 dyn_size; } && PERF_SAMPLE_STACK_USER
770 *
771 * { u64 weight; } && PERF_SAMPLE_WEIGHT
772 * { u64 data_src; } && PERF_SAMPLE_DATA_SRC
773 * { u64 transaction; } && PERF_SAMPLE_TRANSACTION
774 * { u64 abi; # enum perf_sample_regs_abi
775 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_INTR
776 * };
777 */
778 PERF_RECORD_SAMPLE = 9,
779
780 /*
781 * The MMAP2 records are an augmented version of MMAP, they add
782 * maj, min, ino numbers to be used to uniquely identify each mapping
783 *
784 * struct {
785 * struct perf_event_header header;
786 *
787 * u32 pid, tid;
788 * u64 addr;
789 * u64 len;
790 * u64 pgoff;
791 * u32 maj;
792 * u32 min;
793 * u64 ino;
794 * u64 ino_generation;
795 * u32 prot, flags;
796 * char filename[];
797 * struct sample_id sample_id;
798 * };
799 */
800 PERF_RECORD_MMAP2 = 10,
801
802 /*
803 * Records that new data landed in the AUX buffer part.
804 *
805 * struct {
806 * struct perf_event_header header;
807 *
808 * u64 aux_offset;
809 * u64 aux_size;
810 * u64 flags;
811 * struct sample_id sample_id;
812 * };
813 */
814 PERF_RECORD_AUX = 11,
815
816 /*
817 * Indicates that instruction trace has started
818 *
819 * struct {
820 * struct perf_event_header header;
821 * u32 pid;
822 * u32 tid;
823 * };
824 */
825 PERF_RECORD_ITRACE_START = 12,
826
827 /*
828 * Records the dropped/lost sample number.
829 *
830 * struct {
831 * struct perf_event_header header;
832 *
833 * u64 lost;
834 * struct sample_id sample_id;
835 * };
836 */
837 PERF_RECORD_LOST_SAMPLES = 13,
838
839 /*
840 * Records a context switch in or out (flagged by
841 * PERF_RECORD_MISC_SWITCH_OUT). See also
842 * PERF_RECORD_SWITCH_CPU_WIDE.
843 *
844 * struct {
845 * struct perf_event_header header;
846 * struct sample_id sample_id;
847 * };
848 */
849 PERF_RECORD_SWITCH = 14,
850
851 /*
852 * CPU-wide version of PERF_RECORD_SWITCH with next_prev_pid and
853 * next_prev_tid that are the next (switching out) or previous
854 * (switching in) pid/tid.
855 *
856 * struct {
857 * struct perf_event_header header;
858 * u32 next_prev_pid;
859 * u32 next_prev_tid;
860 * struct sample_id sample_id;
861 * };
862 */
863 PERF_RECORD_SWITCH_CPU_WIDE = 15,
864
865 PERF_RECORD_MAX, /* non-ABI */
866 };
867
868 #define PERF_MAX_STACK_DEPTH 127
869 #define PERF_MAX_CONTEXTS_PER_STACK 8
870
871 enum perf_callchain_context {
872 PERF_CONTEXT_HV = (__u64)-32,
873 PERF_CONTEXT_KERNEL = (__u64)-128,
874 PERF_CONTEXT_USER = (__u64)-512,
875
876 PERF_CONTEXT_GUEST = (__u64)-2048,
877 PERF_CONTEXT_GUEST_KERNEL = (__u64)-2176,
878 PERF_CONTEXT_GUEST_USER = (__u64)-2560,
879
880 PERF_CONTEXT_MAX = (__u64)-4095,
881 };
882
883 /**
884 * PERF_RECORD_AUX::flags bits
885 */
886 #define PERF_AUX_FLAG_TRUNCATED 0x01 /* record was truncated to fit */
887 #define PERF_AUX_FLAG_OVERWRITE 0x02 /* snapshot from overwrite mode */
888
889 #define PERF_FLAG_FD_NO_GROUP (1UL << 0)
890 #define PERF_FLAG_FD_OUTPUT (1UL << 1)
891 #define PERF_FLAG_PID_CGROUP (1UL << 2) /* pid=cgroup id, per-cpu mode only */
892 #define PERF_FLAG_FD_CLOEXEC (1UL << 3) /* O_CLOEXEC */
893
894 union perf_mem_data_src {
895 __u64 val;
896 struct {
897 __u64 mem_op:5, /* type of opcode */
898 mem_lvl:14, /* memory hierarchy level */
899 mem_snoop:5, /* snoop mode */
900 mem_lock:2, /* lock instr */
901 mem_dtlb:7, /* tlb access */
902 mem_rsvd:31;
903 };
904 };
905
906 /* type of opcode (load/store/prefetch,code) */
907 #define PERF_MEM_OP_NA 0x01 /* not available */
908 #define PERF_MEM_OP_LOAD 0x02 /* load instruction */
909 #define PERF_MEM_OP_STORE 0x04 /* store instruction */
910 #define PERF_MEM_OP_PFETCH 0x08 /* prefetch */
911 #define PERF_MEM_OP_EXEC 0x10 /* code (execution) */
912 #define PERF_MEM_OP_SHIFT 0
913
914 /* memory hierarchy (memory level, hit or miss) */
915 #define PERF_MEM_LVL_NA 0x01 /* not available */
916 #define PERF_MEM_LVL_HIT 0x02 /* hit level */
917 #define PERF_MEM_LVL_MISS 0x04 /* miss level */
918 #define PERF_MEM_LVL_L1 0x08 /* L1 */
919 #define PERF_MEM_LVL_LFB 0x10 /* Line Fill Buffer */
920 #define PERF_MEM_LVL_L2 0x20 /* L2 */
921 #define PERF_MEM_LVL_L3 0x40 /* L3 */
922 #define PERF_MEM_LVL_LOC_RAM 0x80 /* Local DRAM */
923 #define PERF_MEM_LVL_REM_RAM1 0x100 /* Remote DRAM (1 hop) */
924 #define PERF_MEM_LVL_REM_RAM2 0x200 /* Remote DRAM (2 hops) */
925 #define PERF_MEM_LVL_REM_CCE1 0x400 /* Remote Cache (1 hop) */
926 #define PERF_MEM_LVL_REM_CCE2 0x800 /* Remote Cache (2 hops) */
927 #define PERF_MEM_LVL_IO 0x1000 /* I/O memory */
928 #define PERF_MEM_LVL_UNC 0x2000 /* Uncached memory */
929 #define PERF_MEM_LVL_SHIFT 5
930
931 /* snoop mode */
932 #define PERF_MEM_SNOOP_NA 0x01 /* not available */
933 #define PERF_MEM_SNOOP_NONE 0x02 /* no snoop */
934 #define PERF_MEM_SNOOP_HIT 0x04 /* snoop hit */
935 #define PERF_MEM_SNOOP_MISS 0x08 /* snoop miss */
936 #define PERF_MEM_SNOOP_HITM 0x10 /* snoop hit modified */
937 #define PERF_MEM_SNOOP_SHIFT 19
938
939 /* locked instruction */
940 #define PERF_MEM_LOCK_NA 0x01 /* not available */
941 #define PERF_MEM_LOCK_LOCKED 0x02 /* locked transaction */
942 #define PERF_MEM_LOCK_SHIFT 24
943
944 /* TLB access */
945 #define PERF_MEM_TLB_NA 0x01 /* not available */
946 #define PERF_MEM_TLB_HIT 0x02 /* hit level */
947 #define PERF_MEM_TLB_MISS 0x04 /* miss level */
948 #define PERF_MEM_TLB_L1 0x08 /* L1 */
949 #define PERF_MEM_TLB_L2 0x10 /* L2 */
950 #define PERF_MEM_TLB_WK 0x20 /* Hardware Walker*/
951 #define PERF_MEM_TLB_OS 0x40 /* OS fault handler */
952 #define PERF_MEM_TLB_SHIFT 26
953
954 #define PERF_MEM_S(a, s) \
955 (((__u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT)
956
957 /*
958 * single taken branch record layout:
959 *
960 * from: source instruction (may not always be a branch insn)
961 * to: branch target
962 * mispred: branch target was mispredicted
963 * predicted: branch target was predicted
964 *
965 * support for mispred, predicted is optional. In case it
966 * is not supported mispred = predicted = 0.
967 *
968 * in_tx: running in a hardware transaction
969 * abort: aborting a hardware transaction
970 * cycles: cycles from last branch (or 0 if not supported)
971 */
972 struct perf_branch_entry {
973 __u64 from;
974 __u64 to;
975 __u64 mispred:1, /* target mispredicted */
976 predicted:1,/* target predicted */
977 in_tx:1, /* in transaction */
978 abort:1, /* transaction abort */
979 cycles:16, /* cycle count to last branch */
980 reserved:44;
981 };
982
983 #endif /* _UAPI_LINUX_PERF_EVENT_H */
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