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x86/intel_rdt: Fix incorrect returned value when creating rdgroup sub-directory in...
[cris-mirror.git] / drivers / ata / libahci.c
bloba0de7a38430c954b31c7b4e6e01a790ee98e85c2
1 /*
2 * libahci.c - Common AHCI SATA low-level routines
3 *
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/driver-api/libata.rst
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/gfp.h>
37 #include <linux/module.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/device.h>
43 #include <scsi/scsi_host.h>
44 #include <scsi/scsi_cmnd.h>
45 #include <linux/libata.h>
46 #include <linux/pci.h>
47 #include "ahci.h"
48 #include "libata.h"
49
50 static int ahci_skip_host_reset;
51 int ahci_ignore_sss;
52 EXPORT_SYMBOL_GPL(ahci_ignore_sss);
53
54 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
55 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
56
57 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
58 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
59
60 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
61 unsigned hints);
62 static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
63 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
64 size_t size);
65 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
66 ssize_t size);
67
68
69
70 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
71 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
72 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
73 static int ahci_port_start(struct ata_port *ap);
74 static void ahci_port_stop(struct ata_port *ap);
75 static void ahci_qc_prep(struct ata_queued_cmd *qc);
76 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
77 static void ahci_freeze(struct ata_port *ap);
78 static void ahci_thaw(struct ata_port *ap);
79 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep);
80 static void ahci_enable_fbs(struct ata_port *ap);
81 static void ahci_disable_fbs(struct ata_port *ap);
82 static void ahci_pmp_attach(struct ata_port *ap);
83 static void ahci_pmp_detach(struct ata_port *ap);
84 static int ahci_softreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
88 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
90 static void ahci_postreset(struct ata_link *link, unsigned int *class);
91 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
92 static void ahci_dev_config(struct ata_device *dev);
93 #ifdef CONFIG_PM
94 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
95 #endif
96 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
97 static ssize_t ahci_activity_store(struct ata_device *dev,
98 enum sw_activity val);
99 static void ahci_init_sw_activity(struct ata_link *link);
100
101 static ssize_t ahci_show_host_caps(struct device *dev,
102 struct device_attribute *attr, char *buf);
103 static ssize_t ahci_show_host_cap2(struct device *dev,
104 struct device_attribute *attr, char *buf);
105 static ssize_t ahci_show_host_version(struct device *dev,
106 struct device_attribute *attr, char *buf);
107 static ssize_t ahci_show_port_cmd(struct device *dev,
108 struct device_attribute *attr, char *buf);
109 static ssize_t ahci_read_em_buffer(struct device *dev,
110 struct device_attribute *attr, char *buf);
111 static ssize_t ahci_store_em_buffer(struct device *dev,
112 struct device_attribute *attr,
113 const char *buf, size_t size);
114 static ssize_t ahci_show_em_supported(struct device *dev,
115 struct device_attribute *attr, char *buf);
116 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance);
117
118 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
119 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
120 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
121 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
122 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
123 ahci_read_em_buffer, ahci_store_em_buffer);
124 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
125
126 struct device_attribute *ahci_shost_attrs[] = {
127 &dev_attr_link_power_management_policy,
128 &dev_attr_em_message_type,
129 &dev_attr_em_message,
130 &dev_attr_ahci_host_caps,
131 &dev_attr_ahci_host_cap2,
132 &dev_attr_ahci_host_version,
133 &dev_attr_ahci_port_cmd,
134 &dev_attr_em_buffer,
135 &dev_attr_em_message_supported,
136 NULL
137 };
138 EXPORT_SYMBOL_GPL(ahci_shost_attrs);
139
140 struct device_attribute *ahci_sdev_attrs[] = {
141 &dev_attr_sw_activity,
142 &dev_attr_unload_heads,
143 &dev_attr_ncq_prio_enable,
144 NULL
145 };
146 EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
147
148 struct ata_port_operations ahci_ops = {
149 .inherits = &sata_pmp_port_ops,
150
151 .qc_defer = ahci_pmp_qc_defer,
152 .qc_prep = ahci_qc_prep,
153 .qc_issue = ahci_qc_issue,
154 .qc_fill_rtf = ahci_qc_fill_rtf,
155
156 .freeze = ahci_freeze,
157 .thaw = ahci_thaw,
158 .softreset = ahci_softreset,
159 .hardreset = ahci_hardreset,
160 .postreset = ahci_postreset,
161 .pmp_softreset = ahci_softreset,
162 .error_handler = ahci_error_handler,
163 .post_internal_cmd = ahci_post_internal_cmd,
164 .dev_config = ahci_dev_config,
165
166 .scr_read = ahci_scr_read,
167 .scr_write = ahci_scr_write,
168 .pmp_attach = ahci_pmp_attach,
169 .pmp_detach = ahci_pmp_detach,
170
171 .set_lpm = ahci_set_lpm,
172 .em_show = ahci_led_show,
173 .em_store = ahci_led_store,
174 .sw_activity_show = ahci_activity_show,
175 .sw_activity_store = ahci_activity_store,
176 .transmit_led_message = ahci_transmit_led_message,
177 #ifdef CONFIG_PM
178 .port_suspend = ahci_port_suspend,
179 .port_resume = ahci_port_resume,
180 #endif
181 .port_start = ahci_port_start,
182 .port_stop = ahci_port_stop,
183 };
184 EXPORT_SYMBOL_GPL(ahci_ops);
185
186 struct ata_port_operations ahci_pmp_retry_srst_ops = {
187 .inherits = &ahci_ops,
188 .softreset = ahci_pmp_retry_softreset,
189 };
190 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
191
192 static bool ahci_em_messages __read_mostly = true;
193 EXPORT_SYMBOL_GPL(ahci_em_messages);
194 module_param(ahci_em_messages, bool, 0444);
195 /* add other LED protocol types when they become supported */
196 MODULE_PARM_DESC(ahci_em_messages,
197 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
198
199 /* device sleep idle timeout in ms */
200 static int devslp_idle_timeout __read_mostly = 1000;
201 module_param(devslp_idle_timeout, int, 0644);
202 MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout");
203
204 static void ahci_enable_ahci(void __iomem *mmio)
205 {
206 int i;
207 u32 tmp;
208
209 /* turn on AHCI_EN */
210 tmp = readl(mmio + HOST_CTL);
211 if (tmp & HOST_AHCI_EN)
212 return;
213
214 /* Some controllers need AHCI_EN to be written multiple times.
215 * Try a few times before giving up.
216 */
217 for (i = 0; i < 5; i++) {
218 tmp |= HOST_AHCI_EN;
219 writel(tmp, mmio + HOST_CTL);
220 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
221 if (tmp & HOST_AHCI_EN)
222 return;
223 msleep(10);
224 }
225
226 WARN_ON(1);
227 }
228
229 /**
230 * ahci_rpm_get_port - Make sure the port is powered on
231 * @ap: Port to power on
232 *
233 * Whenever there is need to access the AHCI host registers outside of
234 * normal execution paths, call this function to make sure the host is
235 * actually powered on.
236 */
237 static int ahci_rpm_get_port(struct ata_port *ap)
238 {
239 return pm_runtime_get_sync(ap->dev);
240 }
241
242 /**
243 * ahci_rpm_put_port - Undoes ahci_rpm_get_port()
244 * @ap: Port to power down
245 *
246 * Undoes ahci_rpm_get_port() and possibly powers down the AHCI host
247 * if it has no more active users.
248 */
249 static void ahci_rpm_put_port(struct ata_port *ap)
250 {
251 pm_runtime_put(ap->dev);
252 }
253
254 static ssize_t ahci_show_host_caps(struct device *dev,
255 struct device_attribute *attr, char *buf)
256 {
257 struct Scsi_Host *shost = class_to_shost(dev);
258 struct ata_port *ap = ata_shost_to_port(shost);
259 struct ahci_host_priv *hpriv = ap->host->private_data;
260
261 return sprintf(buf, "%x\n", hpriv->cap);
262 }
263
264 static ssize_t ahci_show_host_cap2(struct device *dev,
265 struct device_attribute *attr, char *buf)
266 {
267 struct Scsi_Host *shost = class_to_shost(dev);
268 struct ata_port *ap = ata_shost_to_port(shost);
269 struct ahci_host_priv *hpriv = ap->host->private_data;
270
271 return sprintf(buf, "%x\n", hpriv->cap2);
272 }
273
274 static ssize_t ahci_show_host_version(struct device *dev,
275 struct device_attribute *attr, char *buf)
276 {
277 struct Scsi_Host *shost = class_to_shost(dev);
278 struct ata_port *ap = ata_shost_to_port(shost);
279 struct ahci_host_priv *hpriv = ap->host->private_data;
280
281 return sprintf(buf, "%x\n", hpriv->version);
282 }
283
284 static ssize_t ahci_show_port_cmd(struct device *dev,
285 struct device_attribute *attr, char *buf)
286 {
287 struct Scsi_Host *shost = class_to_shost(dev);
288 struct ata_port *ap = ata_shost_to_port(shost);
289 void __iomem *port_mmio = ahci_port_base(ap);
290 ssize_t ret;
291
292 ahci_rpm_get_port(ap);
293 ret = sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
294 ahci_rpm_put_port(ap);
295
296 return ret;
297 }
298
299 static ssize_t ahci_read_em_buffer(struct device *dev,
300 struct device_attribute *attr, char *buf)
301 {
302 struct Scsi_Host *shost = class_to_shost(dev);
303 struct ata_port *ap = ata_shost_to_port(shost);
304 struct ahci_host_priv *hpriv = ap->host->private_data;
305 void __iomem *mmio = hpriv->mmio;
306 void __iomem *em_mmio = mmio + hpriv->em_loc;
307 u32 em_ctl, msg;
308 unsigned long flags;
309 size_t count;
310 int i;
311
312 ahci_rpm_get_port(ap);
313 spin_lock_irqsave(ap->lock, flags);
314
315 em_ctl = readl(mmio + HOST_EM_CTL);
316 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
317 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
318 spin_unlock_irqrestore(ap->lock, flags);
319 ahci_rpm_put_port(ap);
320 return -EINVAL;
321 }
322
323 if (!(em_ctl & EM_CTL_MR)) {
324 spin_unlock_irqrestore(ap->lock, flags);
325 ahci_rpm_put_port(ap);
326 return -EAGAIN;
327 }
328
329 if (!(em_ctl & EM_CTL_SMB))
330 em_mmio += hpriv->em_buf_sz;
331
332 count = hpriv->em_buf_sz;
333
334 /* the count should not be larger than PAGE_SIZE */
335 if (count > PAGE_SIZE) {
336 if (printk_ratelimit())
337 ata_port_warn(ap,
338 "EM read buffer size too large: "
339 "buffer size %u, page size %lu\n",
340 hpriv->em_buf_sz, PAGE_SIZE);
341 count = PAGE_SIZE;
342 }
343
344 for (i = 0; i < count; i += 4) {
345 msg = readl(em_mmio + i);
346 buf[i] = msg & 0xff;
347 buf[i + 1] = (msg >> 8) & 0xff;
348 buf[i + 2] = (msg >> 16) & 0xff;
349 buf[i + 3] = (msg >> 24) & 0xff;
350 }
351
352 spin_unlock_irqrestore(ap->lock, flags);
353 ahci_rpm_put_port(ap);
354
355 return i;
356 }
357
358 static ssize_t ahci_store_em_buffer(struct device *dev,
359 struct device_attribute *attr,
360 const char *buf, size_t size)
361 {
362 struct Scsi_Host *shost = class_to_shost(dev);
363 struct ata_port *ap = ata_shost_to_port(shost);
364 struct ahci_host_priv *hpriv = ap->host->private_data;
365 void __iomem *mmio = hpriv->mmio;
366 void __iomem *em_mmio = mmio + hpriv->em_loc;
367 const unsigned char *msg_buf = buf;
368 u32 em_ctl, msg;
369 unsigned long flags;
370 int i;
371
372 /* check size validity */
373 if (!(ap->flags & ATA_FLAG_EM) ||
374 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
375 size % 4 || size > hpriv->em_buf_sz)
376 return -EINVAL;
377
378 ahci_rpm_get_port(ap);
379 spin_lock_irqsave(ap->lock, flags);
380
381 em_ctl = readl(mmio + HOST_EM_CTL);
382 if (em_ctl & EM_CTL_TM) {
383 spin_unlock_irqrestore(ap->lock, flags);
384 ahci_rpm_put_port(ap);
385 return -EBUSY;
386 }
387
388 for (i = 0; i < size; i += 4) {
389 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
390 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
391 writel(msg, em_mmio + i);
392 }
393
394 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
395
396 spin_unlock_irqrestore(ap->lock, flags);
397 ahci_rpm_put_port(ap);
398
399 return size;
400 }
401
402 static ssize_t ahci_show_em_supported(struct device *dev,
403 struct device_attribute *attr, char *buf)
404 {
405 struct Scsi_Host *shost = class_to_shost(dev);
406 struct ata_port *ap = ata_shost_to_port(shost);
407 struct ahci_host_priv *hpriv = ap->host->private_data;
408 void __iomem *mmio = hpriv->mmio;
409 u32 em_ctl;
410
411 ahci_rpm_get_port(ap);
412 em_ctl = readl(mmio + HOST_EM_CTL);
413 ahci_rpm_put_port(ap);
414
415 return sprintf(buf, "%s%s%s%s\n",
416 em_ctl & EM_CTL_LED ? "led " : "",
417 em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
418 em_ctl & EM_CTL_SES ? "ses-2 " : "",
419 em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
420 }
421
422 /**
423 * ahci_save_initial_config - Save and fixup initial config values
424 * @dev: target AHCI device
425 * @hpriv: host private area to store config values
426 *
427 * Some registers containing configuration info might be setup by
428 * BIOS and might be cleared on reset. This function saves the
429 * initial values of those registers into @hpriv such that they
430 * can be restored after controller reset.
431 *
432 * If inconsistent, config values are fixed up by this function.
433 *
434 * If it is not set already this function sets hpriv->start_engine to
435 * ahci_start_engine.
436 *
437 * LOCKING:
438 * None.
439 */
440 void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
441 {
442 void __iomem *mmio = hpriv->mmio;
443 u32 cap, cap2, vers, port_map;
444 int i;
445
446 /* make sure AHCI mode is enabled before accessing CAP */
447 ahci_enable_ahci(mmio);
448
449 /* Values prefixed with saved_ are written back to host after
450 * reset. Values without are used for driver operation.
451 */
452 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
453 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
454
455 /* CAP2 register is only defined for AHCI 1.2 and later */
456 vers = readl(mmio + HOST_VERSION);
457 if ((vers >> 16) > 1 ||
458 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
459 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
460 else
461 hpriv->saved_cap2 = cap2 = 0;
462
463 /* some chips have errata preventing 64bit use */
464 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
465 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
466 cap &= ~HOST_CAP_64;
467 }
468
469 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
470 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
471 cap &= ~HOST_CAP_NCQ;
472 }
473
474 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
475 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
476 cap |= HOST_CAP_NCQ;
477 }
478
479 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
480 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
481 cap &= ~HOST_CAP_PMP;
482 }
483
484 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
485 dev_info(dev,
486 "controller can't do SNTF, turning off CAP_SNTF\n");
487 cap &= ~HOST_CAP_SNTF;
488 }
489
490 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) {
491 dev_info(dev,
492 "controller can't do DEVSLP, turning off\n");
493 cap2 &= ~HOST_CAP2_SDS;
494 cap2 &= ~HOST_CAP2_SADM;
495 }
496
497 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
498 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
499 cap |= HOST_CAP_FBS;
500 }
501
502 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) {
503 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n");
504 cap &= ~HOST_CAP_FBS;
505 }
506
507 if (!(cap & HOST_CAP_ALPM) && (hpriv->flags & AHCI_HFLAG_YES_ALPM)) {
508 dev_info(dev, "controller can do ALPM, turning on CAP_ALPM\n");
509 cap |= HOST_CAP_ALPM;
510 }
511
512 if (hpriv->force_port_map && port_map != hpriv->force_port_map) {
513 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
514 port_map, hpriv->force_port_map);
515 port_map = hpriv->force_port_map;
516 hpriv->saved_port_map = port_map;
517 }
518
519 if (hpriv->mask_port_map) {
520 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
521 port_map,
522 port_map & hpriv->mask_port_map);
523 port_map &= hpriv->mask_port_map;
524 }
525
526 /* cross check port_map and cap.n_ports */
527 if (port_map) {
528 int map_ports = 0;
529
530 for (i = 0; i < AHCI_MAX_PORTS; i++)
531 if (port_map & (1 << i))
532 map_ports++;
533
534 /* If PI has more ports than n_ports, whine, clear
535 * port_map and let it be generated from n_ports.
536 */
537 if (map_ports > ahci_nr_ports(cap)) {
538 dev_warn(dev,
539 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
540 port_map, ahci_nr_ports(cap));
541 port_map = 0;
542 }
543 }
544
545 /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */
546 if (!port_map && vers < 0x10300) {
547 port_map = (1 << ahci_nr_ports(cap)) - 1;
548 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map);
549
550 /* write the fixed up value to the PI register */
551 hpriv->saved_port_map = port_map;
552 }
553
554 /* record values to use during operation */
555 hpriv->cap = cap;
556 hpriv->cap2 = cap2;
557 hpriv->version = readl(mmio + HOST_VERSION);
558 hpriv->port_map = port_map;
559
560 if (!hpriv->start_engine)
561 hpriv->start_engine = ahci_start_engine;
562
563 if (!hpriv->irq_handler)
564 hpriv->irq_handler = ahci_single_level_irq_intr;
565 }
566 EXPORT_SYMBOL_GPL(ahci_save_initial_config);
567
568 /**
569 * ahci_restore_initial_config - Restore initial config
570 * @host: target ATA host
571 *
572 * Restore initial config stored by ahci_save_initial_config().
573 *
574 * LOCKING:
575 * None.
576 */
577 static void ahci_restore_initial_config(struct ata_host *host)
578 {
579 struct ahci_host_priv *hpriv = host->private_data;
580 void __iomem *mmio = hpriv->mmio;
581
582 writel(hpriv->saved_cap, mmio + HOST_CAP);
583 if (hpriv->saved_cap2)
584 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
585 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
586 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
587 }
588
589 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
590 {
591 static const int offset[] = {
592 [SCR_STATUS] = PORT_SCR_STAT,
593 [SCR_CONTROL] = PORT_SCR_CTL,
594 [SCR_ERROR] = PORT_SCR_ERR,
595 [SCR_ACTIVE] = PORT_SCR_ACT,
596 [SCR_NOTIFICATION] = PORT_SCR_NTF,
597 };
598 struct ahci_host_priv *hpriv = ap->host->private_data;
599
600 if (sc_reg < ARRAY_SIZE(offset) &&
601 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
602 return offset[sc_reg];
603 return 0;
604 }
605
606 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
607 {
608 void __iomem *port_mmio = ahci_port_base(link->ap);
609 int offset = ahci_scr_offset(link->ap, sc_reg);
610
611 if (offset) {
612 *val = readl(port_mmio + offset);
613 return 0;
614 }
615 return -EINVAL;
616 }
617
618 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
619 {
620 void __iomem *port_mmio = ahci_port_base(link->ap);
621 int offset = ahci_scr_offset(link->ap, sc_reg);
622
623 if (offset) {
624 writel(val, port_mmio + offset);
625 return 0;
626 }
627 return -EINVAL;
628 }
629
630 void ahci_start_engine(struct ata_port *ap)
631 {
632 void __iomem *port_mmio = ahci_port_base(ap);
633 u32 tmp;
634
635 /* start DMA */
636 tmp = readl(port_mmio + PORT_CMD);
637 tmp |= PORT_CMD_START;
638 writel(tmp, port_mmio + PORT_CMD);
639 readl(port_mmio + PORT_CMD); /* flush */
640 }
641 EXPORT_SYMBOL_GPL(ahci_start_engine);
642
643 int ahci_stop_engine(struct ata_port *ap)
644 {
645 void __iomem *port_mmio = ahci_port_base(ap);
646 struct ahci_host_priv *hpriv = ap->host->private_data;
647 u32 tmp;
648
649 /*
650 * On some controllers, stopping a port's DMA engine while the port
651 * is in ALPM state (partial or slumber) results in failures on
652 * subsequent DMA engine starts. For those controllers, put the
653 * port back in active state before stopping its DMA engine.
654 */
655 if ((hpriv->flags & AHCI_HFLAG_WAKE_BEFORE_STOP) &&
656 (ap->link.lpm_policy > ATA_LPM_MAX_POWER) &&
657 ahci_set_lpm(&ap->link, ATA_LPM_MAX_POWER, ATA_LPM_WAKE_ONLY)) {
658 dev_err(ap->host->dev, "Failed to wake up port before engine stop\n");
659 return -EIO;
660 }
661
662 tmp = readl(port_mmio + PORT_CMD);
663
664 /* check if the HBA is idle */
665 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
666 return 0;
667
668 /* setting HBA to idle */
669 tmp &= ~PORT_CMD_START;
670 writel(tmp, port_mmio + PORT_CMD);
671
672 /* wait for engine to stop. This could be as long as 500 msec */
673 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
674 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
675 if (tmp & PORT_CMD_LIST_ON)
676 return -EIO;
677
678 return 0;
679 }
680 EXPORT_SYMBOL_GPL(ahci_stop_engine);
681
682 void ahci_start_fis_rx(struct ata_port *ap)
683 {
684 void __iomem *port_mmio = ahci_port_base(ap);
685 struct ahci_host_priv *hpriv = ap->host->private_data;
686 struct ahci_port_priv *pp = ap->private_data;
687 u32 tmp;
688
689 /* set FIS registers */
690 if (hpriv->cap & HOST_CAP_64)
691 writel((pp->cmd_slot_dma >> 16) >> 16,
692 port_mmio + PORT_LST_ADDR_HI);
693 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
694
695 if (hpriv->cap & HOST_CAP_64)
696 writel((pp->rx_fis_dma >> 16) >> 16,
697 port_mmio + PORT_FIS_ADDR_HI);
698 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
699
700 /* enable FIS reception */
701 tmp = readl(port_mmio + PORT_CMD);
702 tmp |= PORT_CMD_FIS_RX;
703 writel(tmp, port_mmio + PORT_CMD);
704
705 /* flush */
706 readl(port_mmio + PORT_CMD);
707 }
708 EXPORT_SYMBOL_GPL(ahci_start_fis_rx);
709
710 static int ahci_stop_fis_rx(struct ata_port *ap)
711 {
712 void __iomem *port_mmio = ahci_port_base(ap);
713 u32 tmp;
714
715 /* disable FIS reception */
716 tmp = readl(port_mmio + PORT_CMD);
717 tmp &= ~PORT_CMD_FIS_RX;
718 writel(tmp, port_mmio + PORT_CMD);
719
720 /* wait for completion, spec says 500ms, give it 1000 */
721 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
722 PORT_CMD_FIS_ON, 10, 1000);
723 if (tmp & PORT_CMD_FIS_ON)
724 return -EBUSY;
725
726 return 0;
727 }
728
729 static void ahci_power_up(struct ata_port *ap)
730 {
731 struct ahci_host_priv *hpriv = ap->host->private_data;
732 void __iomem *port_mmio = ahci_port_base(ap);
733 u32 cmd;
734
735 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
736
737 /* spin up device */
738 if (hpriv->cap & HOST_CAP_SSS) {
739 cmd |= PORT_CMD_SPIN_UP;
740 writel(cmd, port_mmio + PORT_CMD);
741 }
742
743 /* wake up link */
744 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
745 }
746
747 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
748 unsigned int hints)
749 {
750 struct ata_port *ap = link->ap;
751 struct ahci_host_priv *hpriv = ap->host->private_data;
752 struct ahci_port_priv *pp = ap->private_data;
753 void __iomem *port_mmio = ahci_port_base(ap);
754
755 if (policy != ATA_LPM_MAX_POWER) {
756 /* wakeup flag only applies to the max power policy */
757 hints &= ~ATA_LPM_WAKE_ONLY;
758
759 /*
760 * Disable interrupts on Phy Ready. This keeps us from
761 * getting woken up due to spurious phy ready
762 * interrupts.
763 */
764 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
765 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
766
767 sata_link_scr_lpm(link, policy, false);
768 }
769
770 if (hpriv->cap & HOST_CAP_ALPM) {
771 u32 cmd = readl(port_mmio + PORT_CMD);
772
773 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
774 if (!(hints & ATA_LPM_WAKE_ONLY))
775 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
776 cmd |= PORT_CMD_ICC_ACTIVE;
777
778 writel(cmd, port_mmio + PORT_CMD);
779 readl(port_mmio + PORT_CMD);
780
781 /* wait 10ms to be sure we've come out of LPM state */
782 ata_msleep(ap, 10);
783
784 if (hints & ATA_LPM_WAKE_ONLY)
785 return 0;
786 } else {
787 cmd |= PORT_CMD_ALPE;
788 if (policy == ATA_LPM_MIN_POWER)
789 cmd |= PORT_CMD_ASP;
790
791 /* write out new cmd value */
792 writel(cmd, port_mmio + PORT_CMD);
793 }
794 }
795
796 /* set aggressive device sleep */
797 if ((hpriv->cap2 & HOST_CAP2_SDS) &&
798 (hpriv->cap2 & HOST_CAP2_SADM) &&
799 (link->device->flags & ATA_DFLAG_DEVSLP)) {
800 if (policy == ATA_LPM_MIN_POWER)
801 ahci_set_aggressive_devslp(ap, true);
802 else
803 ahci_set_aggressive_devslp(ap, false);
804 }
805
806 if (policy == ATA_LPM_MAX_POWER) {
807 sata_link_scr_lpm(link, policy, false);
808
809 /* turn PHYRDY IRQ back on */
810 pp->intr_mask |= PORT_IRQ_PHYRDY;
811 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
812 }
813
814 return 0;
815 }
816
817 #ifdef CONFIG_PM
818 static void ahci_power_down(struct ata_port *ap)
819 {
820 struct ahci_host_priv *hpriv = ap->host->private_data;
821 void __iomem *port_mmio = ahci_port_base(ap);
822 u32 cmd, scontrol;
823
824 if (!(hpriv->cap & HOST_CAP_SSS))
825 return;
826
827 /* put device into listen mode, first set PxSCTL.DET to 0 */
828 scontrol = readl(port_mmio + PORT_SCR_CTL);
829 scontrol &= ~0xf;
830 writel(scontrol, port_mmio + PORT_SCR_CTL);
831
832 /* then set PxCMD.SUD to 0 */
833 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
834 cmd &= ~PORT_CMD_SPIN_UP;
835 writel(cmd, port_mmio + PORT_CMD);
836 }
837 #endif
838
839 static void ahci_start_port(struct ata_port *ap)
840 {
841 struct ahci_host_priv *hpriv = ap->host->private_data;
842 struct ahci_port_priv *pp = ap->private_data;
843 struct ata_link *link;
844 struct ahci_em_priv *emp;
845 ssize_t rc;
846 int i;
847
848 /* enable FIS reception */
849 ahci_start_fis_rx(ap);
850
851 /* enable DMA */
852 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
853 hpriv->start_engine(ap);
854
855 /* turn on LEDs */
856 if (ap->flags & ATA_FLAG_EM) {
857 ata_for_each_link(link, ap, EDGE) {
858 emp = &pp->em_priv[link->pmp];
859
860 /* EM Transmit bit maybe busy during init */
861 for (i = 0; i < EM_MAX_RETRY; i++) {
862 rc = ap->ops->transmit_led_message(ap,
863 emp->led_state,
864 4);
865 /*
866 * If busy, give a breather but do not
867 * release EH ownership by using msleep()
868 * instead of ata_msleep(). EM Transmit
869 * bit is busy for the whole host and
870 * releasing ownership will cause other
871 * ports to fail the same way.
872 */
873 if (rc == -EBUSY)
874 msleep(1);
875 else
876 break;
877 }
878 }
879 }
880
881 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
882 ata_for_each_link(link, ap, EDGE)
883 ahci_init_sw_activity(link);
884
885 }
886
887 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
888 {
889 int rc;
890
891 /* disable DMA */
892 rc = ahci_stop_engine(ap);
893 if (rc) {
894 *emsg = "failed to stop engine";
895 return rc;
896 }
897
898 /* disable FIS reception */
899 rc = ahci_stop_fis_rx(ap);
900 if (rc) {
901 *emsg = "failed stop FIS RX";
902 return rc;
903 }
904
905 return 0;
906 }
907
908 int ahci_reset_controller(struct ata_host *host)
909 {
910 struct ahci_host_priv *hpriv = host->private_data;
911 void __iomem *mmio = hpriv->mmio;
912 u32 tmp;
913
914 /* we must be in AHCI mode, before using anything
915 * AHCI-specific, such as HOST_RESET.
916 */
917 ahci_enable_ahci(mmio);
918
919 /* global controller reset */
920 if (!ahci_skip_host_reset) {
921 tmp = readl(mmio + HOST_CTL);
922 if ((tmp & HOST_RESET) == 0) {
923 writel(tmp | HOST_RESET, mmio + HOST_CTL);
924 readl(mmio + HOST_CTL); /* flush */
925 }
926
927 /*
928 * to perform host reset, OS should set HOST_RESET
929 * and poll until this bit is read to be "0".
930 * reset must complete within 1 second, or
931 * the hardware should be considered fried.
932 */
933 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
934 HOST_RESET, 10, 1000);
935
936 if (tmp & HOST_RESET) {
937 dev_err(host->dev, "controller reset failed (0x%x)\n",
938 tmp);
939 return -EIO;
940 }
941
942 /* turn on AHCI mode */
943 ahci_enable_ahci(mmio);
944
945 /* Some registers might be cleared on reset. Restore
946 * initial values.
947 */
948 if (!(hpriv->flags & AHCI_HFLAG_NO_WRITE_TO_RO))
949 ahci_restore_initial_config(host);
950 } else
951 dev_info(host->dev, "skipping global host reset\n");
952
953 return 0;
954 }
955 EXPORT_SYMBOL_GPL(ahci_reset_controller);
956
957 static void ahci_sw_activity(struct ata_link *link)
958 {
959 struct ata_port *ap = link->ap;
960 struct ahci_port_priv *pp = ap->private_data;
961 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
962
963 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
964 return;
965
966 emp->activity++;
967 if (!timer_pending(&emp->timer))
968 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
969 }
970
971 static void ahci_sw_activity_blink(struct timer_list *t)
972 {
973 struct ahci_em_priv *emp = from_timer(emp, t, timer);
974 struct ata_link *link = emp->link;
975 struct ata_port *ap = link->ap;
976
977 unsigned long led_message = emp->led_state;
978 u32 activity_led_state;
979 unsigned long flags;
980
981 led_message &= EM_MSG_LED_VALUE;
982 led_message |= ap->port_no | (link->pmp << 8);
983
984 /* check to see if we've had activity. If so,
985 * toggle state of LED and reset timer. If not,
986 * turn LED to desired idle state.
987 */
988 spin_lock_irqsave(ap->lock, flags);
989 if (emp->saved_activity != emp->activity) {
990 emp->saved_activity = emp->activity;
991 /* get the current LED state */
992 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
993
994 if (activity_led_state)
995 activity_led_state = 0;
996 else
997 activity_led_state = 1;
998
999 /* clear old state */
1000 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1001
1002 /* toggle state */
1003 led_message |= (activity_led_state << 16);
1004 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1005 } else {
1006 /* switch to idle */
1007 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1008 if (emp->blink_policy == BLINK_OFF)
1009 led_message |= (1 << 16);
1010 }
1011 spin_unlock_irqrestore(ap->lock, flags);
1012 ap->ops->transmit_led_message(ap, led_message, 4);
1013 }
1014
1015 static void ahci_init_sw_activity(struct ata_link *link)
1016 {
1017 struct ata_port *ap = link->ap;
1018 struct ahci_port_priv *pp = ap->private_data;
1019 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1020
1021 /* init activity stats, setup timer */
1022 emp->saved_activity = emp->activity = 0;
1023 emp->link = link;
1024 timer_setup(&emp->timer, ahci_sw_activity_blink, 0);
1025
1026 /* check our blink policy and set flag for link if it's enabled */
1027 if (emp->blink_policy)
1028 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1029 }
1030
1031 int ahci_reset_em(struct ata_host *host)
1032 {
1033 struct ahci_host_priv *hpriv = host->private_data;
1034 void __iomem *mmio = hpriv->mmio;
1035 u32 em_ctl;
1036
1037 em_ctl = readl(mmio + HOST_EM_CTL);
1038 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1039 return -EINVAL;
1040
1041 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1042 return 0;
1043 }
1044 EXPORT_SYMBOL_GPL(ahci_reset_em);
1045
1046 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1047 ssize_t size)
1048 {
1049 struct ahci_host_priv *hpriv = ap->host->private_data;
1050 struct ahci_port_priv *pp = ap->private_data;
1051 void __iomem *mmio = hpriv->mmio;
1052 u32 em_ctl;
1053 u32 message[] = {0, 0};
1054 unsigned long flags;
1055 int pmp;
1056 struct ahci_em_priv *emp;
1057
1058 /* get the slot number from the message */
1059 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1060 if (pmp < EM_MAX_SLOTS)
1061 emp = &pp->em_priv[pmp];
1062 else
1063 return -EINVAL;
1064
1065 ahci_rpm_get_port(ap);
1066 spin_lock_irqsave(ap->lock, flags);
1067
1068 /*
1069 * if we are still busy transmitting a previous message,
1070 * do not allow
1071 */
1072 em_ctl = readl(mmio + HOST_EM_CTL);
1073 if (em_ctl & EM_CTL_TM) {
1074 spin_unlock_irqrestore(ap->lock, flags);
1075 ahci_rpm_put_port(ap);
1076 return -EBUSY;
1077 }
1078
1079 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
1080 /*
1081 * create message header - this is all zero except for
1082 * the message size, which is 4 bytes.
1083 */
1084 message[0] |= (4 << 8);
1085
1086 /* ignore 0:4 of byte zero, fill in port info yourself */
1087 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
1088
1089 /* write message to EM_LOC */
1090 writel(message[0], mmio + hpriv->em_loc);
1091 writel(message[1], mmio + hpriv->em_loc+4);
1092
1093 /*
1094 * tell hardware to transmit the message
1095 */
1096 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1097 }
1098
1099 /* save off new led state for port/slot */
1100 emp->led_state = state;
1101
1102 spin_unlock_irqrestore(ap->lock, flags);
1103 ahci_rpm_put_port(ap);
1104
1105 return size;
1106 }
1107
1108 static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1109 {
1110 struct ahci_port_priv *pp = ap->private_data;
1111 struct ata_link *link;
1112 struct ahci_em_priv *emp;
1113 int rc = 0;
1114
1115 ata_for_each_link(link, ap, EDGE) {
1116 emp = &pp->em_priv[link->pmp];
1117 rc += sprintf(buf, "%lx\n", emp->led_state);
1118 }
1119 return rc;
1120 }
1121
1122 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1123 size_t size)
1124 {
1125 unsigned int state;
1126 int pmp;
1127 struct ahci_port_priv *pp = ap->private_data;
1128 struct ahci_em_priv *emp;
1129
1130 if (kstrtouint(buf, 0, &state) < 0)
1131 return -EINVAL;
1132
1133 /* get the slot number from the message */
1134 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1135 if (pmp < EM_MAX_SLOTS)
1136 emp = &pp->em_priv[pmp];
1137 else
1138 return -EINVAL;
1139
1140 /* mask off the activity bits if we are in sw_activity
1141 * mode, user should turn off sw_activity before setting
1142 * activity led through em_message
1143 */
1144 if (emp->blink_policy)
1145 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1146
1147 return ap->ops->transmit_led_message(ap, state, size);
1148 }
1149
1150 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1151 {
1152 struct ata_link *link = dev->link;
1153 struct ata_port *ap = link->ap;
1154 struct ahci_port_priv *pp = ap->private_data;
1155 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1156 u32 port_led_state = emp->led_state;
1157
1158 /* save the desired Activity LED behavior */
1159 if (val == OFF) {
1160 /* clear LFLAG */
1161 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1162
1163 /* set the LED to OFF */
1164 port_led_state &= EM_MSG_LED_VALUE_OFF;
1165 port_led_state |= (ap->port_no | (link->pmp << 8));
1166 ap->ops->transmit_led_message(ap, port_led_state, 4);
1167 } else {
1168 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1169 if (val == BLINK_OFF) {
1170 /* set LED to ON for idle */
1171 port_led_state &= EM_MSG_LED_VALUE_OFF;
1172 port_led_state |= (ap->port_no | (link->pmp << 8));
1173 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1174 ap->ops->transmit_led_message(ap, port_led_state, 4);
1175 }
1176 }
1177 emp->blink_policy = val;
1178 return 0;
1179 }
1180
1181 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1182 {
1183 struct ata_link *link = dev->link;
1184 struct ata_port *ap = link->ap;
1185 struct ahci_port_priv *pp = ap->private_data;
1186 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1187
1188 /* display the saved value of activity behavior for this
1189 * disk.
1190 */
1191 return sprintf(buf, "%d\n", emp->blink_policy);
1192 }
1193
1194 static void ahci_port_init(struct device *dev, struct ata_port *ap,
1195 int port_no, void __iomem *mmio,
1196 void __iomem *port_mmio)
1197 {
1198 struct ahci_host_priv *hpriv = ap->host->private_data;
1199 const char *emsg = NULL;
1200 int rc;
1201 u32 tmp;
1202
1203 /* make sure port is not active */
1204 rc = ahci_deinit_port(ap, &emsg);
1205 if (rc)
1206 dev_warn(dev, "%s (%d)\n", emsg, rc);
1207
1208 /* clear SError */
1209 tmp = readl(port_mmio + PORT_SCR_ERR);
1210 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1211 writel(tmp, port_mmio + PORT_SCR_ERR);
1212
1213 /* clear port IRQ */
1214 tmp = readl(port_mmio + PORT_IRQ_STAT);
1215 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1216 if (tmp)
1217 writel(tmp, port_mmio + PORT_IRQ_STAT);
1218
1219 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1220
1221 /* mark esata ports */
1222 tmp = readl(port_mmio + PORT_CMD);
1223 if ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS))
1224 ap->pflags |= ATA_PFLAG_EXTERNAL;
1225 }
1226
1227 void ahci_init_controller(struct ata_host *host)
1228 {
1229 struct ahci_host_priv *hpriv = host->private_data;
1230 void __iomem *mmio = hpriv->mmio;
1231 int i;
1232 void __iomem *port_mmio;
1233 u32 tmp;
1234
1235 for (i = 0; i < host->n_ports; i++) {
1236 struct ata_port *ap = host->ports[i];
1237
1238 port_mmio = ahci_port_base(ap);
1239 if (ata_port_is_dummy(ap))
1240 continue;
1241
1242 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1243 }
1244
1245 tmp = readl(mmio + HOST_CTL);
1246 VPRINTK("HOST_CTL 0x%x\n", tmp);
1247 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1248 tmp = readl(mmio + HOST_CTL);
1249 VPRINTK("HOST_CTL 0x%x\n", tmp);
1250 }
1251 EXPORT_SYMBOL_GPL(ahci_init_controller);
1252
1253 static void ahci_dev_config(struct ata_device *dev)
1254 {
1255 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1256
1257 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1258 dev->max_sectors = 255;
1259 ata_dev_info(dev,
1260 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1261 }
1262 }
1263
1264 unsigned int ahci_dev_classify(struct ata_port *ap)
1265 {
1266 void __iomem *port_mmio = ahci_port_base(ap);
1267 struct ata_taskfile tf;
1268 u32 tmp;
1269
1270 tmp = readl(port_mmio + PORT_SIG);
1271 tf.lbah = (tmp >> 24) & 0xff;
1272 tf.lbam = (tmp >> 16) & 0xff;
1273 tf.lbal = (tmp >> 8) & 0xff;
1274 tf.nsect = (tmp) & 0xff;
1275
1276 return ata_dev_classify(&tf);
1277 }
1278 EXPORT_SYMBOL_GPL(ahci_dev_classify);
1279
1280 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1281 u32 opts)
1282 {
1283 dma_addr_t cmd_tbl_dma;
1284
1285 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1286
1287 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1288 pp->cmd_slot[tag].status = 0;
1289 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1290 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1291 }
1292 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
1293
1294 int ahci_kick_engine(struct ata_port *ap)
1295 {
1296 void __iomem *port_mmio = ahci_port_base(ap);
1297 struct ahci_host_priv *hpriv = ap->host->private_data;
1298 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1299 u32 tmp;
1300 int busy, rc;
1301
1302 /* stop engine */
1303 rc = ahci_stop_engine(ap);
1304 if (rc)
1305 goto out_restart;
1306
1307 /* need to do CLO?
1308 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1309 */
1310 busy = status & (ATA_BUSY | ATA_DRQ);
1311 if (!busy && !sata_pmp_attached(ap)) {
1312 rc = 0;
1313 goto out_restart;
1314 }
1315
1316 if (!(hpriv->cap & HOST_CAP_CLO)) {
1317 rc = -EOPNOTSUPP;
1318 goto out_restart;
1319 }
1320
1321 /* perform CLO */
1322 tmp = readl(port_mmio + PORT_CMD);
1323 tmp |= PORT_CMD_CLO;
1324 writel(tmp, port_mmio + PORT_CMD);
1325
1326 rc = 0;
1327 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
1328 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1329 if (tmp & PORT_CMD_CLO)
1330 rc = -EIO;
1331
1332 /* restart engine */
1333 out_restart:
1334 hpriv->start_engine(ap);
1335 return rc;
1336 }
1337 EXPORT_SYMBOL_GPL(ahci_kick_engine);
1338
1339 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1340 struct ata_taskfile *tf, int is_cmd, u16 flags,
1341 unsigned long timeout_msec)
1342 {
1343 const u32 cmd_fis_len = 5; /* five dwords */
1344 struct ahci_port_priv *pp = ap->private_data;
1345 void __iomem *port_mmio = ahci_port_base(ap);
1346 u8 *fis = pp->cmd_tbl;
1347 u32 tmp;
1348
1349 /* prep the command */
1350 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1351 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1352
1353 /* set port value for softreset of Port Multiplier */
1354 if (pp->fbs_enabled && pp->fbs_last_dev != pmp) {
1355 tmp = readl(port_mmio + PORT_FBS);
1356 tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1357 tmp |= pmp << PORT_FBS_DEV_OFFSET;
1358 writel(tmp, port_mmio + PORT_FBS);
1359 pp->fbs_last_dev = pmp;
1360 }
1361
1362 /* issue & wait */
1363 writel(1, port_mmio + PORT_CMD_ISSUE);
1364
1365 if (timeout_msec) {
1366 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1367 0x1, 0x1, 1, timeout_msec);
1368 if (tmp & 0x1) {
1369 ahci_kick_engine(ap);
1370 return -EBUSY;
1371 }
1372 } else
1373 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1374
1375 return 0;
1376 }
1377
1378 int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1379 int pmp, unsigned long deadline,
1380 int (*check_ready)(struct ata_link *link))
1381 {
1382 struct ata_port *ap = link->ap;
1383 struct ahci_host_priv *hpriv = ap->host->private_data;
1384 struct ahci_port_priv *pp = ap->private_data;
1385 const char *reason = NULL;
1386 unsigned long now, msecs;
1387 struct ata_taskfile tf;
1388 bool fbs_disabled = false;
1389 int rc;
1390
1391 DPRINTK("ENTER\n");
1392
1393 /* prepare for SRST (AHCI-1.1 10.4.1) */
1394 rc = ahci_kick_engine(ap);
1395 if (rc && rc != -EOPNOTSUPP)
1396 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
1397
1398 /*
1399 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall
1400 * clear PxFBS.EN to '0' prior to issuing software reset to devices
1401 * that is attached to port multiplier.
1402 */
1403 if (!ata_is_host_link(link) && pp->fbs_enabled) {
1404 ahci_disable_fbs(ap);
1405 fbs_disabled = true;
1406 }
1407
1408 ata_tf_init(link->device, &tf);
1409
1410 /* issue the first H2D Register FIS */
1411 msecs = 0;
1412 now = jiffies;
1413 if (time_after(deadline, now))
1414 msecs = jiffies_to_msecs(deadline - now);
1415
1416 tf.ctl |= ATA_SRST;
1417 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1418 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1419 rc = -EIO;
1420 reason = "1st FIS failed";
1421 goto fail;
1422 }
1423
1424 /* spec says at least 5us, but be generous and sleep for 1ms */
1425 ata_msleep(ap, 1);
1426
1427 /* issue the second H2D Register FIS */
1428 tf.ctl &= ~ATA_SRST;
1429 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1430
1431 /* wait for link to become ready */
1432 rc = ata_wait_after_reset(link, deadline, check_ready);
1433 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1434 /*
1435 * Workaround for cases where link online status can't
1436 * be trusted. Treat device readiness timeout as link
1437 * offline.
1438 */
1439 ata_link_info(link, "device not ready, treating as offline\n");
1440 *class = ATA_DEV_NONE;
1441 } else if (rc) {
1442 /* link occupied, -ENODEV too is an error */
1443 reason = "device not ready";
1444 goto fail;
1445 } else
1446 *class = ahci_dev_classify(ap);
1447
1448 /* re-enable FBS if disabled before */
1449 if (fbs_disabled)
1450 ahci_enable_fbs(ap);
1451
1452 DPRINTK("EXIT, class=%u\n", *class);
1453 return 0;
1454
1455 fail:
1456 ata_link_err(link, "softreset failed (%s)\n", reason);
1457 return rc;
1458 }
1459
1460 int ahci_check_ready(struct ata_link *link)
1461 {
1462 void __iomem *port_mmio = ahci_port_base(link->ap);
1463 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1464
1465 return ata_check_ready(status);
1466 }
1467 EXPORT_SYMBOL_GPL(ahci_check_ready);
1468
1469 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1470 unsigned long deadline)
1471 {
1472 int pmp = sata_srst_pmp(link);
1473
1474 DPRINTK("ENTER\n");
1475
1476 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1477 }
1478 EXPORT_SYMBOL_GPL(ahci_do_softreset);
1479
1480 static int ahci_bad_pmp_check_ready(struct ata_link *link)
1481 {
1482 void __iomem *port_mmio = ahci_port_base(link->ap);
1483 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1484 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1485
1486 /*
1487 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1488 * which can save timeout delay.
1489 */
1490 if (irq_status & PORT_IRQ_BAD_PMP)
1491 return -EIO;
1492
1493 return ata_check_ready(status);
1494 }
1495
1496 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
1497 unsigned long deadline)
1498 {
1499 struct ata_port *ap = link->ap;
1500 void __iomem *port_mmio = ahci_port_base(ap);
1501 int pmp = sata_srst_pmp(link);
1502 int rc;
1503 u32 irq_sts;
1504
1505 DPRINTK("ENTER\n");
1506
1507 rc = ahci_do_softreset(link, class, pmp, deadline,
1508 ahci_bad_pmp_check_ready);
1509
1510 /*
1511 * Soft reset fails with IPMS set when PMP is enabled but
1512 * SATA HDD/ODD is connected to SATA port, do soft reset
1513 * again to port 0.
1514 */
1515 if (rc == -EIO) {
1516 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1517 if (irq_sts & PORT_IRQ_BAD_PMP) {
1518 ata_link_warn(link,
1519 "applying PMP SRST workaround "
1520 "and retrying\n");
1521 rc = ahci_do_softreset(link, class, 0, deadline,
1522 ahci_check_ready);
1523 }
1524 }
1525
1526 return rc;
1527 }
1528
1529 int ahci_do_hardreset(struct ata_link *link, unsigned int *class,
1530 unsigned long deadline, bool *online)
1531 {
1532 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1533 struct ata_port *ap = link->ap;
1534 struct ahci_port_priv *pp = ap->private_data;
1535 struct ahci_host_priv *hpriv = ap->host->private_data;
1536 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1537 struct ata_taskfile tf;
1538 int rc;
1539
1540 DPRINTK("ENTER\n");
1541
1542 ahci_stop_engine(ap);
1543
1544 /* clear D2H reception area to properly wait for D2H FIS */
1545 ata_tf_init(link->device, &tf);
1546 tf.command = ATA_BUSY;
1547 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1548
1549 rc = sata_link_hardreset(link, timing, deadline, online,
1550 ahci_check_ready);
1551
1552 hpriv->start_engine(ap);
1553
1554 if (*online)
1555 *class = ahci_dev_classify(ap);
1556
1557 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1558 return rc;
1559 }
1560 EXPORT_SYMBOL_GPL(ahci_do_hardreset);
1561
1562 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1563 unsigned long deadline)
1564 {
1565 bool online;
1566
1567 return ahci_do_hardreset(link, class, deadline, &online);
1568 }
1569
1570 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1571 {
1572 struct ata_port *ap = link->ap;
1573 void __iomem *port_mmio = ahci_port_base(ap);
1574 u32 new_tmp, tmp;
1575
1576 ata_std_postreset(link, class);
1577
1578 /* Make sure port's ATAPI bit is set appropriately */
1579 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1580 if (*class == ATA_DEV_ATAPI)
1581 new_tmp |= PORT_CMD_ATAPI;
1582 else
1583 new_tmp &= ~PORT_CMD_ATAPI;
1584 if (new_tmp != tmp) {
1585 writel(new_tmp, port_mmio + PORT_CMD);
1586 readl(port_mmio + PORT_CMD); /* flush */
1587 }
1588 }
1589
1590 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1591 {
1592 struct scatterlist *sg;
1593 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1594 unsigned int si;
1595
1596 VPRINTK("ENTER\n");
1597
1598 /*
1599 * Next, the S/G list.
1600 */
1601 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1602 dma_addr_t addr = sg_dma_address(sg);
1603 u32 sg_len = sg_dma_len(sg);
1604
1605 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1606 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1607 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1608 }
1609
1610 return si;
1611 }
1612
1613 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1614 {
1615 struct ata_port *ap = qc->ap;
1616 struct ahci_port_priv *pp = ap->private_data;
1617
1618 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1619 return ata_std_qc_defer(qc);
1620 else
1621 return sata_pmp_qc_defer_cmd_switch(qc);
1622 }
1623
1624 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1625 {
1626 struct ata_port *ap = qc->ap;
1627 struct ahci_port_priv *pp = ap->private_data;
1628 int is_atapi = ata_is_atapi(qc->tf.protocol);
1629 void *cmd_tbl;
1630 u32 opts;
1631 const u32 cmd_fis_len = 5; /* five dwords */
1632 unsigned int n_elem;
1633
1634 /*
1635 * Fill in command table information. First, the header,
1636 * a SATA Register - Host to Device command FIS.
1637 */
1638 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1639
1640 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1641 if (is_atapi) {
1642 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1643 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1644 }
1645
1646 n_elem = 0;
1647 if (qc->flags & ATA_QCFLAG_DMAMAP)
1648 n_elem = ahci_fill_sg(qc, cmd_tbl);
1649
1650 /*
1651 * Fill in command slot information.
1652 */
1653 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1654 if (qc->tf.flags & ATA_TFLAG_WRITE)
1655 opts |= AHCI_CMD_WRITE;
1656 if (is_atapi)
1657 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1658
1659 ahci_fill_cmd_slot(pp, qc->tag, opts);
1660 }
1661
1662 static void ahci_fbs_dec_intr(struct ata_port *ap)
1663 {
1664 struct ahci_port_priv *pp = ap->private_data;
1665 void __iomem *port_mmio = ahci_port_base(ap);
1666 u32 fbs = readl(port_mmio + PORT_FBS);
1667 int retries = 3;
1668
1669 DPRINTK("ENTER\n");
1670 BUG_ON(!pp->fbs_enabled);
1671
1672 /* time to wait for DEC is not specified by AHCI spec,
1673 * add a retry loop for safety.
1674 */
1675 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1676 fbs = readl(port_mmio + PORT_FBS);
1677 while ((fbs & PORT_FBS_DEC) && retries--) {
1678 udelay(1);
1679 fbs = readl(port_mmio + PORT_FBS);
1680 }
1681
1682 if (fbs & PORT_FBS_DEC)
1683 dev_err(ap->host->dev, "failed to clear device error\n");
1684 }
1685
1686 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1687 {
1688 struct ahci_host_priv *hpriv = ap->host->private_data;
1689 struct ahci_port_priv *pp = ap->private_data;
1690 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1691 struct ata_link *link = NULL;
1692 struct ata_queued_cmd *active_qc;
1693 struct ata_eh_info *active_ehi;
1694 bool fbs_need_dec = false;
1695 u32 serror;
1696
1697 /* determine active link with error */
1698 if (pp->fbs_enabled) {
1699 void __iomem *port_mmio = ahci_port_base(ap);
1700 u32 fbs = readl(port_mmio + PORT_FBS);
1701 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1702
1703 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
1704 link = &ap->pmp_link[pmp];
1705 fbs_need_dec = true;
1706 }
1707
1708 } else
1709 ata_for_each_link(link, ap, EDGE)
1710 if (ata_link_active(link))
1711 break;
1712
1713 if (!link)
1714 link = &ap->link;
1715
1716 active_qc = ata_qc_from_tag(ap, link->active_tag);
1717 active_ehi = &link->eh_info;
1718
1719 /* record irq stat */
1720 ata_ehi_clear_desc(host_ehi);
1721 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1722
1723 /* AHCI needs SError cleared; otherwise, it might lock up */
1724 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1725 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1726 host_ehi->serror |= serror;
1727
1728 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1729 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1730 irq_stat &= ~PORT_IRQ_IF_ERR;
1731
1732 if (irq_stat & PORT_IRQ_TF_ERR) {
1733 /* If qc is active, charge it; otherwise, the active
1734 * link. There's no active qc on NCQ errors. It will
1735 * be determined by EH by reading log page 10h.
1736 */
1737 if (active_qc)
1738 active_qc->err_mask |= AC_ERR_DEV;
1739 else
1740 active_ehi->err_mask |= AC_ERR_DEV;
1741
1742 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1743 host_ehi->serror &= ~SERR_INTERNAL;
1744 }
1745
1746 if (irq_stat & PORT_IRQ_UNK_FIS) {
1747 u32 *unk = pp->rx_fis + RX_FIS_UNK;
1748
1749 active_ehi->err_mask |= AC_ERR_HSM;
1750 active_ehi->action |= ATA_EH_RESET;
1751 ata_ehi_push_desc(active_ehi,
1752 "unknown FIS %08x %08x %08x %08x" ,
1753 unk[0], unk[1], unk[2], unk[3]);
1754 }
1755
1756 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1757 active_ehi->err_mask |= AC_ERR_HSM;
1758 active_ehi->action |= ATA_EH_RESET;
1759 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1760 }
1761
1762 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1763 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1764 host_ehi->action |= ATA_EH_RESET;
1765 ata_ehi_push_desc(host_ehi, "host bus error");
1766 }
1767
1768 if (irq_stat & PORT_IRQ_IF_ERR) {
1769 if (fbs_need_dec)
1770 active_ehi->err_mask |= AC_ERR_DEV;
1771 else {
1772 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1773 host_ehi->action |= ATA_EH_RESET;
1774 }
1775
1776 ata_ehi_push_desc(host_ehi, "interface fatal error");
1777 }
1778
1779 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1780 ata_ehi_hotplugged(host_ehi);
1781 ata_ehi_push_desc(host_ehi, "%s",
1782 irq_stat & PORT_IRQ_CONNECT ?
1783 "connection status changed" : "PHY RDY changed");
1784 }
1785
1786 /* okay, let's hand over to EH */
1787
1788 if (irq_stat & PORT_IRQ_FREEZE)
1789 ata_port_freeze(ap);
1790 else if (fbs_need_dec) {
1791 ata_link_abort(link);
1792 ahci_fbs_dec_intr(ap);
1793 } else
1794 ata_port_abort(ap);
1795 }
1796
1797 static void ahci_handle_port_interrupt(struct ata_port *ap,
1798 void __iomem *port_mmio, u32 status)
1799 {
1800 struct ata_eh_info *ehi = &ap->link.eh_info;
1801 struct ahci_port_priv *pp = ap->private_data;
1802 struct ahci_host_priv *hpriv = ap->host->private_data;
1803 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1804 u32 qc_active = 0;
1805 int rc;
1806
1807 /* ignore BAD_PMP while resetting */
1808 if (unlikely(resetting))
1809 status &= ~PORT_IRQ_BAD_PMP;
1810
1811 if (sata_lpm_ignore_phy_events(&ap->link)) {
1812 status &= ~PORT_IRQ_PHYRDY;
1813 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
1814 }
1815
1816 if (unlikely(status & PORT_IRQ_ERROR)) {
1817 ahci_error_intr(ap, status);
1818 return;
1819 }
1820
1821 if (status & PORT_IRQ_SDB_FIS) {
1822 /* If SNotification is available, leave notification
1823 * handling to sata_async_notification(). If not,
1824 * emulate it by snooping SDB FIS RX area.
1825 *
1826 * Snooping FIS RX area is probably cheaper than
1827 * poking SNotification but some constrollers which
1828 * implement SNotification, ICH9 for example, don't
1829 * store AN SDB FIS into receive area.
1830 */
1831 if (hpriv->cap & HOST_CAP_SNTF)
1832 sata_async_notification(ap);
1833 else {
1834 /* If the 'N' bit in word 0 of the FIS is set,
1835 * we just received asynchronous notification.
1836 * Tell libata about it.
1837 *
1838 * Lack of SNotification should not appear in
1839 * ahci 1.2, so the workaround is unnecessary
1840 * when FBS is enabled.
1841 */
1842 if (pp->fbs_enabled)
1843 WARN_ON_ONCE(1);
1844 else {
1845 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1846 u32 f0 = le32_to_cpu(f[0]);
1847 if (f0 & (1 << 15))
1848 sata_async_notification(ap);
1849 }
1850 }
1851 }
1852
1853 /* pp->active_link is not reliable once FBS is enabled, both
1854 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1855 * NCQ and non-NCQ commands may be in flight at the same time.
1856 */
1857 if (pp->fbs_enabled) {
1858 if (ap->qc_active) {
1859 qc_active = readl(port_mmio + PORT_SCR_ACT);
1860 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1861 }
1862 } else {
1863 /* pp->active_link is valid iff any command is in flight */
1864 if (ap->qc_active && pp->active_link->sactive)
1865 qc_active = readl(port_mmio + PORT_SCR_ACT);
1866 else
1867 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1868 }
1869
1870
1871 rc = ata_qc_complete_multiple(ap, qc_active);
1872
1873 /* while resetting, invalid completions are expected */
1874 if (unlikely(rc < 0 && !resetting)) {
1875 ehi->err_mask |= AC_ERR_HSM;
1876 ehi->action |= ATA_EH_RESET;
1877 ata_port_freeze(ap);
1878 }
1879 }
1880
1881 static void ahci_port_intr(struct ata_port *ap)
1882 {
1883 void __iomem *port_mmio = ahci_port_base(ap);
1884 u32 status;
1885
1886 status = readl(port_mmio + PORT_IRQ_STAT);
1887 writel(status, port_mmio + PORT_IRQ_STAT);
1888
1889 ahci_handle_port_interrupt(ap, port_mmio, status);
1890 }
1891
1892 static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance)
1893 {
1894 struct ata_port *ap = dev_instance;
1895 void __iomem *port_mmio = ahci_port_base(ap);
1896 u32 status;
1897
1898 VPRINTK("ENTER\n");
1899
1900 status = readl(port_mmio + PORT_IRQ_STAT);
1901 writel(status, port_mmio + PORT_IRQ_STAT);
1902
1903 spin_lock(ap->lock);
1904 ahci_handle_port_interrupt(ap, port_mmio, status);
1905 spin_unlock(ap->lock);
1906
1907 VPRINTK("EXIT\n");
1908
1909 return IRQ_HANDLED;
1910 }
1911
1912 u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked)
1913 {
1914 unsigned int i, handled = 0;
1915
1916 for (i = 0; i < host->n_ports; i++) {
1917 struct ata_port *ap;
1918
1919 if (!(irq_masked & (1 << i)))
1920 continue;
1921
1922 ap = host->ports[i];
1923 if (ap) {
1924 ahci_port_intr(ap);
1925 VPRINTK("port %u\n", i);
1926 } else {
1927 VPRINTK("port %u (no irq)\n", i);
1928 if (ata_ratelimit())
1929 dev_warn(host->dev,
1930 "interrupt on disabled port %u\n", i);
1931 }
1932
1933 handled = 1;
1934 }
1935
1936 return handled;
1937 }
1938 EXPORT_SYMBOL_GPL(ahci_handle_port_intr);
1939
1940 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance)
1941 {
1942 struct ata_host *host = dev_instance;
1943 struct ahci_host_priv *hpriv;
1944 unsigned int rc = 0;
1945 void __iomem *mmio;
1946 u32 irq_stat, irq_masked;
1947
1948 VPRINTK("ENTER\n");
1949
1950 hpriv = host->private_data;
1951 mmio = hpriv->mmio;
1952
1953 /* sigh. 0xffffffff is a valid return from h/w */
1954 irq_stat = readl(mmio + HOST_IRQ_STAT);
1955 if (!irq_stat)
1956 return IRQ_NONE;
1957
1958 irq_masked = irq_stat & hpriv->port_map;
1959
1960 spin_lock(&host->lock);
1961
1962 rc = ahci_handle_port_intr(host, irq_masked);
1963
1964 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1965 * it should be cleared after all the port events are cleared;
1966 * otherwise, it will raise a spurious interrupt after each
1967 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1968 * information.
1969 *
1970 * Also, use the unmasked value to clear interrupt as spurious
1971 * pending event on a dummy port might cause screaming IRQ.
1972 */
1973 writel(irq_stat, mmio + HOST_IRQ_STAT);
1974
1975 spin_unlock(&host->lock);
1976
1977 VPRINTK("EXIT\n");
1978
1979 return IRQ_RETVAL(rc);
1980 }
1981
1982 unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1983 {
1984 struct ata_port *ap = qc->ap;
1985 void __iomem *port_mmio = ahci_port_base(ap);
1986 struct ahci_port_priv *pp = ap->private_data;
1987
1988 /* Keep track of the currently active link. It will be used
1989 * in completion path to determine whether NCQ phase is in
1990 * progress.
1991 */
1992 pp->active_link = qc->dev->link;
1993
1994 if (ata_is_ncq(qc->tf.protocol))
1995 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1996
1997 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
1998 u32 fbs = readl(port_mmio + PORT_FBS);
1999 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
2000 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
2001 writel(fbs, port_mmio + PORT_FBS);
2002 pp->fbs_last_dev = qc->dev->link->pmp;
2003 }
2004
2005 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
2006
2007 ahci_sw_activity(qc->dev->link);
2008
2009 return 0;
2010 }
2011 EXPORT_SYMBOL_GPL(ahci_qc_issue);
2012
2013 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2014 {
2015 struct ahci_port_priv *pp = qc->ap->private_data;
2016 u8 *rx_fis = pp->rx_fis;
2017
2018 if (pp->fbs_enabled)
2019 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
2020
2021 /*
2022 * After a successful execution of an ATA PIO data-in command,
2023 * the device doesn't send D2H Reg FIS to update the TF and
2024 * the host should take TF and E_Status from the preceding PIO
2025 * Setup FIS.
2026 */
2027 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
2028 !(qc->flags & ATA_QCFLAG_FAILED)) {
2029 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
2030 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
2031 } else
2032 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
2033
2034 return true;
2035 }
2036
2037 static void ahci_freeze(struct ata_port *ap)
2038 {
2039 void __iomem *port_mmio = ahci_port_base(ap);
2040
2041 /* turn IRQ off */
2042 writel(0, port_mmio + PORT_IRQ_MASK);
2043 }
2044
2045 static void ahci_thaw(struct ata_port *ap)
2046 {
2047 struct ahci_host_priv *hpriv = ap->host->private_data;
2048 void __iomem *mmio = hpriv->mmio;
2049 void __iomem *port_mmio = ahci_port_base(ap);
2050 u32 tmp;
2051 struct ahci_port_priv *pp = ap->private_data;
2052
2053 /* clear IRQ */
2054 tmp = readl(port_mmio + PORT_IRQ_STAT);
2055 writel(tmp, port_mmio + PORT_IRQ_STAT);
2056 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2057
2058 /* turn IRQ back on */
2059 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2060 }
2061
2062 void ahci_error_handler(struct ata_port *ap)
2063 {
2064 struct ahci_host_priv *hpriv = ap->host->private_data;
2065
2066 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2067 /* restart engine */
2068 ahci_stop_engine(ap);
2069 hpriv->start_engine(ap);
2070 }
2071
2072 sata_pmp_error_handler(ap);
2073
2074 if (!ata_dev_enabled(ap->link.device))
2075 ahci_stop_engine(ap);
2076 }
2077 EXPORT_SYMBOL_GPL(ahci_error_handler);
2078
2079 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2080 {
2081 struct ata_port *ap = qc->ap;
2082
2083 /* make DMA engine forget about the failed command */
2084 if (qc->flags & ATA_QCFLAG_FAILED)
2085 ahci_kick_engine(ap);
2086 }
2087
2088 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
2089 {
2090 struct ahci_host_priv *hpriv = ap->host->private_data;
2091 void __iomem *port_mmio = ahci_port_base(ap);
2092 struct ata_device *dev = ap->link.device;
2093 u32 devslp, dm, dito, mdat, deto;
2094 int rc;
2095 unsigned int err_mask;
2096
2097 devslp = readl(port_mmio + PORT_DEVSLP);
2098 if (!(devslp & PORT_DEVSLP_DSP)) {
2099 dev_info(ap->host->dev, "port does not support device sleep\n");
2100 return;
2101 }
2102
2103 /* disable device sleep */
2104 if (!sleep) {
2105 if (devslp & PORT_DEVSLP_ADSE) {
2106 writel(devslp & ~PORT_DEVSLP_ADSE,
2107 port_mmio + PORT_DEVSLP);
2108 err_mask = ata_dev_set_feature(dev,
2109 SETFEATURES_SATA_DISABLE,
2110 SATA_DEVSLP);
2111 if (err_mask && err_mask != AC_ERR_DEV)
2112 ata_dev_warn(dev, "failed to disable DEVSLP\n");
2113 }
2114 return;
2115 }
2116
2117 /* device sleep was already enabled */
2118 if (devslp & PORT_DEVSLP_ADSE)
2119 return;
2120
2121 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
2122 rc = ahci_stop_engine(ap);
2123 if (rc)
2124 return;
2125
2126 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET;
2127 dito = devslp_idle_timeout / (dm + 1);
2128 if (dito > 0x3ff)
2129 dito = 0x3ff;
2130
2131 /* Use the nominal value 10 ms if the read MDAT is zero,
2132 * the nominal value of DETO is 20 ms.
2133 */
2134 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
2135 ATA_LOG_DEVSLP_VALID_MASK) {
2136 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
2137 ATA_LOG_DEVSLP_MDAT_MASK;
2138 if (!mdat)
2139 mdat = 10;
2140 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
2141 if (!deto)
2142 deto = 20;
2143 } else {
2144 mdat = 10;
2145 deto = 20;
2146 }
2147
2148 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) |
2149 (mdat << PORT_DEVSLP_MDAT_OFFSET) |
2150 (deto << PORT_DEVSLP_DETO_OFFSET) |
2151 PORT_DEVSLP_ADSE);
2152 writel(devslp, port_mmio + PORT_DEVSLP);
2153
2154 hpriv->start_engine(ap);
2155
2156 /* enable device sleep feature for the drive */
2157 err_mask = ata_dev_set_feature(dev,
2158 SETFEATURES_SATA_ENABLE,
2159 SATA_DEVSLP);
2160 if (err_mask && err_mask != AC_ERR_DEV)
2161 ata_dev_warn(dev, "failed to enable DEVSLP\n");
2162 }
2163
2164 static void ahci_enable_fbs(struct ata_port *ap)
2165 {
2166 struct ahci_host_priv *hpriv = ap->host->private_data;
2167 struct ahci_port_priv *pp = ap->private_data;
2168 void __iomem *port_mmio = ahci_port_base(ap);
2169 u32 fbs;
2170 int rc;
2171
2172 if (!pp->fbs_supported)
2173 return;
2174
2175 fbs = readl(port_mmio + PORT_FBS);
2176 if (fbs & PORT_FBS_EN) {
2177 pp->fbs_enabled = true;
2178 pp->fbs_last_dev = -1; /* initialization */
2179 return;
2180 }
2181
2182 rc = ahci_stop_engine(ap);
2183 if (rc)
2184 return;
2185
2186 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2187 fbs = readl(port_mmio + PORT_FBS);
2188 if (fbs & PORT_FBS_EN) {
2189 dev_info(ap->host->dev, "FBS is enabled\n");
2190 pp->fbs_enabled = true;
2191 pp->fbs_last_dev = -1; /* initialization */
2192 } else
2193 dev_err(ap->host->dev, "Failed to enable FBS\n");
2194
2195 hpriv->start_engine(ap);
2196 }
2197
2198 static void ahci_disable_fbs(struct ata_port *ap)
2199 {
2200 struct ahci_host_priv *hpriv = ap->host->private_data;
2201 struct ahci_port_priv *pp = ap->private_data;
2202 void __iomem *port_mmio = ahci_port_base(ap);
2203 u32 fbs;
2204 int rc;
2205
2206 if (!pp->fbs_supported)
2207 return;
2208
2209 fbs = readl(port_mmio + PORT_FBS);
2210 if ((fbs & PORT_FBS_EN) == 0) {
2211 pp->fbs_enabled = false;
2212 return;
2213 }
2214
2215 rc = ahci_stop_engine(ap);
2216 if (rc)
2217 return;
2218
2219 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2220 fbs = readl(port_mmio + PORT_FBS);
2221 if (fbs & PORT_FBS_EN)
2222 dev_err(ap->host->dev, "Failed to disable FBS\n");
2223 else {
2224 dev_info(ap->host->dev, "FBS is disabled\n");
2225 pp->fbs_enabled = false;
2226 }
2227
2228 hpriv->start_engine(ap);
2229 }
2230
2231 static void ahci_pmp_attach(struct ata_port *ap)
2232 {
2233 void __iomem *port_mmio = ahci_port_base(ap);
2234 struct ahci_port_priv *pp = ap->private_data;
2235 u32 cmd;
2236
2237 cmd = readl(port_mmio + PORT_CMD);
2238 cmd |= PORT_CMD_PMP;
2239 writel(cmd, port_mmio + PORT_CMD);
2240
2241 ahci_enable_fbs(ap);
2242
2243 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2244
2245 /*
2246 * We must not change the port interrupt mask register if the
2247 * port is marked frozen, the value in pp->intr_mask will be
2248 * restored later when the port is thawed.
2249 *
2250 * Note that during initialization, the port is marked as
2251 * frozen since the irq handler is not yet registered.
2252 */
2253 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2254 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2255 }
2256
2257 static void ahci_pmp_detach(struct ata_port *ap)
2258 {
2259 void __iomem *port_mmio = ahci_port_base(ap);
2260 struct ahci_port_priv *pp = ap->private_data;
2261 u32 cmd;
2262
2263 ahci_disable_fbs(ap);
2264
2265 cmd = readl(port_mmio + PORT_CMD);
2266 cmd &= ~PORT_CMD_PMP;
2267 writel(cmd, port_mmio + PORT_CMD);
2268
2269 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2270
2271 /* see comment above in ahci_pmp_attach() */
2272 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2273 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2274 }
2275
2276 int ahci_port_resume(struct ata_port *ap)
2277 {
2278 ahci_rpm_get_port(ap);
2279
2280 ahci_power_up(ap);
2281 ahci_start_port(ap);
2282
2283 if (sata_pmp_attached(ap))
2284 ahci_pmp_attach(ap);
2285 else
2286 ahci_pmp_detach(ap);
2287
2288 return 0;
2289 }
2290 EXPORT_SYMBOL_GPL(ahci_port_resume);
2291
2292 #ifdef CONFIG_PM
2293 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2294 {
2295 const char *emsg = NULL;
2296 int rc;
2297
2298 rc = ahci_deinit_port(ap, &emsg);
2299 if (rc == 0)
2300 ahci_power_down(ap);
2301 else {
2302 ata_port_err(ap, "%s (%d)\n", emsg, rc);
2303 ata_port_freeze(ap);
2304 }
2305
2306 ahci_rpm_put_port(ap);
2307 return rc;
2308 }
2309 #endif
2310
2311 static int ahci_port_start(struct ata_port *ap)
2312 {
2313 struct ahci_host_priv *hpriv = ap->host->private_data;
2314 struct device *dev = ap->host->dev;
2315 struct ahci_port_priv *pp;
2316 void *mem;
2317 dma_addr_t mem_dma;
2318 size_t dma_sz, rx_fis_sz;
2319
2320 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2321 if (!pp)
2322 return -ENOMEM;
2323
2324 if (ap->host->n_ports > 1) {
2325 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL);
2326 if (!pp->irq_desc) {
2327 devm_kfree(dev, pp);
2328 return -ENOMEM;
2329 }
2330 snprintf(pp->irq_desc, 8,
2331 "%s%d", dev_driver_string(dev), ap->port_no);
2332 }
2333
2334 /* check FBS capability */
2335 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2336 void __iomem *port_mmio = ahci_port_base(ap);
2337 u32 cmd = readl(port_mmio + PORT_CMD);
2338 if (cmd & PORT_CMD_FBSCP)
2339 pp->fbs_supported = true;
2340 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
2341 dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
2342 ap->port_no);
2343 pp->fbs_supported = true;
2344 } else
2345 dev_warn(dev, "port %d is not capable of FBS\n",
2346 ap->port_no);
2347 }
2348
2349 if (pp->fbs_supported) {
2350 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2351 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2352 } else {
2353 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2354 rx_fis_sz = AHCI_RX_FIS_SZ;
2355 }
2356
2357 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2358 if (!mem)
2359 return -ENOMEM;
2360 memset(mem, 0, dma_sz);
2361
2362 /*
2363 * First item in chunk of DMA memory: 32-slot command table,
2364 * 32 bytes each in size
2365 */
2366 pp->cmd_slot = mem;
2367 pp->cmd_slot_dma = mem_dma;
2368
2369 mem += AHCI_CMD_SLOT_SZ;
2370 mem_dma += AHCI_CMD_SLOT_SZ;
2371
2372 /*
2373 * Second item: Received-FIS area
2374 */
2375 pp->rx_fis = mem;
2376 pp->rx_fis_dma = mem_dma;
2377
2378 mem += rx_fis_sz;
2379 mem_dma += rx_fis_sz;
2380
2381 /*
2382 * Third item: data area for storing a single command
2383 * and its scatter-gather table
2384 */
2385 pp->cmd_tbl = mem;
2386 pp->cmd_tbl_dma = mem_dma;
2387
2388 /*
2389 * Save off initial list of interrupts to be enabled.
2390 * This could be changed later
2391 */
2392 pp->intr_mask = DEF_PORT_IRQ;
2393
2394 /*
2395 * Switch to per-port locking in case each port has its own MSI vector.
2396 */
2397 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
2398 spin_lock_init(&pp->lock);
2399 ap->lock = &pp->lock;
2400 }
2401
2402 ap->private_data = pp;
2403
2404 /* engage engines, captain */
2405 return ahci_port_resume(ap);
2406 }
2407
2408 static void ahci_port_stop(struct ata_port *ap)
2409 {
2410 const char *emsg = NULL;
2411 struct ahci_host_priv *hpriv = ap->host->private_data;
2412 void __iomem *host_mmio = hpriv->mmio;
2413 int rc;
2414
2415 /* de-initialize port */
2416 rc = ahci_deinit_port(ap, &emsg);
2417 if (rc)
2418 ata_port_warn(ap, "%s (%d)\n", emsg, rc);
2419
2420 /*
2421 * Clear GHC.IS to prevent stuck INTx after disabling MSI and
2422 * re-enabling INTx.
2423 */
2424 writel(1 << ap->port_no, host_mmio + HOST_IRQ_STAT);
2425 }
2426
2427 void ahci_print_info(struct ata_host *host, const char *scc_s)
2428 {
2429 struct ahci_host_priv *hpriv = host->private_data;
2430 u32 vers, cap, cap2, impl, speed;
2431 const char *speed_s;
2432
2433 vers = hpriv->version;
2434 cap = hpriv->cap;
2435 cap2 = hpriv->cap2;
2436 impl = hpriv->port_map;
2437
2438 speed = (cap >> 20) & 0xf;
2439 if (speed == 1)
2440 speed_s = "1.5";
2441 else if (speed == 2)
2442 speed_s = "3";
2443 else if (speed == 3)
2444 speed_s = "6";
2445 else
2446 speed_s = "?";
2447
2448 dev_info(host->dev,
2449 "AHCI %02x%02x.%02x%02x "
2450 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2451 ,
2452
2453 (vers >> 24) & 0xff,
2454 (vers >> 16) & 0xff,
2455 (vers >> 8) & 0xff,
2456 vers & 0xff,
2457
2458 ((cap >> 8) & 0x1f) + 1,
2459 (cap & 0x1f) + 1,
2460 speed_s,
2461 impl,
2462 scc_s);
2463
2464 dev_info(host->dev,
2465 "flags: "
2466 "%s%s%s%s%s%s%s"
2467 "%s%s%s%s%s%s%s"
2468 "%s%s%s%s%s%s%s"
2469 "%s%s\n"
2470 ,
2471
2472 cap & HOST_CAP_64 ? "64bit " : "",
2473 cap & HOST_CAP_NCQ ? "ncq " : "",
2474 cap & HOST_CAP_SNTF ? "sntf " : "",
2475 cap & HOST_CAP_MPS ? "ilck " : "",
2476 cap & HOST_CAP_SSS ? "stag " : "",
2477 cap & HOST_CAP_ALPM ? "pm " : "",
2478 cap & HOST_CAP_LED ? "led " : "",
2479 cap & HOST_CAP_CLO ? "clo " : "",
2480 cap & HOST_CAP_ONLY ? "only " : "",
2481 cap & HOST_CAP_PMP ? "pmp " : "",
2482 cap & HOST_CAP_FBS ? "fbs " : "",
2483 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2484 cap & HOST_CAP_SSC ? "slum " : "",
2485 cap & HOST_CAP_PART ? "part " : "",
2486 cap & HOST_CAP_CCC ? "ccc " : "",
2487 cap & HOST_CAP_EMS ? "ems " : "",
2488 cap & HOST_CAP_SXS ? "sxs " : "",
2489 cap2 & HOST_CAP2_DESO ? "deso " : "",
2490 cap2 & HOST_CAP2_SADM ? "sadm " : "",
2491 cap2 & HOST_CAP2_SDS ? "sds " : "",
2492 cap2 & HOST_CAP2_APST ? "apst " : "",
2493 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2494 cap2 & HOST_CAP2_BOH ? "boh " : ""
2495 );
2496 }
2497 EXPORT_SYMBOL_GPL(ahci_print_info);
2498
2499 void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2500 struct ata_port_info *pi)
2501 {
2502 u8 messages;
2503 void __iomem *mmio = hpriv->mmio;
2504 u32 em_loc = readl(mmio + HOST_EM_LOC);
2505 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2506
2507 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2508 return;
2509
2510 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2511
2512 if (messages) {
2513 /* store em_loc */
2514 hpriv->em_loc = ((em_loc >> 16) * 4);
2515 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
2516 hpriv->em_msg_type = messages;
2517 pi->flags |= ATA_FLAG_EM;
2518 if (!(em_ctl & EM_CTL_ALHD))
2519 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2520 }
2521 }
2522 EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2523
2524 static int ahci_host_activate_multi_irqs(struct ata_host *host,
2525 struct scsi_host_template *sht)
2526 {
2527 struct ahci_host_priv *hpriv = host->private_data;
2528 int i, rc;
2529
2530 rc = ata_host_start(host);
2531 if (rc)
2532 return rc;
2533 /*
2534 * Requests IRQs according to AHCI-1.1 when multiple MSIs were
2535 * allocated. That is one MSI per port, starting from @irq.
2536 */
2537 for (i = 0; i < host->n_ports; i++) {
2538 struct ahci_port_priv *pp = host->ports[i]->private_data;
2539 int irq = hpriv->get_irq_vector(host, i);
2540
2541 /* Do not receive interrupts sent by dummy ports */
2542 if (!pp) {
2543 disable_irq(irq);
2544 continue;
2545 }
2546
2547 rc = devm_request_irq(host->dev, irq, ahci_multi_irqs_intr_hard,
2548 0, pp->irq_desc, host->ports[i]);
2549
2550 if (rc)
2551 return rc;
2552 ata_port_desc(host->ports[i], "irq %d", irq);
2553 }
2554
2555 return ata_host_register(host, sht);
2556 }
2557
2558 /**
2559 * ahci_host_activate - start AHCI host, request IRQs and register it
2560 * @host: target ATA host
2561 * @sht: scsi_host_template to use when registering the host
2562 *
2563 * LOCKING:
2564 * Inherited from calling layer (may sleep).
2565 *
2566 * RETURNS:
2567 * 0 on success, -errno otherwise.
2568 */
2569 int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht)
2570 {
2571 struct ahci_host_priv *hpriv = host->private_data;
2572 int irq = hpriv->irq;
2573 int rc;
2574
2575 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
2576 if (hpriv->irq_handler)
2577 dev_warn(host->dev,
2578 "both AHCI_HFLAG_MULTI_MSI flag set and custom irq handler implemented\n");
2579 if (!hpriv->get_irq_vector) {
2580 dev_err(host->dev,
2581 "AHCI_HFLAG_MULTI_MSI requires ->get_irq_vector!\n");
2582 return -EIO;
2583 }
2584
2585 rc = ahci_host_activate_multi_irqs(host, sht);
2586 } else {
2587 rc = ata_host_activate(host, irq, hpriv->irq_handler,
2588 IRQF_SHARED, sht);
2589 }
2590
2591
2592 return rc;
2593 }
2594 EXPORT_SYMBOL_GPL(ahci_host_activate);
2595
2596 MODULE_AUTHOR("Jeff Garzik");
2597 MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2598 MODULE_LICENSE("GPL");
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