drivers/clk/ti/mux.c

   1 /*
   2  * TI Multiplexer Clock
   3  *
   4  * Copyright (C) 2013 Texas Instruments, Inc.
   5  *
   6  * Tero Kristo <t-kristo@ti.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  13  * kind, whether express or implied; without even the implied warranty
  14  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/clk-provider.h>
  19 #include <linux/slab.h>
  20 #include <linux/err.h>
  21 #include <linux/of.h>
  22 #include <linux/of_address.h>
  23 #include <linux/clk/ti.h>
  24 #include "clock.h"
  25
  26 #undef pr_fmt
  27 #define pr_fmt(fmt) "%s: " fmt, __func__
  28
  29 static u8 ti_clk_mux_get_parent(struct clk_hw *hw)
  30 {
  31         struct clk_omap_mux *mux = to_clk_omap_mux(hw);
  32         int num_parents = clk_hw_get_num_parents(hw);
  33         u32 val;
  34
  35         /*
  36          * FIXME need a mux-specific flag to determine if val is bitwise or
  37          * numeric. e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges
  38          * from 0x1 to 0x7 (index starts at one)
  39          * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
  40          * val = 0x4 really means "bit 2, index starts at bit 0"
  41          */
  42         val = ti_clk_ll_ops->clk_readl(&mux->reg) >> mux->shift;
  43         val &= mux->mask;
  44
  45         if (mux->table) {
  46                 int i;
  47
  48                 for (i = 0; i < num_parents; i++)
  49                         if (mux->table[i] == val)
  50                                 return i;
  51                 return -EINVAL;
  52         }
  53
  54         if (val && (mux->flags & CLK_MUX_INDEX_BIT))
  55                 val = ffs(val) - 1;
  56
  57         if (val && (mux->flags & CLK_MUX_INDEX_ONE))
  58                 val--;
  59
  60         if (val >= num_parents)
  61                 return -EINVAL;
  62
  63         return val;
  64 }
  65
  66 static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index)
  67 {
  68         struct clk_omap_mux *mux = to_clk_omap_mux(hw);
  69         u32 val;
  70
  71         if (mux->table) {
  72                 index = mux->table[index];
  73         } else {
  74                 if (mux->flags & CLK_MUX_INDEX_BIT)
  75                         index = (1 << ffs(index));
  76
  77                 if (mux->flags & CLK_MUX_INDEX_ONE)
  78                         index++;
  79         }
  80
  81         if (mux->flags & CLK_MUX_HIWORD_MASK) {
  82                 val = mux->mask << (mux->shift + 16);
  83         } else {
  84                 val = ti_clk_ll_ops->clk_readl(&mux->reg);
  85                 val &= ~(mux->mask << mux->shift);
  86         }
  87         val |= index << mux->shift;
  88         ti_clk_ll_ops->clk_writel(val, &mux->reg);
  89
  90         return 0;
  91 }
  92
  93 const struct clk_ops ti_clk_mux_ops = {
  94         .get_parent = ti_clk_mux_get_parent,
  95         .set_parent = ti_clk_mux_set_parent,
  96         .determine_rate = __clk_mux_determine_rate,
  97 };
  98
  99 static struct clk *_register_mux(struct device *dev, const char *name,
 100                                  const char * const *parent_names,
 101                                  u8 num_parents, unsigned long flags,
 102                                  struct clk_omap_reg *reg, u8 shift, u32 mask,
 103                                  u8 clk_mux_flags, u32 *table)
 104 {
 105         struct clk_omap_mux *mux;
 106         struct clk *clk;
 107         struct clk_init_data init;
 108
 109         /* allocate the mux */
 110         mux = kzalloc(sizeof(*mux), GFP_KERNEL);
 111         if (!mux)
 112                 return ERR_PTR(-ENOMEM);
 113
 114         init.name = name;
 115         init.ops = &ti_clk_mux_ops;
 116         init.flags = flags | CLK_IS_BASIC;
 117         init.parent_names = parent_names;
 118         init.num_parents = num_parents;
 119
 120         /* struct clk_mux assignments */
 121         memcpy(&mux->reg, reg, sizeof(*reg));
 122         mux->shift = shift;
 123         mux->mask = mask;
 124         mux->flags = clk_mux_flags;
 125         mux->table = table;
 126         mux->hw.init = &init;
 127
 128         clk = ti_clk_register(dev, &mux->hw, name);
 129
 130         if (IS_ERR(clk))
 131                 kfree(mux);
 132
 133         return clk;
 134 }
 135
 136 struct clk *ti_clk_register_mux(struct ti_clk *setup)
 137 {
 138         struct ti_clk_mux *mux;
 139         u32 flags;
 140         u8 mux_flags = 0;
 141         struct clk_omap_reg reg;
 142         u32 mask;
 143
 144         mux = setup->data;
 145         flags = CLK_SET_RATE_NO_REPARENT;
 146
 147         mask = mux->num_parents;
 148         if (!(mux->flags & CLKF_INDEX_STARTS_AT_ONE))
 149                 mask--;
 150
 151         mask = (1 << fls(mask)) - 1;
 152         reg.index = mux->module;
 153         reg.offset = mux->reg;
 154         reg.ptr = NULL;
 155
 156         if (mux->flags & CLKF_INDEX_STARTS_AT_ONE)
 157                 mux_flags |= CLK_MUX_INDEX_ONE;
 158
 159         if (mux->flags & CLKF_SET_RATE_PARENT)
 160                 flags |= CLK_SET_RATE_PARENT;
 161
 162         return _register_mux(NULL, setup->name, mux->parents, mux->num_parents,
 163                              flags, &reg, mux->bit_shift, mask,
 164                              mux_flags, NULL);
 165 }
 166
 167 /**
 168  * of_mux_clk_setup - Setup function for simple mux rate clock
 169  * @node: DT node for the clock
 170  *
 171  * Sets up a basic clock multiplexer.
 172  */
 173 static void of_mux_clk_setup(struct device_node *node)
 174 {
 175         struct clk *clk;
 176         struct clk_omap_reg reg;
 177         unsigned int num_parents;
 178         const char **parent_names;
 179         u8 clk_mux_flags = 0;
 180         u32 mask = 0;
 181         u32 shift = 0;
 182         u32 flags = CLK_SET_RATE_NO_REPARENT;
 183
 184         num_parents = of_clk_get_parent_count(node);
 185         if (num_parents < 2) {
 186                 pr_err("mux-clock %s must have parents\n", node->name);
 187                 return;
 188         }
 189         parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL);
 190         if (!parent_names)
 191                 goto cleanup;
 192
 193         of_clk_parent_fill(node, parent_names, num_parents);
 194
 195         if (ti_clk_get_reg_addr(node, 0, &reg))
 196                 goto cleanup;
 197
 198         of_property_read_u32(node, "ti,bit-shift", &shift);
 199
 200         if (of_property_read_bool(node, "ti,index-starts-at-one"))
 201                 clk_mux_flags |= CLK_MUX_INDEX_ONE;
 202
 203         if (of_property_read_bool(node, "ti,set-rate-parent"))
 204                 flags |= CLK_SET_RATE_PARENT;
 205
 206         /* Generate bit-mask based on parent info */
 207         mask = num_parents;
 208         if (!(clk_mux_flags & CLK_MUX_INDEX_ONE))
 209                 mask--;
 210
 211         mask = (1 << fls(mask)) - 1;
 212
 213         clk = _register_mux(NULL, node->name, parent_names, num_parents,
 214                             flags, &reg, shift, mask, clk_mux_flags, NULL);
 215
 216         if (!IS_ERR(clk))
 217                 of_clk_add_provider(node, of_clk_src_simple_get, clk);
 218
 219 cleanup:
 220         kfree(parent_names);
 221 }
 222 CLK_OF_DECLARE(mux_clk, "ti,mux-clock", of_mux_clk_setup);
 223
 224 struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup)
 225 {
 226         struct clk_omap_mux *mux;
 227         int num_parents;
 228
 229         if (!setup)
 230                 return NULL;
 231
 232         mux = kzalloc(sizeof(*mux), GFP_KERNEL);
 233         if (!mux)
 234                 return ERR_PTR(-ENOMEM);
 235
 236         mux->shift = setup->bit_shift;
 237
 238         mux->reg.index = setup->module;
 239         mux->reg.offset = setup->reg;
 240
 241         if (setup->flags & CLKF_INDEX_STARTS_AT_ONE)
 242                 mux->flags |= CLK_MUX_INDEX_ONE;
 243
 244         num_parents = setup->num_parents;
 245
 246         mux->mask = num_parents - 1;
 247         mux->mask = (1 << fls(mux->mask)) - 1;
 248
 249         return &mux->hw;
 250 }
 251
 252 static void __init of_ti_composite_mux_clk_setup(struct device_node *node)
 253 {
 254         struct clk_omap_mux *mux;
 255         unsigned int num_parents;
 256         u32 val;
 257
 258         mux = kzalloc(sizeof(*mux), GFP_KERNEL);
 259         if (!mux)
 260                 return;
 261
 262         if (ti_clk_get_reg_addr(node, 0, &mux->reg))
 263                 goto cleanup;
 264
 265         if (!of_property_read_u32(node, "ti,bit-shift", &val))
 266                 mux->shift = val;
 267
 268         if (of_property_read_bool(node, "ti,index-starts-at-one"))
 269                 mux->flags |= CLK_MUX_INDEX_ONE;
 270
 271         num_parents = of_clk_get_parent_count(node);
 272
 273         if (num_parents < 2) {
 274                 pr_err("%s must have parents\n", node->name);
 275                 goto cleanup;
 276         }
 277
 278         mux->mask = num_parents - 1;
 279         mux->mask = (1 << fls(mux->mask)) - 1;
 280
 281         if (!ti_clk_add_component(node, &mux->hw, CLK_COMPONENT_TYPE_MUX))
 282                 return;
 283
 284 cleanup:
 285         kfree(mux);
 286 }
 287 CLK_OF_DECLARE(ti_composite_mux_clk_setup, "ti,composite-mux-clock",
 288                of_ti_composite_mux_clk_setup);