?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
x86/intel_rdt: Fix incorrect returned value when creating rdgroup sub-directory in...
[cris-mirror.git] / drivers / media / dvb-frontends / stv0367.c
blob5435c908e298ce027d16d453a43f4be7b535fe39
1 /*
2 * stv0367.c
3 *
4 * Driver for ST STV0367 DVB-T & DVB-C demodulator IC.
5 *
6 * Copyright (C) ST Microelectronics.
7 * Copyright (C) 2010,2011 NetUP Inc.
8 * Copyright (C) 2010,2011 Igor M. Liplianin <liplianin@netup.ru>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 *
19 * GNU General Public License for more details.
20 */
21
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/string.h>
25 #include <linux/slab.h>
26 #include <linux/i2c.h>
27
28 #include <media/dvb_math.h>
29
30 #include "stv0367.h"
31 #include "stv0367_defs.h"
32 #include "stv0367_regs.h"
33 #include "stv0367_priv.h"
34
35 /* Max transfer size done by I2C transfer functions */
36 #define MAX_XFER_SIZE 64
37
38 static int stvdebug;
39 module_param_named(debug, stvdebug, int, 0644);
40
41 static int i2cdebug;
42 module_param_named(i2c_debug, i2cdebug, int, 0644);
43
44 #define dprintk(args...) \
45 do { \
46 if (stvdebug) \
47 printk(KERN_DEBUG args); \
48 } while (0)
49 /* DVB-C */
50
51 enum active_demod_state { demod_none, demod_ter, demod_cab };
52
53 struct stv0367cab_state {
54 enum stv0367_cab_signal_type state;
55 u32 mclk;
56 u32 adc_clk;
57 s32 search_range;
58 s32 derot_offset;
59 /* results */
60 int locked; /* channel found */
61 u32 freq_khz; /* found frequency (in kHz) */
62 u32 symbol_rate; /* found symbol rate (in Bds) */
63 enum fe_spectral_inversion spect_inv; /* Spectrum Inversion */
64 u32 qamfec_status_reg; /* status reg to poll for FEC Lock */
65 };
66
67 struct stv0367ter_state {
68 /* DVB-T */
69 enum stv0367_ter_signal_type state;
70 enum stv0367_ter_if_iq_mode if_iq_mode;
71 enum stv0367_ter_mode mode;/* mode 2K or 8K */
72 enum fe_guard_interval guard;
73 enum stv0367_ter_hierarchy hierarchy;
74 u32 frequency;
75 enum fe_spectral_inversion sense; /* current search spectrum */
76 u8 force; /* force mode/guard */
77 u8 bw; /* channel width 6, 7 or 8 in MHz */
78 u8 pBW; /* channel width used during previous lock */
79 u32 pBER;
80 u32 pPER;
81 u32 ucblocks;
82 s8 echo_pos; /* echo position */
83 u8 first_lock;
84 u8 unlock_counter;
85 u32 agc_val;
86 };
87
88 struct stv0367_state {
89 struct dvb_frontend fe;
90 struct i2c_adapter *i2c;
91 /* config settings */
92 const struct stv0367_config *config;
93 u8 chip_id;
94 /* DVB-C */
95 struct stv0367cab_state *cab_state;
96 /* DVB-T */
97 struct stv0367ter_state *ter_state;
98 /* flags for operation control */
99 u8 use_i2c_gatectrl;
100 u8 deftabs;
101 u8 reinit_on_setfrontend;
102 u8 auto_if_khz;
103 enum active_demod_state activedemod;
104 };
105
106 #define RF_LOOKUP_TABLE_SIZE 31
107 #define RF_LOOKUP_TABLE2_SIZE 16
108 /* RF Level (for RF AGC->AGC1) Lookup Table, depends on the board and tuner.*/
109 static const s32 stv0367cab_RF_LookUp1[RF_LOOKUP_TABLE_SIZE][RF_LOOKUP_TABLE_SIZE] = {
110 {/*AGC1*/
111 48, 50, 51, 53, 54, 56, 57, 58, 60, 61, 62, 63,
112 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,
113 76, 77, 78, 80, 83, 85, 88,
114 }, {/*RF(dbm)*/
115 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
116 34, 35, 36, 37, 38, 39, 41, 42, 43, 44, 46, 47,
117 49, 50, 52, 53, 54, 55, 56,
118 }
119 };
120 /* RF Level (for IF AGC->AGC2) Lookup Table, depends on the board and tuner.*/
121 static const s32 stv0367cab_RF_LookUp2[RF_LOOKUP_TABLE2_SIZE][RF_LOOKUP_TABLE2_SIZE] = {
122 {/*AGC2*/
123 28, 29, 31, 32, 34, 35, 36, 37,
124 38, 39, 40, 41, 42, 43, 44, 45,
125 }, {/*RF(dbm)*/
126 57, 58, 59, 60, 61, 62, 63, 64,
127 65, 66, 67, 68, 69, 70, 71, 72,
128 }
129 };
130
131 static
132 int stv0367_writeregs(struct stv0367_state *state, u16 reg, u8 *data, int len)
133 {
134 u8 buf[MAX_XFER_SIZE];
135 struct i2c_msg msg = {
136 .addr = state->config->demod_address,
137 .flags = 0,
138 .buf = buf,
139 .len = len + 2
140 };
141 int ret;
142
143 if (2 + len > sizeof(buf)) {
144 printk(KERN_WARNING
145 "%s: i2c wr reg=%04x: len=%d is too big!\n",
146 KBUILD_MODNAME, reg, len);
147 return -EINVAL;
148 }
149
150
151 buf[0] = MSB(reg);
152 buf[1] = LSB(reg);
153 memcpy(buf + 2, data, len);
154
155 if (i2cdebug)
156 printk(KERN_DEBUG "%s: [%02x] %02x: %02x\n", __func__,
157 state->config->demod_address, reg, buf[2]);
158
159 ret = i2c_transfer(state->i2c, &msg, 1);
160 if (ret != 1)
161 printk(KERN_ERR "%s: i2c write error! ([%02x] %02x: %02x)\n",
162 __func__, state->config->demod_address, reg, buf[2]);
163
164 return (ret != 1) ? -EREMOTEIO : 0;
165 }
166
167 static int stv0367_writereg(struct stv0367_state *state, u16 reg, u8 data)
168 {
169 u8 tmp = data; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
170
171 return stv0367_writeregs(state, reg, &tmp, 1);
172 }
173
174 static u8 stv0367_readreg(struct stv0367_state *state, u16 reg)
175 {
176 u8 b0[] = { 0, 0 };
177 u8 b1[] = { 0 };
178 struct i2c_msg msg[] = {
179 {
180 .addr = state->config->demod_address,
181 .flags = 0,
182 .buf = b0,
183 .len = 2
184 }, {
185 .addr = state->config->demod_address,
186 .flags = I2C_M_RD,
187 .buf = b1,
188 .len = 1
189 }
190 };
191 int ret;
192
193 b0[0] = MSB(reg);
194 b0[1] = LSB(reg);
195
196 ret = i2c_transfer(state->i2c, msg, 2);
197 if (ret != 2)
198 printk(KERN_ERR "%s: i2c read error ([%02x] %02x: %02x)\n",
199 __func__, state->config->demod_address, reg, b1[0]);
200
201 if (i2cdebug)
202 printk(KERN_DEBUG "%s: [%02x] %02x: %02x\n", __func__,
203 state->config->demod_address, reg, b1[0]);
204
205 return b1[0];
206 }
207
208 static void extract_mask_pos(u32 label, u8 *mask, u8 *pos)
209 {
210 u8 position = 0, i = 0;
211
212 (*mask) = label & 0xff;
213
214 while ((position == 0) && (i < 8)) {
215 position = ((*mask) >> i) & 0x01;
216 i++;
217 }
218
219 (*pos) = (i - 1);
220 }
221
222 static void stv0367_writebits(struct stv0367_state *state, u32 label, u8 val)
223 {
224 u8 reg, mask, pos;
225
226 reg = stv0367_readreg(state, (label >> 16) & 0xffff);
227 extract_mask_pos(label, &mask, &pos);
228
229 val = mask & (val << pos);
230
231 reg = (reg & (~mask)) | val;
232 stv0367_writereg(state, (label >> 16) & 0xffff, reg);
233
234 }
235
236 static void stv0367_setbits(u8 *reg, u32 label, u8 val)
237 {
238 u8 mask, pos;
239
240 extract_mask_pos(label, &mask, &pos);
241
242 val = mask & (val << pos);
243
244 (*reg) = ((*reg) & (~mask)) | val;
245 }
246
247 static u8 stv0367_readbits(struct stv0367_state *state, u32 label)
248 {
249 u8 val = 0xff;
250 u8 mask, pos;
251
252 extract_mask_pos(label, &mask, &pos);
253
254 val = stv0367_readreg(state, label >> 16);
255 val = (val & mask) >> pos;
256
257 return val;
258 }
259
260 #if 0 /* Currently, unused */
261 static u8 stv0367_getbits(u8 reg, u32 label)
262 {
263 u8 mask, pos;
264
265 extract_mask_pos(label, &mask, &pos);
266
267 return (reg & mask) >> pos;
268 }
269 #endif
270
271 static void stv0367_write_table(struct stv0367_state *state,
272 const struct st_register *deftab)
273 {
274 int i = 0;
275
276 while (1) {
277 if (!deftab[i].addr)
278 break;
279 stv0367_writereg(state, deftab[i].addr, deftab[i].value);
280 i++;
281 }
282 }
283
284 static void stv0367_pll_setup(struct stv0367_state *state,
285 u32 icspeed, u32 xtal)
286 {
287 /* note on regs: R367TER_* and R367CAB_* defines each point to
288 * 0xf0d8, so just use R367TER_ for both cases
289 */
290
291 switch (icspeed) {
292 case STV0367_ICSPEED_58000:
293 switch (xtal) {
294 default:
295 case 27000000:
296 dprintk("STV0367 SetCLKgen for 58MHz IC and 27Mhz crystal\n");
297 /* PLLMDIV: 27, PLLNDIV: 232 */
298 stv0367_writereg(state, R367TER_PLLMDIV, 0x1b);
299 stv0367_writereg(state, R367TER_PLLNDIV, 0xe8);
300 break;
301 }
302 break;
303 default:
304 case STV0367_ICSPEED_53125:
305 switch (xtal) {
306 /* set internal freq to 53.125MHz */
307 case 16000000:
308 stv0367_writereg(state, R367TER_PLLMDIV, 0x2);
309 stv0367_writereg(state, R367TER_PLLNDIV, 0x1b);
310 break;
311 case 25000000:
312 stv0367_writereg(state, R367TER_PLLMDIV, 0xa);
313 stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
314 break;
315 default:
316 case 27000000:
317 dprintk("FE_STV0367TER_SetCLKgen for 27Mhz\n");
318 stv0367_writereg(state, R367TER_PLLMDIV, 0x1);
319 stv0367_writereg(state, R367TER_PLLNDIV, 0x8);
320 break;
321 case 30000000:
322 stv0367_writereg(state, R367TER_PLLMDIV, 0xc);
323 stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
324 break;
325 }
326 }
327
328 stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
329 }
330
331 static int stv0367_get_if_khz(struct stv0367_state *state, u32 *ifkhz)
332 {
333 if (state->auto_if_khz && state->fe.ops.tuner_ops.get_if_frequency) {
334 state->fe.ops.tuner_ops.get_if_frequency(&state->fe, ifkhz);
335 *ifkhz = *ifkhz / 1000; /* hz -> khz */
336 } else
337 *ifkhz = state->config->if_khz;
338
339 return 0;
340 }
341
342 static int stv0367ter_gate_ctrl(struct dvb_frontend *fe, int enable)
343 {
344 struct stv0367_state *state = fe->demodulator_priv;
345 u8 tmp = stv0367_readreg(state, R367TER_I2CRPT);
346
347 dprintk("%s:\n", __func__);
348
349 if (enable) {
350 stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 0);
351 stv0367_setbits(&tmp, F367TER_I2CT_ON, 1);
352 } else {
353 stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 1);
354 stv0367_setbits(&tmp, F367TER_I2CT_ON, 0);
355 }
356
357 stv0367_writereg(state, R367TER_I2CRPT, tmp);
358
359 return 0;
360 }
361
362 static u32 stv0367_get_tuner_freq(struct dvb_frontend *fe)
363 {
364 struct dvb_frontend_ops *frontend_ops = &fe->ops;
365 struct dvb_tuner_ops *tuner_ops = &frontend_ops->tuner_ops;
366 u32 freq = 0;
367 int err = 0;
368
369 dprintk("%s:\n", __func__);
370
371 if (tuner_ops->get_frequency) {
372 err = tuner_ops->get_frequency(fe, &freq);
373 if (err < 0) {
374 printk(KERN_ERR "%s: Invalid parameter\n", __func__);
375 return err;
376 }
377
378 dprintk("%s: frequency=%d\n", __func__, freq);
379
380 } else
381 return -1;
382
383 return freq;
384 }
385
386 static u16 CellsCoeffs_8MHz_367cofdm[3][6][5] = {
387 {
388 {0x10EF, 0xE205, 0x10EF, 0xCE49, 0x6DA7}, /* CELL 1 COEFFS 27M*/
389 {0x2151, 0xc557, 0x2151, 0xc705, 0x6f93}, /* CELL 2 COEFFS */
390 {0x2503, 0xc000, 0x2503, 0xc375, 0x7194}, /* CELL 3 COEFFS */
391 {0x20E9, 0xca94, 0x20e9, 0xc153, 0x7194}, /* CELL 4 COEFFS */
392 {0x06EF, 0xF852, 0x06EF, 0xC057, 0x7207}, /* CELL 5 COEFFS */
393 {0x0000, 0x0ECC, 0x0ECC, 0x0000, 0x3647} /* CELL 6 COEFFS */
394 }, {
395 {0x10A0, 0xE2AF, 0x10A1, 0xCE76, 0x6D6D}, /* CELL 1 COEFFS 25M*/
396 {0x20DC, 0xC676, 0x20D9, 0xC80A, 0x6F29},
397 {0x2532, 0xC000, 0x251D, 0xC391, 0x706F},
398 {0x1F7A, 0xCD2B, 0x2032, 0xC15E, 0x711F},
399 {0x0698, 0xFA5E, 0x0568, 0xC059, 0x7193},
400 {0x0000, 0x0918, 0x149C, 0x0000, 0x3642} /* CELL 6 COEFFS */
401 }, {
402 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
403 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
404 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
405 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
406 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
407 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
408 }
409 };
410
411 static u16 CellsCoeffs_7MHz_367cofdm[3][6][5] = {
412 {
413 {0x12CA, 0xDDAF, 0x12CA, 0xCCEB, 0x6FB1}, /* CELL 1 COEFFS 27M*/
414 {0x2329, 0xC000, 0x2329, 0xC6B0, 0x725F}, /* CELL 2 COEFFS */
415 {0x2394, 0xC000, 0x2394, 0xC2C7, 0x7410}, /* CELL 3 COEFFS */
416 {0x251C, 0xC000, 0x251C, 0xC103, 0x74D9}, /* CELL 4 COEFFS */
417 {0x0804, 0xF546, 0x0804, 0xC040, 0x7544}, /* CELL 5 COEFFS */
418 {0x0000, 0x0CD9, 0x0CD9, 0x0000, 0x370A} /* CELL 6 COEFFS */
419 }, {
420 {0x1285, 0xDE47, 0x1285, 0xCD17, 0x6F76}, /*25M*/
421 {0x234C, 0xC000, 0x2348, 0xC6DA, 0x7206},
422 {0x23B4, 0xC000, 0x23AC, 0xC2DB, 0x73B3},
423 {0x253D, 0xC000, 0x25B6, 0xC10B, 0x747F},
424 {0x0721, 0xF79C, 0x065F, 0xC041, 0x74EB},
425 {0x0000, 0x08FA, 0x1162, 0x0000, 0x36FF}
426 }, {
427 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
428 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
429 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
430 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
431 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
432 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
433 }
434 };
435
436 static u16 CellsCoeffs_6MHz_367cofdm[3][6][5] = {
437 {
438 {0x1699, 0xD5B8, 0x1699, 0xCBC3, 0x713B}, /* CELL 1 COEFFS 27M*/
439 {0x2245, 0xC000, 0x2245, 0xC568, 0x74D5}, /* CELL 2 COEFFS */
440 {0x227F, 0xC000, 0x227F, 0xC1FC, 0x76C6}, /* CELL 3 COEFFS */
441 {0x235E, 0xC000, 0x235E, 0xC0A7, 0x778A}, /* CELL 4 COEFFS */
442 {0x0ECB, 0xEA0B, 0x0ECB, 0xC027, 0x77DD}, /* CELL 5 COEFFS */
443 {0x0000, 0x0B68, 0x0B68, 0x0000, 0xC89A}, /* CELL 6 COEFFS */
444 }, {
445 {0x1655, 0xD64E, 0x1658, 0xCBEF, 0x70FE}, /*25M*/
446 {0x225E, 0xC000, 0x2256, 0xC589, 0x7489},
447 {0x2293, 0xC000, 0x2295, 0xC209, 0x767E},
448 {0x2377, 0xC000, 0x23AA, 0xC0AB, 0x7746},
449 {0x0DC7, 0xEBC8, 0x0D07, 0xC027, 0x7799},
450 {0x0000, 0x0888, 0x0E9C, 0x0000, 0x3757}
451
452 }, {
453 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
454 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
455 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
456 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
457 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
458 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
459 }
460 };
461
462 static u32 stv0367ter_get_mclk(struct stv0367_state *state, u32 ExtClk_Hz)
463 {
464 u32 mclk_Hz = 0; /* master clock frequency (Hz) */
465 u32 m, n, p;
466
467 dprintk("%s:\n", __func__);
468
469 if (stv0367_readbits(state, F367TER_BYPASS_PLLXN) == 0) {
470 n = (u32)stv0367_readbits(state, F367TER_PLL_NDIV);
471 if (n == 0)
472 n = n + 1;
473
474 m = (u32)stv0367_readbits(state, F367TER_PLL_MDIV);
475 if (m == 0)
476 m = m + 1;
477
478 p = (u32)stv0367_readbits(state, F367TER_PLL_PDIV);
479 if (p > 5)
480 p = 5;
481
482 mclk_Hz = ((ExtClk_Hz / 2) * n) / (m * (1 << p));
483
484 dprintk("N=%d M=%d P=%d mclk_Hz=%d ExtClk_Hz=%d\n",
485 n, m, p, mclk_Hz, ExtClk_Hz);
486 } else
487 mclk_Hz = ExtClk_Hz;
488
489 dprintk("%s: mclk_Hz=%d\n", __func__, mclk_Hz);
490
491 return mclk_Hz;
492 }
493
494 static int stv0367ter_filt_coeff_init(struct stv0367_state *state,
495 u16 CellsCoeffs[3][6][5], u32 DemodXtal)
496 {
497 int i, j, k, freq;
498
499 dprintk("%s:\n", __func__);
500
501 freq = stv0367ter_get_mclk(state, DemodXtal);
502
503 if (freq == 53125000)
504 k = 1; /* equivalent to Xtal 25M on 362*/
505 else if (freq == 54000000)
506 k = 0; /* equivalent to Xtal 27M on 362*/
507 else if (freq == 52500000)
508 k = 2; /* equivalent to Xtal 30M on 362*/
509 else
510 return 0;
511
512 for (i = 1; i <= 6; i++) {
513 stv0367_writebits(state, F367TER_IIR_CELL_NB, i - 1);
514
515 for (j = 1; j <= 5; j++) {
516 stv0367_writereg(state,
517 (R367TER_IIRCX_COEFF1_MSB + 2 * (j - 1)),
518 MSB(CellsCoeffs[k][i-1][j-1]));
519 stv0367_writereg(state,
520 (R367TER_IIRCX_COEFF1_LSB + 2 * (j - 1)),
521 LSB(CellsCoeffs[k][i-1][j-1]));
522 }
523 }
524
525 return 1;
526
527 }
528
529 static void stv0367ter_agc_iir_lock_detect_set(struct stv0367_state *state)
530 {
531 dprintk("%s:\n", __func__);
532
533 stv0367_writebits(state, F367TER_LOCK_DETECT_LSB, 0x00);
534
535 /* Lock detect 1 */
536 stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x00);
537 stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06);
538 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04);
539
540 /* Lock detect 2 */
541 stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x01);
542 stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06);
543 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04);
544
545 /* Lock detect 3 */
546 stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x02);
547 stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01);
548 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00);
549
550 /* Lock detect 4 */
551 stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x03);
552 stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01);
553 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00);
554
555 }
556
557 static int stv0367_iir_filt_init(struct stv0367_state *state, u8 Bandwidth,
558 u32 DemodXtalValue)
559 {
560 dprintk("%s:\n", __func__);
561
562 stv0367_writebits(state, F367TER_NRST_IIR, 0);
563
564 switch (Bandwidth) {
565 case 6:
566 if (!stv0367ter_filt_coeff_init(state,
567 CellsCoeffs_6MHz_367cofdm,
568 DemodXtalValue))
569 return 0;
570 break;
571 case 7:
572 if (!stv0367ter_filt_coeff_init(state,
573 CellsCoeffs_7MHz_367cofdm,
574 DemodXtalValue))
575 return 0;
576 break;
577 case 8:
578 if (!stv0367ter_filt_coeff_init(state,
579 CellsCoeffs_8MHz_367cofdm,
580 DemodXtalValue))
581 return 0;
582 break;
583 default:
584 return 0;
585 }
586
587 stv0367_writebits(state, F367TER_NRST_IIR, 1);
588
589 return 1;
590 }
591
592 static void stv0367ter_agc_iir_rst(struct stv0367_state *state)
593 {
594
595 u8 com_n;
596
597 dprintk("%s:\n", __func__);
598
599 com_n = stv0367_readbits(state, F367TER_COM_N);
600
601 stv0367_writebits(state, F367TER_COM_N, 0x07);
602
603 stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x00);
604 stv0367_writebits(state, F367TER_COM_AGC_ON, 0x00);
605
606 stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x01);
607 stv0367_writebits(state, F367TER_COM_AGC_ON, 0x01);
608
609 stv0367_writebits(state, F367TER_COM_N, com_n);
610
611 }
612
613 static int stv0367ter_duration(s32 mode, int tempo1, int tempo2, int tempo3)
614 {
615 int local_tempo = 0;
616 switch (mode) {
617 case 0:
618 local_tempo = tempo1;
619 break;
620 case 1:
621 local_tempo = tempo2;
622 break ;
623
624 case 2:
625 local_tempo = tempo3;
626 break;
627
628 default:
629 break;
630 }
631 /* msleep(local_tempo); */
632 return local_tempo;
633 }
634
635 static enum
636 stv0367_ter_signal_type stv0367ter_check_syr(struct stv0367_state *state)
637 {
638 int wd = 100;
639 unsigned short int SYR_var;
640 s32 SYRStatus;
641
642 dprintk("%s:\n", __func__);
643
644 SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK);
645
646 while ((!SYR_var) && (wd > 0)) {
647 usleep_range(2000, 3000);
648 wd -= 2;
649 SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK);
650 }
651
652 if (!SYR_var)
653 SYRStatus = FE_TER_NOSYMBOL;
654 else
655 SYRStatus = FE_TER_SYMBOLOK;
656
657 dprintk("stv0367ter_check_syr SYRStatus %s\n",
658 SYR_var == 0 ? "No Symbol" : "OK");
659
660 return SYRStatus;
661 }
662
663 static enum
664 stv0367_ter_signal_type stv0367ter_check_cpamp(struct stv0367_state *state,
665 s32 FFTmode)
666 {
667
668 s32 CPAMPvalue = 0, CPAMPStatus, CPAMPMin;
669 int wd = 0;
670
671 dprintk("%s:\n", __func__);
672
673 switch (FFTmode) {
674 case 0: /*2k mode*/
675 CPAMPMin = 20;
676 wd = 10;
677 break;
678 case 1: /*8k mode*/
679 CPAMPMin = 80;
680 wd = 55;
681 break;
682 case 2: /*4k mode*/
683 CPAMPMin = 40;
684 wd = 30;
685 break;
686 default:
687 CPAMPMin = 0xffff; /*drives to NOCPAMP */
688 break;
689 }
690
691 dprintk("%s: CPAMPMin=%d wd=%d\n", __func__, CPAMPMin, wd);
692
693 CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT);
694 while ((CPAMPvalue < CPAMPMin) && (wd > 0)) {
695 usleep_range(1000, 2000);
696 wd -= 1;
697 CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT);
698 /*dprintk("CPAMPvalue= %d at wd=%d\n",CPAMPvalue,wd); */
699 }
700 dprintk("******last CPAMPvalue= %d at wd=%d\n", CPAMPvalue, wd);
701 if (CPAMPvalue < CPAMPMin) {
702 CPAMPStatus = FE_TER_NOCPAMP;
703 dprintk("%s: CPAMP failed\n", __func__);
704 } else {
705 dprintk("%s: CPAMP OK !\n", __func__);
706 CPAMPStatus = FE_TER_CPAMPOK;
707 }
708
709 return CPAMPStatus;
710 }
711
712 static enum stv0367_ter_signal_type
713 stv0367ter_lock_algo(struct stv0367_state *state)
714 {
715 enum stv0367_ter_signal_type ret_flag;
716 short int wd, tempo;
717 u8 try, u_var1 = 0, u_var2 = 0, u_var3 = 0, u_var4 = 0, mode, guard;
718 u8 tmp, tmp2;
719
720 dprintk("%s:\n", __func__);
721
722 if (state == NULL)
723 return FE_TER_SWNOK;
724
725 try = 0;
726 do {
727 ret_flag = FE_TER_LOCKOK;
728
729 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
730
731 if (state->config->if_iq_mode != 0)
732 stv0367_writebits(state, F367TER_COM_N, 0x07);
733
734 stv0367_writebits(state, F367TER_GUARD, 3);/* suggest 2k 1/4 */
735 stv0367_writebits(state, F367TER_MODE, 0);
736 stv0367_writebits(state, F367TER_SYR_TR_DIS, 0);
737 usleep_range(5000, 10000);
738
739 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
740
741
742 if (stv0367ter_check_syr(state) == FE_TER_NOSYMBOL)
743 return FE_TER_NOSYMBOL;
744 else { /*
745 if chip locked on wrong mode first try,
746 it must lock correctly second try */
747 mode = stv0367_readbits(state, F367TER_SYR_MODE);
748 if (stv0367ter_check_cpamp(state, mode) ==
749 FE_TER_NOCPAMP) {
750 if (try == 0)
751 ret_flag = FE_TER_NOCPAMP;
752
753 }
754 }
755
756 try++;
757 } while ((try < 10) && (ret_flag != FE_TER_LOCKOK));
758
759 tmp = stv0367_readreg(state, R367TER_SYR_STAT);
760 tmp2 = stv0367_readreg(state, R367TER_STATUS);
761 dprintk("state=%p\n", state);
762 dprintk("LOCK OK! mode=%d SYR_STAT=0x%x R367TER_STATUS=0x%x\n",
763 mode, tmp, tmp2);
764
765 tmp = stv0367_readreg(state, R367TER_PRVIT);
766 tmp2 = stv0367_readreg(state, R367TER_I2CRPT);
767 dprintk("PRVIT=0x%x I2CRPT=0x%x\n", tmp, tmp2);
768
769 tmp = stv0367_readreg(state, R367TER_GAIN_SRC1);
770 dprintk("GAIN_SRC1=0x%x\n", tmp);
771
772 if ((mode != 0) && (mode != 1) && (mode != 2))
773 return FE_TER_SWNOK;
774
775 /*guard=stv0367_readbits(state,F367TER_SYR_GUARD); */
776
777 /*suppress EPQ auto for SYR_GARD 1/16 or 1/32
778 and set channel predictor in automatic */
779 #if 0
780 switch (guard) {
781
782 case 0:
783 case 1:
784 stv0367_writebits(state, F367TER_AUTO_LE_EN, 0);
785 stv0367_writereg(state, R367TER_CHC_CTL, 0x01);
786 break;
787 case 2:
788 case 3:
789 stv0367_writebits(state, F367TER_AUTO_LE_EN, 1);
790 stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
791 break;
792
793 default:
794 return FE_TER_SWNOK;
795 }
796 #endif
797
798 /*reset fec an reedsolo FOR 367 only*/
799 stv0367_writebits(state, F367TER_RST_SFEC, 1);
800 stv0367_writebits(state, F367TER_RST_REEDSOLO, 1);
801 usleep_range(1000, 2000);
802 stv0367_writebits(state, F367TER_RST_SFEC, 0);
803 stv0367_writebits(state, F367TER_RST_REEDSOLO, 0);
804
805 u_var1 = stv0367_readbits(state, F367TER_LK);
806 u_var2 = stv0367_readbits(state, F367TER_PRF);
807 u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK);
808 /* u_var4=stv0367_readbits(state,F367TER_TSFIFO_LINEOK); */
809
810 wd = stv0367ter_duration(mode, 125, 500, 250);
811 tempo = stv0367ter_duration(mode, 4, 16, 8);
812
813 /*while ( ((!u_var1)||(!u_var2)||(!u_var3)||(!u_var4)) && (wd>=0)) */
814 while (((!u_var1) || (!u_var2) || (!u_var3)) && (wd >= 0)) {
815 usleep_range(1000 * tempo, 1000 * (tempo + 1));
816 wd -= tempo;
817 u_var1 = stv0367_readbits(state, F367TER_LK);
818 u_var2 = stv0367_readbits(state, F367TER_PRF);
819 u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK);
820 /*u_var4=stv0367_readbits(state, F367TER_TSFIFO_LINEOK); */
821 }
822
823 if (!u_var1)
824 return FE_TER_NOLOCK;
825
826
827 if (!u_var2)
828 return FE_TER_NOPRFOUND;
829
830 if (!u_var3)
831 return FE_TER_NOTPS;
832
833 guard = stv0367_readbits(state, F367TER_SYR_GUARD);
834 stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
835 switch (guard) {
836 case 0:
837 case 1:
838 stv0367_writebits(state, F367TER_AUTO_LE_EN, 0);
839 /*stv0367_writereg(state,R367TER_CHC_CTL, 0x1);*/
840 stv0367_writebits(state, F367TER_SYR_FILTER, 0);
841 break;
842 case 2:
843 case 3:
844 stv0367_writebits(state, F367TER_AUTO_LE_EN, 1);
845 /*stv0367_writereg(state,R367TER_CHC_CTL, 0x11);*/
846 stv0367_writebits(state, F367TER_SYR_FILTER, 1);
847 break;
848
849 default:
850 return FE_TER_SWNOK;
851 }
852
853 /* apply Sfec workaround if 8K 64QAM CR!=1/2*/
854 if ((stv0367_readbits(state, F367TER_TPS_CONST) == 2) &&
855 (mode == 1) &&
856 (stv0367_readbits(state, F367TER_TPS_HPCODE) != 0)) {
857 stv0367_writereg(state, R367TER_SFDLYSETH, 0xc0);
858 stv0367_writereg(state, R367TER_SFDLYSETM, 0x60);
859 stv0367_writereg(state, R367TER_SFDLYSETL, 0x0);
860 } else
861 stv0367_writereg(state, R367TER_SFDLYSETH, 0x0);
862
863 wd = stv0367ter_duration(mode, 125, 500, 250);
864 u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK);
865
866 while ((!u_var4) && (wd >= 0)) {
867 usleep_range(1000 * tempo, 1000 * (tempo + 1));
868 wd -= tempo;
869 u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK);
870 }
871
872 if (!u_var4)
873 return FE_TER_NOLOCK;
874
875 /* for 367 leave COM_N at 0x7 for IQ_mode*/
876 /*if(ter_state->if_iq_mode!=FE_TER_NORMAL_IF_TUNER) {
877 tempo=0;
878 while ((stv0367_readbits(state,F367TER_COM_USEGAINTRK)!=1) &&
879 (stv0367_readbits(state,F367TER_COM_AGCLOCK)!=1)&&(tempo<100)) {
880 ChipWaitOrAbort(state,1);
881 tempo+=1;
882 }
883
884 stv0367_writebits(state,F367TER_COM_N,0x17);
885 } */
886
887 stv0367_writebits(state, F367TER_SYR_TR_DIS, 1);
888
889 dprintk("FE_TER_LOCKOK !!!\n");
890
891 return FE_TER_LOCKOK;
892
893 }
894
895 static void stv0367ter_set_ts_mode(struct stv0367_state *state,
896 enum stv0367_ts_mode PathTS)
897 {
898
899 dprintk("%s:\n", __func__);
900
901 if (state == NULL)
902 return;
903
904 stv0367_writebits(state, F367TER_TS_DIS, 0);
905 switch (PathTS) {
906 default:
907 /*for removing warning :default we can assume in parallel mode*/
908 case STV0367_PARALLEL_PUNCT_CLOCK:
909 stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 0);
910 stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 0);
911 break;
912 case STV0367_SERIAL_PUNCT_CLOCK:
913 stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 1);
914 stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 1);
915 break;
916 }
917 }
918
919 static void stv0367ter_set_clk_pol(struct stv0367_state *state,
920 enum stv0367_clk_pol clock)
921 {
922
923 dprintk("%s:\n", __func__);
924
925 if (state == NULL)
926 return;
927
928 switch (clock) {
929 case STV0367_RISINGEDGE_CLOCK:
930 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 1);
931 break;
932 case STV0367_FALLINGEDGE_CLOCK:
933 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0);
934 break;
935 /*case FE_TER_CLOCK_POLARITY_DEFAULT:*/
936 default:
937 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0);
938 break;
939 }
940 }
941
942 #if 0
943 static void stv0367ter_core_sw(struct stv0367_state *state)
944 {
945
946 dprintk("%s:\n", __func__);
947
948 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
949 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
950 msleep(350);
951 }
952 #endif
953 static int stv0367ter_standby(struct dvb_frontend *fe, u8 standby_on)
954 {
955 struct stv0367_state *state = fe->demodulator_priv;
956
957 dprintk("%s:\n", __func__);
958
959 if (standby_on) {
960 stv0367_writebits(state, F367TER_STDBY, 1);
961 stv0367_writebits(state, F367TER_STDBY_FEC, 1);
962 stv0367_writebits(state, F367TER_STDBY_CORE, 1);
963 } else {
964 stv0367_writebits(state, F367TER_STDBY, 0);
965 stv0367_writebits(state, F367TER_STDBY_FEC, 0);
966 stv0367_writebits(state, F367TER_STDBY_CORE, 0);
967 }
968
969 return 0;
970 }
971
972 static int stv0367ter_sleep(struct dvb_frontend *fe)
973 {
974 return stv0367ter_standby(fe, 1);
975 }
976
977 static int stv0367ter_init(struct dvb_frontend *fe)
978 {
979 struct stv0367_state *state = fe->demodulator_priv;
980 struct stv0367ter_state *ter_state = state->ter_state;
981
982 dprintk("%s:\n", __func__);
983
984 ter_state->pBER = 0;
985
986 stv0367_write_table(state,
987 stv0367_deftabs[state->deftabs][STV0367_TAB_TER]);
988
989 stv0367_pll_setup(state, STV0367_ICSPEED_53125, state->config->xtal);
990
991 stv0367_writereg(state, R367TER_I2CRPT, 0xa0);
992 stv0367_writereg(state, R367TER_ANACTRL, 0x00);
993
994 /*Set TS1 and TS2 to serial or parallel mode */
995 stv0367ter_set_ts_mode(state, state->config->ts_mode);
996 stv0367ter_set_clk_pol(state, state->config->clk_pol);
997
998 state->chip_id = stv0367_readreg(state, R367TER_ID);
999 ter_state->first_lock = 0;
1000 ter_state->unlock_counter = 2;
1001
1002 return 0;
1003 }
1004
1005 static int stv0367ter_algo(struct dvb_frontend *fe)
1006 {
1007 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1008 struct stv0367_state *state = fe->demodulator_priv;
1009 struct stv0367ter_state *ter_state = state->ter_state;
1010 int offset = 0, tempo = 0;
1011 u8 u_var;
1012 u8 /*constell,*/ counter;
1013 s8 step;
1014 s32 timing_offset = 0;
1015 u32 trl_nomrate = 0, InternalFreq = 0, temp = 0, ifkhz = 0;
1016
1017 dprintk("%s:\n", __func__);
1018
1019 stv0367_get_if_khz(state, &ifkhz);
1020
1021 ter_state->frequency = p->frequency;
1022 ter_state->force = FE_TER_FORCENONE
1023 + stv0367_readbits(state, F367TER_FORCE) * 2;
1024 ter_state->if_iq_mode = state->config->if_iq_mode;
1025 switch (state->config->if_iq_mode) {
1026 case FE_TER_NORMAL_IF_TUNER: /* Normal IF mode */
1027 dprintk("ALGO: FE_TER_NORMAL_IF_TUNER selected\n");
1028 stv0367_writebits(state, F367TER_TUNER_BB, 0);
1029 stv0367_writebits(state, F367TER_LONGPATH_IF, 0);
1030 stv0367_writebits(state, F367TER_DEMUX_SWAP, 0);
1031 break;
1032 case FE_TER_LONGPATH_IF_TUNER: /* Long IF mode */
1033 dprintk("ALGO: FE_TER_LONGPATH_IF_TUNER selected\n");
1034 stv0367_writebits(state, F367TER_TUNER_BB, 0);
1035 stv0367_writebits(state, F367TER_LONGPATH_IF, 1);
1036 stv0367_writebits(state, F367TER_DEMUX_SWAP, 1);
1037 break;
1038 case FE_TER_IQ_TUNER: /* IQ mode */
1039 dprintk("ALGO: FE_TER_IQ_TUNER selected\n");
1040 stv0367_writebits(state, F367TER_TUNER_BB, 1);
1041 stv0367_writebits(state, F367TER_PPM_INVSEL, 0);
1042 break;
1043 default:
1044 printk(KERN_ERR "ALGO: wrong TUNER type selected\n");
1045 return -EINVAL;
1046 }
1047
1048 usleep_range(5000, 7000);
1049
1050 switch (p->inversion) {
1051 case INVERSION_AUTO:
1052 default:
1053 dprintk("%s: inversion AUTO\n", __func__);
1054 if (ter_state->if_iq_mode == FE_TER_IQ_TUNER)
1055 stv0367_writebits(state, F367TER_IQ_INVERT,
1056 ter_state->sense);
1057 else
1058 stv0367_writebits(state, F367TER_INV_SPECTR,
1059 ter_state->sense);
1060
1061 break;
1062 case INVERSION_ON:
1063 case INVERSION_OFF:
1064 if (ter_state->if_iq_mode == FE_TER_IQ_TUNER)
1065 stv0367_writebits(state, F367TER_IQ_INVERT,
1066 p->inversion);
1067 else
1068 stv0367_writebits(state, F367TER_INV_SPECTR,
1069 p->inversion);
1070
1071 break;
1072 }
1073
1074 if ((ter_state->if_iq_mode != FE_TER_NORMAL_IF_TUNER) &&
1075 (ter_state->pBW != ter_state->bw)) {
1076 stv0367ter_agc_iir_lock_detect_set(state);
1077
1078 /*set fine agc target to 180 for LPIF or IQ mode*/
1079 /* set Q_AGCTarget */
1080 stv0367_writebits(state, F367TER_SEL_IQNTAR, 1);
1081 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB);
1082 /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */
1083
1084 /* set Q_AGCTarget */
1085 stv0367_writebits(state, F367TER_SEL_IQNTAR, 0);
1086 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB);
1087 /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */
1088
1089 if (!stv0367_iir_filt_init(state, ter_state->bw,
1090 state->config->xtal))
1091 return -EINVAL;
1092 /*set IIR filter once for 6,7 or 8MHz BW*/
1093 ter_state->pBW = ter_state->bw;
1094
1095 stv0367ter_agc_iir_rst(state);
1096 }
1097
1098 if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO)
1099 stv0367_writebits(state, F367TER_BDI_LPSEL, 0x01);
1100 else
1101 stv0367_writebits(state, F367TER_BDI_LPSEL, 0x00);
1102
1103 InternalFreq = stv0367ter_get_mclk(state, state->config->xtal) / 1000;
1104 temp = (int)
1105 ((((ter_state->bw * 64 * (1 << 15) * 100)
1106 / (InternalFreq)) * 10) / 7);
1107
1108 stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB, temp % 2);
1109 temp = temp / 2;
1110 stv0367_writebits(state, F367TER_TRL_NOMRATE_HI, temp / 256);
1111 stv0367_writebits(state, F367TER_TRL_NOMRATE_LO, temp % 256);
1112
1113 temp = stv0367_readbits(state, F367TER_TRL_NOMRATE_HI) * 512 +
1114 stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2 +
1115 stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB);
1116 temp = (int)(((1 << 17) * ter_state->bw * 1000) / (7 * (InternalFreq)));
1117 stv0367_writebits(state, F367TER_GAIN_SRC_HI, temp / 256);
1118 stv0367_writebits(state, F367TER_GAIN_SRC_LO, temp % 256);
1119 temp = stv0367_readbits(state, F367TER_GAIN_SRC_HI) * 256 +
1120 stv0367_readbits(state, F367TER_GAIN_SRC_LO);
1121
1122 temp = (int)
1123 ((InternalFreq - ifkhz) * (1 << 16) / (InternalFreq));
1124
1125 dprintk("DEROT temp=0x%x\n", temp);
1126 stv0367_writebits(state, F367TER_INC_DEROT_HI, temp / 256);
1127 stv0367_writebits(state, F367TER_INC_DEROT_LO, temp % 256);
1128
1129 ter_state->echo_pos = 0;
1130 ter_state->ucblocks = 0; /* liplianin */
1131 ter_state->pBER = 0; /* liplianin */
1132 stv0367_writebits(state, F367TER_LONG_ECHO, ter_state->echo_pos);
1133
1134 if (stv0367ter_lock_algo(state) != FE_TER_LOCKOK)
1135 return 0;
1136
1137 ter_state->state = FE_TER_LOCKOK;
1138
1139 ter_state->mode = stv0367_readbits(state, F367TER_SYR_MODE);
1140 ter_state->guard = stv0367_readbits(state, F367TER_SYR_GUARD);
1141
1142 ter_state->first_lock = 1; /* we know sense now :) */
1143
1144 ter_state->agc_val =
1145 (stv0367_readbits(state, F367TER_AGC1_VAL_LO) << 16) +
1146 (stv0367_readbits(state, F367TER_AGC1_VAL_HI) << 24) +
1147 stv0367_readbits(state, F367TER_AGC2_VAL_LO) +
1148 (stv0367_readbits(state, F367TER_AGC2_VAL_HI) << 8);
1149
1150 /* Carrier offset calculation */
1151 stv0367_writebits(state, F367TER_FREEZE, 1);
1152 offset = (stv0367_readbits(state, F367TER_CRL_FOFFSET_VHI) << 16) ;
1153 offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_HI) << 8);
1154 offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_LO));
1155 stv0367_writebits(state, F367TER_FREEZE, 0);
1156 if (offset > 8388607)
1157 offset -= 16777216;
1158
1159 offset = offset * 2 / 16384;
1160
1161 if (ter_state->mode == FE_TER_MODE_2K)
1162 offset = (offset * 4464) / 1000;/*** 1 FFT BIN=4.464khz***/
1163 else if (ter_state->mode == FE_TER_MODE_4K)
1164 offset = (offset * 223) / 100;/*** 1 FFT BIN=2.23khz***/
1165 else if (ter_state->mode == FE_TER_MODE_8K)
1166 offset = (offset * 111) / 100;/*** 1 FFT BIN=1.1khz***/
1167
1168 if (stv0367_readbits(state, F367TER_PPM_INVSEL) == 1) {
1169 if ((stv0367_readbits(state, F367TER_INV_SPECTR) ==
1170 (stv0367_readbits(state,
1171 F367TER_STATUS_INV_SPECRUM) == 1)))
1172 offset = offset * -1;
1173 }
1174
1175 if (ter_state->bw == 6)
1176 offset = (offset * 6) / 8;
1177 else if (ter_state->bw == 7)
1178 offset = (offset * 7) / 8;
1179
1180 ter_state->frequency += offset;
1181
1182 tempo = 10; /* exit even if timing_offset stays null */
1183 while ((timing_offset == 0) && (tempo > 0)) {
1184 usleep_range(10000, 20000); /*was 20ms */
1185 /* fine tuning of timing offset if required */
1186 timing_offset = stv0367_readbits(state, F367TER_TRL_TOFFSET_LO)
1187 + 256 * stv0367_readbits(state,
1188 F367TER_TRL_TOFFSET_HI);
1189 if (timing_offset >= 32768)
1190 timing_offset -= 65536;
1191 trl_nomrate = (512 * stv0367_readbits(state,
1192 F367TER_TRL_NOMRATE_HI)
1193 + stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2
1194 + stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB));
1195
1196 timing_offset = ((signed)(1000000 / trl_nomrate) *
1197 timing_offset) / 2048;
1198 tempo--;
1199 }
1200
1201 if (timing_offset <= 0) {
1202 timing_offset = (timing_offset - 11) / 22;
1203 step = -1;
1204 } else {
1205 timing_offset = (timing_offset + 11) / 22;
1206 step = 1;
1207 }
1208
1209 for (counter = 0; counter < abs(timing_offset); counter++) {
1210 trl_nomrate += step;
1211 stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB,
1212 trl_nomrate % 2);
1213 stv0367_writebits(state, F367TER_TRL_NOMRATE_LO,
1214 trl_nomrate / 2);
1215 usleep_range(1000, 2000);
1216 }
1217
1218 usleep_range(5000, 6000);
1219 /* unlocks could happen in case of trl centring big step,
1220 then a core off/on restarts demod */
1221 u_var = stv0367_readbits(state, F367TER_LK);
1222
1223 if (!u_var) {
1224 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
1225 msleep(20);
1226 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
1227 }
1228
1229 return 0;
1230 }
1231
1232 static int stv0367ter_set_frontend(struct dvb_frontend *fe)
1233 {
1234 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1235 struct stv0367_state *state = fe->demodulator_priv;
1236 struct stv0367ter_state *ter_state = state->ter_state;
1237
1238 /*u8 trials[2]; */
1239 s8 num_trials, index;
1240 u8 SenseTrials[] = { INVERSION_ON, INVERSION_OFF };
1241
1242 if (state->reinit_on_setfrontend)
1243 stv0367ter_init(fe);
1244
1245 if (fe->ops.tuner_ops.set_params) {
1246 if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
1247 fe->ops.i2c_gate_ctrl(fe, 1);
1248 fe->ops.tuner_ops.set_params(fe);
1249 if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
1250 fe->ops.i2c_gate_ctrl(fe, 0);
1251 }
1252
1253 switch (p->transmission_mode) {
1254 default:
1255 case TRANSMISSION_MODE_AUTO:
1256 case TRANSMISSION_MODE_2K:
1257 ter_state->mode = FE_TER_MODE_2K;
1258 break;
1259 /* case TRANSMISSION_MODE_4K:
1260 pLook.mode = FE_TER_MODE_4K;
1261 break;*/
1262 case TRANSMISSION_MODE_8K:
1263 ter_state->mode = FE_TER_MODE_8K;
1264 break;
1265 }
1266
1267 switch (p->guard_interval) {
1268 default:
1269 case GUARD_INTERVAL_1_32:
1270 case GUARD_INTERVAL_1_16:
1271 case GUARD_INTERVAL_1_8:
1272 case GUARD_INTERVAL_1_4:
1273 ter_state->guard = p->guard_interval;
1274 break;
1275 case GUARD_INTERVAL_AUTO:
1276 ter_state->guard = GUARD_INTERVAL_1_32;
1277 break;
1278 }
1279
1280 switch (p->bandwidth_hz) {
1281 case 6000000:
1282 ter_state->bw = FE_TER_CHAN_BW_6M;
1283 break;
1284 case 7000000:
1285 ter_state->bw = FE_TER_CHAN_BW_7M;
1286 break;
1287 case 8000000:
1288 default:
1289 ter_state->bw = FE_TER_CHAN_BW_8M;
1290 }
1291
1292 ter_state->hierarchy = FE_TER_HIER_NONE;
1293
1294 switch (p->inversion) {
1295 case INVERSION_OFF:
1296 case INVERSION_ON:
1297 num_trials = 1;
1298 break;
1299 default:
1300 num_trials = 2;
1301 if (ter_state->first_lock)
1302 num_trials = 1;
1303 break;
1304 }
1305
1306 ter_state->state = FE_TER_NOLOCK;
1307 index = 0;
1308
1309 while (((index) < num_trials) && (ter_state->state != FE_TER_LOCKOK)) {
1310 if (!ter_state->first_lock) {
1311 if (p->inversion == INVERSION_AUTO)
1312 ter_state->sense = SenseTrials[index];
1313
1314 }
1315 stv0367ter_algo(fe);
1316
1317 if ((ter_state->state == FE_TER_LOCKOK) &&
1318 (p->inversion == INVERSION_AUTO) &&
1319 (index == 1)) {
1320 /* invert spectrum sense */
1321 SenseTrials[index] = SenseTrials[0];
1322 SenseTrials[(index + 1) % 2] = (SenseTrials[1] + 1) % 2;
1323 }
1324
1325 index++;
1326 }
1327
1328 return 0;
1329 }
1330
1331 static int stv0367ter_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1332 {
1333 struct stv0367_state *state = fe->demodulator_priv;
1334 struct stv0367ter_state *ter_state = state->ter_state;
1335 u32 errs = 0;
1336
1337 /*wait for counting completion*/
1338 if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0) {
1339 errs =
1340 ((u32)stv0367_readbits(state, F367TER_ERR_CNT1)
1341 * (1 << 16))
1342 + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI)
1343 * (1 << 8))
1344 + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO));
1345 ter_state->ucblocks = errs;
1346 }
1347
1348 (*ucblocks) = ter_state->ucblocks;
1349
1350 return 0;
1351 }
1352
1353 static int stv0367ter_get_frontend(struct dvb_frontend *fe,
1354 struct dtv_frontend_properties *p)
1355 {
1356 struct stv0367_state *state = fe->demodulator_priv;
1357 struct stv0367ter_state *ter_state = state->ter_state;
1358 enum stv0367_ter_mode mode;
1359 int constell = 0,/* snr = 0,*/ Data = 0;
1360
1361 p->frequency = stv0367_get_tuner_freq(fe);
1362 if ((int)p->frequency < 0)
1363 p->frequency = -p->frequency;
1364
1365 constell = stv0367_readbits(state, F367TER_TPS_CONST);
1366 if (constell == 0)
1367 p->modulation = QPSK;
1368 else if (constell == 1)
1369 p->modulation = QAM_16;
1370 else
1371 p->modulation = QAM_64;
1372
1373 p->inversion = stv0367_readbits(state, F367TER_INV_SPECTR);
1374
1375 /* Get the Hierarchical mode */
1376 Data = stv0367_readbits(state, F367TER_TPS_HIERMODE);
1377
1378 switch (Data) {
1379 case 0:
1380 p->hierarchy = HIERARCHY_NONE;
1381 break;
1382 case 1:
1383 p->hierarchy = HIERARCHY_1;
1384 break;
1385 case 2:
1386 p->hierarchy = HIERARCHY_2;
1387 break;
1388 case 3:
1389 p->hierarchy = HIERARCHY_4;
1390 break;
1391 default:
1392 p->hierarchy = HIERARCHY_AUTO;
1393 break; /* error */
1394 }
1395
1396 /* Get the FEC Rate */
1397 if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO)
1398 Data = stv0367_readbits(state, F367TER_TPS_LPCODE);
1399 else
1400 Data = stv0367_readbits(state, F367TER_TPS_HPCODE);
1401
1402 switch (Data) {
1403 case 0:
1404 p->code_rate_HP = FEC_1_2;
1405 break;
1406 case 1:
1407 p->code_rate_HP = FEC_2_3;
1408 break;
1409 case 2:
1410 p->code_rate_HP = FEC_3_4;
1411 break;
1412 case 3:
1413 p->code_rate_HP = FEC_5_6;
1414 break;
1415 case 4:
1416 p->code_rate_HP = FEC_7_8;
1417 break;
1418 default:
1419 p->code_rate_HP = FEC_AUTO;
1420 break; /* error */
1421 }
1422
1423 mode = stv0367_readbits(state, F367TER_SYR_MODE);
1424
1425 switch (mode) {
1426 case FE_TER_MODE_2K:
1427 p->transmission_mode = TRANSMISSION_MODE_2K;
1428 break;
1429 /* case FE_TER_MODE_4K:
1430 p->transmission_mode = TRANSMISSION_MODE_4K;
1431 break;*/
1432 case FE_TER_MODE_8K:
1433 p->transmission_mode = TRANSMISSION_MODE_8K;
1434 break;
1435 default:
1436 p->transmission_mode = TRANSMISSION_MODE_AUTO;
1437 }
1438
1439 p->guard_interval = stv0367_readbits(state, F367TER_SYR_GUARD);
1440
1441 return 0;
1442 }
1443
1444 static u32 stv0367ter_snr_readreg(struct dvb_frontend *fe)
1445 {
1446 struct stv0367_state *state = fe->demodulator_priv;
1447 u32 snru32 = 0;
1448 int cpt = 0;
1449 u8 cut = stv0367_readbits(state, F367TER_IDENTIFICATIONREG);
1450
1451 while (cpt < 10) {
1452 usleep_range(2000, 3000);
1453 if (cut == 0x50) /*cut 1.0 cut 1.1*/
1454 snru32 += stv0367_readbits(state, F367TER_CHCSNR) / 4;
1455 else /*cu2.0*/
1456 snru32 += 125 * stv0367_readbits(state, F367TER_CHCSNR);
1457
1458 cpt++;
1459 }
1460 snru32 /= 10;/*average on 10 values*/
1461
1462 return snru32;
1463 }
1464
1465 static int stv0367ter_read_snr(struct dvb_frontend *fe, u16 *snr)
1466 {
1467 u32 snrval = stv0367ter_snr_readreg(fe);
1468
1469 *snr = snrval / 1000;
1470
1471 return 0;
1472 }
1473
1474 #if 0
1475 static int stv0367ter_status(struct dvb_frontend *fe)
1476 {
1477
1478 struct stv0367_state *state = fe->demodulator_priv;
1479 struct stv0367ter_state *ter_state = state->ter_state;
1480 int locked = FALSE;
1481
1482 locked = (stv0367_readbits(state, F367TER_LK));
1483 if (!locked)
1484 ter_state->unlock_counter += 1;
1485 else
1486 ter_state->unlock_counter = 0;
1487
1488 if (ter_state->unlock_counter > 2) {
1489 if (!stv0367_readbits(state, F367TER_TPS_LOCK) ||
1490 (!stv0367_readbits(state, F367TER_LK))) {
1491 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
1492 usleep_range(2000, 3000);
1493 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
1494 msleep(350);
1495 locked = (stv0367_readbits(state, F367TER_TPS_LOCK)) &&
1496 (stv0367_readbits(state, F367TER_LK));
1497 }
1498
1499 }
1500
1501 return locked;
1502 }
1503 #endif
1504 static int stv0367ter_read_status(struct dvb_frontend *fe,
1505 enum fe_status *status)
1506 {
1507 struct stv0367_state *state = fe->demodulator_priv;
1508
1509 dprintk("%s:\n", __func__);
1510
1511 *status = 0;
1512
1513 if (stv0367_readbits(state, F367TER_LK)) {
1514 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI
1515 | FE_HAS_SYNC | FE_HAS_LOCK;
1516 dprintk("%s: stv0367 has locked\n", __func__);
1517 }
1518
1519 return 0;
1520 }
1521
1522 static int stv0367ter_read_ber(struct dvb_frontend *fe, u32 *ber)
1523 {
1524 struct stv0367_state *state = fe->demodulator_priv;
1525 struct stv0367ter_state *ter_state = state->ter_state;
1526 u32 Errors = 0, tber = 0, temporary = 0;
1527 int abc = 0, def = 0;
1528
1529
1530 /*wait for counting completion*/
1531 if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0)
1532 Errors = ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT)
1533 * (1 << 16))
1534 + ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT_HI)
1535 * (1 << 8))
1536 + ((u32)stv0367_readbits(state,
1537 F367TER_SFEC_ERR_CNT_LO));
1538 /*measurement not completed, load previous value*/
1539 else {
1540 tber = ter_state->pBER;
1541 return 0;
1542 }
1543
1544 abc = stv0367_readbits(state, F367TER_SFEC_ERR_SOURCE);
1545 def = stv0367_readbits(state, F367TER_SFEC_NUM_EVENT);
1546
1547 if (Errors == 0) {
1548 tber = 0;
1549 } else if (abc == 0x7) {
1550 if (Errors <= 4) {
1551 temporary = (Errors * 1000000000) / (8 * (1 << 14));
1552 } else if (Errors <= 42) {
1553 temporary = (Errors * 100000000) / (8 * (1 << 14));
1554 temporary = temporary * 10;
1555 } else if (Errors <= 429) {
1556 temporary = (Errors * 10000000) / (8 * (1 << 14));
1557 temporary = temporary * 100;
1558 } else if (Errors <= 4294) {
1559 temporary = (Errors * 1000000) / (8 * (1 << 14));
1560 temporary = temporary * 1000;
1561 } else if (Errors <= 42949) {
1562 temporary = (Errors * 100000) / (8 * (1 << 14));
1563 temporary = temporary * 10000;
1564 } else if (Errors <= 429496) {
1565 temporary = (Errors * 10000) / (8 * (1 << 14));
1566 temporary = temporary * 100000;
1567 } else { /*if (Errors<4294967) 2^22 max error*/
1568 temporary = (Errors * 1000) / (8 * (1 << 14));
1569 temporary = temporary * 100000; /* still to *10 */
1570 }
1571
1572 /* Byte error*/
1573 if (def == 2)
1574 /*tber=Errors/(8*(1 <<14));*/
1575 tber = temporary;
1576 else if (def == 3)
1577 /*tber=Errors/(8*(1 <<16));*/
1578 tber = temporary / 4;
1579 else if (def == 4)
1580 /*tber=Errors/(8*(1 <<18));*/
1581 tber = temporary / 16;
1582 else if (def == 5)
1583 /*tber=Errors/(8*(1 <<20));*/
1584 tber = temporary / 64;
1585 else if (def == 6)
1586 /*tber=Errors/(8*(1 <<22));*/
1587 tber = temporary / 256;
1588 else
1589 /* should not pass here*/
1590 tber = 0;
1591
1592 if ((Errors < 4294967) && (Errors > 429496))
1593 tber *= 10;
1594
1595 }
1596
1597 /* save actual value */
1598 ter_state->pBER = tber;
1599
1600 (*ber) = tber;
1601
1602 return 0;
1603 }
1604 #if 0
1605 static u32 stv0367ter_get_per(struct stv0367_state *state)
1606 {
1607 struct stv0367ter_state *ter_state = state->ter_state;
1608 u32 Errors = 0, Per = 0, temporary = 0;
1609 int abc = 0, def = 0, cpt = 0;
1610
1611 while (((stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 1) &&
1612 (cpt < 400)) || ((Errors == 0) && (cpt < 400))) {
1613 usleep_range(1000, 2000);
1614 Errors = ((u32)stv0367_readbits(state, F367TER_ERR_CNT1)
1615 * (1 << 16))
1616 + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI)
1617 * (1 << 8))
1618 + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO));
1619 cpt++;
1620 }
1621 abc = stv0367_readbits(state, F367TER_ERR_SRC1);
1622 def = stv0367_readbits(state, F367TER_NUM_EVT1);
1623
1624 if (Errors == 0)
1625 Per = 0;
1626 else if (abc == 0x9) {
1627 if (Errors <= 4) {
1628 temporary = (Errors * 1000000000) / (8 * (1 << 8));
1629 } else if (Errors <= 42) {
1630 temporary = (Errors * 100000000) / (8 * (1 << 8));
1631 temporary = temporary * 10;
1632 } else if (Errors <= 429) {
1633 temporary = (Errors * 10000000) / (8 * (1 << 8));
1634 temporary = temporary * 100;
1635 } else if (Errors <= 4294) {
1636 temporary = (Errors * 1000000) / (8 * (1 << 8));
1637 temporary = temporary * 1000;
1638 } else if (Errors <= 42949) {
1639 temporary = (Errors * 100000) / (8 * (1 << 8));
1640 temporary = temporary * 10000;
1641 } else { /*if(Errors<=429496) 2^16 errors max*/
1642 temporary = (Errors * 10000) / (8 * (1 << 8));
1643 temporary = temporary * 100000;
1644 }
1645
1646 /* pkt error*/
1647 if (def == 2)
1648 /*Per=Errors/(1 << 8);*/
1649 Per = temporary;
1650 else if (def == 3)
1651 /*Per=Errors/(1 << 10);*/
1652 Per = temporary / 4;
1653 else if (def == 4)
1654 /*Per=Errors/(1 << 12);*/
1655 Per = temporary / 16;
1656 else if (def == 5)
1657 /*Per=Errors/(1 << 14);*/
1658 Per = temporary / 64;
1659 else if (def == 6)
1660 /*Per=Errors/(1 << 16);*/
1661 Per = temporary / 256;
1662 else
1663 Per = 0;
1664
1665 }
1666 /* save actual value */
1667 ter_state->pPER = Per;
1668
1669 return Per;
1670 }
1671 #endif
1672 static int stv0367_get_tune_settings(struct dvb_frontend *fe,
1673 struct dvb_frontend_tune_settings
1674 *fe_tune_settings)
1675 {
1676 fe_tune_settings->min_delay_ms = 1000;
1677 fe_tune_settings->step_size = 0;
1678 fe_tune_settings->max_drift = 0;
1679
1680 return 0;
1681 }
1682
1683 static void stv0367_release(struct dvb_frontend *fe)
1684 {
1685 struct stv0367_state *state = fe->demodulator_priv;
1686
1687 kfree(state->ter_state);
1688 kfree(state->cab_state);
1689 kfree(state);
1690 }
1691
1692 static const struct dvb_frontend_ops stv0367ter_ops = {
1693 .delsys = { SYS_DVBT },
1694 .info = {
1695 .name = "ST STV0367 DVB-T",
1696 .frequency_min = 47000000,
1697 .frequency_max = 862000000,
1698 .frequency_stepsize = 15625,
1699 .frequency_tolerance = 0,
1700 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
1701 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
1702 FE_CAN_FEC_AUTO |
1703 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
1704 FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_QAM_AUTO |
1705 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
1706 FE_CAN_INVERSION_AUTO |
1707 FE_CAN_MUTE_TS
1708 },
1709 .release = stv0367_release,
1710 .init = stv0367ter_init,
1711 .sleep = stv0367ter_sleep,
1712 .i2c_gate_ctrl = stv0367ter_gate_ctrl,
1713 .set_frontend = stv0367ter_set_frontend,
1714 .get_frontend = stv0367ter_get_frontend,
1715 .get_tune_settings = stv0367_get_tune_settings,
1716 .read_status = stv0367ter_read_status,
1717 .read_ber = stv0367ter_read_ber,/* too slow */
1718 /* .read_signal_strength = stv0367_read_signal_strength,*/
1719 .read_snr = stv0367ter_read_snr,
1720 .read_ucblocks = stv0367ter_read_ucblocks,
1721 };
1722
1723 struct dvb_frontend *stv0367ter_attach(const struct stv0367_config *config,
1724 struct i2c_adapter *i2c)
1725 {
1726 struct stv0367_state *state = NULL;
1727 struct stv0367ter_state *ter_state = NULL;
1728
1729 /* allocate memory for the internal state */
1730 state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
1731 if (state == NULL)
1732 goto error;
1733 ter_state = kzalloc(sizeof(struct stv0367ter_state), GFP_KERNEL);
1734 if (ter_state == NULL)
1735 goto error;
1736
1737 /* setup the state */
1738 state->i2c = i2c;
1739 state->config = config;
1740 state->ter_state = ter_state;
1741 state->fe.ops = stv0367ter_ops;
1742 state->fe.demodulator_priv = state;
1743 state->chip_id = stv0367_readreg(state, 0xf000);
1744
1745 /* demod operation options */
1746 state->use_i2c_gatectrl = 1;
1747 state->deftabs = STV0367_DEFTAB_GENERIC;
1748 state->reinit_on_setfrontend = 1;
1749 state->auto_if_khz = 0;
1750
1751 dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
1752
1753 /* check if the demod is there */
1754 if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
1755 goto error;
1756
1757 return &state->fe;
1758
1759 error:
1760 kfree(ter_state);
1761 kfree(state);
1762 return NULL;
1763 }
1764 EXPORT_SYMBOL(stv0367ter_attach);
1765
1766 static int stv0367cab_gate_ctrl(struct dvb_frontend *fe, int enable)
1767 {
1768 struct stv0367_state *state = fe->demodulator_priv;
1769
1770 dprintk("%s:\n", __func__);
1771
1772 stv0367_writebits(state, F367CAB_I2CT_ON, (enable > 0) ? 1 : 0);
1773
1774 return 0;
1775 }
1776
1777 static u32 stv0367cab_get_mclk(struct dvb_frontend *fe, u32 ExtClk_Hz)
1778 {
1779 struct stv0367_state *state = fe->demodulator_priv;
1780 u32 mclk_Hz = 0;/* master clock frequency (Hz) */
1781 u32 M, N, P;
1782
1783
1784 if (stv0367_readbits(state, F367CAB_BYPASS_PLLXN) == 0) {
1785 N = (u32)stv0367_readbits(state, F367CAB_PLL_NDIV);
1786 if (N == 0)
1787 N = N + 1;
1788
1789 M = (u32)stv0367_readbits(state, F367CAB_PLL_MDIV);
1790 if (M == 0)
1791 M = M + 1;
1792
1793 P = (u32)stv0367_readbits(state, F367CAB_PLL_PDIV);
1794
1795 if (P > 5)
1796 P = 5;
1797
1798 mclk_Hz = ((ExtClk_Hz / 2) * N) / (M * (1 << P));
1799 dprintk("stv0367cab_get_mclk BYPASS_PLLXN mclk_Hz=%d\n",
1800 mclk_Hz);
1801 } else
1802 mclk_Hz = ExtClk_Hz;
1803
1804 dprintk("stv0367cab_get_mclk final mclk_Hz=%d\n", mclk_Hz);
1805
1806 return mclk_Hz;
1807 }
1808
1809 static u32 stv0367cab_get_adc_freq(struct dvb_frontend *fe, u32 ExtClk_Hz)
1810 {
1811 u32 ADCClk_Hz = ExtClk_Hz;
1812
1813 ADCClk_Hz = stv0367cab_get_mclk(fe, ExtClk_Hz);
1814
1815 return ADCClk_Hz;
1816 }
1817
1818 static enum stv0367cab_mod stv0367cab_SetQamSize(struct stv0367_state *state,
1819 u32 SymbolRate,
1820 enum stv0367cab_mod QAMSize)
1821 {
1822 /* Set QAM size */
1823 stv0367_writebits(state, F367CAB_QAM_MODE, QAMSize);
1824
1825 /* Set Registers settings specific to the QAM size */
1826 switch (QAMSize) {
1827 case FE_CAB_MOD_QAM4:
1828 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1829 break;
1830 case FE_CAB_MOD_QAM16:
1831 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x64);
1832 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1833 stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
1834 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1835 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
1836 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
1837 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
1838 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x8a);
1839 break;
1840 case FE_CAB_MOD_QAM32:
1841 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1842 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x6e);
1843 stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
1844 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1845 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xb7);
1846 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x9d);
1847 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
1848 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
1849 break;
1850 case FE_CAB_MOD_QAM64:
1851 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x82);
1852 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
1853 if (SymbolRate > 4500000) {
1854 stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
1855 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1856 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa5);
1857 } else if (SymbolRate > 2500000) {
1858 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
1859 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1860 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
1861 } else {
1862 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
1863 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
1864 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
1865 }
1866 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
1867 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
1868 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x99);
1869 break;
1870 case FE_CAB_MOD_QAM128:
1871 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1872 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x76);
1873 stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
1874 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xb1);
1875 if (SymbolRate > 4500000)
1876 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
1877 else if (SymbolRate > 2500000)
1878 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
1879 else
1880 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0x97);
1881
1882 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x8e);
1883 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
1884 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
1885 break;
1886 case FE_CAB_MOD_QAM256:
1887 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x94);
1888 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
1889 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
1890 if (SymbolRate > 4500000)
1891 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1892 else if (SymbolRate > 2500000)
1893 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1894 else
1895 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
1896
1897 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
1898 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x85);
1899 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
1900 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
1901 break;
1902 case FE_CAB_MOD_QAM512:
1903 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1904 break;
1905 case FE_CAB_MOD_QAM1024:
1906 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1907 break;
1908 default:
1909 break;
1910 }
1911
1912 return QAMSize;
1913 }
1914
1915 static u32 stv0367cab_set_derot_freq(struct stv0367_state *state,
1916 u32 adc_hz, s32 derot_hz)
1917 {
1918 u32 sampled_if = 0;
1919 u32 adc_khz;
1920
1921 adc_khz = adc_hz / 1000;
1922
1923 dprintk("%s: adc_hz=%d derot_hz=%d\n", __func__, adc_hz, derot_hz);
1924
1925 if (adc_khz != 0) {
1926 if (derot_hz < 1000000)
1927 derot_hz = adc_hz / 4; /* ZIF operation */
1928 if (derot_hz > adc_hz)
1929 derot_hz = derot_hz - adc_hz;
1930 sampled_if = (u32)derot_hz / 1000;
1931 sampled_if *= 32768;
1932 sampled_if /= adc_khz;
1933 sampled_if *= 256;
1934 }
1935
1936 if (sampled_if > 8388607)
1937 sampled_if = 8388607;
1938
1939 dprintk("%s: sampled_if=0x%x\n", __func__, sampled_if);
1940
1941 stv0367_writereg(state, R367CAB_MIX_NCO_LL, sampled_if);
1942 stv0367_writereg(state, R367CAB_MIX_NCO_HL, (sampled_if >> 8));
1943 stv0367_writebits(state, F367CAB_MIX_NCO_INC_HH, (sampled_if >> 16));
1944
1945 return derot_hz;
1946 }
1947
1948 static u32 stv0367cab_get_derot_freq(struct stv0367_state *state, u32 adc_hz)
1949 {
1950 u32 sampled_if;
1951
1952 sampled_if = stv0367_readbits(state, F367CAB_MIX_NCO_INC_LL) +
1953 (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HL) << 8) +
1954 (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HH) << 16);
1955
1956 sampled_if /= 256;
1957 sampled_if *= (adc_hz / 1000);
1958 sampled_if += 1;
1959 sampled_if /= 32768;
1960
1961 return sampled_if;
1962 }
1963
1964 static u32 stv0367cab_set_srate(struct stv0367_state *state, u32 adc_hz,
1965 u32 mclk_hz, u32 SymbolRate,
1966 enum stv0367cab_mod QAMSize)
1967 {
1968 u32 QamSizeCorr = 0;
1969 u32 u32_tmp = 0, u32_tmp1 = 0;
1970 u32 adp_khz;
1971
1972 dprintk("%s:\n", __func__);
1973
1974 /* Set Correction factor of SRC gain */
1975 switch (QAMSize) {
1976 case FE_CAB_MOD_QAM4:
1977 QamSizeCorr = 1110;
1978 break;
1979 case FE_CAB_MOD_QAM16:
1980 QamSizeCorr = 1032;
1981 break;
1982 case FE_CAB_MOD_QAM32:
1983 QamSizeCorr = 954;
1984 break;
1985 case FE_CAB_MOD_QAM64:
1986 QamSizeCorr = 983;
1987 break;
1988 case FE_CAB_MOD_QAM128:
1989 QamSizeCorr = 957;
1990 break;
1991 case FE_CAB_MOD_QAM256:
1992 QamSizeCorr = 948;
1993 break;
1994 case FE_CAB_MOD_QAM512:
1995 QamSizeCorr = 0;
1996 break;
1997 case FE_CAB_MOD_QAM1024:
1998 QamSizeCorr = 944;
1999 break;
2000 default:
2001 break;
2002 }
2003
2004 /* Transfer ratio calculation */
2005 if (adc_hz != 0) {
2006 u32_tmp = 256 * SymbolRate;
2007 u32_tmp = u32_tmp / adc_hz;
2008 }
2009 stv0367_writereg(state, R367CAB_EQU_CRL_TFR, (u8)u32_tmp);
2010
2011 /* Symbol rate and SRC gain calculation */
2012 adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */
2013 if (adp_khz != 0) {
2014 u32_tmp = SymbolRate;
2015 u32_tmp1 = SymbolRate;
2016
2017 if (u32_tmp < 2097152) { /* 2097152 = 2^21 */
2018 /* Symbol rate calculation */
2019 u32_tmp *= 2048; /* 2048 = 2^11 */
2020 u32_tmp = u32_tmp / adp_khz;
2021 u32_tmp = u32_tmp * 16384; /* 16384 = 2^14 */
2022 u32_tmp /= 125 ; /* 125 = 1000/2^3 */
2023 u32_tmp = u32_tmp * 8; /* 8 = 2^3 */
2024
2025 /* SRC Gain Calculation */
2026 u32_tmp1 *= 2048; /* *2*2^10 */
2027 u32_tmp1 /= 439; /* *2/878 */
2028 u32_tmp1 *= 256; /* *2^8 */
2029 u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2030 u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2031 u32_tmp1 = u32_tmp1 / 10000000;
2032
2033 } else if (u32_tmp < 4194304) { /* 4194304 = 2**22 */
2034 /* Symbol rate calculation */
2035 u32_tmp *= 1024 ; /* 1024 = 2**10 */
2036 u32_tmp = u32_tmp / adp_khz;
2037 u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */
2038 u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2039 u32_tmp = u32_tmp * 16; /* 16 = 2**4 */
2040
2041 /* SRC Gain Calculation */
2042 u32_tmp1 *= 1024; /* *2*2^9 */
2043 u32_tmp1 /= 439; /* *2/878 */
2044 u32_tmp1 *= 256; /* *2^8 */
2045 u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz)*/
2046 u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2047 u32_tmp1 = u32_tmp1 / 5000000;
2048 } else if (u32_tmp < 8388607) { /* 8388607 = 2**23 */
2049 /* Symbol rate calculation */
2050 u32_tmp *= 512 ; /* 512 = 2**9 */
2051 u32_tmp = u32_tmp / adp_khz;
2052 u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */
2053 u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2054 u32_tmp = u32_tmp * 32; /* 32 = 2**5 */
2055
2056 /* SRC Gain Calculation */
2057 u32_tmp1 *= 512; /* *2*2^8 */
2058 u32_tmp1 /= 439; /* *2/878 */
2059 u32_tmp1 *= 256; /* *2^8 */
2060 u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2061 u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2062 u32_tmp1 = u32_tmp1 / 2500000;
2063 } else {
2064 /* Symbol rate calculation */
2065 u32_tmp *= 256 ; /* 256 = 2**8 */
2066 u32_tmp = u32_tmp / adp_khz;
2067 u32_tmp = u32_tmp * 16384; /* 16384 = 2**13 */
2068 u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2069 u32_tmp = u32_tmp * 64; /* 64 = 2**6 */
2070
2071 /* SRC Gain Calculation */
2072 u32_tmp1 *= 256; /* 2*2^7 */
2073 u32_tmp1 /= 439; /* *2/878 */
2074 u32_tmp1 *= 256; /* *2^8 */
2075 u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2076 u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2077 u32_tmp1 = u32_tmp1 / 1250000;
2078 }
2079 }
2080 #if 0
2081 /* Filters' coefficients are calculated and written
2082 into registers only if the filters are enabled */
2083 if (stv0367_readbits(state, F367CAB_ADJ_EN)) {
2084 stv0367cab_SetIirAdjacentcoefficient(state, mclk_hz,
2085 SymbolRate);
2086 /* AllPass filter must be enabled
2087 when the adjacents filter is used */
2088 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 1);
2089 stv0367cab_SetAllPasscoefficient(state, mclk_hz, SymbolRate);
2090 } else
2091 /* AllPass filter must be disabled
2092 when the adjacents filter is not used */
2093 #endif
2094 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0);
2095
2096 stv0367_writereg(state, R367CAB_SRC_NCO_LL, u32_tmp);
2097 stv0367_writereg(state, R367CAB_SRC_NCO_LH, (u32_tmp >> 8));
2098 stv0367_writereg(state, R367CAB_SRC_NCO_HL, (u32_tmp >> 16));
2099 stv0367_writereg(state, R367CAB_SRC_NCO_HH, (u32_tmp >> 24));
2100
2101 stv0367_writereg(state, R367CAB_IQDEM_GAIN_SRC_L, u32_tmp1 & 0x00ff);
2102 stv0367_writebits(state, F367CAB_GAIN_SRC_HI, (u32_tmp1 >> 8) & 0x00ff);
2103
2104 return SymbolRate ;
2105 }
2106
2107 static u32 stv0367cab_GetSymbolRate(struct stv0367_state *state, u32 mclk_hz)
2108 {
2109 u32 regsym;
2110 u32 adp_khz;
2111
2112 regsym = stv0367_readreg(state, R367CAB_SRC_NCO_LL) +
2113 (stv0367_readreg(state, R367CAB_SRC_NCO_LH) << 8) +
2114 (stv0367_readreg(state, R367CAB_SRC_NCO_HL) << 16) +
2115 (stv0367_readreg(state, R367CAB_SRC_NCO_HH) << 24);
2116
2117 adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */
2118
2119 if (regsym < 134217728) { /* 134217728L = 2**27*/
2120 regsym = regsym * 32; /* 32 = 2**5 */
2121 regsym = regsym / 32768; /* 32768L = 2**15 */
2122 regsym = adp_khz * regsym; /* AdpClk in kHz */
2123 regsym = regsym / 128; /* 128 = 2**7 */
2124 regsym *= 125 ; /* 125 = 1000/2**3 */
2125 regsym /= 2048 ; /* 2048 = 2**11 */
2126 } else if (regsym < 268435456) { /* 268435456L = 2**28 */
2127 regsym = regsym * 16; /* 16 = 2**4 */
2128 regsym = regsym / 32768; /* 32768L = 2**15 */
2129 regsym = adp_khz * regsym; /* AdpClk in kHz */
2130 regsym = regsym / 128; /* 128 = 2**7 */
2131 regsym *= 125 ; /* 125 = 1000/2**3*/
2132 regsym /= 1024 ; /* 256 = 2**10*/
2133 } else if (regsym < 536870912) { /* 536870912L = 2**29*/
2134 regsym = regsym * 8; /* 8 = 2**3 */
2135 regsym = regsym / 32768; /* 32768L = 2**15 */
2136 regsym = adp_khz * regsym; /* AdpClk in kHz */
2137 regsym = regsym / 128; /* 128 = 2**7 */
2138 regsym *= 125 ; /* 125 = 1000/2**3 */
2139 regsym /= 512 ; /* 128 = 2**9 */
2140 } else {
2141 regsym = regsym * 4; /* 4 = 2**2 */
2142 regsym = regsym / 32768; /* 32768L = 2**15 */
2143 regsym = adp_khz * regsym; /* AdpClk in kHz */
2144 regsym = regsym / 128; /* 128 = 2**7 */
2145 regsym *= 125 ; /* 125 = 1000/2**3 */
2146 regsym /= 256 ; /* 64 = 2**8 */
2147 }
2148
2149 return regsym;
2150 }
2151
2152 static u32 stv0367cab_fsm_status(struct stv0367_state *state)
2153 {
2154 return stv0367_readbits(state, F367CAB_FSM_STATUS);
2155 }
2156
2157 static u32 stv0367cab_qamfec_lock(struct stv0367_state *state)
2158 {
2159 return stv0367_readbits(state,
2160 (state->cab_state->qamfec_status_reg ?
2161 state->cab_state->qamfec_status_reg :
2162 F367CAB_QAMFEC_LOCK));
2163 }
2164
2165 static
2166 enum stv0367_cab_signal_type stv0367cab_fsm_signaltype(u32 qam_fsm_status)
2167 {
2168 enum stv0367_cab_signal_type signaltype = FE_CAB_NOAGC;
2169
2170 switch (qam_fsm_status) {
2171 case 1:
2172 signaltype = FE_CAB_NOAGC;
2173 break;
2174 case 2:
2175 signaltype = FE_CAB_NOTIMING;
2176 break;
2177 case 3:
2178 signaltype = FE_CAB_TIMINGOK;
2179 break;
2180 case 4:
2181 signaltype = FE_CAB_NOCARRIER;
2182 break;
2183 case 5:
2184 signaltype = FE_CAB_CARRIEROK;
2185 break;
2186 case 7:
2187 signaltype = FE_CAB_NOBLIND;
2188 break;
2189 case 8:
2190 signaltype = FE_CAB_BLINDOK;
2191 break;
2192 case 10:
2193 signaltype = FE_CAB_NODEMOD;
2194 break;
2195 case 11:
2196 signaltype = FE_CAB_DEMODOK;
2197 break;
2198 case 12:
2199 signaltype = FE_CAB_DEMODOK;
2200 break;
2201 case 13:
2202 signaltype = FE_CAB_NODEMOD;
2203 break;
2204 case 14:
2205 signaltype = FE_CAB_NOBLIND;
2206 break;
2207 case 15:
2208 signaltype = FE_CAB_NOSIGNAL;
2209 break;
2210 default:
2211 break;
2212 }
2213
2214 return signaltype;
2215 }
2216
2217 static int stv0367cab_read_status(struct dvb_frontend *fe,
2218 enum fe_status *status)
2219 {
2220 struct stv0367_state *state = fe->demodulator_priv;
2221
2222 dprintk("%s:\n", __func__);
2223
2224 *status = 0;
2225
2226 /* update cab_state->state from QAM_FSM_STATUS */
2227 state->cab_state->state = stv0367cab_fsm_signaltype(
2228 stv0367cab_fsm_status(state));
2229
2230 if (stv0367cab_qamfec_lock(state)) {
2231 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI
2232 | FE_HAS_SYNC | FE_HAS_LOCK;
2233 dprintk("%s: stv0367 has locked\n", __func__);
2234 } else {
2235 if (state->cab_state->state > FE_CAB_NOSIGNAL)
2236 *status |= FE_HAS_SIGNAL;
2237
2238 if (state->cab_state->state > FE_CAB_NOCARRIER)
2239 *status |= FE_HAS_CARRIER;
2240
2241 if (state->cab_state->state >= FE_CAB_DEMODOK)
2242 *status |= FE_HAS_VITERBI;
2243
2244 if (state->cab_state->state >= FE_CAB_DATAOK)
2245 *status |= FE_HAS_SYNC;
2246 }
2247
2248 return 0;
2249 }
2250
2251 static int stv0367cab_standby(struct dvb_frontend *fe, u8 standby_on)
2252 {
2253 struct stv0367_state *state = fe->demodulator_priv;
2254
2255 dprintk("%s:\n", __func__);
2256
2257 if (standby_on) {
2258 stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x03);
2259 stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x01);
2260 stv0367_writebits(state, F367CAB_STDBY, 1);
2261 stv0367_writebits(state, F367CAB_STDBY_CORE, 1);
2262 stv0367_writebits(state, F367CAB_EN_BUFFER_I, 0);
2263 stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 0);
2264 stv0367_writebits(state, F367CAB_POFFQ, 1);
2265 stv0367_writebits(state, F367CAB_POFFI, 1);
2266 } else {
2267 stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x00);
2268 stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x00);
2269 stv0367_writebits(state, F367CAB_STDBY, 0);
2270 stv0367_writebits(state, F367CAB_STDBY_CORE, 0);
2271 stv0367_writebits(state, F367CAB_EN_BUFFER_I, 1);
2272 stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 1);
2273 stv0367_writebits(state, F367CAB_POFFQ, 0);
2274 stv0367_writebits(state, F367CAB_POFFI, 0);
2275 }
2276
2277 return 0;
2278 }
2279
2280 static int stv0367cab_sleep(struct dvb_frontend *fe)
2281 {
2282 return stv0367cab_standby(fe, 1);
2283 }
2284
2285 static int stv0367cab_init(struct dvb_frontend *fe)
2286 {
2287 struct stv0367_state *state = fe->demodulator_priv;
2288 struct stv0367cab_state *cab_state = state->cab_state;
2289
2290 dprintk("%s:\n", __func__);
2291
2292 stv0367_write_table(state,
2293 stv0367_deftabs[state->deftabs][STV0367_TAB_CAB]);
2294
2295 switch (state->config->ts_mode) {
2296 case STV0367_DVBCI_CLOCK:
2297 dprintk("Setting TSMode = STV0367_DVBCI_CLOCK\n");
2298 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x03);
2299 break;
2300 case STV0367_SERIAL_PUNCT_CLOCK:
2301 case STV0367_SERIAL_CONT_CLOCK:
2302 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x01);
2303 break;
2304 case STV0367_PARALLEL_PUNCT_CLOCK:
2305 case STV0367_OUTPUTMODE_DEFAULT:
2306 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x00);
2307 break;
2308 }
2309
2310 switch (state->config->clk_pol) {
2311 case STV0367_RISINGEDGE_CLOCK:
2312 stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x00);
2313 break;
2314 case STV0367_FALLINGEDGE_CLOCK:
2315 case STV0367_CLOCKPOLARITY_DEFAULT:
2316 stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x01);
2317 break;
2318 }
2319
2320 stv0367_writebits(state, F367CAB_SYNC_STRIP, 0x00);
2321
2322 stv0367_writebits(state, F367CAB_CT_NBST, 0x01);
2323
2324 stv0367_writebits(state, F367CAB_TS_SWAP, 0x01);
2325
2326 stv0367_writebits(state, F367CAB_FIFO_BYPASS, 0x00);
2327
2328 stv0367_writereg(state, R367CAB_ANACTRL, 0x00);/*PLL enabled and used */
2329
2330 cab_state->mclk = stv0367cab_get_mclk(fe, state->config->xtal);
2331 cab_state->adc_clk = stv0367cab_get_adc_freq(fe, state->config->xtal);
2332
2333 return 0;
2334 }
2335 static
2336 enum stv0367_cab_signal_type stv0367cab_algo(struct stv0367_state *state,
2337 struct dtv_frontend_properties *p)
2338 {
2339 struct stv0367cab_state *cab_state = state->cab_state;
2340 enum stv0367_cab_signal_type signalType = FE_CAB_NOAGC;
2341 u32 QAMFEC_Lock, QAM_Lock, u32_tmp, ifkhz,
2342 LockTime, TRLTimeOut, AGCTimeOut, CRLSymbols,
2343 CRLTimeOut, EQLTimeOut, DemodTimeOut, FECTimeOut;
2344 u8 TrackAGCAccum;
2345 s32 tmp;
2346
2347 dprintk("%s:\n", __func__);
2348
2349 stv0367_get_if_khz(state, &ifkhz);
2350
2351 /* Timeouts calculation */
2352 /* A max lock time of 25 ms is allowed for delayed AGC */
2353 AGCTimeOut = 25;
2354 /* 100000 symbols needed by the TRL as a maximum value */
2355 TRLTimeOut = 100000000 / p->symbol_rate;
2356 /* CRLSymbols is the needed number of symbols to achieve a lock
2357 within [-4%, +4%] of the symbol rate.
2358 CRL timeout is calculated
2359 for a lock within [-search_range, +search_range].
2360 EQL timeout can be changed depending on
2361 the micro-reflections we want to handle.
2362 A characterization must be performed
2363 with these echoes to get new timeout values.
2364 */
2365 switch (p->modulation) {
2366 case QAM_16:
2367 CRLSymbols = 150000;
2368 EQLTimeOut = 100;
2369 break;
2370 case QAM_32:
2371 CRLSymbols = 250000;
2372 EQLTimeOut = 100;
2373 break;
2374 case QAM_64:
2375 CRLSymbols = 200000;
2376 EQLTimeOut = 100;
2377 break;
2378 case QAM_128:
2379 CRLSymbols = 250000;
2380 EQLTimeOut = 100;
2381 break;
2382 case QAM_256:
2383 CRLSymbols = 250000;
2384 EQLTimeOut = 100;
2385 break;
2386 default:
2387 CRLSymbols = 200000;
2388 EQLTimeOut = 100;
2389 break;
2390 }
2391 #if 0
2392 if (pIntParams->search_range < 0) {
2393 CRLTimeOut = (25 * CRLSymbols *
2394 (-pIntParams->search_range / 1000)) /
2395 (pIntParams->symbol_rate / 1000);
2396 } else
2397 #endif
2398 CRLTimeOut = (25 * CRLSymbols * (cab_state->search_range / 1000)) /
2399 (p->symbol_rate / 1000);
2400
2401 CRLTimeOut = (1000 * CRLTimeOut) / p->symbol_rate;
2402 /* Timeouts below 50ms are coerced */
2403 if (CRLTimeOut < 50)
2404 CRLTimeOut = 50;
2405 /* A maximum of 100 TS packets is needed to get FEC lock even in case
2406 the spectrum inversion needs to be changed.
2407 This is equal to 20 ms in case of the lowest symbol rate of 0.87Msps
2408 */
2409 FECTimeOut = 20;
2410 DemodTimeOut = AGCTimeOut + TRLTimeOut + CRLTimeOut + EQLTimeOut;
2411
2412 dprintk("%s: DemodTimeOut=%d\n", __func__, DemodTimeOut);
2413
2414 /* Reset the TRL to ensure nothing starts until the
2415 AGC is stable which ensures a better lock time
2416 */
2417 stv0367_writereg(state, R367CAB_CTRL_1, 0x04);
2418 /* Set AGC accumulation time to minimum and lock threshold to maximum
2419 in order to speed up the AGC lock */
2420 TrackAGCAccum = stv0367_readbits(state, F367CAB_AGC_ACCUMRSTSEL);
2421 stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, 0x0);
2422 /* Modulus Mapper is disabled */
2423 stv0367_writebits(state, F367CAB_MODULUSMAP_EN, 0);
2424 /* Disable the sweep function */
2425 stv0367_writebits(state, F367CAB_SWEEP_EN, 0);
2426 /* The sweep function is never used, Sweep rate must be set to 0 */
2427 /* Set the derotator frequency in Hz */
2428 stv0367cab_set_derot_freq(state, cab_state->adc_clk,
2429 (1000 * (s32)ifkhz + cab_state->derot_offset));
2430 /* Disable the Allpass Filter when the symbol rate is out of range */
2431 if ((p->symbol_rate > 10800000) | (p->symbol_rate < 1800000)) {
2432 stv0367_writebits(state, F367CAB_ADJ_EN, 0);
2433 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0);
2434 }
2435 #if 0
2436 /* Check if the tuner is locked */
2437 tuner_lock = stv0367cab_tuner_get_status(fe);
2438 if (tuner_lock == 0)
2439 return FE_367CAB_NOTUNER;
2440 #endif
2441 /* Release the TRL to start demodulator acquisition */
2442 /* Wait for QAM lock */
2443 LockTime = 0;
2444 stv0367_writereg(state, R367CAB_CTRL_1, 0x00);
2445 do {
2446 QAM_Lock = stv0367cab_fsm_status(state);
2447 if ((LockTime >= (DemodTimeOut - EQLTimeOut)) &&
2448 (QAM_Lock == 0x04))
2449 /*
2450 * We don't wait longer, the frequency/phase offset
2451 * must be too big
2452 */
2453 LockTime = DemodTimeOut;
2454 else if ((LockTime >= (AGCTimeOut + TRLTimeOut)) &&
2455 (QAM_Lock == 0x02))
2456 /*
2457 * We don't wait longer, either there is no signal or
2458 * it is not the right symbol rate or it is an analog
2459 * carrier
2460 */
2461 {
2462 LockTime = DemodTimeOut;
2463 u32_tmp = stv0367_readbits(state,
2464 F367CAB_AGC_PWR_WORD_LO) +
2465 (stv0367_readbits(state,
2466 F367CAB_AGC_PWR_WORD_ME) << 8) +
2467 (stv0367_readbits(state,
2468 F367CAB_AGC_PWR_WORD_HI) << 16);
2469 if (u32_tmp >= 131072)
2470 u32_tmp = 262144 - u32_tmp;
2471 u32_tmp = u32_tmp / (1 << (11 - stv0367_readbits(state,
2472 F367CAB_AGC_IF_BWSEL)));
2473
2474 if (u32_tmp < stv0367_readbits(state,
2475 F367CAB_AGC_PWRREF_LO) +
2476 256 * stv0367_readbits(state,
2477 F367CAB_AGC_PWRREF_HI) - 10)
2478 QAM_Lock = 0x0f;
2479 } else {
2480 usleep_range(10000, 20000);
2481 LockTime += 10;
2482 }
2483 dprintk("QAM_Lock=0x%x LockTime=%d\n", QAM_Lock, LockTime);
2484 tmp = stv0367_readreg(state, R367CAB_IT_STATUS1);
2485
2486 dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp);
2487
2488 } while (((QAM_Lock != 0x0c) && (QAM_Lock != 0x0b)) &&
2489 (LockTime < DemodTimeOut));
2490
2491 dprintk("QAM_Lock=0x%x\n", QAM_Lock);
2492
2493 tmp = stv0367_readreg(state, R367CAB_IT_STATUS1);
2494 dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp);
2495 tmp = stv0367_readreg(state, R367CAB_IT_STATUS2);
2496 dprintk("R367CAB_IT_STATUS2=0x%x\n", tmp);
2497
2498 tmp = stv0367cab_get_derot_freq(state, cab_state->adc_clk);
2499 dprintk("stv0367cab_get_derot_freq=0x%x\n", tmp);
2500
2501 if ((QAM_Lock == 0x0c) || (QAM_Lock == 0x0b)) {
2502 /* Wait for FEC lock */
2503 LockTime = 0;
2504 do {
2505 usleep_range(5000, 7000);
2506 LockTime += 5;
2507 QAMFEC_Lock = stv0367cab_qamfec_lock(state);
2508 } while (!QAMFEC_Lock && (LockTime < FECTimeOut));
2509 } else
2510 QAMFEC_Lock = 0;
2511
2512 if (QAMFEC_Lock) {
2513 signalType = FE_CAB_DATAOK;
2514 cab_state->spect_inv = stv0367_readbits(state,
2515 F367CAB_QUAD_INV);
2516 #if 0
2517 /* not clear for me */
2518 if (ifkhz != 0) {
2519 if (ifkhz > cab_state->adc_clk / 1000) {
2520 cab_state->freq_khz =
2521 FE_Cab_TunerGetFrequency(pIntParams->hTuner)
2522 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
2523 - cab_state->adc_clk / 1000 + ifkhz;
2524 } else {
2525 cab_state->freq_khz =
2526 FE_Cab_TunerGetFrequency(pIntParams->hTuner)
2527 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
2528 + ifkhz;
2529 }
2530 } else {
2531 cab_state->freq_khz =
2532 FE_Cab_TunerGetFrequency(pIntParams->hTuner) +
2533 stv0367cab_get_derot_freq(state,
2534 cab_state->adc_clk) -
2535 cab_state->adc_clk / 4000;
2536 }
2537 #endif
2538 cab_state->symbol_rate = stv0367cab_GetSymbolRate(state,
2539 cab_state->mclk);
2540 cab_state->locked = 1;
2541
2542 /* stv0367_setbits(state, F367CAB_AGC_ACCUMRSTSEL,7);*/
2543 } else
2544 signalType = stv0367cab_fsm_signaltype(QAM_Lock);
2545
2546 /* Set the AGC control values to tracking values */
2547 stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, TrackAGCAccum);
2548 return signalType;
2549 }
2550
2551 static int stv0367cab_set_frontend(struct dvb_frontend *fe)
2552 {
2553 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2554 struct stv0367_state *state = fe->demodulator_priv;
2555 struct stv0367cab_state *cab_state = state->cab_state;
2556 enum stv0367cab_mod QAMSize = 0;
2557
2558 dprintk("%s: freq = %d, srate = %d\n", __func__,
2559 p->frequency, p->symbol_rate);
2560
2561 cab_state->derot_offset = 0;
2562
2563 switch (p->modulation) {
2564 case QAM_16:
2565 QAMSize = FE_CAB_MOD_QAM16;
2566 break;
2567 case QAM_32:
2568 QAMSize = FE_CAB_MOD_QAM32;
2569 break;
2570 case QAM_64:
2571 QAMSize = FE_CAB_MOD_QAM64;
2572 break;
2573 case QAM_128:
2574 QAMSize = FE_CAB_MOD_QAM128;
2575 break;
2576 case QAM_256:
2577 QAMSize = FE_CAB_MOD_QAM256;
2578 break;
2579 default:
2580 break;
2581 }
2582
2583 if (state->reinit_on_setfrontend)
2584 stv0367cab_init(fe);
2585
2586 /* Tuner Frequency Setting */
2587 if (fe->ops.tuner_ops.set_params) {
2588 if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
2589 fe->ops.i2c_gate_ctrl(fe, 1);
2590 fe->ops.tuner_ops.set_params(fe);
2591 if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
2592 fe->ops.i2c_gate_ctrl(fe, 0);
2593 }
2594
2595 stv0367cab_SetQamSize(
2596 state,
2597 p->symbol_rate,
2598 QAMSize);
2599
2600 stv0367cab_set_srate(state,
2601 cab_state->adc_clk,
2602 cab_state->mclk,
2603 p->symbol_rate,
2604 QAMSize);
2605 /* Search algorithm launch, [-1.1*RangeOffset, +1.1*RangeOffset] scan */
2606 cab_state->state = stv0367cab_algo(state, p);
2607 return 0;
2608 }
2609
2610 static int stv0367cab_get_frontend(struct dvb_frontend *fe,
2611 struct dtv_frontend_properties *p)
2612 {
2613 struct stv0367_state *state = fe->demodulator_priv;
2614 struct stv0367cab_state *cab_state = state->cab_state;
2615 u32 ifkhz = 0;
2616
2617 enum stv0367cab_mod QAMSize;
2618
2619 dprintk("%s:\n", __func__);
2620
2621 stv0367_get_if_khz(state, &ifkhz);
2622 p->symbol_rate = stv0367cab_GetSymbolRate(state, cab_state->mclk);
2623
2624 QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE);
2625 switch (QAMSize) {
2626 case FE_CAB_MOD_QAM16:
2627 p->modulation = QAM_16;
2628 break;
2629 case FE_CAB_MOD_QAM32:
2630 p->modulation = QAM_32;
2631 break;
2632 case FE_CAB_MOD_QAM64:
2633 p->modulation = QAM_64;
2634 break;
2635 case FE_CAB_MOD_QAM128:
2636 p->modulation = QAM_128;
2637 break;
2638 case FE_CAB_MOD_QAM256:
2639 p->modulation = QAM_256;
2640 break;
2641 default:
2642 break;
2643 }
2644
2645 p->frequency = stv0367_get_tuner_freq(fe);
2646
2647 dprintk("%s: tuner frequency = %d\n", __func__, p->frequency);
2648
2649 if (ifkhz == 0) {
2650 p->frequency +=
2651 (stv0367cab_get_derot_freq(state, cab_state->adc_clk) -
2652 cab_state->adc_clk / 4000);
2653 return 0;
2654 }
2655
2656 if (ifkhz > cab_state->adc_clk / 1000)
2657 p->frequency += (ifkhz
2658 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
2659 - cab_state->adc_clk / 1000);
2660 else
2661 p->frequency += (ifkhz
2662 - stv0367cab_get_derot_freq(state, cab_state->adc_clk));
2663
2664 return 0;
2665 }
2666
2667 #if 0
2668 void stv0367cab_GetErrorCount(state, enum stv0367cab_mod QAMSize,
2669 u32 symbol_rate, FE_367qam_Monitor *Monitor_results)
2670 {
2671 stv0367cab_OptimiseNByteAndGetBER(state, QAMSize, symbol_rate, Monitor_results);
2672 stv0367cab_GetPacketsCount(state, Monitor_results);
2673
2674 return;
2675 }
2676
2677 static int stv0367cab_read_ber(struct dvb_frontend *fe, u32 *ber)
2678 {
2679 struct stv0367_state *state = fe->demodulator_priv;
2680
2681 return 0;
2682 }
2683 #endif
2684 static s32 stv0367cab_get_rf_lvl(struct stv0367_state *state)
2685 {
2686 s32 rfLevel = 0;
2687 s32 RfAgcPwm = 0, IfAgcPwm = 0;
2688 u8 i;
2689
2690 stv0367_writebits(state, F367CAB_STDBY_ADCGP, 0x0);
2691
2692 RfAgcPwm =
2693 (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_LO) & 0x03) +
2694 (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_HI) << 2);
2695 RfAgcPwm = 100 * RfAgcPwm / 1023;
2696
2697 IfAgcPwm =
2698 stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_LO) +
2699 (stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_HI) << 8);
2700 if (IfAgcPwm >= 2048)
2701 IfAgcPwm -= 2048;
2702 else
2703 IfAgcPwm += 2048;
2704
2705 IfAgcPwm = 100 * IfAgcPwm / 4095;
2706
2707 /* For DTT75467 on NIM */
2708 if (RfAgcPwm < 90 && IfAgcPwm < 28) {
2709 for (i = 0; i < RF_LOOKUP_TABLE_SIZE; i++) {
2710 if (RfAgcPwm <= stv0367cab_RF_LookUp1[0][i]) {
2711 rfLevel = (-1) * stv0367cab_RF_LookUp1[1][i];
2712 break;
2713 }
2714 }
2715 if (i == RF_LOOKUP_TABLE_SIZE)
2716 rfLevel = -56;
2717 } else { /*if IF AGC>10*/
2718 for (i = 0; i < RF_LOOKUP_TABLE2_SIZE; i++) {
2719 if (IfAgcPwm <= stv0367cab_RF_LookUp2[0][i]) {
2720 rfLevel = (-1) * stv0367cab_RF_LookUp2[1][i];
2721 break;
2722 }
2723 }
2724 if (i == RF_LOOKUP_TABLE2_SIZE)
2725 rfLevel = -72;
2726 }
2727 return rfLevel;
2728 }
2729
2730 static int stv0367cab_read_strength(struct dvb_frontend *fe, u16 *strength)
2731 {
2732 struct stv0367_state *state = fe->demodulator_priv;
2733
2734 s32 signal = stv0367cab_get_rf_lvl(state);
2735
2736 dprintk("%s: signal=%d dBm\n", __func__, signal);
2737
2738 if (signal <= -72)
2739 *strength = 65535;
2740 else
2741 *strength = (22 + signal) * (-1311);
2742
2743 dprintk("%s: strength=%d\n", __func__, (*strength));
2744
2745 return 0;
2746 }
2747
2748 static int stv0367cab_snr_power(struct dvb_frontend *fe)
2749 {
2750 struct stv0367_state *state = fe->demodulator_priv;
2751 enum stv0367cab_mod QAMSize;
2752
2753 QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE);
2754 switch (QAMSize) {
2755 case FE_CAB_MOD_QAM4:
2756 return 21904;
2757 case FE_CAB_MOD_QAM16:
2758 return 20480;
2759 case FE_CAB_MOD_QAM32:
2760 return 23040;
2761 case FE_CAB_MOD_QAM64:
2762 return 21504;
2763 case FE_CAB_MOD_QAM128:
2764 return 23616;
2765 case FE_CAB_MOD_QAM256:
2766 return 21760;
2767 case FE_CAB_MOD_QAM1024:
2768 return 21280;
2769 default:
2770 break;
2771 }
2772
2773 return 1;
2774 }
2775
2776 static int stv0367cab_snr_readreg(struct dvb_frontend *fe, int avgdiv)
2777 {
2778 struct stv0367_state *state = fe->demodulator_priv;
2779 u32 regval = 0;
2780 int i;
2781
2782 for (i = 0; i < 10; i++) {
2783 regval += (stv0367_readbits(state, F367CAB_SNR_LO)
2784 + 256 * stv0367_readbits(state, F367CAB_SNR_HI));
2785 }
2786
2787 if (avgdiv)
2788 regval /= 10;
2789
2790 return regval;
2791 }
2792
2793 static int stv0367cab_read_snr(struct dvb_frontend *fe, u16 *snr)
2794 {
2795 struct stv0367_state *state = fe->demodulator_priv;
2796 u32 noisepercentage;
2797 u32 regval = 0, temp = 0;
2798 int power;
2799
2800 power = stv0367cab_snr_power(fe);
2801 regval = stv0367cab_snr_readreg(fe, 1);
2802
2803 if (regval != 0) {
2804 temp = power
2805 * (1 << (3 + stv0367_readbits(state, F367CAB_SNR_PER)));
2806 temp /= regval;
2807 }
2808
2809 /* table values, not needed to calculate logarithms */
2810 if (temp >= 5012)
2811 noisepercentage = 100;
2812 else if (temp >= 3981)
2813 noisepercentage = 93;
2814 else if (temp >= 3162)
2815 noisepercentage = 86;
2816 else if (temp >= 2512)
2817 noisepercentage = 79;
2818 else if (temp >= 1995)
2819 noisepercentage = 72;
2820 else if (temp >= 1585)
2821 noisepercentage = 65;
2822 else if (temp >= 1259)
2823 noisepercentage = 58;
2824 else if (temp >= 1000)
2825 noisepercentage = 50;
2826 else if (temp >= 794)
2827 noisepercentage = 43;
2828 else if (temp >= 501)
2829 noisepercentage = 36;
2830 else if (temp >= 316)
2831 noisepercentage = 29;
2832 else if (temp >= 200)
2833 noisepercentage = 22;
2834 else if (temp >= 158)
2835 noisepercentage = 14;
2836 else if (temp >= 126)
2837 noisepercentage = 7;
2838 else
2839 noisepercentage = 0;
2840
2841 dprintk("%s: noisepercentage=%d\n", __func__, noisepercentage);
2842
2843 *snr = (noisepercentage * 65535) / 100;
2844
2845 return 0;
2846 }
2847
2848 static int stv0367cab_read_ucblcks(struct dvb_frontend *fe, u32 *ucblocks)
2849 {
2850 struct stv0367_state *state = fe->demodulator_priv;
2851 int corrected, tscount;
2852
2853 *ucblocks = (stv0367_readreg(state, R367CAB_RS_COUNTER_5) << 8)
2854 | stv0367_readreg(state, R367CAB_RS_COUNTER_4);
2855 corrected = (stv0367_readreg(state, R367CAB_RS_COUNTER_3) << 8)
2856 | stv0367_readreg(state, R367CAB_RS_COUNTER_2);
2857 tscount = (stv0367_readreg(state, R367CAB_RS_COUNTER_2) << 8)
2858 | stv0367_readreg(state, R367CAB_RS_COUNTER_1);
2859
2860 dprintk("%s: uncorrected blocks=%d corrected blocks=%d tscount=%d\n",
2861 __func__, *ucblocks, corrected, tscount);
2862
2863 return 0;
2864 };
2865
2866 static const struct dvb_frontend_ops stv0367cab_ops = {
2867 .delsys = { SYS_DVBC_ANNEX_A },
2868 .info = {
2869 .name = "ST STV0367 DVB-C",
2870 .frequency_min = 47000000,
2871 .frequency_max = 862000000,
2872 .frequency_stepsize = 62500,
2873 .symbol_rate_min = 870000,
2874 .symbol_rate_max = 11700000,
2875 .caps = 0x400 |/* FE_CAN_QAM_4 */
2876 FE_CAN_QAM_16 | FE_CAN_QAM_32 |
2877 FE_CAN_QAM_64 | FE_CAN_QAM_128 |
2878 FE_CAN_QAM_256 | FE_CAN_FEC_AUTO
2879 },
2880 .release = stv0367_release,
2881 .init = stv0367cab_init,
2882 .sleep = stv0367cab_sleep,
2883 .i2c_gate_ctrl = stv0367cab_gate_ctrl,
2884 .set_frontend = stv0367cab_set_frontend,
2885 .get_frontend = stv0367cab_get_frontend,
2886 .read_status = stv0367cab_read_status,
2887 /* .read_ber = stv0367cab_read_ber, */
2888 .read_signal_strength = stv0367cab_read_strength,
2889 .read_snr = stv0367cab_read_snr,
2890 .read_ucblocks = stv0367cab_read_ucblcks,
2891 .get_tune_settings = stv0367_get_tune_settings,
2892 };
2893
2894 struct dvb_frontend *stv0367cab_attach(const struct stv0367_config *config,
2895 struct i2c_adapter *i2c)
2896 {
2897 struct stv0367_state *state = NULL;
2898 struct stv0367cab_state *cab_state = NULL;
2899
2900 /* allocate memory for the internal state */
2901 state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
2902 if (state == NULL)
2903 goto error;
2904 cab_state = kzalloc(sizeof(struct stv0367cab_state), GFP_KERNEL);
2905 if (cab_state == NULL)
2906 goto error;
2907
2908 /* setup the state */
2909 state->i2c = i2c;
2910 state->config = config;
2911 cab_state->search_range = 280000;
2912 cab_state->qamfec_status_reg = F367CAB_QAMFEC_LOCK;
2913 state->cab_state = cab_state;
2914 state->fe.ops = stv0367cab_ops;
2915 state->fe.demodulator_priv = state;
2916 state->chip_id = stv0367_readreg(state, 0xf000);
2917
2918 /* demod operation options */
2919 state->use_i2c_gatectrl = 1;
2920 state->deftabs = STV0367_DEFTAB_GENERIC;
2921 state->reinit_on_setfrontend = 1;
2922 state->auto_if_khz = 0;
2923
2924 dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
2925
2926 /* check if the demod is there */
2927 if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
2928 goto error;
2929
2930 return &state->fe;
2931
2932 error:
2933 kfree(cab_state);
2934 kfree(state);
2935 return NULL;
2936 }
2937 EXPORT_SYMBOL(stv0367cab_attach);
2938
2939 /*
2940 * Functions for operation on Digital Devices hardware
2941 */
2942
2943 static void stv0367ddb_setup_ter(struct stv0367_state *state)
2944 {
2945 stv0367_writereg(state, R367TER_DEBUG_LT4, 0x00);
2946 stv0367_writereg(state, R367TER_DEBUG_LT5, 0x00);
2947 stv0367_writereg(state, R367TER_DEBUG_LT6, 0x00); /* R367CAB_CTRL_1 */
2948 stv0367_writereg(state, R367TER_DEBUG_LT7, 0x00); /* R367CAB_CTRL_2 */
2949 stv0367_writereg(state, R367TER_DEBUG_LT8, 0x00);
2950 stv0367_writereg(state, R367TER_DEBUG_LT9, 0x00);
2951
2952 /* Tuner Setup */
2953 /* Buffer Q disabled, I Enabled, unsigned ADC */
2954 stv0367_writereg(state, R367TER_ANADIGCTRL, 0x89);
2955 stv0367_writereg(state, R367TER_DUAL_AD12, 0x04); /* ADCQ disabled */
2956
2957 /* Clock setup */
2958 /* PLL bypassed and disabled */
2959 stv0367_writereg(state, R367TER_ANACTRL, 0x0D);
2960 stv0367_writereg(state, R367TER_TOPCTRL, 0x00); /* Set OFDM */
2961
2962 /* IC runs at 54 MHz with a 27 MHz crystal */
2963 stv0367_pll_setup(state, STV0367_ICSPEED_53125, state->config->xtal);
2964
2965 msleep(50);
2966 /* PLL enabled and used */
2967 stv0367_writereg(state, R367TER_ANACTRL, 0x00);
2968
2969 state->activedemod = demod_ter;
2970 }
2971
2972 static void stv0367ddb_setup_cab(struct stv0367_state *state)
2973 {
2974 stv0367_writereg(state, R367TER_DEBUG_LT4, 0x00);
2975 stv0367_writereg(state, R367TER_DEBUG_LT5, 0x01);
2976 stv0367_writereg(state, R367TER_DEBUG_LT6, 0x06); /* R367CAB_CTRL_1 */
2977 stv0367_writereg(state, R367TER_DEBUG_LT7, 0x03); /* R367CAB_CTRL_2 */
2978 stv0367_writereg(state, R367TER_DEBUG_LT8, 0x00);
2979 stv0367_writereg(state, R367TER_DEBUG_LT9, 0x00);
2980
2981 /* Tuner Setup */
2982 /* Buffer Q disabled, I Enabled, signed ADC */
2983 stv0367_writereg(state, R367TER_ANADIGCTRL, 0x8B);
2984 /* ADCQ disabled */
2985 stv0367_writereg(state, R367TER_DUAL_AD12, 0x04);
2986
2987 /* Clock setup */
2988 /* PLL bypassed and disabled */
2989 stv0367_writereg(state, R367TER_ANACTRL, 0x0D);
2990 /* Set QAM */
2991 stv0367_writereg(state, R367TER_TOPCTRL, 0x10);
2992
2993 /* IC runs at 58 MHz with a 27 MHz crystal */
2994 stv0367_pll_setup(state, STV0367_ICSPEED_58000, state->config->xtal);
2995
2996 msleep(50);
2997 /* PLL enabled and used */
2998 stv0367_writereg(state, R367TER_ANACTRL, 0x00);
2999
3000 state->cab_state->mclk = stv0367cab_get_mclk(&state->fe,
3001 state->config->xtal);
3002 state->cab_state->adc_clk = stv0367cab_get_adc_freq(&state->fe,
3003 state->config->xtal);
3004
3005 state->activedemod = demod_cab;
3006 }
3007
3008 static int stv0367ddb_set_frontend(struct dvb_frontend *fe)
3009 {
3010 struct stv0367_state *state = fe->demodulator_priv;
3011
3012 switch (fe->dtv_property_cache.delivery_system) {
3013 case SYS_DVBT:
3014 if (state->activedemod != demod_ter)
3015 stv0367ddb_setup_ter(state);
3016
3017 return stv0367ter_set_frontend(fe);
3018 case SYS_DVBC_ANNEX_A:
3019 if (state->activedemod != demod_cab)
3020 stv0367ddb_setup_cab(state);
3021
3022 /* protect against division error oopses */
3023 if (fe->dtv_property_cache.symbol_rate == 0) {
3024 printk(KERN_ERR "Invalid symbol rate\n");
3025 return -EINVAL;
3026 }
3027
3028 return stv0367cab_set_frontend(fe);
3029 default:
3030 break;
3031 }
3032
3033 return -EINVAL;
3034 }
3035
3036 static void stv0367ddb_read_signal_strength(struct dvb_frontend *fe)
3037 {
3038 struct stv0367_state *state = fe->demodulator_priv;
3039 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3040 s32 signalstrength;
3041
3042 switch (state->activedemod) {
3043 case demod_cab:
3044 signalstrength = stv0367cab_get_rf_lvl(state) * 1000;
3045 break;
3046 default:
3047 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3048 return;
3049 }
3050
3051 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
3052 p->strength.stat[0].uvalue = signalstrength;
3053 }
3054
3055 static void stv0367ddb_read_snr(struct dvb_frontend *fe)
3056 {
3057 struct stv0367_state *state = fe->demodulator_priv;
3058 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3059 int cab_pwr;
3060 u32 regval, tmpval, snrval = 0;
3061
3062 switch (state->activedemod) {
3063 case demod_ter:
3064 snrval = stv0367ter_snr_readreg(fe);
3065 break;
3066 case demod_cab:
3067 cab_pwr = stv0367cab_snr_power(fe);
3068 regval = stv0367cab_snr_readreg(fe, 0);
3069
3070 /* prevent division by zero */
3071 if (!regval) {
3072 snrval = 0;
3073 break;
3074 }
3075
3076 tmpval = (cab_pwr * 320) / regval;
3077 snrval = ((tmpval != 0) ? (intlog2(tmpval) / 5581) : 0);
3078 break;
3079 default:
3080 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3081 return;
3082 }
3083
3084 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
3085 p->cnr.stat[0].uvalue = snrval;
3086 }
3087
3088 static void stv0367ddb_read_ucblocks(struct dvb_frontend *fe)
3089 {
3090 struct stv0367_state *state = fe->demodulator_priv;
3091 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3092 u32 ucblocks = 0;
3093
3094 switch (state->activedemod) {
3095 case demod_ter:
3096 stv0367ter_read_ucblocks(fe, &ucblocks);
3097 break;
3098 case demod_cab:
3099 stv0367cab_read_ucblcks(fe, &ucblocks);
3100 break;
3101 default:
3102 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3103 return;
3104 }
3105
3106 p->block_error.stat[0].scale = FE_SCALE_COUNTER;
3107 p->block_error.stat[0].uvalue = ucblocks;
3108 }
3109
3110 static int stv0367ddb_read_status(struct dvb_frontend *fe,
3111 enum fe_status *status)
3112 {
3113 struct stv0367_state *state = fe->demodulator_priv;
3114 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3115 int ret = 0;
3116
3117 switch (state->activedemod) {
3118 case demod_ter:
3119 ret = stv0367ter_read_status(fe, status);
3120 break;
3121 case demod_cab:
3122 ret = stv0367cab_read_status(fe, status);
3123 break;
3124 default:
3125 break;
3126 }
3127
3128 /* stop and report on *_read_status failure */
3129 if (ret)
3130 return ret;
3131
3132 stv0367ddb_read_signal_strength(fe);
3133
3134 /* read carrier/noise when a carrier is detected */
3135 if (*status & FE_HAS_CARRIER)
3136 stv0367ddb_read_snr(fe);
3137 else
3138 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3139
3140 /* read uncorrected blocks on FE_HAS_LOCK */
3141 if (*status & FE_HAS_LOCK)
3142 stv0367ddb_read_ucblocks(fe);
3143 else
3144 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3145
3146 return 0;
3147 }
3148
3149 static int stv0367ddb_get_frontend(struct dvb_frontend *fe,
3150 struct dtv_frontend_properties *p)
3151 {
3152 struct stv0367_state *state = fe->demodulator_priv;
3153
3154 switch (state->activedemod) {
3155 case demod_ter:
3156 return stv0367ter_get_frontend(fe, p);
3157 case demod_cab:
3158 return stv0367cab_get_frontend(fe, p);
3159 default:
3160 break;
3161 }
3162
3163 return 0;
3164 }
3165
3166 static int stv0367ddb_sleep(struct dvb_frontend *fe)
3167 {
3168 struct stv0367_state *state = fe->demodulator_priv;
3169
3170 switch (state->activedemod) {
3171 case demod_ter:
3172 state->activedemod = demod_none;
3173 return stv0367ter_sleep(fe);
3174 case demod_cab:
3175 state->activedemod = demod_none;
3176 return stv0367cab_sleep(fe);
3177 default:
3178 break;
3179 }
3180
3181 return -EINVAL;
3182 }
3183
3184 static int stv0367ddb_init(struct stv0367_state *state)
3185 {
3186 struct stv0367ter_state *ter_state = state->ter_state;
3187 struct dtv_frontend_properties *p = &state->fe.dtv_property_cache;
3188
3189 stv0367_writereg(state, R367TER_TOPCTRL, 0x10);
3190
3191 if (stv0367_deftabs[state->deftabs][STV0367_TAB_BASE])
3192 stv0367_write_table(state,
3193 stv0367_deftabs[state->deftabs][STV0367_TAB_BASE]);
3194
3195 stv0367_write_table(state,
3196 stv0367_deftabs[state->deftabs][STV0367_TAB_CAB]);
3197
3198 stv0367_writereg(state, R367TER_TOPCTRL, 0x00);
3199 stv0367_write_table(state,
3200 stv0367_deftabs[state->deftabs][STV0367_TAB_TER]);
3201
3202 stv0367_writereg(state, R367TER_GAIN_SRC1, 0x2A);
3203 stv0367_writereg(state, R367TER_GAIN_SRC2, 0xD6);
3204 stv0367_writereg(state, R367TER_INC_DEROT1, 0x55);
3205 stv0367_writereg(state, R367TER_INC_DEROT2, 0x55);
3206 stv0367_writereg(state, R367TER_TRL_CTL, 0x14);
3207 stv0367_writereg(state, R367TER_TRL_NOMRATE1, 0xAE);
3208 stv0367_writereg(state, R367TER_TRL_NOMRATE2, 0x56);
3209 stv0367_writereg(state, R367TER_FEPATH_CFG, 0x0);
3210
3211 /* OFDM TS Setup */
3212
3213 stv0367_writereg(state, R367TER_TSCFGH, 0x70);
3214 stv0367_writereg(state, R367TER_TSCFGM, 0xC0);
3215 stv0367_writereg(state, R367TER_TSCFGL, 0x20);
3216 stv0367_writereg(state, R367TER_TSSPEED, 0x40); /* Fixed at 54 MHz */
3217
3218 stv0367_writereg(state, R367TER_TSCFGH, 0x71);
3219 stv0367_writereg(state, R367TER_TSCFGH, 0x70);
3220
3221 stv0367_writereg(state, R367TER_TOPCTRL, 0x10);
3222
3223 /* Also needed for QAM */
3224 stv0367_writereg(state, R367TER_AGC12C, 0x01); /* AGC Pin setup */
3225
3226 stv0367_writereg(state, R367TER_AGCCTRL1, 0x8A);
3227
3228 /* QAM TS setup, note exact format also depends on descrambler */
3229 /* settings */
3230 /* Inverted Clock, Swap, serial */
3231 stv0367_writereg(state, R367CAB_OUTFORMAT_0, 0x85);
3232
3233 /* Clock setup (PLL bypassed and disabled) */
3234 stv0367_writereg(state, R367TER_ANACTRL, 0x0D);
3235
3236 /* IC runs at 58 MHz with a 27 MHz crystal */
3237 stv0367_pll_setup(state, STV0367_ICSPEED_58000, state->config->xtal);
3238
3239 /* Tuner setup */
3240 /* Buffer Q disabled, I Enabled, signed ADC */
3241 stv0367_writereg(state, R367TER_ANADIGCTRL, 0x8b);
3242 stv0367_writereg(state, R367TER_DUAL_AD12, 0x04); /* ADCQ disabled */
3243
3244 /* Improves the C/N lock limit */
3245 stv0367_writereg(state, R367CAB_FSM_SNR2_HTH, 0x23);
3246 /* ZIF/IF Automatic mode */
3247 stv0367_writereg(state, R367CAB_IQ_QAM, 0x01);
3248 /* Improving burst noise performances */
3249 stv0367_writereg(state, R367CAB_EQU_FFE_LEAKAGE, 0x83);
3250 /* Improving ACI performances */
3251 stv0367_writereg(state, R367CAB_IQDEM_ADJ_EN, 0x05);
3252
3253 /* PLL enabled and used */
3254 stv0367_writereg(state, R367TER_ANACTRL, 0x00);
3255
3256 stv0367_writereg(state, R367TER_I2CRPT, (0x08 | ((5 & 0x07) << 4)));
3257
3258 ter_state->pBER = 0;
3259 ter_state->first_lock = 0;
3260 ter_state->unlock_counter = 2;
3261
3262 p->strength.len = 1;
3263 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3264 p->cnr.len = 1;
3265 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3266 p->block_error.len = 1;
3267 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3268
3269 return 0;
3270 }
3271
3272 static const struct dvb_frontend_ops stv0367ddb_ops = {
3273 .delsys = { SYS_DVBC_ANNEX_A, SYS_DVBT },
3274 .info = {
3275 .name = "ST STV0367 DDB DVB-C/T",
3276 .frequency_min = 47000000,
3277 .frequency_max = 865000000,
3278 .frequency_stepsize = 166667,
3279 .frequency_tolerance = 0,
3280 .symbol_rate_min = 870000,
3281 .symbol_rate_max = 11700000,
3282 .caps = /* DVB-C */
3283 0x400 |/* FE_CAN_QAM_4 */
3284 FE_CAN_QAM_16 | FE_CAN_QAM_32 |
3285 FE_CAN_QAM_64 | FE_CAN_QAM_128 |
3286 FE_CAN_QAM_256 |
3287 /* DVB-T */
3288 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
3289 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
3290 FE_CAN_QPSK | FE_CAN_TRANSMISSION_MODE_AUTO |
3291 FE_CAN_RECOVER | FE_CAN_INVERSION_AUTO |
3292 FE_CAN_MUTE_TS
3293 },
3294 .release = stv0367_release,
3295 .sleep = stv0367ddb_sleep,
3296 .i2c_gate_ctrl = stv0367cab_gate_ctrl, /* valid for TER and CAB */
3297 .set_frontend = stv0367ddb_set_frontend,
3298 .get_frontend = stv0367ddb_get_frontend,
3299 .get_tune_settings = stv0367_get_tune_settings,
3300 .read_status = stv0367ddb_read_status,
3301 };
3302
3303 struct dvb_frontend *stv0367ddb_attach(const struct stv0367_config *config,
3304 struct i2c_adapter *i2c)
3305 {
3306 struct stv0367_state *state = NULL;
3307 struct stv0367ter_state *ter_state = NULL;
3308 struct stv0367cab_state *cab_state = NULL;
3309
3310 /* allocate memory for the internal state */
3311 state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
3312 if (state == NULL)
3313 goto error;
3314 ter_state = kzalloc(sizeof(struct stv0367ter_state), GFP_KERNEL);
3315 if (ter_state == NULL)
3316 goto error;
3317 cab_state = kzalloc(sizeof(struct stv0367cab_state), GFP_KERNEL);
3318 if (cab_state == NULL)
3319 goto error;
3320
3321 /* setup the state */
3322 state->i2c = i2c;
3323 state->config = config;
3324 state->ter_state = ter_state;
3325 cab_state->search_range = 280000;
3326 cab_state->qamfec_status_reg = F367CAB_DESCR_SYNCSTATE;
3327 state->cab_state = cab_state;
3328 state->fe.ops = stv0367ddb_ops;
3329 state->fe.demodulator_priv = state;
3330 state->chip_id = stv0367_readreg(state, R367TER_ID);
3331
3332 /* demod operation options */
3333 state->use_i2c_gatectrl = 0;
3334 state->deftabs = STV0367_DEFTAB_DDB;
3335 state->reinit_on_setfrontend = 0;
3336 state->auto_if_khz = 1;
3337 state->activedemod = demod_none;
3338
3339 dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
3340
3341 /* check if the demod is there */
3342 if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
3343 goto error;
3344
3345 dev_info(&i2c->dev, "Found %s with ChipID %02X at adr %02X\n",
3346 state->fe.ops.info.name, state->chip_id,
3347 config->demod_address);
3348
3349 stv0367ddb_init(state);
3350
3351 return &state->fe;
3352
3353 error:
3354 kfree(cab_state);
3355 kfree(ter_state);
3356 kfree(state);
3357 return NULL;
3358 }
3359 EXPORT_SYMBOL(stv0367ddb_attach);
3360
3361 MODULE_PARM_DESC(debug, "Set debug");
3362 MODULE_PARM_DESC(i2c_debug, "Set i2c debug");
3363
3364 MODULE_AUTHOR("Igor M. Liplianin");
3365 MODULE_DESCRIPTION("ST STV0367 DVB-C/T demodulator driver");
3366 MODULE_LICENSE("GPL");
CRIS linux kernel tree