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x86/intel_rdt: Fix incorrect returned value when creating rdgroup sub-directory in...
[cris-mirror.git] / drivers / net / ethernet / amd / xgbe / xgbe-drv.c
blob100adee778dfd62f5d3d559dccc9f2b5a8bb94a4
1 /*
2 * AMD 10Gb Ethernet driver
3 *
4 * This file is available to you under your choice of the following two
5 * licenses:
6 *
7 * License 1: GPLv2
8 *
9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
10 *
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 *
24 * This file incorporates work covered by the following copyright and
25 * permission notice:
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
29 * and you.
30 *
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
40 *
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
43 *
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
55 *
56 *
57 * License 2: Modified BSD
58 *
59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
60 * All rights reserved.
61 *
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
72 *
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
83 *
84 * This file incorporates work covered by the following copyright and
85 * permission notice:
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
89 * and you.
90 *
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
100 *
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
103 *
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
115 */
116
117 #include <linux/module.h>
118 #include <linux/spinlock.h>
119 #include <linux/tcp.h>
120 #include <linux/if_vlan.h>
121 #include <linux/interrupt.h>
122 #include <net/busy_poll.h>
123 #include <linux/clk.h>
124 #include <linux/if_ether.h>
125 #include <linux/net_tstamp.h>
126 #include <linux/phy.h>
127 #include <net/vxlan.h>
128
129 #include "xgbe.h"
130 #include "xgbe-common.h"
131
132 static unsigned int ecc_sec_info_threshold = 10;
133 static unsigned int ecc_sec_warn_threshold = 10000;
134 static unsigned int ecc_sec_period = 600;
135 static unsigned int ecc_ded_threshold = 2;
136 static unsigned int ecc_ded_period = 600;
137
138 #ifdef CONFIG_AMD_XGBE_HAVE_ECC
139 /* Only expose the ECC parameters if supported */
140 module_param(ecc_sec_info_threshold, uint, S_IWUSR | S_IRUGO);
141 MODULE_PARM_DESC(ecc_sec_info_threshold,
142 " ECC corrected error informational threshold setting");
143
144 module_param(ecc_sec_warn_threshold, uint, S_IWUSR | S_IRUGO);
145 MODULE_PARM_DESC(ecc_sec_warn_threshold,
146 " ECC corrected error warning threshold setting");
147
148 module_param(ecc_sec_period, uint, S_IWUSR | S_IRUGO);
149 MODULE_PARM_DESC(ecc_sec_period, " ECC corrected error period (in seconds)");
150
151 module_param(ecc_ded_threshold, uint, S_IWUSR | S_IRUGO);
152 MODULE_PARM_DESC(ecc_ded_threshold, " ECC detected error threshold setting");
153
154 module_param(ecc_ded_period, uint, S_IWUSR | S_IRUGO);
155 MODULE_PARM_DESC(ecc_ded_period, " ECC detected error period (in seconds)");
156 #endif
157
158 static int xgbe_one_poll(struct napi_struct *, int);
159 static int xgbe_all_poll(struct napi_struct *, int);
160 static void xgbe_stop(struct xgbe_prv_data *);
161
162 static void *xgbe_alloc_node(size_t size, int node)
163 {
164 void *mem;
165
166 mem = kzalloc_node(size, GFP_KERNEL, node);
167 if (!mem)
168 mem = kzalloc(size, GFP_KERNEL);
169
170 return mem;
171 }
172
173 static void xgbe_free_channels(struct xgbe_prv_data *pdata)
174 {
175 unsigned int i;
176
177 for (i = 0; i < ARRAY_SIZE(pdata->channel); i++) {
178 if (!pdata->channel[i])
179 continue;
180
181 kfree(pdata->channel[i]->rx_ring);
182 kfree(pdata->channel[i]->tx_ring);
183 kfree(pdata->channel[i]);
184
185 pdata->channel[i] = NULL;
186 }
187
188 pdata->channel_count = 0;
189 }
190
191 static int xgbe_alloc_channels(struct xgbe_prv_data *pdata)
192 {
193 struct xgbe_channel *channel;
194 struct xgbe_ring *ring;
195 unsigned int count, i;
196 unsigned int cpu;
197 int node;
198
199 count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count);
200 for (i = 0; i < count; i++) {
201 /* Attempt to use a CPU on the node the device is on */
202 cpu = cpumask_local_spread(i, dev_to_node(pdata->dev));
203
204 /* Set the allocation node based on the returned CPU */
205 node = cpu_to_node(cpu);
206
207 channel = xgbe_alloc_node(sizeof(*channel), node);
208 if (!channel)
209 goto err_mem;
210 pdata->channel[i] = channel;
211
212 snprintf(channel->name, sizeof(channel->name), "channel-%u", i);
213 channel->pdata = pdata;
214 channel->queue_index = i;
215 channel->dma_regs = pdata->xgmac_regs + DMA_CH_BASE +
216 (DMA_CH_INC * i);
217 channel->node = node;
218 cpumask_set_cpu(cpu, &channel->affinity_mask);
219
220 if (pdata->per_channel_irq)
221 channel->dma_irq = pdata->channel_irq[i];
222
223 if (i < pdata->tx_ring_count) {
224 ring = xgbe_alloc_node(sizeof(*ring), node);
225 if (!ring)
226 goto err_mem;
227
228 spin_lock_init(&ring->lock);
229 ring->node = node;
230
231 channel->tx_ring = ring;
232 }
233
234 if (i < pdata->rx_ring_count) {
235 ring = xgbe_alloc_node(sizeof(*ring), node);
236 if (!ring)
237 goto err_mem;
238
239 spin_lock_init(&ring->lock);
240 ring->node = node;
241
242 channel->rx_ring = ring;
243 }
244
245 netif_dbg(pdata, drv, pdata->netdev,
246 "%s: cpu=%u, node=%d\n", channel->name, cpu, node);
247
248 netif_dbg(pdata, drv, pdata->netdev,
249 "%s: dma_regs=%p, dma_irq=%d, tx=%p, rx=%p\n",
250 channel->name, channel->dma_regs, channel->dma_irq,
251 channel->tx_ring, channel->rx_ring);
252 }
253
254 pdata->channel_count = count;
255
256 return 0;
257
258 err_mem:
259 xgbe_free_channels(pdata);
260
261 return -ENOMEM;
262 }
263
264 static inline unsigned int xgbe_tx_avail_desc(struct xgbe_ring *ring)
265 {
266 return (ring->rdesc_count - (ring->cur - ring->dirty));
267 }
268
269 static inline unsigned int xgbe_rx_dirty_desc(struct xgbe_ring *ring)
270 {
271 return (ring->cur - ring->dirty);
272 }
273
274 static int xgbe_maybe_stop_tx_queue(struct xgbe_channel *channel,
275 struct xgbe_ring *ring, unsigned int count)
276 {
277 struct xgbe_prv_data *pdata = channel->pdata;
278
279 if (count > xgbe_tx_avail_desc(ring)) {
280 netif_info(pdata, drv, pdata->netdev,
281 "Tx queue stopped, not enough descriptors available\n");
282 netif_stop_subqueue(pdata->netdev, channel->queue_index);
283 ring->tx.queue_stopped = 1;
284
285 /* If we haven't notified the hardware because of xmit_more
286 * support, tell it now
287 */
288 if (ring->tx.xmit_more)
289 pdata->hw_if.tx_start_xmit(channel, ring);
290
291 return NETDEV_TX_BUSY;
292 }
293
294 return 0;
295 }
296
297 static int xgbe_calc_rx_buf_size(struct net_device *netdev, unsigned int mtu)
298 {
299 unsigned int rx_buf_size;
300
301 rx_buf_size = mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
302 rx_buf_size = clamp_val(rx_buf_size, XGBE_RX_MIN_BUF_SIZE, PAGE_SIZE);
303
304 rx_buf_size = (rx_buf_size + XGBE_RX_BUF_ALIGN - 1) &
305 ~(XGBE_RX_BUF_ALIGN - 1);
306
307 return rx_buf_size;
308 }
309
310 static void xgbe_enable_rx_tx_int(struct xgbe_prv_data *pdata,
311 struct xgbe_channel *channel)
312 {
313 struct xgbe_hw_if *hw_if = &pdata->hw_if;
314 enum xgbe_int int_id;
315
316 if (channel->tx_ring && channel->rx_ring)
317 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
318 else if (channel->tx_ring)
319 int_id = XGMAC_INT_DMA_CH_SR_TI;
320 else if (channel->rx_ring)
321 int_id = XGMAC_INT_DMA_CH_SR_RI;
322 else
323 return;
324
325 hw_if->enable_int(channel, int_id);
326 }
327
328 static void xgbe_enable_rx_tx_ints(struct xgbe_prv_data *pdata)
329 {
330 unsigned int i;
331
332 for (i = 0; i < pdata->channel_count; i++)
333 xgbe_enable_rx_tx_int(pdata, pdata->channel[i]);
334 }
335
336 static void xgbe_disable_rx_tx_int(struct xgbe_prv_data *pdata,
337 struct xgbe_channel *channel)
338 {
339 struct xgbe_hw_if *hw_if = &pdata->hw_if;
340 enum xgbe_int int_id;
341
342 if (channel->tx_ring && channel->rx_ring)
343 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
344 else if (channel->tx_ring)
345 int_id = XGMAC_INT_DMA_CH_SR_TI;
346 else if (channel->rx_ring)
347 int_id = XGMAC_INT_DMA_CH_SR_RI;
348 else
349 return;
350
351 hw_if->disable_int(channel, int_id);
352 }
353
354 static void xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata)
355 {
356 unsigned int i;
357
358 for (i = 0; i < pdata->channel_count; i++)
359 xgbe_disable_rx_tx_int(pdata, pdata->channel[i]);
360 }
361
362 static bool xgbe_ecc_sec(struct xgbe_prv_data *pdata, unsigned long *period,
363 unsigned int *count, const char *area)
364 {
365 if (time_before(jiffies, *period)) {
366 (*count)++;
367 } else {
368 *period = jiffies + (ecc_sec_period * HZ);
369 *count = 1;
370 }
371
372 if (*count > ecc_sec_info_threshold)
373 dev_warn_once(pdata->dev,
374 "%s ECC corrected errors exceed informational threshold\n",
375 area);
376
377 if (*count > ecc_sec_warn_threshold) {
378 dev_warn_once(pdata->dev,
379 "%s ECC corrected errors exceed warning threshold\n",
380 area);
381 return true;
382 }
383
384 return false;
385 }
386
387 static bool xgbe_ecc_ded(struct xgbe_prv_data *pdata, unsigned long *period,
388 unsigned int *count, const char *area)
389 {
390 if (time_before(jiffies, *period)) {
391 (*count)++;
392 } else {
393 *period = jiffies + (ecc_ded_period * HZ);
394 *count = 1;
395 }
396
397 if (*count > ecc_ded_threshold) {
398 netdev_alert(pdata->netdev,
399 "%s ECC detected errors exceed threshold\n",
400 area);
401 return true;
402 }
403
404 return false;
405 }
406
407 static void xgbe_ecc_isr_task(unsigned long data)
408 {
409 struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
410 unsigned int ecc_isr;
411 bool stop = false;
412
413 /* Mask status with only the interrupts we care about */
414 ecc_isr = XP_IOREAD(pdata, XP_ECC_ISR);
415 ecc_isr &= XP_IOREAD(pdata, XP_ECC_IER);
416 netif_dbg(pdata, intr, pdata->netdev, "ECC_ISR=%#010x\n", ecc_isr);
417
418 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, TX_DED)) {
419 stop |= xgbe_ecc_ded(pdata, &pdata->tx_ded_period,
420 &pdata->tx_ded_count, "TX fifo");
421 }
422
423 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, RX_DED)) {
424 stop |= xgbe_ecc_ded(pdata, &pdata->rx_ded_period,
425 &pdata->rx_ded_count, "RX fifo");
426 }
427
428 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, DESC_DED)) {
429 stop |= xgbe_ecc_ded(pdata, &pdata->desc_ded_period,
430 &pdata->desc_ded_count,
431 "descriptor cache");
432 }
433
434 if (stop) {
435 pdata->hw_if.disable_ecc_ded(pdata);
436 schedule_work(&pdata->stopdev_work);
437 goto out;
438 }
439
440 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, TX_SEC)) {
441 if (xgbe_ecc_sec(pdata, &pdata->tx_sec_period,
442 &pdata->tx_sec_count, "TX fifo"))
443 pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_TX);
444 }
445
446 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, RX_SEC))
447 if (xgbe_ecc_sec(pdata, &pdata->rx_sec_period,
448 &pdata->rx_sec_count, "RX fifo"))
449 pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_RX);
450
451 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, DESC_SEC))
452 if (xgbe_ecc_sec(pdata, &pdata->desc_sec_period,
453 &pdata->desc_sec_count, "descriptor cache"))
454 pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_DESC);
455
456 out:
457 /* Clear all ECC interrupts */
458 XP_IOWRITE(pdata, XP_ECC_ISR, ecc_isr);
459
460 /* Reissue interrupt if status is not clear */
461 if (pdata->vdata->irq_reissue_support)
462 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 1);
463 }
464
465 static irqreturn_t xgbe_ecc_isr(int irq, void *data)
466 {
467 struct xgbe_prv_data *pdata = data;
468
469 if (pdata->isr_as_tasklet)
470 tasklet_schedule(&pdata->tasklet_ecc);
471 else
472 xgbe_ecc_isr_task((unsigned long)pdata);
473
474 return IRQ_HANDLED;
475 }
476
477 static void xgbe_isr_task(unsigned long data)
478 {
479 struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
480 struct xgbe_hw_if *hw_if = &pdata->hw_if;
481 struct xgbe_channel *channel;
482 unsigned int dma_isr, dma_ch_isr;
483 unsigned int mac_isr, mac_tssr, mac_mdioisr;
484 unsigned int i;
485
486 /* The DMA interrupt status register also reports MAC and MTL
487 * interrupts. So for polling mode, we just need to check for
488 * this register to be non-zero
489 */
490 dma_isr = XGMAC_IOREAD(pdata, DMA_ISR);
491 if (!dma_isr)
492 goto isr_done;
493
494 netif_dbg(pdata, intr, pdata->netdev, "DMA_ISR=%#010x\n", dma_isr);
495
496 for (i = 0; i < pdata->channel_count; i++) {
497 if (!(dma_isr & (1 << i)))
498 continue;
499
500 channel = pdata->channel[i];
501
502 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
503 netif_dbg(pdata, intr, pdata->netdev, "DMA_CH%u_ISR=%#010x\n",
504 i, dma_ch_isr);
505
506 /* The TI or RI interrupt bits may still be set even if using
507 * per channel DMA interrupts. Check to be sure those are not
508 * enabled before using the private data napi structure.
509 */
510 if (!pdata->per_channel_irq &&
511 (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) ||
512 XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI))) {
513 if (napi_schedule_prep(&pdata->napi)) {
514 /* Disable Tx and Rx interrupts */
515 xgbe_disable_rx_tx_ints(pdata);
516
517 /* Turn on polling */
518 __napi_schedule_irqoff(&pdata->napi);
519 }
520 } else {
521 /* Don't clear Rx/Tx status if doing per channel DMA
522 * interrupts, these will be cleared by the ISR for
523 * per channel DMA interrupts.
524 */
525 XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, TI, 0);
526 XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, RI, 0);
527 }
528
529 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RBU))
530 pdata->ext_stats.rx_buffer_unavailable++;
531
532 /* Restart the device on a Fatal Bus Error */
533 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE))
534 schedule_work(&pdata->restart_work);
535
536 /* Clear interrupt signals */
537 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
538 }
539
540 if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) {
541 mac_isr = XGMAC_IOREAD(pdata, MAC_ISR);
542
543 netif_dbg(pdata, intr, pdata->netdev, "MAC_ISR=%#010x\n",
544 mac_isr);
545
546 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS))
547 hw_if->tx_mmc_int(pdata);
548
549 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS))
550 hw_if->rx_mmc_int(pdata);
551
552 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, TSIS)) {
553 mac_tssr = XGMAC_IOREAD(pdata, MAC_TSSR);
554
555 netif_dbg(pdata, intr, pdata->netdev,
556 "MAC_TSSR=%#010x\n", mac_tssr);
557
558 if (XGMAC_GET_BITS(mac_tssr, MAC_TSSR, TXTSC)) {
559 /* Read Tx Timestamp to clear interrupt */
560 pdata->tx_tstamp =
561 hw_if->get_tx_tstamp(pdata);
562 queue_work(pdata->dev_workqueue,
563 &pdata->tx_tstamp_work);
564 }
565 }
566
567 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, SMI)) {
568 mac_mdioisr = XGMAC_IOREAD(pdata, MAC_MDIOISR);
569
570 netif_dbg(pdata, intr, pdata->netdev,
571 "MAC_MDIOISR=%#010x\n", mac_mdioisr);
572
573 if (XGMAC_GET_BITS(mac_mdioisr, MAC_MDIOISR,
574 SNGLCOMPINT))
575 complete(&pdata->mdio_complete);
576 }
577 }
578
579 isr_done:
580 /* If there is not a separate AN irq, handle it here */
581 if (pdata->dev_irq == pdata->an_irq)
582 pdata->phy_if.an_isr(pdata);
583
584 /* If there is not a separate ECC irq, handle it here */
585 if (pdata->vdata->ecc_support && (pdata->dev_irq == pdata->ecc_irq))
586 xgbe_ecc_isr_task((unsigned long)pdata);
587
588 /* If there is not a separate I2C irq, handle it here */
589 if (pdata->vdata->i2c_support && (pdata->dev_irq == pdata->i2c_irq))
590 pdata->i2c_if.i2c_isr(pdata);
591
592 /* Reissue interrupt if status is not clear */
593 if (pdata->vdata->irq_reissue_support) {
594 unsigned int reissue_mask;
595
596 reissue_mask = 1 << 0;
597 if (!pdata->per_channel_irq)
598 reissue_mask |= 0xffff << 4;
599
600 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, reissue_mask);
601 }
602 }
603
604 static irqreturn_t xgbe_isr(int irq, void *data)
605 {
606 struct xgbe_prv_data *pdata = data;
607
608 if (pdata->isr_as_tasklet)
609 tasklet_schedule(&pdata->tasklet_dev);
610 else
611 xgbe_isr_task((unsigned long)pdata);
612
613 return IRQ_HANDLED;
614 }
615
616 static irqreturn_t xgbe_dma_isr(int irq, void *data)
617 {
618 struct xgbe_channel *channel = data;
619 struct xgbe_prv_data *pdata = channel->pdata;
620 unsigned int dma_status;
621
622 /* Per channel DMA interrupts are enabled, so we use the per
623 * channel napi structure and not the private data napi structure
624 */
625 if (napi_schedule_prep(&channel->napi)) {
626 /* Disable Tx and Rx interrupts */
627 if (pdata->channel_irq_mode)
628 xgbe_disable_rx_tx_int(pdata, channel);
629 else
630 disable_irq_nosync(channel->dma_irq);
631
632 /* Turn on polling */
633 __napi_schedule_irqoff(&channel->napi);
634 }
635
636 /* Clear Tx/Rx signals */
637 dma_status = 0;
638 XGMAC_SET_BITS(dma_status, DMA_CH_SR, TI, 1);
639 XGMAC_SET_BITS(dma_status, DMA_CH_SR, RI, 1);
640 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_status);
641
642 return IRQ_HANDLED;
643 }
644
645 static void xgbe_tx_timer(struct timer_list *t)
646 {
647 struct xgbe_channel *channel = from_timer(channel, t, tx_timer);
648 struct xgbe_prv_data *pdata = channel->pdata;
649 struct napi_struct *napi;
650
651 DBGPR("-->xgbe_tx_timer\n");
652
653 napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
654
655 if (napi_schedule_prep(napi)) {
656 /* Disable Tx and Rx interrupts */
657 if (pdata->per_channel_irq)
658 if (pdata->channel_irq_mode)
659 xgbe_disable_rx_tx_int(pdata, channel);
660 else
661 disable_irq_nosync(channel->dma_irq);
662 else
663 xgbe_disable_rx_tx_ints(pdata);
664
665 /* Turn on polling */
666 __napi_schedule(napi);
667 }
668
669 channel->tx_timer_active = 0;
670
671 DBGPR("<--xgbe_tx_timer\n");
672 }
673
674 static void xgbe_service(struct work_struct *work)
675 {
676 struct xgbe_prv_data *pdata = container_of(work,
677 struct xgbe_prv_data,
678 service_work);
679
680 pdata->phy_if.phy_status(pdata);
681 }
682
683 static void xgbe_service_timer(struct timer_list *t)
684 {
685 struct xgbe_prv_data *pdata = from_timer(pdata, t, service_timer);
686
687 queue_work(pdata->dev_workqueue, &pdata->service_work);
688
689 mod_timer(&pdata->service_timer, jiffies + HZ);
690 }
691
692 static void xgbe_init_timers(struct xgbe_prv_data *pdata)
693 {
694 struct xgbe_channel *channel;
695 unsigned int i;
696
697 timer_setup(&pdata->service_timer, xgbe_service_timer, 0);
698
699 for (i = 0; i < pdata->channel_count; i++) {
700 channel = pdata->channel[i];
701 if (!channel->tx_ring)
702 break;
703
704 timer_setup(&channel->tx_timer, xgbe_tx_timer, 0);
705 }
706 }
707
708 static void xgbe_start_timers(struct xgbe_prv_data *pdata)
709 {
710 mod_timer(&pdata->service_timer, jiffies + HZ);
711 }
712
713 static void xgbe_stop_timers(struct xgbe_prv_data *pdata)
714 {
715 struct xgbe_channel *channel;
716 unsigned int i;
717
718 del_timer_sync(&pdata->service_timer);
719
720 for (i = 0; i < pdata->channel_count; i++) {
721 channel = pdata->channel[i];
722 if (!channel->tx_ring)
723 break;
724
725 del_timer_sync(&channel->tx_timer);
726 }
727 }
728
729 void xgbe_get_all_hw_features(struct xgbe_prv_data *pdata)
730 {
731 unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
732 struct xgbe_hw_features *hw_feat = &pdata->hw_feat;
733
734 mac_hfr0 = XGMAC_IOREAD(pdata, MAC_HWF0R);
735 mac_hfr1 = XGMAC_IOREAD(pdata, MAC_HWF1R);
736 mac_hfr2 = XGMAC_IOREAD(pdata, MAC_HWF2R);
737
738 memset(hw_feat, 0, sizeof(*hw_feat));
739
740 hw_feat->version = XGMAC_IOREAD(pdata, MAC_VR);
741
742 /* Hardware feature register 0 */
743 hw_feat->gmii = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL);
744 hw_feat->vlhash = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH);
745 hw_feat->sma = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL);
746 hw_feat->rwk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL);
747 hw_feat->mgk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL);
748 hw_feat->mmc = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL);
749 hw_feat->aoe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL);
750 hw_feat->ts = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL);
751 hw_feat->eee = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL);
752 hw_feat->tx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL);
753 hw_feat->rx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL);
754 hw_feat->addn_mac = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R,
755 ADDMACADRSEL);
756 hw_feat->ts_src = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL);
757 hw_feat->sa_vlan_ins = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS);
758 hw_feat->vxn = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VXN);
759
760 /* Hardware feature register 1 */
761 hw_feat->rx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
762 RXFIFOSIZE);
763 hw_feat->tx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
764 TXFIFOSIZE);
765 hw_feat->adv_ts_hi = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADVTHWORD);
766 hw_feat->dma_width = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64);
767 hw_feat->dcb = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN);
768 hw_feat->sph = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN);
769 hw_feat->tso = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN);
770 hw_feat->dma_debug = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA);
771 hw_feat->rss = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN);
772 hw_feat->tc_cnt = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC);
773 hw_feat->hash_table_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
774 HASHTBLSZ);
775 hw_feat->l3l4_filter_num = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
776 L3L4FNUM);
777
778 /* Hardware feature register 2 */
779 hw_feat->rx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT);
780 hw_feat->tx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT);
781 hw_feat->rx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT);
782 hw_feat->tx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT);
783 hw_feat->pps_out_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM);
784 hw_feat->aux_snap_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, AUXSNAPNUM);
785
786 /* Translate the Hash Table size into actual number */
787 switch (hw_feat->hash_table_size) {
788 case 0:
789 break;
790 case 1:
791 hw_feat->hash_table_size = 64;
792 break;
793 case 2:
794 hw_feat->hash_table_size = 128;
795 break;
796 case 3:
797 hw_feat->hash_table_size = 256;
798 break;
799 }
800
801 /* Translate the address width setting into actual number */
802 switch (hw_feat->dma_width) {
803 case 0:
804 hw_feat->dma_width = 32;
805 break;
806 case 1:
807 hw_feat->dma_width = 40;
808 break;
809 case 2:
810 hw_feat->dma_width = 48;
811 break;
812 default:
813 hw_feat->dma_width = 32;
814 }
815
816 /* The Queue, Channel and TC counts are zero based so increment them
817 * to get the actual number
818 */
819 hw_feat->rx_q_cnt++;
820 hw_feat->tx_q_cnt++;
821 hw_feat->rx_ch_cnt++;
822 hw_feat->tx_ch_cnt++;
823 hw_feat->tc_cnt++;
824
825 /* Translate the fifo sizes into actual numbers */
826 hw_feat->rx_fifo_size = 1 << (hw_feat->rx_fifo_size + 7);
827 hw_feat->tx_fifo_size = 1 << (hw_feat->tx_fifo_size + 7);
828
829 if (netif_msg_probe(pdata)) {
830 dev_dbg(pdata->dev, "Hardware features:\n");
831
832 /* Hardware feature register 0 */
833 dev_dbg(pdata->dev, " 1GbE support : %s\n",
834 hw_feat->gmii ? "yes" : "no");
835 dev_dbg(pdata->dev, " VLAN hash filter : %s\n",
836 hw_feat->vlhash ? "yes" : "no");
837 dev_dbg(pdata->dev, " MDIO interface : %s\n",
838 hw_feat->sma ? "yes" : "no");
839 dev_dbg(pdata->dev, " Wake-up packet support : %s\n",
840 hw_feat->rwk ? "yes" : "no");
841 dev_dbg(pdata->dev, " Magic packet support : %s\n",
842 hw_feat->mgk ? "yes" : "no");
843 dev_dbg(pdata->dev, " Management counters : %s\n",
844 hw_feat->mmc ? "yes" : "no");
845 dev_dbg(pdata->dev, " ARP offload : %s\n",
846 hw_feat->aoe ? "yes" : "no");
847 dev_dbg(pdata->dev, " IEEE 1588-2008 Timestamp : %s\n",
848 hw_feat->ts ? "yes" : "no");
849 dev_dbg(pdata->dev, " Energy Efficient Ethernet : %s\n",
850 hw_feat->eee ? "yes" : "no");
851 dev_dbg(pdata->dev, " TX checksum offload : %s\n",
852 hw_feat->tx_coe ? "yes" : "no");
853 dev_dbg(pdata->dev, " RX checksum offload : %s\n",
854 hw_feat->rx_coe ? "yes" : "no");
855 dev_dbg(pdata->dev, " Additional MAC addresses : %u\n",
856 hw_feat->addn_mac);
857 dev_dbg(pdata->dev, " Timestamp source : %s\n",
858 (hw_feat->ts_src == 1) ? "internal" :
859 (hw_feat->ts_src == 2) ? "external" :
860 (hw_feat->ts_src == 3) ? "internal/external" : "n/a");
861 dev_dbg(pdata->dev, " SA/VLAN insertion : %s\n",
862 hw_feat->sa_vlan_ins ? "yes" : "no");
863 dev_dbg(pdata->dev, " VXLAN/NVGRE support : %s\n",
864 hw_feat->vxn ? "yes" : "no");
865
866 /* Hardware feature register 1 */
867 dev_dbg(pdata->dev, " RX fifo size : %u\n",
868 hw_feat->rx_fifo_size);
869 dev_dbg(pdata->dev, " TX fifo size : %u\n",
870 hw_feat->tx_fifo_size);
871 dev_dbg(pdata->dev, " IEEE 1588 high word : %s\n",
872 hw_feat->adv_ts_hi ? "yes" : "no");
873 dev_dbg(pdata->dev, " DMA width : %u\n",
874 hw_feat->dma_width);
875 dev_dbg(pdata->dev, " Data Center Bridging : %s\n",
876 hw_feat->dcb ? "yes" : "no");
877 dev_dbg(pdata->dev, " Split header : %s\n",
878 hw_feat->sph ? "yes" : "no");
879 dev_dbg(pdata->dev, " TCP Segmentation Offload : %s\n",
880 hw_feat->tso ? "yes" : "no");
881 dev_dbg(pdata->dev, " Debug memory interface : %s\n",
882 hw_feat->dma_debug ? "yes" : "no");
883 dev_dbg(pdata->dev, " Receive Side Scaling : %s\n",
884 hw_feat->rss ? "yes" : "no");
885 dev_dbg(pdata->dev, " Traffic Class count : %u\n",
886 hw_feat->tc_cnt);
887 dev_dbg(pdata->dev, " Hash table size : %u\n",
888 hw_feat->hash_table_size);
889 dev_dbg(pdata->dev, " L3/L4 Filters : %u\n",
890 hw_feat->l3l4_filter_num);
891
892 /* Hardware feature register 2 */
893 dev_dbg(pdata->dev, " RX queue count : %u\n",
894 hw_feat->rx_q_cnt);
895 dev_dbg(pdata->dev, " TX queue count : %u\n",
896 hw_feat->tx_q_cnt);
897 dev_dbg(pdata->dev, " RX DMA channel count : %u\n",
898 hw_feat->rx_ch_cnt);
899 dev_dbg(pdata->dev, " TX DMA channel count : %u\n",
900 hw_feat->rx_ch_cnt);
901 dev_dbg(pdata->dev, " PPS outputs : %u\n",
902 hw_feat->pps_out_num);
903 dev_dbg(pdata->dev, " Auxiliary snapshot inputs : %u\n",
904 hw_feat->aux_snap_num);
905 }
906 }
907
908 static void xgbe_disable_vxlan_offloads(struct xgbe_prv_data *pdata)
909 {
910 struct net_device *netdev = pdata->netdev;
911
912 if (!pdata->vxlan_offloads_set)
913 return;
914
915 netdev_info(netdev, "disabling VXLAN offloads\n");
916
917 netdev->hw_enc_features &= ~(NETIF_F_SG |
918 NETIF_F_IP_CSUM |
919 NETIF_F_IPV6_CSUM |
920 NETIF_F_RXCSUM |
921 NETIF_F_TSO |
922 NETIF_F_TSO6 |
923 NETIF_F_GRO |
924 NETIF_F_GSO_UDP_TUNNEL |
925 NETIF_F_GSO_UDP_TUNNEL_CSUM);
926
927 netdev->features &= ~(NETIF_F_GSO_UDP_TUNNEL |
928 NETIF_F_GSO_UDP_TUNNEL_CSUM);
929
930 pdata->vxlan_offloads_set = 0;
931 }
932
933 static void xgbe_disable_vxlan_hw(struct xgbe_prv_data *pdata)
934 {
935 if (!pdata->vxlan_port_set)
936 return;
937
938 pdata->hw_if.disable_vxlan(pdata);
939
940 pdata->vxlan_port_set = 0;
941 pdata->vxlan_port = 0;
942 }
943
944 static void xgbe_disable_vxlan_accel(struct xgbe_prv_data *pdata)
945 {
946 xgbe_disable_vxlan_offloads(pdata);
947
948 xgbe_disable_vxlan_hw(pdata);
949 }
950
951 static void xgbe_enable_vxlan_offloads(struct xgbe_prv_data *pdata)
952 {
953 struct net_device *netdev = pdata->netdev;
954
955 if (pdata->vxlan_offloads_set)
956 return;
957
958 netdev_info(netdev, "enabling VXLAN offloads\n");
959
960 netdev->hw_enc_features |= NETIF_F_SG |
961 NETIF_F_IP_CSUM |
962 NETIF_F_IPV6_CSUM |
963 NETIF_F_RXCSUM |
964 NETIF_F_TSO |
965 NETIF_F_TSO6 |
966 NETIF_F_GRO |
967 pdata->vxlan_features;
968
969 netdev->features |= pdata->vxlan_features;
970
971 pdata->vxlan_offloads_set = 1;
972 }
973
974 static void xgbe_enable_vxlan_hw(struct xgbe_prv_data *pdata)
975 {
976 struct xgbe_vxlan_data *vdata;
977
978 if (pdata->vxlan_port_set)
979 return;
980
981 if (list_empty(&pdata->vxlan_ports))
982 return;
983
984 vdata = list_first_entry(&pdata->vxlan_ports,
985 struct xgbe_vxlan_data, list);
986
987 pdata->vxlan_port_set = 1;
988 pdata->vxlan_port = be16_to_cpu(vdata->port);
989
990 pdata->hw_if.enable_vxlan(pdata);
991 }
992
993 static void xgbe_enable_vxlan_accel(struct xgbe_prv_data *pdata)
994 {
995 /* VXLAN acceleration desired? */
996 if (!pdata->vxlan_features)
997 return;
998
999 /* VXLAN acceleration possible? */
1000 if (pdata->vxlan_force_disable)
1001 return;
1002
1003 xgbe_enable_vxlan_hw(pdata);
1004
1005 xgbe_enable_vxlan_offloads(pdata);
1006 }
1007
1008 static void xgbe_reset_vxlan_accel(struct xgbe_prv_data *pdata)
1009 {
1010 xgbe_disable_vxlan_hw(pdata);
1011
1012 if (pdata->vxlan_features)
1013 xgbe_enable_vxlan_offloads(pdata);
1014
1015 pdata->vxlan_force_disable = 0;
1016 }
1017
1018 static void xgbe_napi_enable(struct xgbe_prv_data *pdata, unsigned int add)
1019 {
1020 struct xgbe_channel *channel;
1021 unsigned int i;
1022
1023 if (pdata->per_channel_irq) {
1024 for (i = 0; i < pdata->channel_count; i++) {
1025 channel = pdata->channel[i];
1026 if (add)
1027 netif_napi_add(pdata->netdev, &channel->napi,
1028 xgbe_one_poll, NAPI_POLL_WEIGHT);
1029
1030 napi_enable(&channel->napi);
1031 }
1032 } else {
1033 if (add)
1034 netif_napi_add(pdata->netdev, &pdata->napi,
1035 xgbe_all_poll, NAPI_POLL_WEIGHT);
1036
1037 napi_enable(&pdata->napi);
1038 }
1039 }
1040
1041 static void xgbe_napi_disable(struct xgbe_prv_data *pdata, unsigned int del)
1042 {
1043 struct xgbe_channel *channel;
1044 unsigned int i;
1045
1046 if (pdata->per_channel_irq) {
1047 for (i = 0; i < pdata->channel_count; i++) {
1048 channel = pdata->channel[i];
1049 napi_disable(&channel->napi);
1050
1051 if (del)
1052 netif_napi_del(&channel->napi);
1053 }
1054 } else {
1055 napi_disable(&pdata->napi);
1056
1057 if (del)
1058 netif_napi_del(&pdata->napi);
1059 }
1060 }
1061
1062 static int xgbe_request_irqs(struct xgbe_prv_data *pdata)
1063 {
1064 struct xgbe_channel *channel;
1065 struct net_device *netdev = pdata->netdev;
1066 unsigned int i;
1067 int ret;
1068
1069 tasklet_init(&pdata->tasklet_dev, xgbe_isr_task, (unsigned long)pdata);
1070 tasklet_init(&pdata->tasklet_ecc, xgbe_ecc_isr_task,
1071 (unsigned long)pdata);
1072
1073 ret = devm_request_irq(pdata->dev, pdata->dev_irq, xgbe_isr, 0,
1074 netdev_name(netdev), pdata);
1075 if (ret) {
1076 netdev_alert(netdev, "error requesting irq %d\n",
1077 pdata->dev_irq);
1078 return ret;
1079 }
1080
1081 if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq)) {
1082 ret = devm_request_irq(pdata->dev, pdata->ecc_irq, xgbe_ecc_isr,
1083 0, pdata->ecc_name, pdata);
1084 if (ret) {
1085 netdev_alert(netdev, "error requesting ecc irq %d\n",
1086 pdata->ecc_irq);
1087 goto err_dev_irq;
1088 }
1089 }
1090
1091 if (!pdata->per_channel_irq)
1092 return 0;
1093
1094 for (i = 0; i < pdata->channel_count; i++) {
1095 channel = pdata->channel[i];
1096 snprintf(channel->dma_irq_name,
1097 sizeof(channel->dma_irq_name) - 1,
1098 "%s-TxRx-%u", netdev_name(netdev),
1099 channel->queue_index);
1100
1101 ret = devm_request_irq(pdata->dev, channel->dma_irq,
1102 xgbe_dma_isr, 0,
1103 channel->dma_irq_name, channel);
1104 if (ret) {
1105 netdev_alert(netdev, "error requesting irq %d\n",
1106 channel->dma_irq);
1107 goto err_dma_irq;
1108 }
1109
1110 irq_set_affinity_hint(channel->dma_irq,
1111 &channel->affinity_mask);
1112 }
1113
1114 return 0;
1115
1116 err_dma_irq:
1117 /* Using an unsigned int, 'i' will go to UINT_MAX and exit */
1118 for (i--; i < pdata->channel_count; i--) {
1119 channel = pdata->channel[i];
1120
1121 irq_set_affinity_hint(channel->dma_irq, NULL);
1122 devm_free_irq(pdata->dev, channel->dma_irq, channel);
1123 }
1124
1125 if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq))
1126 devm_free_irq(pdata->dev, pdata->ecc_irq, pdata);
1127
1128 err_dev_irq:
1129 devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
1130
1131 return ret;
1132 }
1133
1134 static void xgbe_free_irqs(struct xgbe_prv_data *pdata)
1135 {
1136 struct xgbe_channel *channel;
1137 unsigned int i;
1138
1139 devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
1140
1141 if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq))
1142 devm_free_irq(pdata->dev, pdata->ecc_irq, pdata);
1143
1144 if (!pdata->per_channel_irq)
1145 return;
1146
1147 for (i = 0; i < pdata->channel_count; i++) {
1148 channel = pdata->channel[i];
1149
1150 irq_set_affinity_hint(channel->dma_irq, NULL);
1151 devm_free_irq(pdata->dev, channel->dma_irq, channel);
1152 }
1153 }
1154
1155 void xgbe_init_tx_coalesce(struct xgbe_prv_data *pdata)
1156 {
1157 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1158
1159 DBGPR("-->xgbe_init_tx_coalesce\n");
1160
1161 pdata->tx_usecs = XGMAC_INIT_DMA_TX_USECS;
1162 pdata->tx_frames = XGMAC_INIT_DMA_TX_FRAMES;
1163
1164 hw_if->config_tx_coalesce(pdata);
1165
1166 DBGPR("<--xgbe_init_tx_coalesce\n");
1167 }
1168
1169 void xgbe_init_rx_coalesce(struct xgbe_prv_data *pdata)
1170 {
1171 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1172
1173 DBGPR("-->xgbe_init_rx_coalesce\n");
1174
1175 pdata->rx_riwt = hw_if->usec_to_riwt(pdata, XGMAC_INIT_DMA_RX_USECS);
1176 pdata->rx_usecs = XGMAC_INIT_DMA_RX_USECS;
1177 pdata->rx_frames = XGMAC_INIT_DMA_RX_FRAMES;
1178
1179 hw_if->config_rx_coalesce(pdata);
1180
1181 DBGPR("<--xgbe_init_rx_coalesce\n");
1182 }
1183
1184 static void xgbe_free_tx_data(struct xgbe_prv_data *pdata)
1185 {
1186 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1187 struct xgbe_ring *ring;
1188 struct xgbe_ring_data *rdata;
1189 unsigned int i, j;
1190
1191 DBGPR("-->xgbe_free_tx_data\n");
1192
1193 for (i = 0; i < pdata->channel_count; i++) {
1194 ring = pdata->channel[i]->tx_ring;
1195 if (!ring)
1196 break;
1197
1198 for (j = 0; j < ring->rdesc_count; j++) {
1199 rdata = XGBE_GET_DESC_DATA(ring, j);
1200 desc_if->unmap_rdata(pdata, rdata);
1201 }
1202 }
1203
1204 DBGPR("<--xgbe_free_tx_data\n");
1205 }
1206
1207 static void xgbe_free_rx_data(struct xgbe_prv_data *pdata)
1208 {
1209 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1210 struct xgbe_ring *ring;
1211 struct xgbe_ring_data *rdata;
1212 unsigned int i, j;
1213
1214 DBGPR("-->xgbe_free_rx_data\n");
1215
1216 for (i = 0; i < pdata->channel_count; i++) {
1217 ring = pdata->channel[i]->rx_ring;
1218 if (!ring)
1219 break;
1220
1221 for (j = 0; j < ring->rdesc_count; j++) {
1222 rdata = XGBE_GET_DESC_DATA(ring, j);
1223 desc_if->unmap_rdata(pdata, rdata);
1224 }
1225 }
1226
1227 DBGPR("<--xgbe_free_rx_data\n");
1228 }
1229
1230 static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
1231 {
1232 pdata->phy_link = -1;
1233 pdata->phy_speed = SPEED_UNKNOWN;
1234
1235 return pdata->phy_if.phy_reset(pdata);
1236 }
1237
1238 int xgbe_powerdown(struct net_device *netdev, unsigned int caller)
1239 {
1240 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1241 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1242 unsigned long flags;
1243
1244 DBGPR("-->xgbe_powerdown\n");
1245
1246 if (!netif_running(netdev) ||
1247 (caller == XGMAC_IOCTL_CONTEXT && pdata->power_down)) {
1248 netdev_alert(netdev, "Device is already powered down\n");
1249 DBGPR("<--xgbe_powerdown\n");
1250 return -EINVAL;
1251 }
1252
1253 spin_lock_irqsave(&pdata->lock, flags);
1254
1255 if (caller == XGMAC_DRIVER_CONTEXT)
1256 netif_device_detach(netdev);
1257
1258 netif_tx_stop_all_queues(netdev);
1259
1260 xgbe_stop_timers(pdata);
1261 flush_workqueue(pdata->dev_workqueue);
1262
1263 hw_if->powerdown_tx(pdata);
1264 hw_if->powerdown_rx(pdata);
1265
1266 xgbe_napi_disable(pdata, 0);
1267
1268 pdata->power_down = 1;
1269
1270 spin_unlock_irqrestore(&pdata->lock, flags);
1271
1272 DBGPR("<--xgbe_powerdown\n");
1273
1274 return 0;
1275 }
1276
1277 int xgbe_powerup(struct net_device *netdev, unsigned int caller)
1278 {
1279 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1280 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1281 unsigned long flags;
1282
1283 DBGPR("-->xgbe_powerup\n");
1284
1285 if (!netif_running(netdev) ||
1286 (caller == XGMAC_IOCTL_CONTEXT && !pdata->power_down)) {
1287 netdev_alert(netdev, "Device is already powered up\n");
1288 DBGPR("<--xgbe_powerup\n");
1289 return -EINVAL;
1290 }
1291
1292 spin_lock_irqsave(&pdata->lock, flags);
1293
1294 pdata->power_down = 0;
1295
1296 xgbe_napi_enable(pdata, 0);
1297
1298 hw_if->powerup_tx(pdata);
1299 hw_if->powerup_rx(pdata);
1300
1301 if (caller == XGMAC_DRIVER_CONTEXT)
1302 netif_device_attach(netdev);
1303
1304 netif_tx_start_all_queues(netdev);
1305
1306 xgbe_start_timers(pdata);
1307
1308 spin_unlock_irqrestore(&pdata->lock, flags);
1309
1310 DBGPR("<--xgbe_powerup\n");
1311
1312 return 0;
1313 }
1314
1315 static int xgbe_start(struct xgbe_prv_data *pdata)
1316 {
1317 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1318 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1319 struct net_device *netdev = pdata->netdev;
1320 int ret;
1321
1322 DBGPR("-->xgbe_start\n");
1323
1324 ret = hw_if->init(pdata);
1325 if (ret)
1326 return ret;
1327
1328 xgbe_napi_enable(pdata, 1);
1329
1330 ret = xgbe_request_irqs(pdata);
1331 if (ret)
1332 goto err_napi;
1333
1334 ret = phy_if->phy_start(pdata);
1335 if (ret)
1336 goto err_irqs;
1337
1338 hw_if->enable_tx(pdata);
1339 hw_if->enable_rx(pdata);
1340
1341 udp_tunnel_get_rx_info(netdev);
1342
1343 netif_tx_start_all_queues(netdev);
1344
1345 xgbe_start_timers(pdata);
1346 queue_work(pdata->dev_workqueue, &pdata->service_work);
1347
1348 clear_bit(XGBE_STOPPED, &pdata->dev_state);
1349
1350 DBGPR("<--xgbe_start\n");
1351
1352 return 0;
1353
1354 err_irqs:
1355 xgbe_free_irqs(pdata);
1356
1357 err_napi:
1358 xgbe_napi_disable(pdata, 1);
1359
1360 hw_if->exit(pdata);
1361
1362 return ret;
1363 }
1364
1365 static void xgbe_stop(struct xgbe_prv_data *pdata)
1366 {
1367 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1368 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1369 struct xgbe_channel *channel;
1370 struct net_device *netdev = pdata->netdev;
1371 struct netdev_queue *txq;
1372 unsigned int i;
1373
1374 DBGPR("-->xgbe_stop\n");
1375
1376 if (test_bit(XGBE_STOPPED, &pdata->dev_state))
1377 return;
1378
1379 netif_tx_stop_all_queues(netdev);
1380
1381 xgbe_stop_timers(pdata);
1382 flush_workqueue(pdata->dev_workqueue);
1383
1384 xgbe_reset_vxlan_accel(pdata);
1385
1386 hw_if->disable_tx(pdata);
1387 hw_if->disable_rx(pdata);
1388
1389 phy_if->phy_stop(pdata);
1390
1391 xgbe_free_irqs(pdata);
1392
1393 xgbe_napi_disable(pdata, 1);
1394
1395 hw_if->exit(pdata);
1396
1397 for (i = 0; i < pdata->channel_count; i++) {
1398 channel = pdata->channel[i];
1399 if (!channel->tx_ring)
1400 continue;
1401
1402 txq = netdev_get_tx_queue(netdev, channel->queue_index);
1403 netdev_tx_reset_queue(txq);
1404 }
1405
1406 set_bit(XGBE_STOPPED, &pdata->dev_state);
1407
1408 DBGPR("<--xgbe_stop\n");
1409 }
1410
1411 static void xgbe_stopdev(struct work_struct *work)
1412 {
1413 struct xgbe_prv_data *pdata = container_of(work,
1414 struct xgbe_prv_data,
1415 stopdev_work);
1416
1417 rtnl_lock();
1418
1419 xgbe_stop(pdata);
1420
1421 xgbe_free_tx_data(pdata);
1422 xgbe_free_rx_data(pdata);
1423
1424 rtnl_unlock();
1425
1426 netdev_alert(pdata->netdev, "device stopped\n");
1427 }
1428
1429 static void xgbe_restart_dev(struct xgbe_prv_data *pdata)
1430 {
1431 DBGPR("-->xgbe_restart_dev\n");
1432
1433 /* If not running, "restart" will happen on open */
1434 if (!netif_running(pdata->netdev))
1435 return;
1436
1437 xgbe_stop(pdata);
1438
1439 xgbe_free_tx_data(pdata);
1440 xgbe_free_rx_data(pdata);
1441
1442 xgbe_start(pdata);
1443
1444 DBGPR("<--xgbe_restart_dev\n");
1445 }
1446
1447 static void xgbe_restart(struct work_struct *work)
1448 {
1449 struct xgbe_prv_data *pdata = container_of(work,
1450 struct xgbe_prv_data,
1451 restart_work);
1452
1453 rtnl_lock();
1454
1455 xgbe_restart_dev(pdata);
1456
1457 rtnl_unlock();
1458 }
1459
1460 static void xgbe_tx_tstamp(struct work_struct *work)
1461 {
1462 struct xgbe_prv_data *pdata = container_of(work,
1463 struct xgbe_prv_data,
1464 tx_tstamp_work);
1465 struct skb_shared_hwtstamps hwtstamps;
1466 u64 nsec;
1467 unsigned long flags;
1468
1469 spin_lock_irqsave(&pdata->tstamp_lock, flags);
1470 if (!pdata->tx_tstamp_skb)
1471 goto unlock;
1472
1473 if (pdata->tx_tstamp) {
1474 nsec = timecounter_cyc2time(&pdata->tstamp_tc,
1475 pdata->tx_tstamp);
1476
1477 memset(&hwtstamps, 0, sizeof(hwtstamps));
1478 hwtstamps.hwtstamp = ns_to_ktime(nsec);
1479 skb_tstamp_tx(pdata->tx_tstamp_skb, &hwtstamps);
1480 }
1481
1482 dev_kfree_skb_any(pdata->tx_tstamp_skb);
1483
1484 pdata->tx_tstamp_skb = NULL;
1485
1486 unlock:
1487 spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
1488 }
1489
1490 static int xgbe_get_hwtstamp_settings(struct xgbe_prv_data *pdata,
1491 struct ifreq *ifreq)
1492 {
1493 if (copy_to_user(ifreq->ifr_data, &pdata->tstamp_config,
1494 sizeof(pdata->tstamp_config)))
1495 return -EFAULT;
1496
1497 return 0;
1498 }
1499
1500 static int xgbe_set_hwtstamp_settings(struct xgbe_prv_data *pdata,
1501 struct ifreq *ifreq)
1502 {
1503 struct hwtstamp_config config;
1504 unsigned int mac_tscr;
1505
1506 if (copy_from_user(&config, ifreq->ifr_data, sizeof(config)))
1507 return -EFAULT;
1508
1509 if (config.flags)
1510 return -EINVAL;
1511
1512 mac_tscr = 0;
1513
1514 switch (config.tx_type) {
1515 case HWTSTAMP_TX_OFF:
1516 break;
1517
1518 case HWTSTAMP_TX_ON:
1519 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1520 break;
1521
1522 default:
1523 return -ERANGE;
1524 }
1525
1526 switch (config.rx_filter) {
1527 case HWTSTAMP_FILTER_NONE:
1528 break;
1529
1530 case HWTSTAMP_FILTER_NTP_ALL:
1531 case HWTSTAMP_FILTER_ALL:
1532 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1);
1533 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1534 break;
1535
1536 /* PTP v2, UDP, any kind of event packet */
1537 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1538 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1539 /* PTP v1, UDP, any kind of event packet */
1540 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1541 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1542 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1543 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1544 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1545 break;
1546
1547 /* PTP v2, UDP, Sync packet */
1548 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1549 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1550 /* PTP v1, UDP, Sync packet */
1551 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1552 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1553 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1554 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1555 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1556 break;
1557
1558 /* PTP v2, UDP, Delay_req packet */
1559 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1560 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1561 /* PTP v1, UDP, Delay_req packet */
1562 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1563 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1564 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1565 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1566 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1567 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1568 break;
1569
1570 /* 802.AS1, Ethernet, any kind of event packet */
1571 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1572 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1573 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1574 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1575 break;
1576
1577 /* 802.AS1, Ethernet, Sync packet */
1578 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1579 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1580 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1581 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1582 break;
1583
1584 /* 802.AS1, Ethernet, Delay_req packet */
1585 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1586 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1587 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1588 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1589 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1590 break;
1591
1592 /* PTP v2/802.AS1, any layer, any kind of event packet */
1593 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1594 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1595 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1596 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1597 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1598 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1599 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1600 break;
1601
1602 /* PTP v2/802.AS1, any layer, Sync packet */
1603 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1604 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1605 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1606 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1607 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1608 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1609 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1610 break;
1611
1612 /* PTP v2/802.AS1, any layer, Delay_req packet */
1613 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1614 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1615 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1616 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1617 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1618 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1619 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1620 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1621 break;
1622
1623 default:
1624 return -ERANGE;
1625 }
1626
1627 pdata->hw_if.config_tstamp(pdata, mac_tscr);
1628
1629 memcpy(&pdata->tstamp_config, &config, sizeof(config));
1630
1631 return 0;
1632 }
1633
1634 static void xgbe_prep_tx_tstamp(struct xgbe_prv_data *pdata,
1635 struct sk_buff *skb,
1636 struct xgbe_packet_data *packet)
1637 {
1638 unsigned long flags;
1639
1640 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) {
1641 spin_lock_irqsave(&pdata->tstamp_lock, flags);
1642 if (pdata->tx_tstamp_skb) {
1643 /* Another timestamp in progress, ignore this one */
1644 XGMAC_SET_BITS(packet->attributes,
1645 TX_PACKET_ATTRIBUTES, PTP, 0);
1646 } else {
1647 pdata->tx_tstamp_skb = skb_get(skb);
1648 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1649 }
1650 spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
1651 }
1652
1653 skb_tx_timestamp(skb);
1654 }
1655
1656 static void xgbe_prep_vlan(struct sk_buff *skb, struct xgbe_packet_data *packet)
1657 {
1658 if (skb_vlan_tag_present(skb))
1659 packet->vlan_ctag = skb_vlan_tag_get(skb);
1660 }
1661
1662 static int xgbe_prep_tso(struct sk_buff *skb, struct xgbe_packet_data *packet)
1663 {
1664 int ret;
1665
1666 if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1667 TSO_ENABLE))
1668 return 0;
1669
1670 ret = skb_cow_head(skb, 0);
1671 if (ret)
1672 return ret;
1673
1674 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, VXLAN)) {
1675 packet->header_len = skb_inner_transport_offset(skb) +
1676 inner_tcp_hdrlen(skb);
1677 packet->tcp_header_len = inner_tcp_hdrlen(skb);
1678 } else {
1679 packet->header_len = skb_transport_offset(skb) +
1680 tcp_hdrlen(skb);
1681 packet->tcp_header_len = tcp_hdrlen(skb);
1682 }
1683 packet->tcp_payload_len = skb->len - packet->header_len;
1684 packet->mss = skb_shinfo(skb)->gso_size;
1685
1686 DBGPR(" packet->header_len=%u\n", packet->header_len);
1687 DBGPR(" packet->tcp_header_len=%u, packet->tcp_payload_len=%u\n",
1688 packet->tcp_header_len, packet->tcp_payload_len);
1689 DBGPR(" packet->mss=%u\n", packet->mss);
1690
1691 /* Update the number of packets that will ultimately be transmitted
1692 * along with the extra bytes for each extra packet
1693 */
1694 packet->tx_packets = skb_shinfo(skb)->gso_segs;
1695 packet->tx_bytes += (packet->tx_packets - 1) * packet->header_len;
1696
1697 return 0;
1698 }
1699
1700 static bool xgbe_is_vxlan(struct xgbe_prv_data *pdata, struct sk_buff *skb)
1701 {
1702 struct xgbe_vxlan_data *vdata;
1703
1704 if (pdata->vxlan_force_disable)
1705 return false;
1706
1707 if (!skb->encapsulation)
1708 return false;
1709
1710 if (skb->ip_summed != CHECKSUM_PARTIAL)
1711 return false;
1712
1713 switch (skb->protocol) {
1714 case htons(ETH_P_IP):
1715 if (ip_hdr(skb)->protocol != IPPROTO_UDP)
1716 return false;
1717 break;
1718
1719 case htons(ETH_P_IPV6):
1720 if (ipv6_hdr(skb)->nexthdr != IPPROTO_UDP)
1721 return false;
1722 break;
1723
1724 default:
1725 return false;
1726 }
1727
1728 /* See if we have the UDP port in our list */
1729 list_for_each_entry(vdata, &pdata->vxlan_ports, list) {
1730 if ((skb->protocol == htons(ETH_P_IP)) &&
1731 (vdata->sa_family == AF_INET) &&
1732 (vdata->port == udp_hdr(skb)->dest))
1733 return true;
1734 else if ((skb->protocol == htons(ETH_P_IPV6)) &&
1735 (vdata->sa_family == AF_INET6) &&
1736 (vdata->port == udp_hdr(skb)->dest))
1737 return true;
1738 }
1739
1740 return false;
1741 }
1742
1743 static int xgbe_is_tso(struct sk_buff *skb)
1744 {
1745 if (skb->ip_summed != CHECKSUM_PARTIAL)
1746 return 0;
1747
1748 if (!skb_is_gso(skb))
1749 return 0;
1750
1751 DBGPR(" TSO packet to be processed\n");
1752
1753 return 1;
1754 }
1755
1756 static void xgbe_packet_info(struct xgbe_prv_data *pdata,
1757 struct xgbe_ring *ring, struct sk_buff *skb,
1758 struct xgbe_packet_data *packet)
1759 {
1760 struct skb_frag_struct *frag;
1761 unsigned int context_desc;
1762 unsigned int len;
1763 unsigned int i;
1764
1765 packet->skb = skb;
1766
1767 context_desc = 0;
1768 packet->rdesc_count = 0;
1769
1770 packet->tx_packets = 1;
1771 packet->tx_bytes = skb->len;
1772
1773 if (xgbe_is_tso(skb)) {
1774 /* TSO requires an extra descriptor if mss is different */
1775 if (skb_shinfo(skb)->gso_size != ring->tx.cur_mss) {
1776 context_desc = 1;
1777 packet->rdesc_count++;
1778 }
1779
1780 /* TSO requires an extra descriptor for TSO header */
1781 packet->rdesc_count++;
1782
1783 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1784 TSO_ENABLE, 1);
1785 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1786 CSUM_ENABLE, 1);
1787 } else if (skb->ip_summed == CHECKSUM_PARTIAL)
1788 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1789 CSUM_ENABLE, 1);
1790
1791 if (xgbe_is_vxlan(pdata, skb))
1792 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1793 VXLAN, 1);
1794
1795 if (skb_vlan_tag_present(skb)) {
1796 /* VLAN requires an extra descriptor if tag is different */
1797 if (skb_vlan_tag_get(skb) != ring->tx.cur_vlan_ctag)
1798 /* We can share with the TSO context descriptor */
1799 if (!context_desc) {
1800 context_desc = 1;
1801 packet->rdesc_count++;
1802 }
1803
1804 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1805 VLAN_CTAG, 1);
1806 }
1807
1808 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1809 (pdata->tstamp_config.tx_type == HWTSTAMP_TX_ON))
1810 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1811 PTP, 1);
1812
1813 for (len = skb_headlen(skb); len;) {
1814 packet->rdesc_count++;
1815 len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
1816 }
1817
1818 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1819 frag = &skb_shinfo(skb)->frags[i];
1820 for (len = skb_frag_size(frag); len; ) {
1821 packet->rdesc_count++;
1822 len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
1823 }
1824 }
1825 }
1826
1827 static int xgbe_open(struct net_device *netdev)
1828 {
1829 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1830 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1831 int ret;
1832
1833 DBGPR("-->xgbe_open\n");
1834
1835 /* Create the various names based on netdev name */
1836 snprintf(pdata->an_name, sizeof(pdata->an_name) - 1, "%s-pcs",
1837 netdev_name(netdev));
1838
1839 snprintf(pdata->ecc_name, sizeof(pdata->ecc_name) - 1, "%s-ecc",
1840 netdev_name(netdev));
1841
1842 snprintf(pdata->i2c_name, sizeof(pdata->i2c_name) - 1, "%s-i2c",
1843 netdev_name(netdev));
1844
1845 /* Create workqueues */
1846 pdata->dev_workqueue =
1847 create_singlethread_workqueue(netdev_name(netdev));
1848 if (!pdata->dev_workqueue) {
1849 netdev_err(netdev, "device workqueue creation failed\n");
1850 return -ENOMEM;
1851 }
1852
1853 pdata->an_workqueue =
1854 create_singlethread_workqueue(pdata->an_name);
1855 if (!pdata->an_workqueue) {
1856 netdev_err(netdev, "phy workqueue creation failed\n");
1857 ret = -ENOMEM;
1858 goto err_dev_wq;
1859 }
1860
1861 /* Reset the phy settings */
1862 ret = xgbe_phy_reset(pdata);
1863 if (ret)
1864 goto err_an_wq;
1865
1866 /* Enable the clocks */
1867 ret = clk_prepare_enable(pdata->sysclk);
1868 if (ret) {
1869 netdev_alert(netdev, "dma clk_prepare_enable failed\n");
1870 goto err_an_wq;
1871 }
1872
1873 ret = clk_prepare_enable(pdata->ptpclk);
1874 if (ret) {
1875 netdev_alert(netdev, "ptp clk_prepare_enable failed\n");
1876 goto err_sysclk;
1877 }
1878
1879 /* Calculate the Rx buffer size before allocating rings */
1880 ret = xgbe_calc_rx_buf_size(netdev, netdev->mtu);
1881 if (ret < 0)
1882 goto err_ptpclk;
1883 pdata->rx_buf_size = ret;
1884
1885 /* Allocate the channel and ring structures */
1886 ret = xgbe_alloc_channels(pdata);
1887 if (ret)
1888 goto err_ptpclk;
1889
1890 /* Allocate the ring descriptors and buffers */
1891 ret = desc_if->alloc_ring_resources(pdata);
1892 if (ret)
1893 goto err_channels;
1894
1895 INIT_WORK(&pdata->service_work, xgbe_service);
1896 INIT_WORK(&pdata->restart_work, xgbe_restart);
1897 INIT_WORK(&pdata->stopdev_work, xgbe_stopdev);
1898 INIT_WORK(&pdata->tx_tstamp_work, xgbe_tx_tstamp);
1899 xgbe_init_timers(pdata);
1900
1901 ret = xgbe_start(pdata);
1902 if (ret)
1903 goto err_rings;
1904
1905 clear_bit(XGBE_DOWN, &pdata->dev_state);
1906
1907 DBGPR("<--xgbe_open\n");
1908
1909 return 0;
1910
1911 err_rings:
1912 desc_if->free_ring_resources(pdata);
1913
1914 err_channels:
1915 xgbe_free_channels(pdata);
1916
1917 err_ptpclk:
1918 clk_disable_unprepare(pdata->ptpclk);
1919
1920 err_sysclk:
1921 clk_disable_unprepare(pdata->sysclk);
1922
1923 err_an_wq:
1924 destroy_workqueue(pdata->an_workqueue);
1925
1926 err_dev_wq:
1927 destroy_workqueue(pdata->dev_workqueue);
1928
1929 return ret;
1930 }
1931
1932 static int xgbe_close(struct net_device *netdev)
1933 {
1934 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1935 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1936
1937 DBGPR("-->xgbe_close\n");
1938
1939 /* Stop the device */
1940 xgbe_stop(pdata);
1941
1942 /* Free the ring descriptors and buffers */
1943 desc_if->free_ring_resources(pdata);
1944
1945 /* Free the channel and ring structures */
1946 xgbe_free_channels(pdata);
1947
1948 /* Disable the clocks */
1949 clk_disable_unprepare(pdata->ptpclk);
1950 clk_disable_unprepare(pdata->sysclk);
1951
1952 flush_workqueue(pdata->an_workqueue);
1953 destroy_workqueue(pdata->an_workqueue);
1954
1955 flush_workqueue(pdata->dev_workqueue);
1956 destroy_workqueue(pdata->dev_workqueue);
1957
1958 set_bit(XGBE_DOWN, &pdata->dev_state);
1959
1960 DBGPR("<--xgbe_close\n");
1961
1962 return 0;
1963 }
1964
1965 static int xgbe_xmit(struct sk_buff *skb, struct net_device *netdev)
1966 {
1967 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1968 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1969 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1970 struct xgbe_channel *channel;
1971 struct xgbe_ring *ring;
1972 struct xgbe_packet_data *packet;
1973 struct netdev_queue *txq;
1974 int ret;
1975
1976 DBGPR("-->xgbe_xmit: skb->len = %d\n", skb->len);
1977
1978 channel = pdata->channel[skb->queue_mapping];
1979 txq = netdev_get_tx_queue(netdev, channel->queue_index);
1980 ring = channel->tx_ring;
1981 packet = &ring->packet_data;
1982
1983 ret = NETDEV_TX_OK;
1984
1985 if (skb->len == 0) {
1986 netif_err(pdata, tx_err, netdev,
1987 "empty skb received from stack\n");
1988 dev_kfree_skb_any(skb);
1989 goto tx_netdev_return;
1990 }
1991
1992 /* Calculate preliminary packet info */
1993 memset(packet, 0, sizeof(*packet));
1994 xgbe_packet_info(pdata, ring, skb, packet);
1995
1996 /* Check that there are enough descriptors available */
1997 ret = xgbe_maybe_stop_tx_queue(channel, ring, packet->rdesc_count);
1998 if (ret)
1999 goto tx_netdev_return;
2000
2001 ret = xgbe_prep_tso(skb, packet);
2002 if (ret) {
2003 netif_err(pdata, tx_err, netdev,
2004 "error processing TSO packet\n");
2005 dev_kfree_skb_any(skb);
2006 goto tx_netdev_return;
2007 }
2008 xgbe_prep_vlan(skb, packet);
2009
2010 if (!desc_if->map_tx_skb(channel, skb)) {
2011 dev_kfree_skb_any(skb);
2012 goto tx_netdev_return;
2013 }
2014
2015 xgbe_prep_tx_tstamp(pdata, skb, packet);
2016
2017 /* Report on the actual number of bytes (to be) sent */
2018 netdev_tx_sent_queue(txq, packet->tx_bytes);
2019
2020 /* Configure required descriptor fields for transmission */
2021 hw_if->dev_xmit(channel);
2022
2023 if (netif_msg_pktdata(pdata))
2024 xgbe_print_pkt(netdev, skb, true);
2025
2026 /* Stop the queue in advance if there may not be enough descriptors */
2027 xgbe_maybe_stop_tx_queue(channel, ring, XGBE_TX_MAX_DESCS);
2028
2029 ret = NETDEV_TX_OK;
2030
2031 tx_netdev_return:
2032 return ret;
2033 }
2034
2035 static void xgbe_set_rx_mode(struct net_device *netdev)
2036 {
2037 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2038 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2039
2040 DBGPR("-->xgbe_set_rx_mode\n");
2041
2042 hw_if->config_rx_mode(pdata);
2043
2044 DBGPR("<--xgbe_set_rx_mode\n");
2045 }
2046
2047 static int xgbe_set_mac_address(struct net_device *netdev, void *addr)
2048 {
2049 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2050 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2051 struct sockaddr *saddr = addr;
2052
2053 DBGPR("-->xgbe_set_mac_address\n");
2054
2055 if (!is_valid_ether_addr(saddr->sa_data))
2056 return -EADDRNOTAVAIL;
2057
2058 memcpy(netdev->dev_addr, saddr->sa_data, netdev->addr_len);
2059
2060 hw_if->set_mac_address(pdata, netdev->dev_addr);
2061
2062 DBGPR("<--xgbe_set_mac_address\n");
2063
2064 return 0;
2065 }
2066
2067 static int xgbe_ioctl(struct net_device *netdev, struct ifreq *ifreq, int cmd)
2068 {
2069 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2070 int ret;
2071
2072 switch (cmd) {
2073 case SIOCGHWTSTAMP:
2074 ret = xgbe_get_hwtstamp_settings(pdata, ifreq);
2075 break;
2076
2077 case SIOCSHWTSTAMP:
2078 ret = xgbe_set_hwtstamp_settings(pdata, ifreq);
2079 break;
2080
2081 default:
2082 ret = -EOPNOTSUPP;
2083 }
2084
2085 return ret;
2086 }
2087
2088 static int xgbe_change_mtu(struct net_device *netdev, int mtu)
2089 {
2090 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2091 int ret;
2092
2093 DBGPR("-->xgbe_change_mtu\n");
2094
2095 ret = xgbe_calc_rx_buf_size(netdev, mtu);
2096 if (ret < 0)
2097 return ret;
2098
2099 pdata->rx_buf_size = ret;
2100 netdev->mtu = mtu;
2101
2102 xgbe_restart_dev(pdata);
2103
2104 DBGPR("<--xgbe_change_mtu\n");
2105
2106 return 0;
2107 }
2108
2109 static void xgbe_tx_timeout(struct net_device *netdev)
2110 {
2111 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2112
2113 netdev_warn(netdev, "tx timeout, device restarting\n");
2114 schedule_work(&pdata->restart_work);
2115 }
2116
2117 static void xgbe_get_stats64(struct net_device *netdev,
2118 struct rtnl_link_stats64 *s)
2119 {
2120 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2121 struct xgbe_mmc_stats *pstats = &pdata->mmc_stats;
2122
2123 DBGPR("-->%s\n", __func__);
2124
2125 pdata->hw_if.read_mmc_stats(pdata);
2126
2127 s->rx_packets = pstats->rxframecount_gb;
2128 s->rx_bytes = pstats->rxoctetcount_gb;
2129 s->rx_errors = pstats->rxframecount_gb -
2130 pstats->rxbroadcastframes_g -
2131 pstats->rxmulticastframes_g -
2132 pstats->rxunicastframes_g;
2133 s->multicast = pstats->rxmulticastframes_g;
2134 s->rx_length_errors = pstats->rxlengtherror;
2135 s->rx_crc_errors = pstats->rxcrcerror;
2136 s->rx_fifo_errors = pstats->rxfifooverflow;
2137
2138 s->tx_packets = pstats->txframecount_gb;
2139 s->tx_bytes = pstats->txoctetcount_gb;
2140 s->tx_errors = pstats->txframecount_gb - pstats->txframecount_g;
2141 s->tx_dropped = netdev->stats.tx_dropped;
2142
2143 DBGPR("<--%s\n", __func__);
2144 }
2145
2146 static int xgbe_vlan_rx_add_vid(struct net_device *netdev, __be16 proto,
2147 u16 vid)
2148 {
2149 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2150 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2151
2152 DBGPR("-->%s\n", __func__);
2153
2154 set_bit(vid, pdata->active_vlans);
2155 hw_if->update_vlan_hash_table(pdata);
2156
2157 DBGPR("<--%s\n", __func__);
2158
2159 return 0;
2160 }
2161
2162 static int xgbe_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto,
2163 u16 vid)
2164 {
2165 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2166 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2167
2168 DBGPR("-->%s\n", __func__);
2169
2170 clear_bit(vid, pdata->active_vlans);
2171 hw_if->update_vlan_hash_table(pdata);
2172
2173 DBGPR("<--%s\n", __func__);
2174
2175 return 0;
2176 }
2177
2178 #ifdef CONFIG_NET_POLL_CONTROLLER
2179 static void xgbe_poll_controller(struct net_device *netdev)
2180 {
2181 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2182 struct xgbe_channel *channel;
2183 unsigned int i;
2184
2185 DBGPR("-->xgbe_poll_controller\n");
2186
2187 if (pdata->per_channel_irq) {
2188 for (i = 0; i < pdata->channel_count; i++) {
2189 channel = pdata->channel[i];
2190 xgbe_dma_isr(channel->dma_irq, channel);
2191 }
2192 } else {
2193 disable_irq(pdata->dev_irq);
2194 xgbe_isr(pdata->dev_irq, pdata);
2195 enable_irq(pdata->dev_irq);
2196 }
2197
2198 DBGPR("<--xgbe_poll_controller\n");
2199 }
2200 #endif /* End CONFIG_NET_POLL_CONTROLLER */
2201
2202 static int xgbe_setup_tc(struct net_device *netdev, enum tc_setup_type type,
2203 void *type_data)
2204 {
2205 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2206 struct tc_mqprio_qopt *mqprio = type_data;
2207 u8 tc;
2208
2209 if (type != TC_SETUP_QDISC_MQPRIO)
2210 return -EOPNOTSUPP;
2211
2212 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
2213 tc = mqprio->num_tc;
2214
2215 if (tc > pdata->hw_feat.tc_cnt)
2216 return -EINVAL;
2217
2218 pdata->num_tcs = tc;
2219 pdata->hw_if.config_tc(pdata);
2220
2221 return 0;
2222 }
2223
2224 static netdev_features_t xgbe_fix_features(struct net_device *netdev,
2225 netdev_features_t features)
2226 {
2227 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2228 netdev_features_t vxlan_base, vxlan_mask;
2229
2230 vxlan_base = NETIF_F_GSO_UDP_TUNNEL | NETIF_F_RX_UDP_TUNNEL_PORT;
2231 vxlan_mask = vxlan_base | NETIF_F_GSO_UDP_TUNNEL_CSUM;
2232
2233 pdata->vxlan_features = features & vxlan_mask;
2234
2235 /* Only fix VXLAN-related features */
2236 if (!pdata->vxlan_features)
2237 return features;
2238
2239 /* If VXLAN isn't supported then clear any features:
2240 * This is needed because NETIF_F_RX_UDP_TUNNEL_PORT gets
2241 * automatically set if ndo_udp_tunnel_add is set.
2242 */
2243 if (!pdata->hw_feat.vxn)
2244 return features & ~vxlan_mask;
2245
2246 /* VXLAN CSUM requires VXLAN base */
2247 if ((features & NETIF_F_GSO_UDP_TUNNEL_CSUM) &&
2248 !(features & NETIF_F_GSO_UDP_TUNNEL)) {
2249 netdev_notice(netdev,
2250 "forcing tx udp tunnel support\n");
2251 features |= NETIF_F_GSO_UDP_TUNNEL;
2252 }
2253
2254 /* Can't do one without doing the other */
2255 if ((features & vxlan_base) != vxlan_base) {
2256 netdev_notice(netdev,
2257 "forcing both tx and rx udp tunnel support\n");
2258 features |= vxlan_base;
2259 }
2260
2261 if (features & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) {
2262 if (!(features & NETIF_F_GSO_UDP_TUNNEL_CSUM)) {
2263 netdev_notice(netdev,
2264 "forcing tx udp tunnel checksumming on\n");
2265 features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
2266 }
2267 } else {
2268 if (features & NETIF_F_GSO_UDP_TUNNEL_CSUM) {
2269 netdev_notice(netdev,
2270 "forcing tx udp tunnel checksumming off\n");
2271 features &= ~NETIF_F_GSO_UDP_TUNNEL_CSUM;
2272 }
2273 }
2274
2275 pdata->vxlan_features = features & vxlan_mask;
2276
2277 /* Adjust UDP Tunnel based on current state */
2278 if (pdata->vxlan_force_disable) {
2279 netdev_notice(netdev,
2280 "VXLAN acceleration disabled, turning off udp tunnel features\n");
2281 features &= ~vxlan_mask;
2282 }
2283
2284 return features;
2285 }
2286
2287 static int xgbe_set_features(struct net_device *netdev,
2288 netdev_features_t features)
2289 {
2290 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2291 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2292 netdev_features_t rxhash, rxcsum, rxvlan, rxvlan_filter;
2293 netdev_features_t udp_tunnel;
2294 int ret = 0;
2295
2296 rxhash = pdata->netdev_features & NETIF_F_RXHASH;
2297 rxcsum = pdata->netdev_features & NETIF_F_RXCSUM;
2298 rxvlan = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_RX;
2299 rxvlan_filter = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_FILTER;
2300 udp_tunnel = pdata->netdev_features & NETIF_F_GSO_UDP_TUNNEL;
2301
2302 if ((features & NETIF_F_RXHASH) && !rxhash)
2303 ret = hw_if->enable_rss(pdata);
2304 else if (!(features & NETIF_F_RXHASH) && rxhash)
2305 ret = hw_if->disable_rss(pdata);
2306 if (ret)
2307 return ret;
2308
2309 if ((features & NETIF_F_RXCSUM) && !rxcsum)
2310 hw_if->enable_rx_csum(pdata);
2311 else if (!(features & NETIF_F_RXCSUM) && rxcsum)
2312 hw_if->disable_rx_csum(pdata);
2313
2314 if ((features & NETIF_F_HW_VLAN_CTAG_RX) && !rxvlan)
2315 hw_if->enable_rx_vlan_stripping(pdata);
2316 else if (!(features & NETIF_F_HW_VLAN_CTAG_RX) && rxvlan)
2317 hw_if->disable_rx_vlan_stripping(pdata);
2318
2319 if ((features & NETIF_F_HW_VLAN_CTAG_FILTER) && !rxvlan_filter)
2320 hw_if->enable_rx_vlan_filtering(pdata);
2321 else if (!(features & NETIF_F_HW_VLAN_CTAG_FILTER) && rxvlan_filter)
2322 hw_if->disable_rx_vlan_filtering(pdata);
2323
2324 if ((features & NETIF_F_GSO_UDP_TUNNEL) && !udp_tunnel)
2325 xgbe_enable_vxlan_accel(pdata);
2326 else if (!(features & NETIF_F_GSO_UDP_TUNNEL) && udp_tunnel)
2327 xgbe_disable_vxlan_accel(pdata);
2328
2329 pdata->netdev_features = features;
2330
2331 DBGPR("<--xgbe_set_features\n");
2332
2333 return 0;
2334 }
2335
2336 static void xgbe_udp_tunnel_add(struct net_device *netdev,
2337 struct udp_tunnel_info *ti)
2338 {
2339 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2340 struct xgbe_vxlan_data *vdata;
2341
2342 if (!pdata->hw_feat.vxn)
2343 return;
2344
2345 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2346 return;
2347
2348 pdata->vxlan_port_count++;
2349
2350 netif_dbg(pdata, drv, netdev,
2351 "adding VXLAN tunnel, family=%hx/port=%hx\n",
2352 ti->sa_family, be16_to_cpu(ti->port));
2353
2354 if (pdata->vxlan_force_disable)
2355 return;
2356
2357 vdata = kzalloc(sizeof(*vdata), GFP_ATOMIC);
2358 if (!vdata) {
2359 /* Can no longer properly track VXLAN ports */
2360 pdata->vxlan_force_disable = 1;
2361 netif_dbg(pdata, drv, netdev,
2362 "internal error, disabling VXLAN accelerations\n");
2363
2364 xgbe_disable_vxlan_accel(pdata);
2365
2366 return;
2367 }
2368 vdata->sa_family = ti->sa_family;
2369 vdata->port = ti->port;
2370
2371 list_add_tail(&vdata->list, &pdata->vxlan_ports);
2372
2373 /* First port added? */
2374 if (pdata->vxlan_port_count == 1) {
2375 xgbe_enable_vxlan_accel(pdata);
2376
2377 return;
2378 }
2379 }
2380
2381 static void xgbe_udp_tunnel_del(struct net_device *netdev,
2382 struct udp_tunnel_info *ti)
2383 {
2384 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2385 struct xgbe_vxlan_data *vdata;
2386
2387 if (!pdata->hw_feat.vxn)
2388 return;
2389
2390 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2391 return;
2392
2393 netif_dbg(pdata, drv, netdev,
2394 "deleting VXLAN tunnel, family=%hx/port=%hx\n",
2395 ti->sa_family, be16_to_cpu(ti->port));
2396
2397 /* Don't need safe version since loop terminates with deletion */
2398 list_for_each_entry(vdata, &pdata->vxlan_ports, list) {
2399 if (vdata->sa_family != ti->sa_family)
2400 continue;
2401
2402 if (vdata->port != ti->port)
2403 continue;
2404
2405 list_del(&vdata->list);
2406 kfree(vdata);
2407
2408 break;
2409 }
2410
2411 pdata->vxlan_port_count--;
2412 if (!pdata->vxlan_port_count) {
2413 xgbe_reset_vxlan_accel(pdata);
2414
2415 return;
2416 }
2417
2418 if (pdata->vxlan_force_disable)
2419 return;
2420
2421 /* See if VXLAN tunnel id needs to be changed */
2422 vdata = list_first_entry(&pdata->vxlan_ports,
2423 struct xgbe_vxlan_data, list);
2424 if (pdata->vxlan_port == be16_to_cpu(vdata->port))
2425 return;
2426
2427 pdata->vxlan_port = be16_to_cpu(vdata->port);
2428 pdata->hw_if.set_vxlan_id(pdata);
2429 }
2430
2431 static netdev_features_t xgbe_features_check(struct sk_buff *skb,
2432 struct net_device *netdev,
2433 netdev_features_t features)
2434 {
2435 features = vlan_features_check(skb, features);
2436 features = vxlan_features_check(skb, features);
2437
2438 return features;
2439 }
2440
2441 static const struct net_device_ops xgbe_netdev_ops = {
2442 .ndo_open = xgbe_open,
2443 .ndo_stop = xgbe_close,
2444 .ndo_start_xmit = xgbe_xmit,
2445 .ndo_set_rx_mode = xgbe_set_rx_mode,
2446 .ndo_set_mac_address = xgbe_set_mac_address,
2447 .ndo_validate_addr = eth_validate_addr,
2448 .ndo_do_ioctl = xgbe_ioctl,
2449 .ndo_change_mtu = xgbe_change_mtu,
2450 .ndo_tx_timeout = xgbe_tx_timeout,
2451 .ndo_get_stats64 = xgbe_get_stats64,
2452 .ndo_vlan_rx_add_vid = xgbe_vlan_rx_add_vid,
2453 .ndo_vlan_rx_kill_vid = xgbe_vlan_rx_kill_vid,
2454 #ifdef CONFIG_NET_POLL_CONTROLLER
2455 .ndo_poll_controller = xgbe_poll_controller,
2456 #endif
2457 .ndo_setup_tc = xgbe_setup_tc,
2458 .ndo_fix_features = xgbe_fix_features,
2459 .ndo_set_features = xgbe_set_features,
2460 .ndo_udp_tunnel_add = xgbe_udp_tunnel_add,
2461 .ndo_udp_tunnel_del = xgbe_udp_tunnel_del,
2462 .ndo_features_check = xgbe_features_check,
2463 };
2464
2465 const struct net_device_ops *xgbe_get_netdev_ops(void)
2466 {
2467 return &xgbe_netdev_ops;
2468 }
2469
2470 static void xgbe_rx_refresh(struct xgbe_channel *channel)
2471 {
2472 struct xgbe_prv_data *pdata = channel->pdata;
2473 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2474 struct xgbe_desc_if *desc_if = &pdata->desc_if;
2475 struct xgbe_ring *ring = channel->rx_ring;
2476 struct xgbe_ring_data *rdata;
2477
2478 while (ring->dirty != ring->cur) {
2479 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
2480
2481 /* Reset rdata values */
2482 desc_if->unmap_rdata(pdata, rdata);
2483
2484 if (desc_if->map_rx_buffer(pdata, ring, rdata))
2485 break;
2486
2487 hw_if->rx_desc_reset(pdata, rdata, ring->dirty);
2488
2489 ring->dirty++;
2490 }
2491
2492 /* Make sure everything is written before the register write */
2493 wmb();
2494
2495 /* Update the Rx Tail Pointer Register with address of
2496 * the last cleaned entry */
2497 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty - 1);
2498 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO,
2499 lower_32_bits(rdata->rdesc_dma));
2500 }
2501
2502 static struct sk_buff *xgbe_create_skb(struct xgbe_prv_data *pdata,
2503 struct napi_struct *napi,
2504 struct xgbe_ring_data *rdata,
2505 unsigned int len)
2506 {
2507 struct sk_buff *skb;
2508 u8 *packet;
2509
2510 skb = napi_alloc_skb(napi, rdata->rx.hdr.dma_len);
2511 if (!skb)
2512 return NULL;
2513
2514 /* Pull in the header buffer which may contain just the header
2515 * or the header plus data
2516 */
2517 dma_sync_single_range_for_cpu(pdata->dev, rdata->rx.hdr.dma_base,
2518 rdata->rx.hdr.dma_off,
2519 rdata->rx.hdr.dma_len, DMA_FROM_DEVICE);
2520
2521 packet = page_address(rdata->rx.hdr.pa.pages) +
2522 rdata->rx.hdr.pa.pages_offset;
2523 skb_copy_to_linear_data(skb, packet, len);
2524 skb_put(skb, len);
2525
2526 return skb;
2527 }
2528
2529 static unsigned int xgbe_rx_buf1_len(struct xgbe_ring_data *rdata,
2530 struct xgbe_packet_data *packet)
2531 {
2532 /* Always zero if not the first descriptor */
2533 if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, FIRST))
2534 return 0;
2535
2536 /* First descriptor with split header, return header length */
2537 if (rdata->rx.hdr_len)
2538 return rdata->rx.hdr_len;
2539
2540 /* First descriptor but not the last descriptor and no split header,
2541 * so the full buffer was used
2542 */
2543 if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, LAST))
2544 return rdata->rx.hdr.dma_len;
2545
2546 /* First descriptor and last descriptor and no split header, so
2547 * calculate how much of the buffer was used
2548 */
2549 return min_t(unsigned int, rdata->rx.hdr.dma_len, rdata->rx.len);
2550 }
2551
2552 static unsigned int xgbe_rx_buf2_len(struct xgbe_ring_data *rdata,
2553 struct xgbe_packet_data *packet,
2554 unsigned int len)
2555 {
2556 /* Always the full buffer if not the last descriptor */
2557 if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, LAST))
2558 return rdata->rx.buf.dma_len;
2559
2560 /* Last descriptor so calculate how much of the buffer was used
2561 * for the last bit of data
2562 */
2563 return rdata->rx.len - len;
2564 }
2565
2566 static int xgbe_tx_poll(struct xgbe_channel *channel)
2567 {
2568 struct xgbe_prv_data *pdata = channel->pdata;
2569 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2570 struct xgbe_desc_if *desc_if = &pdata->desc_if;
2571 struct xgbe_ring *ring = channel->tx_ring;
2572 struct xgbe_ring_data *rdata;
2573 struct xgbe_ring_desc *rdesc;
2574 struct net_device *netdev = pdata->netdev;
2575 struct netdev_queue *txq;
2576 int processed = 0;
2577 unsigned int tx_packets = 0, tx_bytes = 0;
2578 unsigned int cur;
2579
2580 DBGPR("-->xgbe_tx_poll\n");
2581
2582 /* Nothing to do if there isn't a Tx ring for this channel */
2583 if (!ring)
2584 return 0;
2585
2586 cur = ring->cur;
2587
2588 /* Be sure we get ring->cur before accessing descriptor data */
2589 smp_rmb();
2590
2591 txq = netdev_get_tx_queue(netdev, channel->queue_index);
2592
2593 while ((processed < XGBE_TX_DESC_MAX_PROC) &&
2594 (ring->dirty != cur)) {
2595 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
2596 rdesc = rdata->rdesc;
2597
2598 if (!hw_if->tx_complete(rdesc))
2599 break;
2600
2601 /* Make sure descriptor fields are read after reading the OWN
2602 * bit */
2603 dma_rmb();
2604
2605 if (netif_msg_tx_done(pdata))
2606 xgbe_dump_tx_desc(pdata, ring, ring->dirty, 1, 0);
2607
2608 if (hw_if->is_last_desc(rdesc)) {
2609 tx_packets += rdata->tx.packets;
2610 tx_bytes += rdata->tx.bytes;
2611 }
2612
2613 /* Free the SKB and reset the descriptor for re-use */
2614 desc_if->unmap_rdata(pdata, rdata);
2615 hw_if->tx_desc_reset(rdata);
2616
2617 processed++;
2618 ring->dirty++;
2619 }
2620
2621 if (!processed)
2622 return 0;
2623
2624 netdev_tx_completed_queue(txq, tx_packets, tx_bytes);
2625
2626 if ((ring->tx.queue_stopped == 1) &&
2627 (xgbe_tx_avail_desc(ring) > XGBE_TX_DESC_MIN_FREE)) {
2628 ring->tx.queue_stopped = 0;
2629 netif_tx_wake_queue(txq);
2630 }
2631
2632 DBGPR("<--xgbe_tx_poll: processed=%d\n", processed);
2633
2634 return processed;
2635 }
2636
2637 static int xgbe_rx_poll(struct xgbe_channel *channel, int budget)
2638 {
2639 struct xgbe_prv_data *pdata = channel->pdata;
2640 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2641 struct xgbe_ring *ring = channel->rx_ring;
2642 struct xgbe_ring_data *rdata;
2643 struct xgbe_packet_data *packet;
2644 struct net_device *netdev = pdata->netdev;
2645 struct napi_struct *napi;
2646 struct sk_buff *skb;
2647 struct skb_shared_hwtstamps *hwtstamps;
2648 unsigned int last, error, context_next, context;
2649 unsigned int len, buf1_len, buf2_len, max_len;
2650 unsigned int received = 0;
2651 int packet_count = 0;
2652
2653 DBGPR("-->xgbe_rx_poll: budget=%d\n", budget);
2654
2655 /* Nothing to do if there isn't a Rx ring for this channel */
2656 if (!ring)
2657 return 0;
2658
2659 last = 0;
2660 context_next = 0;
2661
2662 napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
2663
2664 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
2665 packet = &ring->packet_data;
2666 while (packet_count < budget) {
2667 DBGPR(" cur = %d\n", ring->cur);
2668
2669 /* First time in loop see if we need to restore state */
2670 if (!received && rdata->state_saved) {
2671 skb = rdata->state.skb;
2672 error = rdata->state.error;
2673 len = rdata->state.len;
2674 } else {
2675 memset(packet, 0, sizeof(*packet));
2676 skb = NULL;
2677 error = 0;
2678 len = 0;
2679 }
2680
2681 read_again:
2682 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
2683
2684 if (xgbe_rx_dirty_desc(ring) > (XGBE_RX_DESC_CNT >> 3))
2685 xgbe_rx_refresh(channel);
2686
2687 if (hw_if->dev_read(channel))
2688 break;
2689
2690 received++;
2691 ring->cur++;
2692
2693 last = XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
2694 LAST);
2695 context_next = XGMAC_GET_BITS(packet->attributes,
2696 RX_PACKET_ATTRIBUTES,
2697 CONTEXT_NEXT);
2698 context = XGMAC_GET_BITS(packet->attributes,
2699 RX_PACKET_ATTRIBUTES,
2700 CONTEXT);
2701
2702 /* Earlier error, just drain the remaining data */
2703 if ((!last || context_next) && error)
2704 goto read_again;
2705
2706 if (error || packet->errors) {
2707 if (packet->errors)
2708 netif_err(pdata, rx_err, netdev,
2709 "error in received packet\n");
2710 dev_kfree_skb(skb);
2711 goto next_packet;
2712 }
2713
2714 if (!context) {
2715 /* Get the data length in the descriptor buffers */
2716 buf1_len = xgbe_rx_buf1_len(rdata, packet);
2717 len += buf1_len;
2718 buf2_len = xgbe_rx_buf2_len(rdata, packet, len);
2719 len += buf2_len;
2720
2721 if (!skb) {
2722 skb = xgbe_create_skb(pdata, napi, rdata,
2723 buf1_len);
2724 if (!skb) {
2725 error = 1;
2726 goto skip_data;
2727 }
2728 }
2729
2730 if (buf2_len) {
2731 dma_sync_single_range_for_cpu(pdata->dev,
2732 rdata->rx.buf.dma_base,
2733 rdata->rx.buf.dma_off,
2734 rdata->rx.buf.dma_len,
2735 DMA_FROM_DEVICE);
2736
2737 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
2738 rdata->rx.buf.pa.pages,
2739 rdata->rx.buf.pa.pages_offset,
2740 buf2_len,
2741 rdata->rx.buf.dma_len);
2742 rdata->rx.buf.pa.pages = NULL;
2743 }
2744 }
2745
2746 skip_data:
2747 if (!last || context_next)
2748 goto read_again;
2749
2750 if (!skb)
2751 goto next_packet;
2752
2753 /* Be sure we don't exceed the configured MTU */
2754 max_len = netdev->mtu + ETH_HLEN;
2755 if (!(netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
2756 (skb->protocol == htons(ETH_P_8021Q)))
2757 max_len += VLAN_HLEN;
2758
2759 if (skb->len > max_len) {
2760 netif_err(pdata, rx_err, netdev,
2761 "packet length exceeds configured MTU\n");
2762 dev_kfree_skb(skb);
2763 goto next_packet;
2764 }
2765
2766 if (netif_msg_pktdata(pdata))
2767 xgbe_print_pkt(netdev, skb, false);
2768
2769 skb_checksum_none_assert(skb);
2770 if (XGMAC_GET_BITS(packet->attributes,
2771 RX_PACKET_ATTRIBUTES, CSUM_DONE))
2772 skb->ip_summed = CHECKSUM_UNNECESSARY;
2773
2774 if (XGMAC_GET_BITS(packet->attributes,
2775 RX_PACKET_ATTRIBUTES, TNP)) {
2776 skb->encapsulation = 1;
2777
2778 if (XGMAC_GET_BITS(packet->attributes,
2779 RX_PACKET_ATTRIBUTES, TNPCSUM_DONE))
2780 skb->csum_level = 1;
2781 }
2782
2783 if (XGMAC_GET_BITS(packet->attributes,
2784 RX_PACKET_ATTRIBUTES, VLAN_CTAG))
2785 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2786 packet->vlan_ctag);
2787
2788 if (XGMAC_GET_BITS(packet->attributes,
2789 RX_PACKET_ATTRIBUTES, RX_TSTAMP)) {
2790 u64 nsec;
2791
2792 nsec = timecounter_cyc2time(&pdata->tstamp_tc,
2793 packet->rx_tstamp);
2794 hwtstamps = skb_hwtstamps(skb);
2795 hwtstamps->hwtstamp = ns_to_ktime(nsec);
2796 }
2797
2798 if (XGMAC_GET_BITS(packet->attributes,
2799 RX_PACKET_ATTRIBUTES, RSS_HASH))
2800 skb_set_hash(skb, packet->rss_hash,
2801 packet->rss_hash_type);
2802
2803 skb->dev = netdev;
2804 skb->protocol = eth_type_trans(skb, netdev);
2805 skb_record_rx_queue(skb, channel->queue_index);
2806
2807 napi_gro_receive(napi, skb);
2808
2809 next_packet:
2810 packet_count++;
2811 }
2812
2813 /* Check if we need to save state before leaving */
2814 if (received && (!last || context_next)) {
2815 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
2816 rdata->state_saved = 1;
2817 rdata->state.skb = skb;
2818 rdata->state.len = len;
2819 rdata->state.error = error;
2820 }
2821
2822 DBGPR("<--xgbe_rx_poll: packet_count = %d\n", packet_count);
2823
2824 return packet_count;
2825 }
2826
2827 static int xgbe_one_poll(struct napi_struct *napi, int budget)
2828 {
2829 struct xgbe_channel *channel = container_of(napi, struct xgbe_channel,
2830 napi);
2831 struct xgbe_prv_data *pdata = channel->pdata;
2832 int processed = 0;
2833
2834 DBGPR("-->xgbe_one_poll: budget=%d\n", budget);
2835
2836 /* Cleanup Tx ring first */
2837 xgbe_tx_poll(channel);
2838
2839 /* Process Rx ring next */
2840 processed = xgbe_rx_poll(channel, budget);
2841
2842 /* If we processed everything, we are done */
2843 if ((processed < budget) && napi_complete_done(napi, processed)) {
2844 /* Enable Tx and Rx interrupts */
2845 if (pdata->channel_irq_mode)
2846 xgbe_enable_rx_tx_int(pdata, channel);
2847 else
2848 enable_irq(channel->dma_irq);
2849 }
2850
2851 DBGPR("<--xgbe_one_poll: received = %d\n", processed);
2852
2853 return processed;
2854 }
2855
2856 static int xgbe_all_poll(struct napi_struct *napi, int budget)
2857 {
2858 struct xgbe_prv_data *pdata = container_of(napi, struct xgbe_prv_data,
2859 napi);
2860 struct xgbe_channel *channel;
2861 int ring_budget;
2862 int processed, last_processed;
2863 unsigned int i;
2864
2865 DBGPR("-->xgbe_all_poll: budget=%d\n", budget);
2866
2867 processed = 0;
2868 ring_budget = budget / pdata->rx_ring_count;
2869 do {
2870 last_processed = processed;
2871
2872 for (i = 0; i < pdata->channel_count; i++) {
2873 channel = pdata->channel[i];
2874
2875 /* Cleanup Tx ring first */
2876 xgbe_tx_poll(channel);
2877
2878 /* Process Rx ring next */
2879 if (ring_budget > (budget - processed))
2880 ring_budget = budget - processed;
2881 processed += xgbe_rx_poll(channel, ring_budget);
2882 }
2883 } while ((processed < budget) && (processed != last_processed));
2884
2885 /* If we processed everything, we are done */
2886 if ((processed < budget) && napi_complete_done(napi, processed)) {
2887 /* Enable Tx and Rx interrupts */
2888 xgbe_enable_rx_tx_ints(pdata);
2889 }
2890
2891 DBGPR("<--xgbe_all_poll: received = %d\n", processed);
2892
2893 return processed;
2894 }
2895
2896 void xgbe_dump_tx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring,
2897 unsigned int idx, unsigned int count, unsigned int flag)
2898 {
2899 struct xgbe_ring_data *rdata;
2900 struct xgbe_ring_desc *rdesc;
2901
2902 while (count--) {
2903 rdata = XGBE_GET_DESC_DATA(ring, idx);
2904 rdesc = rdata->rdesc;
2905 netdev_dbg(pdata->netdev,
2906 "TX_NORMAL_DESC[%d %s] = %08x:%08x:%08x:%08x\n", idx,
2907 (flag == 1) ? "QUEUED FOR TX" : "TX BY DEVICE",
2908 le32_to_cpu(rdesc->desc0),
2909 le32_to_cpu(rdesc->desc1),
2910 le32_to_cpu(rdesc->desc2),
2911 le32_to_cpu(rdesc->desc3));
2912 idx++;
2913 }
2914 }
2915
2916 void xgbe_dump_rx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring,
2917 unsigned int idx)
2918 {
2919 struct xgbe_ring_data *rdata;
2920 struct xgbe_ring_desc *rdesc;
2921
2922 rdata = XGBE_GET_DESC_DATA(ring, idx);
2923 rdesc = rdata->rdesc;
2924 netdev_dbg(pdata->netdev,
2925 "RX_NORMAL_DESC[%d RX BY DEVICE] = %08x:%08x:%08x:%08x\n",
2926 idx, le32_to_cpu(rdesc->desc0), le32_to_cpu(rdesc->desc1),
2927 le32_to_cpu(rdesc->desc2), le32_to_cpu(rdesc->desc3));
2928 }
2929
2930 void xgbe_print_pkt(struct net_device *netdev, struct sk_buff *skb, bool tx_rx)
2931 {
2932 struct ethhdr *eth = (struct ethhdr *)skb->data;
2933 unsigned char buffer[128];
2934 unsigned int i;
2935
2936 netdev_dbg(netdev, "\n************** SKB dump ****************\n");
2937
2938 netdev_dbg(netdev, "%s packet of %d bytes\n",
2939 (tx_rx ? "TX" : "RX"), skb->len);
2940
2941 netdev_dbg(netdev, "Dst MAC addr: %pM\n", eth->h_dest);
2942 netdev_dbg(netdev, "Src MAC addr: %pM\n", eth->h_source);
2943 netdev_dbg(netdev, "Protocol: %#06hx\n", ntohs(eth->h_proto));
2944
2945 for (i = 0; i < skb->len; i += 32) {
2946 unsigned int len = min(skb->len - i, 32U);
2947
2948 hex_dump_to_buffer(&skb->data[i], len, 32, 1,
2949 buffer, sizeof(buffer), false);
2950 netdev_dbg(netdev, " %#06x: %s\n", i, buffer);
2951 }
2952
2953 netdev_dbg(netdev, "\n************** SKB dump ****************\n");
2954 }
CRIS linux kernel tree