drivers/net/ethernet/qualcomm/emac/emac-sgmii.c

   1 /* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 /* Qualcomm Technologies, Inc. EMAC SGMII Controller driver.
  14  */
  15
  16 #include <linux/interrupt.h>
  17 #include <linux/iopoll.h>
  18 #include <linux/acpi.h>
  19 #include <linux/of_device.h>
  20 #include "emac.h"
  21 #include "emac-mac.h"
  22 #include "emac-sgmii.h"
  23
  24 /* EMAC_SGMII register offsets */
  25 #define EMAC_SGMII_PHY_AUTONEG_CFG2             0x0048
  26 #define EMAC_SGMII_PHY_SPEED_CFG1               0x0074
  27 #define EMAC_SGMII_PHY_IRQ_CMD                  0x00ac
  28 #define EMAC_SGMII_PHY_INTERRUPT_CLEAR          0x00b0
  29 #define EMAC_SGMII_PHY_INTERRUPT_MASK           0x00b4
  30 #define EMAC_SGMII_PHY_INTERRUPT_STATUS         0x00b8
  31 #define EMAC_SGMII_PHY_RX_CHK_STATUS            0x00d4
  32
  33 #define FORCE_AN_TX_CFG                         BIT(5)
  34 #define FORCE_AN_RX_CFG                         BIT(4)
  35 #define AN_ENABLE                               BIT(0)
  36
  37 #define DUPLEX_MODE                             BIT(4)
  38 #define SPDMODE_1000                            BIT(1)
  39 #define SPDMODE_100                             BIT(0)
  40 #define SPDMODE_10                              0
  41
  42 #define CDR_ALIGN_DET                           BIT(6)
  43
  44 #define IRQ_GLOBAL_CLEAR                        BIT(0)
  45
  46 #define DECODE_CODE_ERR                         BIT(7)
  47 #define DECODE_DISP_ERR                         BIT(6)
  48
  49 #define SGMII_PHY_IRQ_CLR_WAIT_TIME             10
  50
  51 #define SGMII_PHY_INTERRUPT_ERR         (DECODE_CODE_ERR | DECODE_DISP_ERR)
  52 #define SGMII_ISR_MASK                  (SGMII_PHY_INTERRUPT_ERR)
  53
  54 #define SERDES_START_WAIT_TIMES                 100
  55
  56 /* Initialize the SGMII link between the internal and external PHYs. */
  57 static void emac_sgmii_link_init(struct emac_adapter *adpt)
  58 {
  59         struct emac_sgmii *phy = &adpt->phy;
  60         u32 val;
  61
  62         /* Always use autonegotiation. It works no matter how the external
  63          * PHY is configured.
  64          */
  65         val = readl(phy->base + EMAC_SGMII_PHY_AUTONEG_CFG2);
  66         val &= ~(FORCE_AN_RX_CFG | FORCE_AN_TX_CFG);
  67         val |= AN_ENABLE;
  68         writel(val, phy->base + EMAC_SGMII_PHY_AUTONEG_CFG2);
  69 }
  70
  71 static int emac_sgmii_irq_clear(struct emac_adapter *adpt, u8 irq_bits)
  72 {
  73         struct emac_sgmii *phy = &adpt->phy;
  74         u8 status;
  75
  76         writel_relaxed(irq_bits, phy->base + EMAC_SGMII_PHY_INTERRUPT_CLEAR);
  77         writel_relaxed(IRQ_GLOBAL_CLEAR, phy->base + EMAC_SGMII_PHY_IRQ_CMD);
  78         /* Ensure interrupt clear command is written to HW */
  79         wmb();
  80
  81         /* After set the IRQ_GLOBAL_CLEAR bit, the status clearing must
  82          * be confirmed before clearing the bits in other registers.
  83          * It takes a few cycles for hw to clear the interrupt status.
  84          */
  85         if (readl_poll_timeout_atomic(phy->base +
  86                                       EMAC_SGMII_PHY_INTERRUPT_STATUS,
  87                                       status, !(status & irq_bits), 1,
  88                                       SGMII_PHY_IRQ_CLR_WAIT_TIME)) {
  89                 net_err_ratelimited("%s: failed to clear SGMII irq: status:0x%x bits:0x%x\n",
  90                                     adpt->netdev->name, status, irq_bits);
  91                 return -EIO;
  92         }
  93
  94         /* Finalize clearing procedure */
  95         writel_relaxed(0, phy->base + EMAC_SGMII_PHY_IRQ_CMD);
  96         writel_relaxed(0, phy->base + EMAC_SGMII_PHY_INTERRUPT_CLEAR);
  97
  98         /* Ensure that clearing procedure finalization is written to HW */
  99         wmb();
 100
 101         return 0;
 102 }
 103
 104 /* The number of decode errors that triggers a reset */
 105 #define DECODE_ERROR_LIMIT      2
 106
 107 static irqreturn_t emac_sgmii_interrupt(int irq, void *data)
 108 {
 109         struct emac_adapter *adpt = data;
 110         struct emac_sgmii *phy = &adpt->phy;
 111         u8 status;
 112
 113         status = readl(phy->base + EMAC_SGMII_PHY_INTERRUPT_STATUS);
 114         status &= SGMII_ISR_MASK;
 115         if (!status)
 116                 return IRQ_HANDLED;
 117
 118         /* If we get a decoding error and CDR is not locked, then try
 119          * resetting the internal PHY.  The internal PHY uses an embedded
 120          * clock with Clock and Data Recovery (CDR) to recover the
 121          * clock and data.
 122          */
 123         if (status & SGMII_PHY_INTERRUPT_ERR) {
 124                 int count;
 125
 126                 /* The SGMII is capable of recovering from some decode
 127                  * errors automatically.  However, if we get multiple
 128                  * decode errors in a row, then assume that something
 129                  * is wrong and reset the interface.
 130                  */
 131                 count = atomic_inc_return(&phy->decode_error_count);
 132                 if (count == DECODE_ERROR_LIMIT) {
 133                         schedule_work(&adpt->work_thread);
 134                         atomic_set(&phy->decode_error_count, 0);
 135                 }
 136         } else {
 137                 /* We only care about consecutive decode errors. */
 138                 atomic_set(&phy->decode_error_count, 0);
 139         }
 140
 141         if (emac_sgmii_irq_clear(adpt, status))
 142                 schedule_work(&adpt->work_thread);
 143
 144         return IRQ_HANDLED;
 145 }
 146
 147 static void emac_sgmii_reset_prepare(struct emac_adapter *adpt)
 148 {
 149         struct emac_sgmii *phy = &adpt->phy;
 150         u32 val;
 151
 152         /* Reset PHY */
 153         val = readl(phy->base + EMAC_EMAC_WRAPPER_CSR2);
 154         writel(((val & ~PHY_RESET) | PHY_RESET), phy->base +
 155                EMAC_EMAC_WRAPPER_CSR2);
 156         /* Ensure phy-reset command is written to HW before the release cmd */
 157         msleep(50);
 158         val = readl(phy->base + EMAC_EMAC_WRAPPER_CSR2);
 159         writel((val & ~PHY_RESET), phy->base + EMAC_EMAC_WRAPPER_CSR2);
 160         /* Ensure phy-reset release command is written to HW before initializing
 161          * SGMII
 162          */
 163         msleep(50);
 164 }
 165
 166 void emac_sgmii_reset(struct emac_adapter *adpt)
 167 {
 168         int ret;
 169
 170         emac_sgmii_reset_prepare(adpt);
 171         emac_sgmii_link_init(adpt);
 172
 173         ret = adpt->phy.initialize(adpt);
 174         if (ret)
 175                 netdev_err(adpt->netdev,
 176                            "could not reinitialize internal PHY (error=%i)\n",
 177                            ret);
 178 }
 179
 180 static int emac_sgmii_open(struct emac_adapter *adpt)
 181 {
 182         struct emac_sgmii *sgmii = &adpt->phy;
 183         int ret;
 184
 185         if (sgmii->irq) {
 186                 /* Make sure interrupts are cleared and disabled first */
 187                 ret = emac_sgmii_irq_clear(adpt, 0xff);
 188                 if (ret)
 189                         return ret;
 190                 writel(0, sgmii->base + EMAC_SGMII_PHY_INTERRUPT_MASK);
 191
 192                 ret = request_irq(sgmii->irq, emac_sgmii_interrupt, 0,
 193                                   "emac-sgmii", adpt);
 194                 if (ret) {
 195                         netdev_err(adpt->netdev,
 196                                    "could not register handler for internal PHY\n");
 197                         return ret;
 198                 }
 199         }
 200
 201         return 0;
 202 }
 203
 204 static int emac_sgmii_close(struct emac_adapter *adpt)
 205 {
 206         struct emac_sgmii *sgmii = &adpt->phy;
 207
 208         /* Make sure interrupts are disabled */
 209         writel(0, sgmii->base + EMAC_SGMII_PHY_INTERRUPT_MASK);
 210         free_irq(sgmii->irq, adpt);
 211
 212         return 0;
 213 }
 214
 215 /* The error interrupts are only valid after the link is up */
 216 static int emac_sgmii_link_up(struct emac_adapter *adpt)
 217 {
 218         struct emac_sgmii *sgmii = &adpt->phy;
 219         int ret;
 220
 221         /* Clear and enable interrupts */
 222         ret = emac_sgmii_irq_clear(adpt, 0xff);
 223         if (ret)
 224                 return ret;
 225
 226         writel(SGMII_ISR_MASK, sgmii->base + EMAC_SGMII_PHY_INTERRUPT_MASK);
 227
 228         return 0;
 229 }
 230
 231 static int emac_sgmii_link_down(struct emac_adapter *adpt)
 232 {
 233         struct emac_sgmii *sgmii = &adpt->phy;
 234
 235         /* Disable interrupts */
 236         writel(0, sgmii->base + EMAC_SGMII_PHY_INTERRUPT_MASK);
 237         synchronize_irq(sgmii->irq);
 238
 239         return 0;
 240 }
 241
 242 static int emac_sgmii_acpi_match(struct device *dev, void *data)
 243 {
 244 #ifdef CONFIG_ACPI
 245         static const struct acpi_device_id match_table[] = {
 246                 {
 247                         .id = "QCOM8071",
 248                 },
 249                 {}
 250         };
 251         const struct acpi_device_id *id = acpi_match_device(match_table, dev);
 252         emac_sgmii_function *initialize = data;
 253
 254         if (id) {
 255                 acpi_handle handle = ACPI_HANDLE(dev);
 256                 unsigned long long hrv;
 257                 acpi_status status;
 258
 259                 status = acpi_evaluate_integer(handle, "_HRV", NULL, &hrv);
 260                 if (status) {
 261                         if (status == AE_NOT_FOUND)
 262                                 /* Older versions of the QDF2432 ACPI tables do
 263                                  * not have an _HRV property.
 264                                  */
 265                                 hrv = 1;
 266                         else
 267                                 /* Something is wrong with the tables */
 268                                 return 0;
 269                 }
 270
 271                 switch (hrv) {
 272                 case 1:
 273                         *initialize = emac_sgmii_init_qdf2432;
 274                         return 1;
 275                 case 2:
 276                         *initialize = emac_sgmii_init_qdf2400;
 277                         return 1;
 278                 }
 279         }
 280 #endif
 281
 282         return 0;
 283 }
 284
 285 static const struct of_device_id emac_sgmii_dt_match[] = {
 286         {
 287                 .compatible = "qcom,fsm9900-emac-sgmii",
 288                 .data = emac_sgmii_init_fsm9900,
 289         },
 290         {
 291                 .compatible = "qcom,qdf2432-emac-sgmii",
 292                 .data = emac_sgmii_init_qdf2432,
 293         },
 294         {}
 295 };
 296
 297 /* Dummy function for systems without an internal PHY. This avoids having
 298  * to check for NULL pointers before calling the functions.
 299  */
 300 static int emac_sgmii_dummy(struct emac_adapter *adpt)
 301 {
 302         return 0;
 303 }
 304
 305 int emac_sgmii_config(struct platform_device *pdev, struct emac_adapter *adpt)
 306 {
 307         struct platform_device *sgmii_pdev = NULL;
 308         struct emac_sgmii *phy = &adpt->phy;
 309         struct resource *res;
 310         int ret;
 311
 312         if (has_acpi_companion(&pdev->dev)) {
 313                 struct device *dev;
 314
 315                 dev = device_find_child(&pdev->dev, &phy->initialize,
 316                                         emac_sgmii_acpi_match);
 317
 318                 if (!dev) {
 319                         dev_warn(&pdev->dev, "cannot find internal phy node\n");
 320                         /* There is typically no internal PHY on emulation
 321                          * systems, so if we can't find the node, assume
 322                          * we are on an emulation system and stub-out
 323                          * support for the internal PHY.  These systems only
 324                          * use ACPI.
 325                          */
 326                         phy->open = emac_sgmii_dummy;
 327                         phy->close = emac_sgmii_dummy;
 328                         phy->link_up = emac_sgmii_dummy;
 329                         phy->link_down = emac_sgmii_dummy;
 330
 331                         return 0;
 332                 }
 333
 334                 sgmii_pdev = to_platform_device(dev);
 335         } else {
 336                 const struct of_device_id *match;
 337                 struct device_node *np;
 338
 339                 np = of_parse_phandle(pdev->dev.of_node, "internal-phy", 0);
 340                 if (!np) {
 341                         dev_err(&pdev->dev, "missing internal-phy property\n");
 342                         return -ENODEV;
 343                 }
 344
 345                 sgmii_pdev = of_find_device_by_node(np);
 346                 if (!sgmii_pdev) {
 347                         dev_err(&pdev->dev, "invalid internal-phy property\n");
 348                         return -ENODEV;
 349                 }
 350
 351                 match = of_match_device(emac_sgmii_dt_match, &sgmii_pdev->dev);
 352                 if (!match) {
 353                         dev_err(&pdev->dev, "unrecognized internal phy node\n");
 354                         ret = -ENODEV;
 355                         goto error_put_device;
 356                 }
 357
 358                 phy->initialize = (emac_sgmii_function)match->data;
 359         }
 360
 361         phy->open = emac_sgmii_open;
 362         phy->close = emac_sgmii_close;
 363         phy->link_up = emac_sgmii_link_up;
 364         phy->link_down = emac_sgmii_link_down;
 365
 366         /* Base address is the first address */
 367         res = platform_get_resource(sgmii_pdev, IORESOURCE_MEM, 0);
 368         if (!res) {
 369                 ret = -EINVAL;
 370                 goto error_put_device;
 371         }
 372
 373         phy->base = ioremap(res->start, resource_size(res));
 374         if (!phy->base) {
 375                 ret = -ENOMEM;
 376                 goto error_put_device;
 377         }
 378
 379         /* v2 SGMII has a per-lane digital digital, so parse it if it exists */
 380         res = platform_get_resource(sgmii_pdev, IORESOURCE_MEM, 1);
 381         if (res) {
 382                 phy->digital = ioremap(res->start, resource_size(res));
 383                 if (!phy->digital) {
 384                         ret = -ENOMEM;
 385                         goto error_unmap_base;
 386                 }
 387         }
 388
 389         ret = phy->initialize(adpt);
 390         if (ret)
 391                 goto error;
 392
 393         emac_sgmii_link_init(adpt);
 394
 395         ret = platform_get_irq(sgmii_pdev, 0);
 396         if (ret > 0)
 397                 phy->irq = ret;
 398
 399         /* We've remapped the addresses, so we don't need the device any
 400          * more.  of_find_device_by_node() says we should release it.
 401          */
 402         put_device(&sgmii_pdev->dev);
 403
 404         return 0;
 405
 406 error:
 407         if (phy->digital)
 408                 iounmap(phy->digital);
 409 error_unmap_base:
 410         iounmap(phy->base);
 411 error_put_device:
 412         put_device(&sgmii_pdev->dev);
 413
 414         return ret;
 415 }