| blob | e6a60fa59f2b5e32f240374e980c68558bdf3f86 |
1 /*
2 * Copyright(c) 2015 - 2017 Intel Corporation.
3 *
4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license.
6 *
7 * GPL LICENSE SUMMARY
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * BSD LICENSE
19 *
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions
22 * are met:
23 *
24 * - Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * - Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in
28 * the documentation and/or other materials provided with the
29 * distribution.
30 * - Neither the name of Intel Corporation nor the names of its
31 * contributors may be used to endorse or promote products derived
32 * from this software without specific prior written permission.
33 *
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 *
46 */
48 /*
49 * This file contains all of the code that is specific to the HFI chip
50 */
52 #include <linux/pci.h>
53 #include <linux/delay.h>
54 #include <linux/interrupt.h>
55 #include <linux/module.h>
69 #define NUM_IB_PORTS 1
71 uint kdeth_qp;
79 /*
80 * Default time to aggregate two 10K packets from the idle state
81 * (timer not running). The timer starts at the end of the first packet,
82 * so only the time for one 10K packet and header plus a bit extra is needed.
83 * 10 * 1024 + 64 header byte = 10304 byte
84 * 10304 byte / 12.5 GB/s = 824.32ns
85 */
98 uint loopback;
102 /* Other driver tunables */
112 u16 unused0;
113 u32 unused1;
114 };
116 /* str must be a string constant */
117 #define FLAG_ENTRY(str, extra, flag) {flag, str, extra}
118 #define FLAG_ENTRY0(str, flag) {flag, str, 0}
120 /* Send Error Consequences */
121 #define SEC_WRITE_DROPPED 0x1
122 #define SEC_PACKET_DROPPED 0x2
126 #define DEFAULT_KRCVQS 2
127 #define MIN_KERNEL_KCTXTS 2
128 #define FIRST_KERNEL_KCTXT 1
130 /*
131 * RSM instance allocation
132 * 0 - Verbs
133 * 1 - User Fecn Handling
134 * 2 - Vnic
135 */
136 #define RSM_INS_VERBS 0
137 #define RSM_INS_FECN 1
138 #define RSM_INS_VNIC 2
140 /* Bit offset into the GUID which carries HFI id information */
141 #define GUID_HFI_INDEX_SHIFT 39
143 /* extract the emulation revision */
144 #define emulator_rev(dd) ((dd)->irev >> 8)
145 /* parallel and serial emulation versions are 3 and 4 respectively */
146 #define is_emulator_p(dd) ((((dd)->irev) & 0xf) == 3)
147 #define is_emulator_s(dd) ((((dd)->irev) & 0xf) == 4)
149 /* RSM fields for Verbs */
150 /* packet type */
151 #define IB_PACKET_TYPE 2ull
152 #define QW_SHIFT 6ull
153 /* QPN[7..1] */
154 #define QPN_WIDTH 7ull
156 /* LRH.BTH: QW 0, OFFSET 48 - for match */
157 #define LRH_BTH_QW 0ull
158 #define LRH_BTH_BIT_OFFSET 48ull
159 #define LRH_BTH_OFFSET(off) ((LRH_BTH_QW << QW_SHIFT) | (off))
160 #define LRH_BTH_MATCH_OFFSET LRH_BTH_OFFSET(LRH_BTH_BIT_OFFSET)
161 #define LRH_BTH_SELECT
162 #define LRH_BTH_MASK 3ull
163 #define LRH_BTH_VALUE 2ull
165 /* LRH.SC[3..0] QW 0, OFFSET 56 - for match */
166 #define LRH_SC_QW 0ull
167 #define LRH_SC_BIT_OFFSET 56ull
168 #define LRH_SC_OFFSET(off) ((LRH_SC_QW << QW_SHIFT) | (off))
169 #define LRH_SC_MATCH_OFFSET LRH_SC_OFFSET(LRH_SC_BIT_OFFSET)
170 #define LRH_SC_MASK 128ull
171 #define LRH_SC_VALUE 0ull
173 /* SC[n..0] QW 0, OFFSET 60 - for select */
174 #define LRH_SC_SELECT_OFFSET ((LRH_SC_QW << QW_SHIFT) | (60ull))
176 /* QPN[m+n:1] QW 1, OFFSET 1 */
177 #define QPN_SELECT_OFFSET ((1ull << QW_SHIFT) | (1ull))
179 /* RSM fields for Vnic */
180 /* L2_TYPE: QW 0, OFFSET 61 - for match */
181 #define L2_TYPE_QW 0ull
182 #define L2_TYPE_BIT_OFFSET 61ull
183 #define L2_TYPE_OFFSET(off) ((L2_TYPE_QW << QW_SHIFT) | (off))
184 #define L2_TYPE_MATCH_OFFSET L2_TYPE_OFFSET(L2_TYPE_BIT_OFFSET)
185 #define L2_TYPE_MASK 3ull
186 #define L2_16B_VALUE 2ull
188 /* L4_TYPE QW 1, OFFSET 0 - for match */
189 #define L4_TYPE_QW 1ull
190 #define L4_TYPE_BIT_OFFSET 0ull
191 #define L4_TYPE_OFFSET(off) ((L4_TYPE_QW << QW_SHIFT) | (off))
192 #define L4_TYPE_MATCH_OFFSET L4_TYPE_OFFSET(L4_TYPE_BIT_OFFSET)
193 #define L4_16B_TYPE_MASK 0xFFull
194 #define L4_16B_ETH_VALUE 0x78ull
196 /* 16B VESWID - for select */
197 #define L4_16B_HDR_VESWID_OFFSET ((2 << QW_SHIFT) | (16ull))
198 /* 16B ENTROPY - for select */
199 #define L2_16B_ENTROPY_OFFSET ((1 << QW_SHIFT) | (32ull))
201 /* defines to build power on SC2VL table */
202 #define SC2VL_VAL( \
203 num, \
204 sc0, sc0val, \
205 sc1, sc1val, \
206 sc2, sc2val, \
207 sc3, sc3val, \
208 sc4, sc4val, \
209 sc5, sc5val, \
210 sc6, sc6val, \
211 sc7, sc7val) \
212 ( \
213 ((u64)(sc0val) << SEND_SC2VLT##num##_SC##sc0##_SHIFT) | \
214 ((u64)(sc1val) << SEND_SC2VLT##num##_SC##sc1##_SHIFT) | \
215 ((u64)(sc2val) << SEND_SC2VLT##num##_SC##sc2##_SHIFT) | \
216 ((u64)(sc3val) << SEND_SC2VLT##num##_SC##sc3##_SHIFT) | \
217 ((u64)(sc4val) << SEND_SC2VLT##num##_SC##sc4##_SHIFT) | \
218 ((u64)(sc5val) << SEND_SC2VLT##num##_SC##sc5##_SHIFT) | \
219 ((u64)(sc6val) << SEND_SC2VLT##num##_SC##sc6##_SHIFT) | \
220 ((u64)(sc7val) << SEND_SC2VLT##num##_SC##sc7##_SHIFT) \
221 )
223 #define DC_SC_VL_VAL( \
224 range, \
225 e0, e0val, \
226 e1, e1val, \
227 e2, e2val, \
228 e3, e3val, \
229 e4, e4val, \
230 e5, e5val, \
231 e6, e6val, \
232 e7, e7val, \
233 e8, e8val, \
234 e9, e9val, \
235 e10, e10val, \
236 e11, e11val, \
237 e12, e12val, \
238 e13, e13val, \
239 e14, e14val, \
240 e15, e15val) \
241 ( \
242 ((u64)(e0val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e0##_SHIFT) | \
243 ((u64)(e1val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e1##_SHIFT) | \
244 ((u64)(e2val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e2##_SHIFT) | \
245 ((u64)(e3val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e3##_SHIFT) | \
246 ((u64)(e4val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e4##_SHIFT) | \
247 ((u64)(e5val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e5##_SHIFT) | \
248 ((u64)(e6val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e6##_SHIFT) | \
249 ((u64)(e7val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e7##_SHIFT) | \
250 ((u64)(e8val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e8##_SHIFT) | \
251 ((u64)(e9val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e9##_SHIFT) | \
252 ((u64)(e10val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e10##_SHIFT) | \
253 ((u64)(e11val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e11##_SHIFT) | \
254 ((u64)(e12val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e12##_SHIFT) | \
255 ((u64)(e13val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e13##_SHIFT) | \
256 ((u64)(e14val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e14##_SHIFT) | \
257 ((u64)(e15val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e15##_SHIFT) \
258 )
260 /* all CceStatus sub-block freeze bits */
261 #define ALL_FROZE (CCE_STATUS_SDMA_FROZE_SMASK \
262 | CCE_STATUS_RXE_FROZE_SMASK \
263 | CCE_STATUS_TXE_FROZE_SMASK \
264 | CCE_STATUS_TXE_PIO_FROZE_SMASK)
265 /* all CceStatus sub-block TXE pause bits */
266 #define ALL_TXE_PAUSE (CCE_STATUS_TXE_PIO_PAUSED_SMASK \
267 | CCE_STATUS_TXE_PAUSED_SMASK \
268 | CCE_STATUS_SDMA_PAUSED_SMASK)
269 /* all CceStatus sub-block RXE pause bits */
270 #define ALL_RXE_PAUSE CCE_STATUS_RXE_PAUSED_SMASK
272 #define CNTR_MAX 0xFFFFFFFFFFFFFFFFULL
273 #define CNTR_32BIT_MAX 0x00000000FFFFFFFF
275 /*
276 * CCE Error flags.
277 */
280 CCE_ERR_STATUS_CCE_CSR_PARITY_ERR_SMASK),
282 CCE_ERR_STATUS_CCE_CSR_READ_BAD_ADDR_ERR_SMASK),
284 CCE_ERR_STATUS_CCE_CSR_WRITE_BAD_ADDR_ERR_SMASK),
286 CCE_ERR_STATUS_CCE_TRGT_ASYNC_FIFO_PARITY_ERR_SMASK),
288 CCE_ERR_STATUS_CCE_TRGT_ACCESS_ERR_SMASK),
290 CCE_ERR_STATUS_CCE_RSPD_DATA_PARITY_ERR_SMASK),
292 CCE_ERR_STATUS_CCE_CLI0_ASYNC_FIFO_PARITY_ERR_SMASK),
294 CCE_ERR_STATUS_CCE_CSR_CFG_BUS_PARITY_ERR_SMASK),
296 CCE_ERR_STATUS_CCE_CLI2_ASYNC_FIFO_PARITY_ERR_SMASK),
298 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR_SMASK),
300 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR_SMASK),
302 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERROR_SMASK),
304 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERROR_SMASK),
306 CCE_ERR_STATUS_PCIC_RETRY_MEM_COR_ERR_SMASK),
308 CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_COR_ERR_SMASK),
310 CCE_ERR_STATUS_PCIC_POST_HD_QCOR_ERR_SMASK),
312 CCE_ERR_STATUS_PCIC_POST_DAT_QCOR_ERR_SMASK),
314 CCE_ERR_STATUS_PCIC_CPL_HD_QCOR_ERR_SMASK),
316 CCE_ERR_STATUS_PCIC_CPL_DAT_QCOR_ERR_SMASK),
318 CCE_ERR_STATUS_PCIC_NPOST_HQ_PARITY_ERR_SMASK),
320 CCE_ERR_STATUS_PCIC_NPOST_DAT_QPARITY_ERR_SMASK),
322 CCE_ERR_STATUS_PCIC_RETRY_MEM_UNC_ERR_SMASK),
324 CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_UNC_ERR_SMASK),
326 CCE_ERR_STATUS_PCIC_POST_HD_QUNC_ERR_SMASK),
328 CCE_ERR_STATUS_PCIC_POST_DAT_QUNC_ERR_SMASK),
330 CCE_ERR_STATUS_PCIC_CPL_HD_QUNC_ERR_SMASK),
332 CCE_ERR_STATUS_PCIC_CPL_DAT_QUNC_ERR_SMASK),
334 CCE_ERR_STATUS_PCIC_TRANSMIT_FRONT_PARITY_ERR_SMASK),
336 CCE_ERR_STATUS_PCIC_TRANSMIT_BACK_PARITY_ERR_SMASK),
338 CCE_ERR_STATUS_PCIC_RECEIVE_PARITY_ERR_SMASK),
340 CCE_ERR_STATUS_CCE_TRGT_CPL_TIMEOUT_ERR_SMASK),
342 CCE_ERR_STATUS_LA_TRIGGERED_SMASK),
344 CCE_ERR_STATUS_CCE_SEG_READ_BAD_ADDR_ERR_SMASK),
346 CCE_ERR_STATUS_CCE_SEG_WRITE_BAD_ADDR_ERR_SMASK),
348 CCE_ERR_STATUS_CCE_RCPL_ASYNC_FIFO_PARITY_ERR_SMASK),
350 CCE_ERR_STATUS_CCE_RXDMA_CONV_FIFO_PARITY_ERR_SMASK),
352 CCE_ERR_STATUS_CCE_MSIX_TABLE_COR_ERR_SMASK),
354 CCE_ERR_STATUS_CCE_MSIX_TABLE_UNC_ERR_SMASK),
356 CCE_ERR_STATUS_CCE_INT_MAP_COR_ERR_SMASK),
358 CCE_ERR_STATUS_CCE_INT_MAP_UNC_ERR_SMASK),
360 CCE_ERR_STATUS_CCE_MSIX_CSR_PARITY_ERR_SMASK),
361 /*41-63 reserved*/
362 };
364 /*
365 * Misc Error flags
366 */
367 #define MES(text) MISC_ERR_STATUS_MISC_##text##_ERR_SMASK
382 };
384 /*
385 * TXE PIO Error flags and consequences
386 */
389 SEC_WRITE_DROPPED,
390 SEND_PIO_ERR_STATUS_PIO_WRITE_BAD_CTXT_ERR_SMASK),
392 SEC_SPC_FREEZE,
393 SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK),
395 SEC_SPC_FREEZE,
396 SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK),
398 SEC_SPC_FREEZE,
399 SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK),
401 SEC_SPC_FREEZE,
402 SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK),
404 SEC_SPC_FREEZE,
405 SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK),
407 SEC_SPC_FREEZE,
408 SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK),
410 SEC_SPC_FREEZE,
411 SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK),
413 SEC_SPC_FREEZE,
414 SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK),
416 SEC_SPC_FREEZE,
417 SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK),
419 SEC_SPC_FREEZE,
420 SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK),
422 SEC_SPC_FREEZE,
423 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK),
425 SEC_SPC_FREEZE,
426 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK),
429 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_COR_ERR_SMASK),
432 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_COR_ERR_SMASK),
434 SEC_SPC_FREEZE,
435 SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK),
437 SEC_SPC_FREEZE,
438 SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK),
441 SEND_PIO_ERR_STATUS_PIO_INIT_SM_IN_ERR_SMASK),
443 SEC_SPC_FREEZE,
444 SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK),
446 SEC_SPC_FREEZE,
447 SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK),
450 SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_COR_ERR_SMASK),
452 SEC_SPC_FREEZE,
453 SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK),
455 SEC_SPC_FREEZE,
456 SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK),
459 SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK),
462 SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK),
464 SEC_SPC_FREEZE,
465 SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK),
467 SEC_SPC_FREEZE,
468 SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK),
470 SEC_SPC_FREEZE,
471 SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK),
473 SEC_SPC_FREEZE,
474 SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK),
476 SEC_SPC_FREEZE,
477 SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK),
478 /*30-31 reserved*/
480 SEC_SPC_FREEZE,
481 SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK),
483 SEC_SPC_FREEZE,
484 SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK),
486 SEC_SPC_FREEZE,
487 SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK),
489 SEC_SPC_FREEZE,
490 SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK),
491 /*36-63 reserved*/
492 };
494 /* TXE PIO errors that cause an SPC freeze */
495 #define ALL_PIO_FREEZE_ERR \
496 (SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK \
497 | SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK \
498 | SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK \
499 | SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK \
500 | SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK \
501 | SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK \
502 | SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK \
503 | SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK \
504 | SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK \
505 | SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK \
506 | SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK \
507 | SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK \
508 | SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK \
509 | SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK \
510 | SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK \
511 | SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK \
512 | SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK \
513 | SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK \
514 | SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK \
515 | SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK \
516 | SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK \
517 | SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK \
518 | SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK \
519 | SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK \
520 | SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK \
521 | SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK \
522 | SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK \
523 | SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK \
524 | SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK)
526 /*
527 * TXE SDMA Error flags
528 */
531 SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK),
533 SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK),
535 SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK),
537 SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_COR_ERR_SMASK),
538 /*04-63 reserved*/
539 };
541 /* TXE SDMA errors that cause an SPC freeze */
542 #define ALL_SDMA_FREEZE_ERR \
543 (SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK \
544 | SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK \
545 | SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK)
547 /* SendEgressErrInfo bits that correspond to a PortXmitDiscard counter */
548 #define PORT_DISCARD_EGRESS_ERRS \
549 (SEND_EGRESS_ERR_INFO_TOO_LONG_IB_PACKET_ERR_SMASK \
550 | SEND_EGRESS_ERR_INFO_VL_MAPPING_ERR_SMASK \
551 | SEND_EGRESS_ERR_INFO_VL_ERR_SMASK)
553 /*
554 * TXE Egress Error flags
555 */
556 #define SEES(text) SEND_EGRESS_ERR_STATUS_##text##_ERR_SMASK
560 /* 2 reserved */
565 /* 6 reserved */
570 /* 9-10 reserved */
652 };
654 /*
655 * TXE Egress Error Info flags
656 */
657 #define SEEI(text) SEND_EGRESS_ERR_INFO_##text##_ERR_SMASK
681 };
683 /* TXE Egress errors that cause an SPC freeze */
684 #define ALL_TXE_EGRESS_FREEZE_ERR \
685 (SEES(TX_EGRESS_FIFO_UNDERRUN_OR_PARITY) \
686 | SEES(TX_PIO_LAUNCH_INTF_PARITY) \
687 | SEES(TX_SDMA_LAUNCH_INTF_PARITY) \
688 | SEES(TX_SBRD_CTL_STATE_MACHINE_PARITY) \
689 | SEES(TX_LAUNCH_CSR_PARITY) \
690 | SEES(TX_SBRD_CTL_CSR_PARITY) \
691 | SEES(TX_CONFIG_PARITY) \
692 | SEES(TX_LAUNCH_FIFO0_UNC_OR_PARITY) \
693 | SEES(TX_LAUNCH_FIFO1_UNC_OR_PARITY) \
694 | SEES(TX_LAUNCH_FIFO2_UNC_OR_PARITY) \
695 | SEES(TX_LAUNCH_FIFO3_UNC_OR_PARITY) \
696 | SEES(TX_LAUNCH_FIFO4_UNC_OR_PARITY) \
697 | SEES(TX_LAUNCH_FIFO5_UNC_OR_PARITY) \
698 | SEES(TX_LAUNCH_FIFO6_UNC_OR_PARITY) \
699 | SEES(TX_LAUNCH_FIFO7_UNC_OR_PARITY) \
700 | SEES(TX_LAUNCH_FIFO8_UNC_OR_PARITY) \
701 | SEES(TX_CREDIT_RETURN_PARITY))
703 /*
704 * TXE Send error flags
705 */
706 #define SES(name) SEND_ERR_STATUS_SEND_##name##_ERR_SMASK
711 };
713 /*
714 * TXE Send Context Error flags and consequences
715 */
719 SEND_CTXT_ERR_STATUS_PIO_INCONSISTENT_SOP_ERR_SMASK),
722 SEND_CTXT_ERR_STATUS_PIO_DISALLOWED_PACKET_ERR_SMASK),
725 SEND_CTXT_ERR_STATUS_PIO_WRITE_CROSSES_BOUNDARY_ERR_SMASK),
728 SEND_CTXT_ERR_STATUS_PIO_WRITE_OVERFLOW_ERR_SMASK),
731 SEND_CTXT_ERR_STATUS_PIO_WRITE_OUT_OF_BOUNDS_ERR_SMASK),
732 /* 5-63 reserved*/
733 };
735 /*
736 * RXE Receive Error flags
737 */
738 #define RXES(name) RCV_ERR_STATUS_RX_##name##_ERR_SMASK
816 };
818 /* RXE errors that will trigger an SPC freeze */
819 #define ALL_RXE_FREEZE_ERR \
820 (RCV_ERR_STATUS_RX_RCV_QP_MAP_TABLE_UNC_ERR_SMASK \
821 | RCV_ERR_STATUS_RX_RCV_CSR_PARITY_ERR_SMASK \
822 | RCV_ERR_STATUS_RX_DMA_FLAG_UNC_ERR_SMASK \
823 | RCV_ERR_STATUS_RX_RCV_FSM_ENCODING_ERR_SMASK \
824 | RCV_ERR_STATUS_RX_RBUF_FREE_LIST_UNC_ERR_SMASK \
825 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_ERR_SMASK \
826 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR_SMASK \
827 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_UNC_ERR_SMASK \
828 | RCV_ERR_STATUS_RX_RBUF_BLOCK_LIST_READ_UNC_ERR_SMASK \
829 | RCV_ERR_STATUS_RX_RBUF_CSR_QHEAD_BUF_NUM_PARITY_ERR_SMASK \
830 | RCV_ERR_STATUS_RX_RBUF_CSR_QENT_CNT_PARITY_ERR_SMASK \
831 | RCV_ERR_STATUS_RX_RBUF_CSR_QNEXT_BUF_PARITY_ERR_SMASK \
832 | RCV_ERR_STATUS_RX_RBUF_CSR_QVLD_BIT_PARITY_ERR_SMASK \
833 | RCV_ERR_STATUS_RX_RBUF_CSR_QHD_PTR_PARITY_ERR_SMASK \
834 | RCV_ERR_STATUS_RX_RBUF_CSR_QTL_PTR_PARITY_ERR_SMASK \
835 | RCV_ERR_STATUS_RX_RBUF_CSR_QNUM_OF_PKT_PARITY_ERR_SMASK \
836 | RCV_ERR_STATUS_RX_RBUF_CSR_QEOPDW_PARITY_ERR_SMASK \
837 | RCV_ERR_STATUS_RX_RBUF_CTX_ID_PARITY_ERR_SMASK \
838 | RCV_ERR_STATUS_RX_RBUF_BAD_LOOKUP_ERR_SMASK \
839 | RCV_ERR_STATUS_RX_RBUF_FULL_ERR_SMASK \
840 | RCV_ERR_STATUS_RX_RBUF_EMPTY_ERR_SMASK \
841 | RCV_ERR_STATUS_RX_RBUF_FL_RD_ADDR_PARITY_ERR_SMASK \
842 | RCV_ERR_STATUS_RX_RBUF_FL_WR_ADDR_PARITY_ERR_SMASK \
843 | RCV_ERR_STATUS_RX_RBUF_FL_INITDONE_PARITY_ERR_SMASK \
844 | RCV_ERR_STATUS_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR_SMASK \
845 | RCV_ERR_STATUS_RX_RBUF_NEXT_FREE_BUF_UNC_ERR_SMASK \
846 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_ERR_SMASK \
847 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_COR_ERR_SMASK \
848 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART2_PARITY_ERR_SMASK \
849 | RCV_ERR_STATUS_RX_LOOKUP_RCV_ARRAY_UNC_ERR_SMASK \
850 | RCV_ERR_STATUS_RX_LOOKUP_CSR_PARITY_ERR_SMASK \
851 | RCV_ERR_STATUS_RX_HQ_INTR_CSR_PARITY_ERR_SMASK \
852 | RCV_ERR_STATUS_RX_HQ_INTR_FSM_ERR_SMASK \
853 | RCV_ERR_STATUS_RX_RBUF_DESC_PART1_UNC_ERR_SMASK \
854 | RCV_ERR_STATUS_RX_RBUF_DESC_PART1_COR_ERR_SMASK \
855 | RCV_ERR_STATUS_RX_RBUF_DESC_PART2_UNC_ERR_SMASK \
856 | RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK \
857 | RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK \
858 | RCV_ERR_STATUS_RX_RBUF_DATA_UNC_ERR_SMASK \
859 | RCV_ERR_STATUS_RX_DMA_CSR_PARITY_ERR_SMASK \
860 | RCV_ERR_STATUS_RX_DMA_EQ_FSM_ENCODING_ERR_SMASK \
861 | RCV_ERR_STATUS_RX_DMA_DQ_FSM_ENCODING_ERR_SMASK \
862 | RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK \
863 | RCV_ERR_STATUS_RX_CSR_PARITY_ERR_SMASK)
865 #define RXE_FREEZE_ABORT_MASK \
866 (RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK | \
867 RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK | \
868 RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK)
870 /*
871 * DCC Error Flags
872 */
873 #define DCCE(name) DCC_ERR_FLG_##name##_SMASK
921 };
923 /*
924 * LCB error flags
925 */
926 #define LCBE(name) DC_LCB_ERR_FLG_##name##_SMASK
964 };
966 /*
967 * DC8051 Error Flags
968 */
969 #define D8E(name) DC_DC8051_ERR_FLG_##name##_SMASK
982 };
984 /*
985 * DC8051 Information Error flags
986 *
987 * Flags in DC8051_DBG_ERR_INFO_SET_BY_8051.ERROR field.
988 */
994 FAILED_SERDES_INTERNAL_LOOPBACK),
1005 EXTERNAL_DEVICE_REQ_TIMEOUT),
1006 };
1008 /*
1009 * DC8051 Information Host Information flags
1010 *
1011 * Flags in DC8051_DBG_ERR_INFO_SET_BY_8051.HOST_MSG field.
1012 */
1024 };
1061 u32 state);
1088 /*
1089 * Error interrupt table entry. This is used as input to the interrupt
1090 * "clear down" routine used for all second tier error interrupt register.
1091 * Second tier interrupt registers have a single bit representing them
1092 * in the top-level CceIntStatus.
1093 */
1100 };
1102 #define NUM_MISC_ERRS (IS_GENERAL_ERR_END - IS_GENERAL_ERR_START)
1103 #define NUM_DC_ERRS (IS_DC_END - IS_DC_START)
1104 #define NUM_VARIOUS (IS_VARIOUS_END - IS_VARIOUS_START)
1106 /*
1107 * Helpers for building HFI and DC error interrupt table entries. Different
1108 * helpers are needed because of inconsistent register names.
1109 */
1110 #define EE(reg, handler, desc) \
1111 { reg##_STATUS, reg##_CLEAR, reg##_MASK, \
1112 handler, desc }
1113 #define DC_EE1(reg, handler, desc) \
1114 { reg##_FLG, reg##_FLG_CLR, reg##_FLG_EN, handler, desc }
1115 #define DC_EE2(reg, handler, desc) \
1116 { reg##_FLG, reg##_CLR, reg##_EN, handler, desc }
1118 /*
1119 * Table of the "misc" grouping of error interrupts. Each entry refers to
1120 * another register containing more information.
1121 */
1131 /* the rest are reserved */
1132 };
1134 /*
1135 * Index into the Various section of the interrupt sources
1136 * corresponding to the Critical Temperature interrupt.
1137 */
1138 #define TCRIT_INT_SOURCE 4
1140 /*
1141 * SDMA error interrupt entry - refers to another register containing more
1142 * information.
1143 */
1153 /* rest are reserved */
1154 };
1156 /*
1157 * The DC encoding of mtu_cap for 10K MTU in the DCC_CFG_PORT_CONFIG
1158 * register can not be derived from the MTU value because 10K is not
1159 * a power of 2. Therefore, we need a constant. Everything else can
1160 * be calculated.
1161 */
1162 #define DCC_CFG_PORT_MTU_CAP_10240 7
1164 /*
1165 * Table of the DC grouping of error interrupts. Each entry refers to
1166 * another register containing more information.
1167 */
1173 /* the rest are reserved */
1174 };
1177 /*
1178 * counter name
1179 */
1182 /*
1183 * csr to read for name (if applicable)
1184 */
1185 u64 csr;
1187 /*
1188 * offset into dd or ppd to store the counter's value
1189 */
1192 /*
1193 * flags
1194 */
1195 u8 flags;
1197 /*
1198 * accessor for stat element, context either dd or ppd
1199 */
1202 };
1204 #define C_RCV_HDR_OVF_FIRST C_RCV_HDR_OVF_0
1205 #define C_RCV_HDR_OVF_LAST C_RCV_HDR_OVF_159
1207 #define CNTR_ELEM(name, csr, offset, flags, accessor) \
1208 { \
1209 name, \
1210 csr, \
1211 offset, \
1212 flags, \
1213 accessor \
1214 }
1216 /* 32bit RXE */
1217 #define RXE32_PORT_CNTR_ELEM(name, counter, flags) \
1218 CNTR_ELEM(#name, \
1219 (counter * 8 + RCV_COUNTER_ARRAY32), \
1220 0, flags | CNTR_32BIT, \
1221 port_access_u32_csr)
1223 #define RXE32_DEV_CNTR_ELEM(name, counter, flags) \
1224 CNTR_ELEM(#name, \
1225 (counter * 8 + RCV_COUNTER_ARRAY32), \
1226 0, flags | CNTR_32BIT, \
1227 dev_access_u32_csr)
1229 /* 64bit RXE */
1230 #define RXE64_PORT_CNTR_ELEM(name, counter, flags) \
1231 CNTR_ELEM(#name, \
1232 (counter * 8 + RCV_COUNTER_ARRAY64), \
1233 0, flags, \
1234 port_access_u64_csr)
1236 #define RXE64_DEV_CNTR_ELEM(name, counter, flags) \
1237 CNTR_ELEM(#name, \
1238 (counter * 8 + RCV_COUNTER_ARRAY64), \
1239 0, flags, \
1240 dev_access_u64_csr)
1242 #define OVR_LBL(ctx) C_RCV_HDR_OVF_ ## ctx
1243 #define OVR_ELM(ctx) \
1245 (RCV_HDR_OVFL_CNT + ctx * 0x100), \
1246 0, CNTR_NORMAL, port_access_u64_csr)
1248 /* 32bit TXE */
1249 #define TXE32_PORT_CNTR_ELEM(name, counter, flags) \
1250 CNTR_ELEM(#name, \
1251 (counter * 8 + SEND_COUNTER_ARRAY32), \
1252 0, flags | CNTR_32BIT, \
1253 port_access_u32_csr)
1255 /* 64bit TXE */
1256 #define TXE64_PORT_CNTR_ELEM(name, counter, flags) \
1257 CNTR_ELEM(#name, \
1258 (counter * 8 + SEND_COUNTER_ARRAY64), \
1259 0, flags, \
1260 port_access_u64_csr)
1262 # define TX64_DEV_CNTR_ELEM(name, counter, flags) \
1263 CNTR_ELEM(#name,\
1264 counter * 8 + SEND_COUNTER_ARRAY64, \
1265 0, \
1266 flags, \
1267 dev_access_u64_csr)
1269 /* CCE */
1270 #define CCE_PERF_DEV_CNTR_ELEM(name, counter, flags) \
1271 CNTR_ELEM(#name, \
1272 (counter * 8 + CCE_COUNTER_ARRAY32), \
1273 0, flags | CNTR_32BIT, \
1274 dev_access_u32_csr)
1276 #define CCE_INT_DEV_CNTR_ELEM(name, counter, flags) \
1277 CNTR_ELEM(#name, \
1278 (counter * 8 + CCE_INT_COUNTER_ARRAY32), \
1279 0, flags | CNTR_32BIT, \
1280 dev_access_u32_csr)
1282 /* DC */
1283 #define DC_PERF_CNTR(name, counter, flags) \
1284 CNTR_ELEM(#name, \
1285 counter, \
1286 0, \
1287 flags, \
1288 dev_access_u64_csr)
1290 #define DC_PERF_CNTR_LCB(name, counter, flags) \
1291 CNTR_ELEM(#name, \
1292 counter, \
1293 0, \
1294 flags, \
1295 dc_access_lcb_cntr)
1297 /* ibp counters */
1298 #define SW_IBP_CNTR(name, cntr) \
1299 CNTR_ELEM(#name, \
1300 0, \
1301 0, \
1302 CNTR_SYNTH, \
1303 access_ibp_##cntr)
1305 /**
1306 * hfi_addr_from_offset - return addr for readq/writeq
1307 * @dd - the dd device
1308 * @offset - the offset of the CSR within bar0
1309 *
1310 * This routine selects the appropriate base address
1311 * based on the indicated offset.
1312 */
1315 u32 offset)
1316 {
1320 }
1322 /**
1323 * read_csr - read CSR at the indicated offset
1324 * @dd - the dd device
1325 * @offset - the offset of the CSR within bar0
1326 *
1327 * Return: the value read or all FF's if there
1328 * is no mapping
1329 */
1331 {
1335 }
1337 /**
1338 * write_csr - write CSR at the indicated offset
1339 * @dd - the dd device
1340 * @offset - the offset of the CSR within bar0
1341 * @value - value to write
1342 */
1344 {
1348 /* avoid write to RcvArray */
1352 }
1353 }
1355 /**
1356 * get_csr_addr - return te iomem address for offset
1357 * @dd - the dd device
1358 * @offset - the offset of the CSR within bar0
1359 *
1360 * Return: The iomem address to use in subsequent
1361 * writeq/readq operations.
1362 */
1365 u32 offset)
1366 {
1370 }
1374 {
1375 u64 ret;
1385 }
1389 }
1391 /* Dev Access */
1394 {
1405 }
1407 }
1411 {
1417 }
1421 {
1427 }
1431 {
1437 }
1441 u64 data)
1442 {
1448 }
1452 {
1465 }
1469 }
1473 {
1488 }
1492 }
1494 /* Port Access */
1497 {
1503 }
1507 {
1509 u64 val;
1519 }
1522 }
1524 /* Software defined */
1526 u64 data)
1527 {
1528 u64 ret;
1538 }
1543 }
1547 {
1553 }
1557 {
1563 }
1567 u64 data)
1568 {
1574 }
1578 {
1587 else
1591 }
1595 u64 data)
1596 {
1604 }
1608 {
1616 }
1619 {
1626 }
1631 {
1640 /* A write can only zero the counter */
1643 else
1648 }
1651 }
1655 {
1660 }
1664 {
1669 }
1673 {
1677 }
1681 {
1685 }
1689 {
1693 }
1697 {
1701 }
1705 {
1710 }
1712 /* Software counters for the error status bits within MISC_ERR_STATUS */
1715 u64 data)
1716 {
1720 }
1724 u64 data)
1725 {
1729 }
1733 u64 data)
1734 {
1738 }
1743 {
1747 }
1751 u64 data)
1752 {
1756 }
1761 {
1765 }
1770 {
1774 }
1778 u64 data)
1779 {
1783 }
1787 u64 data)
1788 {
1792 }
1797 {
1801 }
1806 {
1810 }
1815 {
1819 }
1823 u64 data)
1824 {
1828 }
1830 /*
1831 * Software counter for the aggregate of
1832 * individual CceErrStatus counters
1833 */
1837 {
1841 }
1843 /*
1844 * Software counters corresponding to each of the
1845 * error status bits within CceErrStatus
1846 */
1849 u64 data)
1850 {
1854 }
1858 u64 data)
1859 {
1863 }
1867 u64 data)
1868 {
1872 }
1876 u64 data)
1877 {
1881 }
1885 u64 data)
1886 {
1890 }
1895 {
1899 }
1904 {
1908 }
1913 {
1917 }
1921 u64 data)
1922 {
1926 }
1930 {
1934 }
1938 u64 data)
1939 {
1943 }
1947 u64 data)
1948 {
1952 }
1957 {
1961 }
1966 {
1970 }
1974 u64 data)
1975 {
1979 }
1983 u64 data)
1984 {
1988 }
1992 u64 data)
1993 {
1997 }
2001 u64 data)
2002 {
2006 }
2011 {
2015 }
2019 u64 data)
2020 {
2024 }
2029 {
2033 }
2038 {
2042 }
2046 u64 data)
2047 {
2051 }
2055 u64 data)
2056 {
2060 }
2064 u64 data)
2065 {
2069 }
2073 u64 data)
2074 {
2078 }
2083 {
2087 }
2091 u64 data)
2092 {
2096 }
2101 {
2105 }
2110 {
2114 }
2119 {
2123 }
2128 {
2132 }
2137 {
2141 }
2146 {
2150 }
2155 {
2159 }
2163 u64 data)
2164 {
2168 }
2172 u64 data)
2173 {
2177 }
2182 {
2186 }
2191 {
2195 }
2200 {
2204 }
2208 u64 data)
2209 {
2213 }
2215 /*
2216 * Software counters corresponding to each of the
2217 * error status bits within RcvErrStatus
2218 */
2221 u64 data)
2222 {
2226 }
2231 {
2235 }
2239 u64 data)
2240 {
2244 }
2248 u64 data)
2249 {
2253 }
2258 {
2262 }
2267 {
2271 }
2275 u64 data)
2276 {
2280 }
2284 u64 data)
2285 {
2289 }
2293 u64 data)
2294 {
2298 }
2303 {
2307 }
2312 {
2316 }
2321 {
2325 }
2330 {
2334 }
2339 {
2343 }
2348 {
2352 }
2357 {
2361 }
2366 {
2370 }
2374 u64 data)
2375 {
2379 }
2384 {
2388 }
2393 {
2397 }
2402 {
2406 }
2411 {
2415 }
2420 {
2424 }
2429 {
2433 }
2438 {
2442 }
2447 {
2451 }
2456 {
2460 }
2465 {
2469 }
2474 {
2478 }
2483 {
2487 }
2492 {
2496 }
2500 u64 data)
2501 {
2505 }
2509 u64 data)
2510 {
2514 }
2518 u64 data)
2519 {
2523 }
2527 u64 data)
2528 {
2532 }
2537 {
2541 }
2546 {
2550 }
2555 {
2559 }
2564 {
2568 }
2573 {
2577 }
2582 {
2586 }
2591 {
2595 }
2600 {
2604 }
2609 {
2613 }
2618 {
2622 }
2627 {
2631 }
2636 {
2640 }
2645 {
2649 }
2654 {
2658 }
2663 {
2667 }
2672 {
2676 }
2680 u64 data)
2681 {
2685 }
2689 u64 data)
2690 {
2694 }
2698 u64 data)
2699 {
2703 }
2707 u64 data)
2708 {
2712 }
2716 u64 data)
2717 {
2721 }
2726 {
2730 }
2735 {
2739 }
2743 u64 data)
2744 {
2748 }
2752 u64 data)
2753 {
2757 }
2761 u64 data)
2762 {
2766 }
2770 u64 data)
2771 {
2775 }
2779 u64 data)
2780 {
2784 }
2788 u64 data)
2789 {
2793 }
2795 /*
2796 * Software counters corresponding to each of the
2797 * error status bits within SendPioErrStatus
2798 */
2802 {
2806 }
2811 {
2815 }
2820 {
2824 }
2829 {
2833 }
2837 u64 data)
2838 {
2842 }
2846 u64 data)
2847 {
2851 }
2855 u64 data)
2856 {
2860 }
2865 {
2869 }
2873 u64 data)
2874 {
2878 }
2882 u64 data)
2883 {
2887 }
2892 {
2896 }
2901 {
2905 }
2910 {
2914 }
2918 u64 data)
2919 {
2923 }
2928 {
2932 }
2937 {
2941 }
2946 {
2950 }
2955 {
2959 }
2963 u64 data)
2964 {
2968 }
2972 u64 data)
2973 {
2977 }
2982 {
2986 }
2991 {
2995 }
3000 {
3004 }
3009 {
3013 }
3018 {
3022 }
3027 {
3031 }
3036 {
3040 }
3045 {
3049 }
3054 {
3058 }
3062 u64 data)
3063 {
3067 }
3071 u64 data)
3072 {
3076 }
3080 u64 data)
3081 {
3085 }
3089 u64 data)
3090 {
3094 }
3098 u64 data)
3099 {
3103 }
3108 {
3112 }
3116 u64 data)
3117 {
3121 }
3123 /*
3124 * Software counters corresponding to each of the
3125 * error status bits within SendDmaErrStatus
3126 */
3130 {
3134 }
3139 {
3143 }
3147 u64 data)
3148 {
3152 }
3156 u64 data)
3157 {
3161 }
3163 /*
3164 * Software counters corresponding to each of the
3165 * error status bits within SendEgressErrStatus
3166 */
3170 {
3174 }
3179 {
3183 }
3187 u64 data)
3188 {
3192 }
3197 {
3201 }
3206 {
3210 }
3214 u64 data)
3215 {
3219 }
3223 u64 data)
3224 {
3228 }
3232 u64 data)
3233 {
3237 }
3241 u64 data)
3242 {
3246 }
3250 u64 data)
3251 {
3255 }
3259 u64 data)
3260 {
3264 }
3268 u64 data)
3269 {
3273 }
3277 u64 data)
3278 {
3282 }
3286 u64 data)
3287 {
3291 }
3295 u64 data)
3296 {
3300 }
3304 u64 data)
3305 {
3309 }
3313 u64 data)
3314 {
3318 }
3322 u64 data)
3323 {
3327 }
3331 u64 data)
3332 {
3336 }
3341 {
3345 }
3350 {
3354 }
3358 u64 data)
3359 {
3363 }
3368 {
3372 }
3377 {
3381 }
3386 {
3390 }
3395 {
3399 }
3404 {
3408 }
3413 {
3417 }
3422 {
3426 }
3431 {
3435 }
3440 {
3444 }
3449 {
3453 }
3458 {
3462 }
3467 {
3471 }
3476 {
3480 }
3485 {
3489 }
3494 {
3498 }
3503 {
3507 }
3512 {
3516 }
3521 {
3525 }
3530 {
3534 }
3539 {
3543 }
3548 {
3552 }
3557 {
3561 }
3566 {
3570 }
3575 {
3579 }
3584 {
3588 }
3593 {
3597 }
3601 u64 data)
3602 {
3606 }
3611 {
3615 }
3619 u64 data)
3620 {
3624 }
3628 u64 data)
3629 {
3633 }
3638 {
3642 }
3646 u64 data)
3647 {
3651 }
3655 u64 data)
3656 {
3660 }
3665 {
3669 }
3674 {
3678 }
3682 u64 data)
3683 {
3687 }
3692 {
3696 }
3700 u64 data)
3701 {
3705 }
3710 {
3714 }
3718 u64 data)
3719 {
3723 }
3728 {
3732 }
3737 {
3741 }
3743 /*
3744 * Software counters corresponding to each of the
3745 * error status bits within SendErrStatus
3746 */
3750 {
3754 }
3759 {
3763 }
3767 u64 data)
3768 {
3772 }
3774 /*
3775 * Software counters corresponding to each of the
3776 * error status bits within SendCtxtErrStatus
3777 */
3781 {
3785 }
3789 u64 data)
3790 {
3794 }
3799 {
3803 }
3808 {
3812 }
3816 u64 data)
3817 {
3821 }
3823 /*
3824 * Software counters corresponding to each of the
3825 * error status bits within SendDmaEngErrStatus
3826 */
3830 {
3834 }
3839 {
3843 }
3848 {
3852 }
3856 u64 data)
3857 {
3861 }
3865 u64 data)
3866 {
3870 }
3875 {
3879 }
3884 {
3888 }
3893 {
3897 }
3901 u64 data)
3902 {
3906 }
3910 u64 data)
3911 {
3915 }
3919 u64 data)
3920 {
3924 }
3928 u64 data)
3929 {
3933 }
3937 u64 data)
3938 {
3942 }
3946 u64 data)
3947 {
3951 }
3955 u64 data)
3956 {
3960 }
3965 {
3969 }
3974 {
3978 }
3982 {
3986 }
3990 u64 data)
3991 {
3995 }
3999 u64 data)
4000 {
4004 }
4009 {
4013 }
4017 u64 data)
4018 {
4022 }
4026 u64 data)
4027 {
4031 }
4035 u64 data)
4036 {
4040 }
4044 u64 data)
4045 {
4060 }
4062 }
4064 #define def_access_sw_cpu(cntr) \
4065 static u64 access_sw_cpu_##cntr(const struct cntr_entry *entry, \
4066 void *context, int vl, int mode, u64 data) \
4067 { \
4068 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context; \
4069 return read_write_cpu(ppd->dd, &ppd->ibport_data.rvp.z_ ##cntr, \
4070 ppd->ibport_data.rvp.cntr, vl, \
4071 mode, data); \
4072 }
4078 #define def_access_ibp_counter(cntr) \
4079 static u64 access_ibp_##cntr(const struct cntr_entry *entry, \
4080 void *context, int vl, int mode, u64 data) \
4081 { \
4082 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context; \
4083 \
4084 if (vl != CNTR_INVALID_VL) \
4085 return 0; \
4086 \
4087 return read_write_sw(ppd->dd, &ppd->ibport_data.rvp.n_ ##cntr, \
4088 mode, data); \
4089 }
4107 CNTR_NORMAL),
4109 CNTR_NORMAL),
4111 RCV_TID_FLOW_GEN_MISMATCH_CNT,
4112 CNTR_NORMAL),
4114 CNTR_NORMAL),
4120 CNTR_NORMAL),
4122 CNTR_NORMAL),
4124 CNTR_NORMAL),
4126 CNTR_NORMAL),
4128 CNTR_NORMAL),
4130 CNTR_NORMAL),
4136 CNTR_SYNTH),
4138 access_dc_rcv_err_cnt),
4140 CNTR_SYNTH),
4142 CNTR_SYNTH),
4144 CNTR_SYNTH),
4148 DCC_PRF_PORT_RCV_MULTICAST_PKT_CNT,
4149 CNTR_SYNTH),
4153 CNTR_SYNTH),
4155 CNTR_SYNTH),
4157 CNTR_SYNTH),
4159 CNTR_SYNTH),
4161 CNTR_SYNTH),
4163 CNTR_SYNTH),
4165 CNTR_SYNTH),
4177 CNTR_SYNTH),
4181 CNTR_SYNTH),
4186 CNTR_SYNTH),
4188 CNTR_SYNTH),
4190 CNTR_SYNTH),
4192 CNTR_SYNTH),
4194 CNTR_SYNTH),
4197 CNTR_SYNTH),
4199 CNTR_SYNTH),
4201 CNTR_SYNTH),
4204 CNTR_SYNTH),
4207 CNTR_SYNTH),
4210 CNTR_SYNTH),
4213 CNTR_SYNTH),
4216 CNTR_SYNTH),
4218 CNTR_SYNTH),
4221 CNTR_SYNTH),
4226 CNTR_SYNTH),
4237 CNTR_SYNTH),
4242 CNTR_SYNTH),
4244 access_sw_cpu_intr),
4246 access_sw_cpu_rcv_limit),
4248 access_sw_vtx_wait),
4250 access_sw_pio_wait),
4252 access_sw_pio_drain),
4254 access_sw_kmem_wait),
4256 access_sw_send_schedule),
4260 dev_access_u32_csr),
4263 access_sde_int_cnt),
4266 access_sde_err_cnt),
4269 access_sde_idle_int_cnt),
4272 access_sde_progress_int_cnt),
4273 /* MISC_ERR_STATUS */
4275 CNTR_NORMAL,
4276 access_misc_pll_lock_fail_err_cnt),
4278 CNTR_NORMAL,
4279 access_misc_mbist_fail_err_cnt),
4281 CNTR_NORMAL,
4282 access_misc_invalid_eep_cmd_err_cnt),
4284 CNTR_NORMAL,
4285 access_misc_efuse_done_parity_err_cnt),
4287 CNTR_NORMAL,
4288 access_misc_efuse_write_err_cnt),
4291 access_misc_efuse_read_bad_addr_err_cnt),
4293 CNTR_NORMAL,
4294 access_misc_efuse_csr_parity_err_cnt),
4296 CNTR_NORMAL,
4297 access_misc_fw_auth_failed_err_cnt),
4299 CNTR_NORMAL,
4300 access_misc_key_mismatch_err_cnt),
4302 CNTR_NORMAL,
4303 access_misc_sbus_write_failed_err_cnt),
4305 CNTR_NORMAL,
4306 access_misc_csr_write_bad_addr_err_cnt),
4308 CNTR_NORMAL,
4309 access_misc_csr_read_bad_addr_err_cnt),
4311 CNTR_NORMAL,
4312 access_misc_csr_parity_err_cnt),
4313 /* CceErrStatus */
4315 CNTR_NORMAL,
4316 access_sw_cce_err_status_aggregated_cnt),
4318 CNTR_NORMAL,
4319 access_cce_msix_csr_parity_err_cnt),
4321 CNTR_NORMAL,
4322 access_cce_int_map_unc_err_cnt),
4324 CNTR_NORMAL,
4325 access_cce_int_map_cor_err_cnt),
4327 CNTR_NORMAL,
4328 access_cce_msix_table_unc_err_cnt),
4330 CNTR_NORMAL,
4331 access_cce_msix_table_cor_err_cnt),
4334 access_cce_rxdma_conv_fifo_parity_err_cnt),
4337 access_cce_rcpl_async_fifo_parity_err_cnt),
4339 CNTR_NORMAL,
4340 access_cce_seg_write_bad_addr_err_cnt),
4342 CNTR_NORMAL,
4343 access_cce_seg_read_bad_addr_err_cnt),
4345 CNTR_NORMAL,
4346 access_la_triggered_cnt),
4348 CNTR_NORMAL,
4349 access_cce_trgt_cpl_timeout_err_cnt),
4351 CNTR_NORMAL,
4352 access_pcic_receive_parity_err_cnt),
4354 CNTR_NORMAL,
4355 access_pcic_transmit_back_parity_err_cnt),
4358 access_pcic_transmit_front_parity_err_cnt),
4360 CNTR_NORMAL,
4361 access_pcic_cpl_dat_q_unc_err_cnt),
4363 CNTR_NORMAL,
4364 access_pcic_cpl_hd_q_unc_err_cnt),
4366 CNTR_NORMAL,
4367 access_pcic_post_dat_q_unc_err_cnt),
4369 CNTR_NORMAL,
4370 access_pcic_post_hd_q_unc_err_cnt),
4372 CNTR_NORMAL,
4373 access_pcic_retry_sot_mem_unc_err_cnt),
4375 CNTR_NORMAL,
4376 access_pcic_retry_mem_unc_err),
4378 CNTR_NORMAL,
4379 access_pcic_n_post_dat_q_parity_err_cnt),
4381 CNTR_NORMAL,
4382 access_pcic_n_post_h_q_parity_err_cnt),
4384 CNTR_NORMAL,
4385 access_pcic_cpl_dat_q_cor_err_cnt),
4387 CNTR_NORMAL,
4388 access_pcic_cpl_hd_q_cor_err_cnt),
4390 CNTR_NORMAL,
4391 access_pcic_post_dat_q_cor_err_cnt),
4393 CNTR_NORMAL,
4394 access_pcic_post_hd_q_cor_err_cnt),
4396 CNTR_NORMAL,
4397 access_pcic_retry_sot_mem_cor_err_cnt),
4399 CNTR_NORMAL,
4400 access_pcic_retry_mem_cor_err_cnt),
4403 CNTR_NORMAL,
4404 access_cce_cli1_async_fifo_dbg_parity_err_cnt),
4407 CNTR_NORMAL,
4408 access_cce_cli1_async_fifo_rxdma_parity_err_cnt
4409 ),
4412 CNTR_NORMAL,
4413 access_cce_cli1_async_fifo_sdma_hd_parity_err_cnt),
4416 CNTR_NORMAL,
4417 access_cce_cl1_async_fifo_pio_crdt_parity_err_cnt),
4420 access_cce_cli2_async_fifo_parity_err_cnt),
4422 CNTR_NORMAL,
4423 access_cce_csr_cfg_bus_parity_err_cnt),
4426 access_cce_cli0_async_fifo_parity_err_cnt),
4428 CNTR_NORMAL,
4429 access_cce_rspd_data_parity_err_cnt),
4431 CNTR_NORMAL,
4432 access_cce_trgt_access_err_cnt),
4435 access_cce_trgt_async_fifo_parity_err_cnt),
4437 CNTR_NORMAL,
4438 access_cce_csr_write_bad_addr_err_cnt),
4440 CNTR_NORMAL,
4441 access_cce_csr_read_bad_addr_err_cnt),
4443 CNTR_NORMAL,
4444 access_ccs_csr_parity_err_cnt),
4446 /* RcvErrStatus */
4448 CNTR_NORMAL,
4449 access_rx_csr_parity_err_cnt),
4451 CNTR_NORMAL,
4452 access_rx_csr_write_bad_addr_err_cnt),
4454 CNTR_NORMAL,
4455 access_rx_csr_read_bad_addr_err_cnt),
4457 CNTR_NORMAL,
4458 access_rx_dma_csr_unc_err_cnt),
4460 CNTR_NORMAL,
4461 access_rx_dma_dq_fsm_encoding_err_cnt),
4463 CNTR_NORMAL,
4464 access_rx_dma_eq_fsm_encoding_err_cnt),
4466 CNTR_NORMAL,
4467 access_rx_dma_csr_parity_err_cnt),
4469 CNTR_NORMAL,
4470 access_rx_rbuf_data_cor_err_cnt),
4472 CNTR_NORMAL,
4473 access_rx_rbuf_data_unc_err_cnt),
4475 CNTR_NORMAL,
4476 access_rx_dma_data_fifo_rd_cor_err_cnt),
4478 CNTR_NORMAL,
4479 access_rx_dma_data_fifo_rd_unc_err_cnt),
4481 CNTR_NORMAL,
4482 access_rx_dma_hdr_fifo_rd_cor_err_cnt),
4484 CNTR_NORMAL,
4485 access_rx_dma_hdr_fifo_rd_unc_err_cnt),
4487 CNTR_NORMAL,
4488 access_rx_rbuf_desc_part2_cor_err_cnt),
4490 CNTR_NORMAL,
4491 access_rx_rbuf_desc_part2_unc_err_cnt),
4493 CNTR_NORMAL,
4494 access_rx_rbuf_desc_part1_cor_err_cnt),
4496 CNTR_NORMAL,
4497 access_rx_rbuf_desc_part1_unc_err_cnt),
4499 CNTR_NORMAL,
4500 access_rx_hq_intr_fsm_err_cnt),
4502 CNTR_NORMAL,
4503 access_rx_hq_intr_csr_parity_err_cnt),
4505 CNTR_NORMAL,
4506 access_rx_lookup_csr_parity_err_cnt),
4508 CNTR_NORMAL,
4509 access_rx_lookup_rcv_array_cor_err_cnt),
4511 CNTR_NORMAL,
4512 access_rx_lookup_rcv_array_unc_err_cnt),
4515 access_rx_lookup_des_part2_parity_err_cnt),
4518 access_rx_lookup_des_part1_unc_cor_err_cnt),
4520 CNTR_NORMAL,
4521 access_rx_lookup_des_part1_unc_err_cnt),
4523 CNTR_NORMAL,
4524 access_rx_rbuf_next_free_buf_cor_err_cnt),
4526 CNTR_NORMAL,
4527 access_rx_rbuf_next_free_buf_unc_err_cnt),
4530 CNTR_NORMAL,
4531 access_rbuf_fl_init_wr_addr_parity_err_cnt),
4534 access_rx_rbuf_fl_initdone_parity_err_cnt),
4537 access_rx_rbuf_fl_write_addr_parity_err_cnt),
4539 CNTR_NORMAL,
4540 access_rx_rbuf_fl_rd_addr_parity_err_cnt),
4542 CNTR_NORMAL,
4543 access_rx_rbuf_empty_err_cnt),
4545 CNTR_NORMAL,
4546 access_rx_rbuf_full_err_cnt),
4548 CNTR_NORMAL,
4549 access_rbuf_bad_lookup_err_cnt),
4551 CNTR_NORMAL,
4552 access_rbuf_ctx_id_parity_err_cnt),
4554 CNTR_NORMAL,
4555 access_rbuf_csr_qeopdw_parity_err_cnt),
4558 CNTR_NORMAL,
4559 access_rx_rbuf_csr_q_num_of_pkt_parity_err_cnt),
4562 CNTR_NORMAL,
4563 access_rx_rbuf_csr_q_t1_ptr_parity_err_cnt),
4566 access_rx_rbuf_csr_q_hd_ptr_parity_err_cnt),
4569 access_rx_rbuf_csr_q_vld_bit_parity_err_cnt),
4572 access_rx_rbuf_csr_q_next_buf_parity_err_cnt),
4575 access_rx_rbuf_csr_q_ent_cnt_parity_err_cnt),
4578 CNTR_NORMAL,
4579 access_rx_rbuf_csr_q_head_buf_num_parity_err_cnt),
4582 access_rx_rbuf_block_list_read_cor_err_cnt),
4585 access_rx_rbuf_block_list_read_unc_err_cnt),
4587 CNTR_NORMAL,
4588 access_rx_rbuf_lookup_des_cor_err_cnt),
4590 CNTR_NORMAL,
4591 access_rx_rbuf_lookup_des_unc_err_cnt),
4594 CNTR_NORMAL,
4595 access_rx_rbuf_lookup_des_reg_unc_cor_err_cnt),
4597 CNTR_NORMAL,
4598 access_rx_rbuf_lookup_des_reg_unc_err_cnt),
4600 CNTR_NORMAL,
4601 access_rx_rbuf_free_list_cor_err_cnt),
4603 CNTR_NORMAL,
4604 access_rx_rbuf_free_list_unc_err_cnt),
4606 CNTR_NORMAL,
4607 access_rx_rcv_fsm_encoding_err_cnt),
4609 CNTR_NORMAL,
4610 access_rx_dma_flag_cor_err_cnt),
4612 CNTR_NORMAL,
4613 access_rx_dma_flag_unc_err_cnt),
4615 CNTR_NORMAL,
4616 access_rx_dc_sop_eop_parity_err_cnt),
4618 CNTR_NORMAL,
4619 access_rx_rcv_csr_parity_err_cnt),
4621 CNTR_NORMAL,
4622 access_rx_rcv_qp_map_table_cor_err_cnt),
4624 CNTR_NORMAL,
4625 access_rx_rcv_qp_map_table_unc_err_cnt),
4627 CNTR_NORMAL,
4628 access_rx_rcv_data_cor_err_cnt),
4630 CNTR_NORMAL,
4631 access_rx_rcv_data_unc_err_cnt),
4633 CNTR_NORMAL,
4634 access_rx_rcv_hdr_cor_err_cnt),
4636 CNTR_NORMAL,
4637 access_rx_rcv_hdr_unc_err_cnt),
4639 CNTR_NORMAL,
4640 access_rx_dc_intf_parity_err_cnt),
4642 CNTR_NORMAL,
4643 access_rx_dma_csr_cor_err_cnt),
4644 /* SendPioErrStatus */
4646 CNTR_NORMAL,
4647 access_pio_pec_sop_head_parity_err_cnt),
4649 CNTR_NORMAL,
4650 access_pio_pcc_sop_head_parity_err_cnt),
4653 access_pio_last_returned_cnt_parity_err_cnt),
4656 access_pio_current_free_cnt_parity_err_cnt),
4658 CNTR_NORMAL,
4659 access_pio_reserved_31_err_cnt),
4661 CNTR_NORMAL,
4662 access_pio_reserved_30_err_cnt),
4664 CNTR_NORMAL,
4665 access_pio_ppmc_sop_len_err_cnt),
4667 CNTR_NORMAL,
4668 access_pio_ppmc_bqc_mem_parity_err_cnt),
4670 CNTR_NORMAL,
4671 access_pio_vl_fifo_parity_err_cnt),
4673 CNTR_NORMAL,
4674 access_pio_vlf_sop_parity_err_cnt),
4676 CNTR_NORMAL,
4677 access_pio_vlf_v1_len_parity_err_cnt),
4679 CNTR_NORMAL,
4680 access_pio_block_qw_count_parity_err_cnt),
4682 CNTR_NORMAL,
4683 access_pio_write_qw_valid_parity_err_cnt),
4685 CNTR_NORMAL,
4686 access_pio_state_machine_err_cnt),
4688 CNTR_NORMAL,
4689 access_pio_write_data_parity_err_cnt),
4691 CNTR_NORMAL,
4692 access_pio_host_addr_mem_cor_err_cnt),
4694 CNTR_NORMAL,
4695 access_pio_host_addr_mem_unc_err_cnt),
4697 CNTR_NORMAL,
4698 access_pio_pkt_evict_sm_or_arb_sm_err_cnt),
4700 CNTR_NORMAL,
4701 access_pio_init_sm_in_err_cnt),
4703 CNTR_NORMAL,
4704 access_pio_ppmc_pbl_fifo_err_cnt),
4707 access_pio_credit_ret_fifo_parity_err_cnt),
4709 CNTR_NORMAL,
4710 access_pio_v1_len_mem_bank1_cor_err_cnt),
4712 CNTR_NORMAL,
4713 access_pio_v1_len_mem_bank0_cor_err_cnt),
4715 CNTR_NORMAL,
4716 access_pio_v1_len_mem_bank1_unc_err_cnt),
4718 CNTR_NORMAL,
4719 access_pio_v1_len_mem_bank0_unc_err_cnt),
4721 CNTR_NORMAL,
4722 access_pio_sm_pkt_reset_parity_err_cnt),
4724 CNTR_NORMAL,
4725 access_pio_pkt_evict_fifo_parity_err_cnt),
4728 CNTR_NORMAL,
4729 access_pio_sbrdctrl_crrel_fifo_parity_err_cnt),
4731 CNTR_NORMAL,
4732 access_pio_sbrdctl_crrel_parity_err_cnt),
4734 CNTR_NORMAL,
4735 access_pio_pec_fifo_parity_err_cnt),
4737 CNTR_NORMAL,
4738 access_pio_pcc_fifo_parity_err_cnt),
4740 CNTR_NORMAL,
4741 access_pio_sb_mem_fifo1_err_cnt),
4743 CNTR_NORMAL,
4744 access_pio_sb_mem_fifo0_err_cnt),
4746 CNTR_NORMAL,
4747 access_pio_csr_parity_err_cnt),
4749 CNTR_NORMAL,
4750 access_pio_write_addr_parity_err_cnt),
4752 CNTR_NORMAL,
4753 access_pio_write_bad_ctxt_err_cnt),
4754 /* SendDmaErrStatus */
4757 access_sdma_pcie_req_tracking_cor_err_cnt),
4760 access_sdma_pcie_req_tracking_unc_err_cnt),
4762 CNTR_NORMAL,
4763 access_sdma_csr_parity_err_cnt),
4765 CNTR_NORMAL,
4766 access_sdma_rpy_tag_err_cnt),
4767 /* SendEgressErrStatus */
4769 CNTR_NORMAL,
4770 access_tx_read_pio_memory_csr_unc_err_cnt),
4773 access_tx_read_sdma_memory_csr_err_cnt),
4775 CNTR_NORMAL,
4776 access_tx_egress_fifo_cor_err_cnt),
4778 CNTR_NORMAL,
4779 access_tx_read_pio_memory_cor_err_cnt),
4781 CNTR_NORMAL,
4782 access_tx_read_sdma_memory_cor_err_cnt),
4784 CNTR_NORMAL,
4785 access_tx_sb_hdr_cor_err_cnt),
4787 CNTR_NORMAL,
4788 access_tx_credit_overrun_err_cnt),
4790 CNTR_NORMAL,
4791 access_tx_launch_fifo8_cor_err_cnt),
4793 CNTR_NORMAL,
4794 access_tx_launch_fifo7_cor_err_cnt),
4796 CNTR_NORMAL,
4797 access_tx_launch_fifo6_cor_err_cnt),
4799 CNTR_NORMAL,
4800 access_tx_launch_fifo5_cor_err_cnt),
4802 CNTR_NORMAL,
4803 access_tx_launch_fifo4_cor_err_cnt),
4805 CNTR_NORMAL,
4806 access_tx_launch_fifo3_cor_err_cnt),
4808 CNTR_NORMAL,
4809 access_tx_launch_fifo2_cor_err_cnt),
4811 CNTR_NORMAL,
4812 access_tx_launch_fifo1_cor_err_cnt),
4814 CNTR_NORMAL,
4815 access_tx_launch_fifo0_cor_err_cnt),
4817 CNTR_NORMAL,
4818 access_tx_credit_return_vl_err_cnt),
4820 CNTR_NORMAL,
4821 access_tx_hcrc_insertion_err_cnt),
4823 CNTR_NORMAL,
4824 access_tx_egress_fifo_unc_err_cnt),
4826 CNTR_NORMAL,
4827 access_tx_read_pio_memory_unc_err_cnt),
4829 CNTR_NORMAL,
4830 access_tx_read_sdma_memory_unc_err_cnt),
4832 CNTR_NORMAL,
4833 access_tx_sb_hdr_unc_err_cnt),
4835 CNTR_NORMAL,
4836 access_tx_credit_return_partiy_err_cnt),
4839 access_tx_launch_fifo8_unc_or_parity_err_cnt),
4842 access_tx_launch_fifo7_unc_or_parity_err_cnt),
4845 access_tx_launch_fifo6_unc_or_parity_err_cnt),
4848 access_tx_launch_fifo5_unc_or_parity_err_cnt),
4851 access_tx_launch_fifo4_unc_or_parity_err_cnt),
4854 access_tx_launch_fifo3_unc_or_parity_err_cnt),
4857 access_tx_launch_fifo2_unc_or_parity_err_cnt),
4860 access_tx_launch_fifo1_unc_or_parity_err_cnt),
4863 access_tx_launch_fifo0_unc_or_parity_err_cnt),
4866 access_tx_sdma15_disallowed_packet_err_cnt),
4869 access_tx_sdma14_disallowed_packet_err_cnt),
4872 access_tx_sdma13_disallowed_packet_err_cnt),
4875 access_tx_sdma12_disallowed_packet_err_cnt),
4878 access_tx_sdma11_disallowed_packet_err_cnt),
4881 access_tx_sdma10_disallowed_packet_err_cnt),
4884 access_tx_sdma9_disallowed_packet_err_cnt),
4887 access_tx_sdma8_disallowed_packet_err_cnt),
4890 access_tx_sdma7_disallowed_packet_err_cnt),
4893 access_tx_sdma6_disallowed_packet_err_cnt),
4896 access_tx_sdma5_disallowed_packet_err_cnt),
4899 access_tx_sdma4_disallowed_packet_err_cnt),
4902 access_tx_sdma3_disallowed_packet_err_cnt),
4905 access_tx_sdma2_disallowed_packet_err_cnt),
4908 access_tx_sdma1_disallowed_packet_err_cnt),
4911 access_tx_sdma0_disallowed_packet_err_cnt),
4913 CNTR_NORMAL,
4914 access_tx_config_parity_err_cnt),
4916 CNTR_NORMAL,
4917 access_tx_sbrd_ctl_csr_parity_err_cnt),
4919 CNTR_NORMAL,
4920 access_tx_launch_csr_parity_err_cnt),
4922 CNTR_NORMAL,
4923 access_tx_illegal_vl_err_cnt),
4926 CNTR_NORMAL,
4927 access_tx_sbrd_ctl_state_machine_parity_err_cnt),
4929 CNTR_NORMAL,
4930 access_egress_reserved_10_err_cnt),
4932 CNTR_NORMAL,
4933 access_egress_reserved_9_err_cnt),
4936 access_tx_sdma_launch_intf_parity_err_cnt),
4938 CNTR_NORMAL,
4939 access_tx_pio_launch_intf_parity_err_cnt),
4941 CNTR_NORMAL,
4942 access_egress_reserved_6_err_cnt),
4944 CNTR_NORMAL,
4945 access_tx_incorrect_link_state_err_cnt),
4947 CNTR_NORMAL,
4948 access_tx_linkdown_err_cnt),
4951 CNTR_NORMAL,
4952 access_tx_egress_fifi_underrun_or_parity_err_cnt),
4954 CNTR_NORMAL,
4955 access_egress_reserved_2_err_cnt),
4957 CNTR_NORMAL,
4958 access_tx_pkt_integrity_mem_unc_err_cnt),
4960 CNTR_NORMAL,
4961 access_tx_pkt_integrity_mem_cor_err_cnt),
4962 /* SendErrStatus */
4964 CNTR_NORMAL,
4965 access_send_csr_write_bad_addr_err_cnt),
4967 CNTR_NORMAL,
4968 access_send_csr_read_bad_addr_err_cnt),
4970 CNTR_NORMAL,
4971 access_send_csr_parity_cnt),
4972 /* SendCtxtErrStatus */
4974 CNTR_NORMAL,
4975 access_pio_write_out_of_bounds_err_cnt),
4977 CNTR_NORMAL,
4978 access_pio_write_overflow_err_cnt),
4981 access_pio_write_crosses_boundary_err_cnt),
4983 CNTR_NORMAL,
4984 access_pio_disallowed_packet_err_cnt),
4986 CNTR_NORMAL,
4987 access_pio_inconsistent_sop_err_cnt),
4988 /* SendDmaEngErrStatus */
4991 access_sdma_header_request_fifo_cor_err_cnt),
4993 CNTR_NORMAL,
4994 access_sdma_header_storage_cor_err_cnt),
4996 CNTR_NORMAL,
4997 access_sdma_packet_tracking_cor_err_cnt),
4999 CNTR_NORMAL,
5000 access_sdma_assembly_cor_err_cnt),
5002 CNTR_NORMAL,
5003 access_sdma_desc_table_cor_err_cnt),
5006 access_sdma_header_request_fifo_unc_err_cnt),
5008 CNTR_NORMAL,
5009 access_sdma_header_storage_unc_err_cnt),
5011 CNTR_NORMAL,
5012 access_sdma_packet_tracking_unc_err_cnt),
5014 CNTR_NORMAL,
5015 access_sdma_assembly_unc_err_cnt),
5017 CNTR_NORMAL,
5018 access_sdma_desc_table_unc_err_cnt),
5020 CNTR_NORMAL,
5021 access_sdma_timeout_err_cnt),
5023 CNTR_NORMAL,
5024 access_sdma_header_length_err_cnt),
5026 CNTR_NORMAL,
5027 access_sdma_header_address_err_cnt),
5029 CNTR_NORMAL,
5030 access_sdma_header_select_err_cnt),
5032 CNTR_NORMAL,
5033 access_sdma_reserved_9_err_cnt),
5035 CNTR_NORMAL,
5036 access_sdma_packet_desc_overflow_err_cnt),
5038 CNTR_NORMAL,
5039 access_sdma_length_mismatch_err_cnt),
5041 CNTR_NORMAL,
5042 access_sdma_halt_err_cnt),
5044 CNTR_NORMAL,
5045 access_sdma_mem_read_err_cnt),
5047 CNTR_NORMAL,
5048 access_sdma_first_desc_err_cnt),
5050 CNTR_NORMAL,
5051 access_sdma_tail_out_of_bounds_err_cnt),
5053 CNTR_NORMAL,
5054 access_sdma_too_long_err_cnt),
5056 CNTR_NORMAL,
5057 access_sdma_gen_mismatch_err_cnt),
5059 CNTR_NORMAL,
5060 access_sdma_wrong_dw_err_cnt),
5061 };
5065 CNTR_NORMAL),
5067 CNTR_NORMAL),
5069 CNTR_NORMAL),
5071 CNTR_NORMAL),
5073 CNTR_NORMAL),
5075 CNTR_NORMAL),
5077 CNTR_NORMAL),
5090 access_sw_link_dn_cnt),
5092 access_sw_link_up_cnt),
5094 access_sw_unknown_frame_cnt),
5096 access_sw_xmit_discards),
5099 access_sw_xmit_discards),
5101 access_xmit_constraint_errs),
5103 access_rcv_constraint_errs),
5117 access_sw_cpu_rc_acks),
5119 access_sw_cpu_rc_qacks),
5121 access_sw_cpu_rc_delayed_comp),
5202 };
5204 /* ======================================================================== */
5206 /* return true if this is chip revision revision a */
5208 {
5209 u8 chip_rev_minor =
5213 }
5215 /* return true if this is chip revision revision b */
5217 {
5218 u8 chip_rev_minor =
5222 }
5224 /*
5225 * Append string s to buffer buf. Arguments curp and len are the current
5226 * position and remaining length, respectively.
5227 *
5228 * return 0 on success, 1 on out of room
5229 */
5231 {
5237 /* add a comma, if first in the buffer */
5242 }
5244 len--;
5245 }
5247 /* copy the string */
5252 }
5254 len--;
5255 }
5257 done:
5258 /* write return values */
5263 }
5265 /*
5266 * Using the given flag table, print a comma separated string into
5267 * the buffer. End in '*' if the buffer is too short.
5268 */
5271 {
5278 /* make sure there is at least 2 so we can form "*" */
5289 }
5290 }
5292 /* any undocumented bits left? */
5296 }
5298 /* add * if ran out of room */
5300 /* may need to back up to add space for a '*' */
5304 }
5306 /* add final nul - space already allocated above */
5309 }
5311 /* first 8 CCE error interrupt source names */
5321 };
5323 /*
5324 * Return the miscellaneous error interrupt name.
5325 */
5327 {
5330 else
5335 }
5337 /*
5338 * Return the SDMA engine error interrupt name.
5339 */
5341 {
5344 }
5346 /*
5347 * Return the send context error interrupt name.
5348 */
5350 {
5353 }
5360 "TCritInt"
5361 };
5363 /*
5364 * Return the various interrupt name.
5365 */
5367 {
5370 else
5373 }
5375 /*
5376 * Return the DC interrupt name.
5377 */
5379 {
5385 };
5389 else
5392 }
5398 };
5400 /*
5401 * Return the SDMA engine interrupt name.
5402 */
5404 {
5405 /* what interrupt */
5407 /* which engine */
5412 else
5415 }
5417 /*
5418 * Return the receive available interrupt name.
5419 */
5421 {
5424 }
5426 /*
5427 * Return the receive urgent interrupt name.
5428 */
5430 {
5433 }
5435 /*
5436 * Return the send credit interrupt name.
5437 */
5439 {
5442 }
5444 /*
5445 * Return the reserved interrupt name.
5446 */
5448 {
5451 }
5454 {
5456 cce_err_status_flags,
5458 }
5461 {
5463 rxe_err_status_flags,
5465 }
5468 {
5471 }
5474 {
5476 pio_err_status_flags,
5478 }
5481 {
5483 sdma_err_status_flags,
5485 }
5488 {
5490 egress_err_status_flags,
5492 }
5495 {
5497 egress_err_info_flags,
5499 }
5502 {
5504 send_err_status_flags,
5506 }
5509 {
5513 /*
5514 * For most these errors, there is nothing that can be done except
5515 * report or record it.
5516 */
5522 /* this error requires a manual drop into SPC freeze mode */
5523 /* then a fix up */
5525 }
5530 /* maintain a counter over all cce_err_status errors */
5532 }
5533 }
5534 }
5536 /*
5537 * Check counters for receive errors that do not have an interrupt
5538 * associated with them.
5539 */
5540 #define RCVERR_CHECK_TIME 10
5542 {
5552 OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN);
5554 }
5558 }
5561 {
5563 /* Assume the hardware counter has been reset */
5566 }
5569 {
5572 }
5575 {
5585 /*
5586 * Freeze mode recovery is disabled for the errors
5587 * in RXE_FREEZE_ABORT_MASK
5588 */
5593 }
5598 }
5599 }
5602 {
5611 }
5612 }
5615 {
5628 }
5629 }
5632 {
5645 }
5646 }
5649 {
5651 }
5654 {
5656 }
5658 /*
5659 * We have had a "disallowed packet" error during egress. Determine the
5660 * integrity check which failed, and update relevant error counter, etc.
5661 *
5662 * Note that the SEND_EGRESS_ERR_INFO register has only a single
5663 * bit of state per integrity check, and so we can miss the reason for an
5664 * egress error if more than one packet fails the same integrity check
5665 * since we cleared the corresponding bit in SEND_EGRESS_ERR_INFO.
5666 */
5669 {
5675 /* clear down all observed info as quickly as possible after read */
5682 /* Eventually add other counters for each bit */
5686 /*
5687 * Count all applicable bits as individual errors and
5688 * attribute them to the packet that triggered this handler.
5689 * This may not be completely accurate due to limitations
5690 * on the available hardware error information. There is
5691 * a single information register and any number of error
5692 * packets may have occurred and contributed to it before
5693 * this routine is called. This means that:
5694 * a) If multiple packets with the same error occur before
5695 * this routine is called, earlier packets are missed.
5696 * There is only a single bit for each error type.
5697 * b) Errors may not be attributed to the correct VL.
5698 * The driver is attributing all bits in the info register
5699 * to the packet that triggered this call, but bits
5700 * could be an accumulation of different packets with
5701 * different VLs.
5702 * c) A single error packet may have multiple counts attached
5703 * to it. There is no way for the driver to know if
5704 * multiple bits set in the info register are due to a
5705 * single packet or multiple packets. The driver assumes
5706 * multiple packets.
5707 */
5716 }
5717 }
5718 }
5720 /*
5721 * Input value is a bit position within the SEND_EGRESS_ERR_STATUS
5722 * register. Does it represent a 'port inactive' error?
5723 */
5725 {
5728 }
5730 /*
5731 * Input value is a bit position within the SEND_EGRESS_ERR_STATUS
5732 * register. Does it represent a 'disallowed packet' error?
5733 */
5735 {
5738 }
5740 /*
5741 * Input value is a bit position of one of the SDMA engine disallowed
5742 * packet errors. Return which engine. Use of this must be guarded by
5743 * disallowed_pkt_err().
5744 */
5746 {
5748 }
5750 /*
5751 * Translate an SDMA engine to a VL. Return -1 if the tranlation cannot
5752 * be done.
5753 */
5755 {
5759 /* range check */
5769 }
5771 /*
5772 * Translate the send context (sofware index) into a VL. Return -1 if the
5773 * translation cannot be done.
5774 */
5776 {
5783 /* there is no information for user (PSM) and ack contexts */
5797 }
5800 {
5814 /* fls64() returns a 1-based offset, we want it zero based */
5826 }
5828 }
5839 }
5840 }
5843 {
5853 }
5854 }
5856 /*
5857 * The maximum number of times the error clear down will loop before
5858 * blocking a repeating error. This value is arbitrary.
5859 */
5860 #define MAX_CLEAR_COUNT 20
5862 /*
5863 * Clear and handle an error register. All error interrupts are funneled
5864 * through here to have a central location to correctly handle single-
5865 * or multi-shot errors.
5866 *
5867 * For non per-context registers, call this routine with a context value
5868 * of 0 so the per-context offset is zero.
5869 *
5870 * If the handler loops too many times, assume that something is wrong
5871 * and can't be fixed, so mask the error bits.
5872 */
5874 u32 context,
5876 {
5877 u64 reg;
5878 u32 count;
5880 /* read in a loop until no more errors are seen */
5889 count++;
5891 u64 mask;
5895 /*
5896 * Read-modify-write so any other masked bits
5897 * remain masked.
5898 */
5903 }
5904 }
5905 }
5907 /*
5908 * CCE block "misc" interrupt. Source is < 16.
5909 */
5911 {
5918 source);
5919 }
5920 }
5923 {
5925 sc_err_status_flags,
5927 }
5929 /*
5930 * Send context error interrupt. Source (hw_context) is < 160.
5931 *
5932 * All send context errors cause the send context to halt. The normal
5933 * clear-down mechanism cannot be used because we cannot clear the
5934 * error bits until several other long-running items are done first.
5935 * This is OK because with the context halted, nothing else is going
5936 * to happen on it anyway.
5937 */
5940 {
5944 u64 status;
5945 u32 sw_index;
5954 }
5961 }
5963 /* tell the software that a halt has begun */
5970 status));
5975 /*
5976 * Automatically restart halted kernel contexts out of interrupt
5977 * context. User contexts must ask the driver to restart the context.
5978 */
5982 /*
5983 * Update the counters for the corresponding status bits.
5984 * Note that these particular counters are aggregated over all
5985 * 160 contexts.
5986 */
5990 }
5991 }
5995 {
6000 #ifdef CONFIG_SDMA_VERBOSITY
6005 #endif
6009 /*
6010 * Update the counters for the corresponding status bits.
6011 * Note that these particular counters are aggregated over
6012 * all 16 DMA engines.
6013 */
6017 }
6018 }
6020 /*
6021 * CCE block SDMA error interrupt. Source is < 16.
6022 */
6024 {
6025 #ifdef CONFIG_SDMA_VERBOSITY
6031 source);
6033 #endif
6035 }
6037 /*
6038 * CCE block "various" interrupt. Source is < 8.
6039 */
6041 {
6044 /*
6045 * TCritInt cannot go through interrupt_clear_down()
6046 * because it is not a second tier interrupt. The handler
6047 * should be called directly.
6048 */
6053 else
6057 }
6060 {
6061 /* src_ctx is always zero */
6069 __func__);
6072 /*
6073 * Cable removed, reset all our information about the
6074 * cache and cable capabilities
6075 */
6078 /*
6079 * We don't set cache_refresh_required here as we expect
6080 * an interrupt when a cable is inserted
6081 */
6086 flags);
6087 /* Invert the ModPresent pin now to detect plug-in */
6093 OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED)) ||
6098 OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED);
6101 /*
6102 * The link is still in POLL. This means
6103 * that the normal link down processing
6104 * will not happen. We have to do it here
6105 * before turning the DC off.
6106 */
6108 }
6111 __func__);
6117 flags);
6119 /*
6120 * Stop inversion of ModPresent pin to detect
6121 * removal of the cable
6122 */
6129 }
6130 }
6134 __func__);
6138 }
6140 /* Schedule the QSFP work only if there is a cable attached. */
6143 }
6146 {
6155 }
6157 }
6160 {
6169 }
6171 }
6173 /*
6174 * Set the LCB selector - allow host access. The DCC selector always
6175 * points to the host.
6176 */
6178 {
6180 DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK |
6181 DC_DC8051_CFG_CSR_ACCESS_SEL_LCB_SMASK);
6182 }
6184 /*
6185 * Clear the LCB selector - allow 8051 access. The DCC selector always
6186 * points to the host.
6187 */
6189 {
6191 DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK);
6192 }
6194 /*
6195 * Acquire LCB access from the 8051. If the host already has access,
6196 * just increment a counter. Otherwise, inform the 8051 that the
6197 * host is taking access.
6198 *
6199 * Returns:
6200 * 0 on success
6201 * -EBUSY if the 8051 has control and cannot be disturbed
6202 * -errno if unable to acquire access from the 8051
6203 */
6205 {
6209 /*
6210 * Use the host link state lock so the operation of this routine
6211 * { link state check, selector change, count increment } can occur
6212 * as a unit against a link state change. Otherwise there is a
6213 * race between the state change and the count increment.
6214 */
6220 }
6222 /* this access is valid only when the link is up */
6228 }
6237 }
6239 }
6241 done:
6244 }
6246 /*
6247 * Release LCB access by decrementing the use count. If the count is moving
6248 * from 1 to 0, inform 8051 that it has control back.
6249 *
6250 * Returns:
6251 * 0 on success
6252 * -errno if unable to release access to the 8051
6253 */
6255 {
6258 /*
6259 * Use the host link state lock because the acquire needed it.
6260 * Here, we only need to keep { selector change, count decrement }
6261 * as a unit.
6262 */
6268 }
6272 __func__);
6274 }
6283 /* restore host access if the grant didn't work */
6286 }
6287 }
6289 done:
6292 }
6294 /*
6295 * Initialize LCB access variables and state. Called during driver load,
6296 * after most of the initialization is finished.
6297 *
6298 * The DC default is LCB access on for the host. The driver defaults to
6299 * leaving access to the 8051. Assign access now - this constrains the call
6300 * to this routine to be after all LCB set-up is done. In particular, after
6301 * hf1_init_dd() -> set_up_interrupts() -> clear_all_interrupts()
6302 */
6304 {
6306 }
6308 /*
6309 * Write a response back to a 8051 request.
6310 */
6312 {
6314 DC_DC8051_CFG_EXT_DEV_0_COMPLETED_SMASK |
6316 DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT |
6318 }
6320 /*
6321 * Handle host requests from the 8051.
6322 */
6324 {
6326 u64 reg;
6328 u8 type;
6334 /* zero out COMPLETED so the response is seen */
6337 /* extract request details */
6351 type);
6365 }
6366 }
6368 /*
6369 * Set up allocation unit vaulue.
6370 */
6372 {
6375 /* do not modify other values in the register */
6379 }
6381 /*
6382 * Set up initial VL15 credits of the remote. Assumes the rest of
6383 * the CM credit registers are zero from a previous global or credit reset.
6384 * Shared limit for VL15 will always be 0.
6385 */
6387 {
6390 /* set initial values for total and shared credit limit */
6392 SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SMASK);
6394 /*
6395 * Set total limit to be equal to VL15 credits.
6396 * Leave shared limit at 0.
6397 */
6403 }
6405 /*
6406 * Zero all credit details from the previous connection and
6407 * reset the CM manager's internal counters.
6408 */
6410 {
6413 /* remove all previous VL credit limits */
6418 /* reset the CM block */
6420 /* reset cached value */
6422 }
6424 /* convert a vCU to a CU */
6426 {
6428 }
6430 /* convert a CU to a vCU */
6432 {
6434 }
6436 /* convert a vAU to an AU */
6438 {
6440 }
6443 {
6446 }
6448 /*
6449 * Graceful LCB shutdown. This leaves the LCB FIFOs in reset.
6450 */
6452 {
6453 u64 reg;
6455 /* clear lcb run: LCB_CFG_RUN.EN = 0 */
6457 /* set tx fifo reset: LCB_CFG_TX_FIFOS_RESET.VAL = 1 */
6460 /* set dcc reset csr: DCC_CFG_RESET.{reset_lcb,reset_rx_fpe} = 1 */
6471 }
6472 }
6474 /*
6475 * This routine should be called after the link has been transitioned to
6476 * OFFLINE (OFFLINE state has the side effect of putting the SerDes into
6477 * reset).
6478 *
6479 * The expectation is that the caller of this routine would have taken
6480 * care of properly transitioning the link into the correct state.
6481 * NOTE: the caller needs to acquire the dd->dc8051_lock lock
6482 * before calling this function.
6483 */
6485 {
6492 /* Shutdown the LCB */
6494 /*
6495 * Going to OFFLINE would have causes the 8051 to put the
6496 * SerDes into reset already. Just need to shut down the 8051,
6497 * itself.
6498 */
6500 }
6503 {
6507 }
6509 /*
6510 * Calling this after the DC has been brought out of reset should not
6511 * do any damage.
6512 * NOTE: the caller needs to acquire the dd->dc8051_lock lock
6513 * before calling this function.
6514 */
6516 {
6522 /* Take the 8051 out of reset */
6524 /* Wait until 8051 is ready */
6527 __func__);
6529 /* Take away reset for LCB and RX FPE (set in lcb_shutdown). */
6531 /* lcb_shutdown() with abort=1 does not restore these */
6534 }
6537 {
6541 }
6543 /*
6544 * These LCB adjustments are for the Aurora SerDes core in the FPGA.
6545 */
6547 {
6549 u32 version;
6554 /*
6555 * These LCB defaults on emulator _s are good, nothing to do here:
6556 * LCB_CFG_TX_FIFOS_RADR
6557 * LCB_CFG_RX_FIFOS_RADR
6558 * LCB_CFG_LN_DCLK
6559 * LCB_CFG_IGNORE_LOST_RCLK
6560 */
6563 /* else this is _p */
6570 /* release 0x12 and below */
6572 /*
6573 * LCB_CFG_RX_FIFOS_RADR.RST_VAL = 0x9
6574 * LCB_CFG_RX_FIFOS_RADR.OK_TO_JUMP_VAL = 0x9
6575 * LCB_CFG_RX_FIFOS_RADR.DO_NOT_JUMP_VAL = 0xa
6576 */
6577 rx_radr =
6581 /*
6582 * LCB_CFG_TX_FIFOS_RADR.ON_REINIT = 0 (default)
6583 * LCB_CFG_TX_FIFOS_RADR.RST_VAL = 6
6584 */
6587 /* release 0x13 up to 0x18 */
6588 /* LCB_CFG_RX_FIFOS_RADR = 0x988 */
6589 rx_radr =
6595 /* release 0x19 */
6596 /* LCB_CFG_RX_FIFOS_RADR = 0xa99 */
6597 rx_radr =
6603 /* release 0x1a */
6604 /* LCB_CFG_RX_FIFOS_RADR = 0x988 */
6605 rx_radr =
6612 /* release 0x1b and higher */
6613 /* LCB_CFG_RX_FIFOS_RADR = 0x877 */
6614 rx_radr =
6619 }
6622 /* LCB_CFG_IGNORE_LOST_RCLK.EN = 1 */
6624 DC_LCB_CFG_IGNORE_LOST_RCLK_EN_SMASK);
6626 }
6628 /*
6629 * Handle a SMA idle message
6630 *
6631 * This is a work-queue function outside of the interrupt.
6632 */
6634 {
6636 sma_message_work);
6638 u64 msg;
6641 /*
6642 * msg is bytes 1-4 of the 40-bit idle message - the command code
6643 * is stripped off
6644 */
6649 /*
6650 * React to the SMA message. Byte[1] (0 for us) is the command.
6651 */
6654 /*
6655 * See OPAv1 table 9-14 - HFI and External Switch Ports Key
6656 * State Transitions
6657 *
6658 * Only expected in INIT or ARMED, discard otherwise.
6659 */
6664 /*
6665 * See OPAv1 table 9-14 - HFI and External Switch Ports Key
6666 * State Transitions
6667 *
6668 * Can activate the node. Discard otherwise.
6669 */
6676 dd,
6678 __func__);
6679 }
6686 }
6687 }
6690 {
6691 u64 rcvctrl;
6700 }
6703 {
6705 }
6708 {
6710 }
6712 /*
6713 * Called from all interrupt handlers to start handling an SPC freeze.
6714 */
6716 {
6724 /* enter frozen mode */
6727 /* notify all SDMA engines that they are going into a freeze */
6730 /* do halt pre-handling on all enabled send contexts */
6735 }
6737 /* Send context are frozen. Notify user space */
6744 }
6745 /* queue non-interrupt handler */
6747 }
6749 /*
6750 * Wait until all 4 sub-blocks indicate that they have frozen or unfrozen,
6751 * depending on the "freeze" parameter.
6752 *
6753 * No need to return an error if it times out, our only option
6754 * is to proceed anyway.
6755 */
6757 {
6759 u64 reg;
6765 /* waiting until all indicators are set */
6769 /* waiting until all indicators are clear */
6772 }
6780 }
6782 }
6783 }
6785 /*
6786 * Do all freeze handling for the RXE block.
6787 */
6789 {
6793 /* disable port */
6796 /* disable all receive contexts */
6801 }
6802 }
6804 /*
6805 * Unfreeze handling for the RXE block - kernel contexts only.
6806 * This will also enable the port. User contexts will do unfreeze
6807 * handling on a per-context basis as they call into the driver.
6808 *
6809 */
6811 {
6812 u32 rcvmask;
6813 u16 i;
6816 /* enable all kernel contexts */
6820 /* Ensure all non-user contexts(including vnic) are enabled */
6825 }
6827 /* HFI1_RCVCTRL_TAILUPD_[ENB|DIS] needs to be set explicitly */
6832 }
6834 /* enable port */
6836 }
6838 /*
6839 * Non-interrupt SPC freeze handling.
6840 *
6841 * This is a work-queue function outside of the triggering interrupt.
6842 */
6844 {
6846 freeze_work);
6849 /* wait for freeze indicators on all affected blocks */
6852 /* SPC is now frozen */
6854 /* do send PIO freeze steps */
6857 /* do send DMA freeze steps */
6860 /* do send egress freeze steps - nothing to do */
6862 /* do receive freeze steps */
6865 /*
6866 * Unfreeze the hardware - clear the freeze, wait for each
6867 * block's frozen bit to clear, then clear the frozen flag.
6868 */
6877 }
6879 /* do send PIO unfreeze steps for kernel contexts */
6882 /* do send DMA unfreeze steps */
6885 /* do send egress unfreeze steps - nothing to do */
6887 /* do receive unfreeze steps for kernel contexts */
6890 /*
6891 * The unfreeze procedure touches global device registers when
6892 * it disables and re-enables RXE. Mark the device unfrozen
6893 * after all that is done so other parts of the driver waiting
6894 * for the device to unfreeze don't do things out of order.
6895 *
6896 * The above implies that the meaning of HFI1_FROZEN flag is
6897 * "Device has gone into freeze mode and freeze mode handling
6898 * is still in progress."
6899 *
6900 * The flag will be removed when freeze mode processing has
6901 * completed.
6902 */
6906 /* no longer frozen */
6907 }
6909 /**
6910 * update_xmit_counters - update PortXmitWait/PortVlXmitWait
6911 * counters.
6912 * @ppd: info of physical Hfi port
6913 * @link_width: new link width after link up or downgrade
6914 *
6915 * Update the PortXmitWait and PortVlXmitWait counters after
6916 * a link up or downgrade event to reflect a link width change.
6917 */
6919 {
6921 u16 tx_width;
6922 u16 link_speed;
6927 /*
6928 * There are C_VL_COUNT number of PortVLXmitWait counters.
6929 * Adding 1 to C_VL_COUNT to include the PortXmitWait counter.
6930 */
6933 }
6935 /*
6936 * Handle a link up interrupt from the 8051.
6937 *
6938 * This is a work-queue function outside of the interrupt.
6939 */
6941 {
6943 link_up_work);
6948 /* cache the read of DC_LCB_STS_ROUND_TRIP_LTP_CNT */
6950 /*
6951 * OPA specifies that certain counters are cleared on a transition
6952 * to link up, so do that.
6953 */
6955 /*
6956 * And (re)set link up default values.
6957 */
6960 /*
6961 * Set VL15 credits. Use cached value from verify cap interrupt.
6962 * In case of quick linkup or simulator, vl15 value will be set by
6963 * handle_linkup_change. VerifyCap interrupt handler will not be
6964 * called in those scenarios.
6965 */
6969 /* enforce link speed enabled */
6971 /* oops - current speed is not enabled, bounce */
6976 OPA_LINKDOWN_REASON_SPEED_POLICY);
6979 }
6980 }
6982 /*
6983 * Several pieces of LNI information were cached for SMA in ppd.
6984 * Reset these on link down
6985 */
6987 {
6992 }
7048 };
7050 /* return the neighbor link down reason string */
7052 {
7061 }
7063 /*
7064 * Handle a link down interrupt from the 8051.
7065 *
7066 * This is a work-queue function outside of the interrupt.
7067 */
7069 {
7071 u8 link_down_reason;
7073 link_down_work);
7083 /* Go offline first, then deal with reading/writing through 8051 */
7090 /* link down reason is only valid if the link was up */
7094 /* the link went down, no idle message reason */
7096 ldr_str);
7099 /*
7100 * The neighbor reason is only valid if an idle message
7101 * was received for it.
7102 */
7112 ldr_str);
7118 }
7120 /*
7121 * If no reason, assume peer-initiated but missed
7122 * LinkGoingDown idle flits.
7123 */
7127 /* went down while polling or going up */
7129 }
7133 /* inform the SMA when the link transitions from up to down */
7140 }
7144 /* disable the port */
7147 /*
7148 * If there is no cable attached, turn the DC off. Otherwise,
7149 * start the link bring up.
7150 */
7153 else
7155 }
7158 {
7160 link_bounce_work);
7162 /*
7163 * Only do something if the link is currently up.
7164 */
7171 }
7172 }
7174 /*
7175 * Mask conversion: Capability exchange to Port LTP. The capability
7176 * exchange has an implicit 16b CRC that is mandatory.
7177 */
7179 {
7190 }
7192 /*
7193 * Convert an OPA Port LTP mask to capability mask
7194 */
7196 {
7207 }
7209 /*
7210 * Convert a single DC LCB CRC mode to an OPA Port LTP mask.
7211 */
7213 {
7222 else
7226 }
7229 {
7234 }
7235 }
7237 /*
7238 * Convert the given link width to the OPA link width bitmask.
7239 */
7241 {
7244 /*
7245 * Simulator and quick linkup do not set the width.
7246 * Just set it to 4x without complaint.
7247 */
7257 /* fall through */
7259 }
7260 }
7262 /*
7263 * Do a population count on the bottom nibble.
7264 */
7267 };
7270 {
7272 }
7274 /*
7275 * Read the active lane information from the 8051 registers and return
7276 * their widths.
7277 *
7278 * Active lane information is found in these 8051 registers:
7279 * enable_lane_tx
7280 * enable_lane_rx
7281 */
7284 {
7286 u8 enable_lane_rx;
7287 u8 enable_lane_tx;
7288 u8 tx_polarity_inversion;
7289 u8 rx_polarity_inversion;
7290 u8 max_rate;
7292 /* read the active lanes */
7297 /* convert to counts */
7301 /*
7302 * Set link_speed_active here, overriding what was set in
7303 * handle_verify_cap(). The ASIC 8051 firmware does not correctly
7304 * set the max_rate field in handle_verify_cap until v0.19.
7305 */
7308 /* max_rate: 0 = 12.5G, 1 = 25G */
7317 /* fall through */
7321 }
7322 }
7329 }
7331 /*
7332 * Read verify_cap_local_fm_link_width[1] to obtain the link widths.
7333 * Valid after the end of VerifyCap and during LinkUp. Does not change
7334 * after link up. I.e. look elsewhere for downgrade information.
7335 *
7336 * Bits are:
7337 * + bits [7:4] contain the number of active transmitters
7338 * + bits [3:0] contain the number of active receivers
7339 * These are numbers 1 through 4 and can be different values if the
7340 * link is asymmetric.
7341 *
7342 * verify_cap_local_fm_link_width[0] retains its original value.
7343 */
7346 {
7358 /* print the active widths */
7360 }
7362 /*
7363 * Set ppd->link_width_active and ppd->link_width_downgrade_active using
7364 * hardware information when the link first comes up.
7365 *
7366 * The link width is not available until after VerifyCap.AllFramesReceived
7367 * (the trigger for handle_verify_cap), so this is outside that routine
7368 * and should be called when the 8051 signals linkup.
7369 */
7371 {
7374 /* get end-of-LNI link widths */
7377 /* use tx_width as the link is supposed to be symmetric on link up */
7379 /* link width downgrade active (LWD.A) starts out matching LW.A */
7382 /* per OPA spec, on link up LWD.E resets to LWD.S */
7384 /* cache the active egress rate (units {10^6 bits/sec]) */
7386 }
7388 /*
7389 * Handle a verify capabilities interrupt from the 8051.
7390 *
7391 * This is a work-queue function outside of the interrupt.
7392 */
7394 {
7396 link_vc_work);
7398 u64 reg;
7399 u8 power_management;
7400 u8 continuous;
7401 u8 vcu;
7402 u8 vau;
7403 u8 z;
7404 u16 vl15buf;
7405 u16 link_widths;
7406 u16 crc_mask;
7407 u16 crc_val;
7408 u16 device_id;
7410 u8 partner_supported_crc;
7411 u8 remote_tx_rate;
7412 u8 device_rev;
7425 /* print the active widths */
7438 /*
7439 * The peer vAU value just read is the peer receiver value. HFI does
7440 * not support a transmit vAU of 0 (AU == 8). We advertised that
7441 * with Z=1 in the fabric capabilities sent to the peer. The peer
7442 * will see our Z=1, and, if it advertised a vAU of 0, will move its
7443 * receive to vAU of 1 (AU == 16). Do the same here. We do not care
7444 * about the peer Z value - our sent vAU is 3 (hardwired) and is not
7445 * subject to the Z value exception.
7446 */
7451 /*
7452 * Set VL15 credits to 0 in global credit register. Cache remote VL15
7453 * credits value and wait for link-up interrupt ot set it.
7454 */
7458 /* set up the LCB CRC mode */
7461 /* order is important: use the lowest bit in common */
7468 else
7475 /* set (14b only) or clear sideband credit */
7483 }
7487 /* remote_tx_rate: 0 = 12.5G, 1 = 25G */
7495 }
7497 /* actual rate is highest bit of the ANDed rates */
7504 }
7509 }
7511 /*
7512 * Cache the values of the supported, enabled, and active
7513 * LTP CRC modes to return in 'portinfo' queries. But the bit
7514 * flags that are returned in the portinfo query differ from
7515 * what's in the link_crc_mask, crc_sizes, and crc_val
7516 * variables. Convert these here.
7517 */
7519 /* supported crc modes */
7522 /* enabled crc modes */
7524 /* active crc mode */
7526 /* set up the remote credit return table */
7529 /*
7530 * The LCB is reset on entry to handle_verify_cap(), so this must
7531 * be applied on every link up.
7532 *
7533 * Adjust LCB error kill enable to kill the link if
7534 * these RBUF errors are seen:
7535 * REPLAY_BUF_MBE_SMASK
7536 * FLIT_INPUT_BUF_MBE_SMASK
7537 */
7540 reg |= DC_LCB_CFG_LINK_KILL_EN_REPLAY_BUF_MBE_SMASK
7543 }
7545 /* pull LCB fifos out of reset - all fifo clocks must be stable */
7548 /* give 8051 access to the LCB CSRs */
7552 /* tell the 8051 to go to LinkUp */
7554 }
7556 /**
7557 * apply_link_downgrade_policy - Apply the link width downgrade enabled
7558 * policy against the current active link widths.
7559 * @ppd: info of physical Hfi port
7560 * @refresh_widths: True indicates link downgrade event
7561 * @return: True indicates a successful link downgrade. False indicates
7562 * link downgrade event failed and the link will bounce back to
7563 * default link width.
7564 *
7565 * Called when the enabled policy changes or the active link widths
7566 * change.
7567 * Refresh_widths indicates that a link downgrade occurred. The
7568 * link_downgraded variable is set by refresh_widths and
7569 * determines the success/failure of the policy application.
7570 */
7573 {
7576 u16 lwde;
7580 /* use the hls lock to avoid a race with actual link up */
7582 retry:
7584 /* only apply if the link is up */
7586 /* still going up..wait and retry */
7592 }
7595 __func__);
7596 }
7598 }
7606 }
7610 /* the 8051 reported a dead link as a downgrade */
7614 /* downgrade is disabled */
7616 /* bounce if not at starting active width */
7630 }
7633 /* Tx or Rx is outside the enabled policy */
7642 }
7644 done:
7649 OPA_LINKDOWN_REASON_WIDTH_POLICY);
7652 }
7655 }
7657 /*
7658 * Handle a link downgrade interrupt from the 8051.
7659 *
7660 * This is a work-queue function outside of the interrupt.
7661 */
7663 {
7665 link_downgrade_work);
7670 }
7673 {
7676 }
7679 {
7682 }
7685 {
7688 }
7691 {
7694 }
7697 {
7700 }
7703 {
7709 /* look at the flags */
7711 /* 8051 information set by firmware */
7712 /* read DC8051_DBG_ERR_INFO_SET_BY_8051 for details */
7717 DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_SHIFT)
7720 /*
7721 * Handle error flags.
7722 */
7724 /*
7725 * LNI error indications are cleared by the 8051
7726 * only when starting polling. Only pay attention
7727 * to them when in the states that occur during
7728 * LNI.
7729 */
7736 err &
7737 FAILED_LNI));
7738 }
7740 }
7741 /* unknown frames can happen durning LNI, just count */
7745 }
7747 /* report remaining errors, but do not do anything */
7750 err));
7751 }
7753 /*
7754 * Handle host message flags.
7755 */
7757 /*
7758 * Presently, the driver does a busy wait for
7759 * host requests to complete. This is only an
7760 * informational message.
7761 * NOTE: The 8051 clears the host message
7762 * information *on the next 8051 command*.
7763 * Therefore, when linkup is achieved,
7764 * this flag will still be set.
7765 */
7767 }
7771 }
7776 }
7780 }
7784 }
7787 /* no downgrade action needed if going down */
7791 }
7795 }
7799 }
7801 /* report remaining messages, but do not do anything */
7805 host_msg));
7806 }
7809 }
7811 /*
7812 * Lost the 8051 heartbeat. If this happens, we
7813 * receive constant interrupts about it. Disable
7814 * the interrupt after the first.
7815 */
7822 }
7824 /* report the error, but do not do anything */
7827 }
7830 /*
7831 * if the link is already going down or disabled, do not
7832 * queue another. If there's a link down entry already
7833 * queued, don't queue another one.
7834 */
7845 __func__);
7846 else
7848 }
7849 }
7850 }
7867 /* no 7 */
7870 };
7880 "BadSLID: Illegal SLID (0, using multicast as SLID, does not include security validation of SLID)",
7893 };
7895 #define OPA_LDR_FMCONFIG_OFFSET 16
7896 #define OPA_LDR_PORTRCV_OFFSET 0
7898 {
7910 /* set status bit */
7912 }
7914 }
7918 /* this counter saturates at (2^32) - 1 */
7922 }
7930 /* set status bit */
7932 }
7946 OPA_PI_MASK_FM_CFG_UNSUPPORTED_VL_MARKER) {
7948 /*
7949 * lcl_reason cannot be derived from info
7950 * for this error
7951 */
7952 lcl_reason =
7953 OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER;
7954 }
7961 }
7967 }
7969 /* just report this */
7971 extra);
7973 }
7982 OPA_EI_STATUS_SMASK)) {
7985 /* set status bit */
7987 OPA_EI_STATUS_SMASK;
7988 /*
7989 * save first 2 flits in the packet that caused
7990 * the error
7991 */
7994 }
8013 }
8019 }
8021 /* just report this */
8027 }
8030 /* informative only */
8033 }
8035 /* informative only */
8038 }
8043 /* report any remaining errors */
8053 __func__);
8056 }
8057 }
8060 {
8065 }
8067 /*
8068 * CCE block DC interrupt. Source is < 8.
8069 */
8071 {
8077 /*
8078 * This indicates that a parity error has occurred on the
8079 * address/control lines presented to the LBM. The error
8080 * is a single pulse, there is no associated error flag,
8081 * and it is non-maskable. This is because if a parity
8082 * error occurs on the request the request is dropped.
8083 * This should never occur, but it is nice to know if it
8084 * ever does.
8085 */
8089 }
8090 }
8092 /*
8093 * TX block send credit interrupt. Source is < 160.
8094 */
8096 {
8098 }
8100 /*
8101 * TX block SDMA interrupt. Source is < 48.
8102 *
8103 * SDMA interrupts are grouped by type:
8104 *
8105 * 0 - N-1 = SDma
8106 * N - 2N-1 = SDmaProgress
8107 * 2N - 3N-1 = SDmaIdle
8108 */
8110 {
8111 /* what interrupt */
8113 /* which engine */
8116 #ifdef CONFIG_SDMA_VERBOSITY
8120 #endif
8125 /* should not happen */
8127 }
8128 }
8130 /*
8131 * RX block receive available interrupt. Source is < 160.
8132 */
8134 {
8141 /* Check for non-user contexts, including vnic */
8144 else
8149 }
8150 /* received an interrupt, but no rcd */
8153 /* received an interrupt, but are not using that context */
8155 }
8158 }
8160 /*
8161 * RX block receive urgent interrupt. Source is < 160.
8162 */
8164 {
8171 /* only pay attention to user urgent interrupts */
8178 }
8179 /* received an interrupt, but no rcd */
8182 /* received an interrupt, but are not using that context */
8184 }
8187 }
8189 /*
8190 * Reserved range interrupt. Should not be called in normal operation.
8191 */
8193 {
8198 }
8201 /*
8202 * start end
8203 * name func interrupt func
8204 */
8225 };
8227 /*
8228 * Interrupt source interrupt - called when the given source has an interrupt.
8229 * Source is a bit index into an array of 64-bit integers.
8230 */
8232 {
8235 /* avoids a double compare by walking the table in-order */
8241 }
8242 }
8243 /* fell off the end */
8245 }
8247 /*
8248 * General interrupt handler. This is able to correctly handle
8249 * all interrupts in case INTx is used.
8250 */
8252 {
8255 u32 bit;
8261 /* phase 1: scan and clear all handled interrupts */
8266 }
8269 /* only clear if anything is set */
8272 }
8274 /* phase 2: call the appropriate handler */
8279 }
8282 }
8285 {
8288 u64 status;
8290 #ifdef CONFIG_SDMA_VERBOSITY
8294 #endif
8298 /* This read_csr is really bad in the hot path */
8303 /* clear the interrupt(s) */
8306 status);
8308 /* handle the interrupt(s) */
8313 }
8315 }
8317 /*
8318 * Clear the receive interrupt. Use a read of the interrupt clear CSR
8319 * to insure that the write completed. This does NOT guarantee that
8320 * queued DMA writes to memory from the chip are pushed.
8321 */
8323 {
8329 /* force the above write on the chip and get a value back */
8331 }
8333 /* force the receive interrupt */
8335 {
8337 }
8339 /*
8340 * Return non-zero if a packet is present.
8341 *
8342 * This routine is called when rechecking for packets after the RcvAvail
8343 * interrupt has been cleared down. First, do a quick check of memory for
8344 * a packet present. If not found, use an expensive CSR read of the context
8345 * tail to determine the actual tail. The CSR read is necessary because there
8346 * is no method to push pending DMAs to memory other than an interrupt and we
8347 * are trying to determine if we need to force an interrupt.
8348 */
8350 {
8351 u32 tail;
8363 /* fall back to a CSR read, correct indpendent of DMA_RTAIL */
8366 }
8368 /*
8369 * Receive packet IRQ handler. This routine expects to be on its own IRQ.
8370 * This routine will try to handle packets immediately (latency), but if
8371 * it finds too many, it will invoke the thread handler (bandwitdh). The
8372 * chip receive interrupt is *not* cleared down until this or the thread (if
8373 * invoked) is finished. The intent is to avoid extra interrupts while we
8374 * are processing packets anyway.
8375 */
8377 {
8387 /* receive interrupt remains blocked while processing packets */
8390 /*
8391 * Too many packets were seen while processing packets in this
8392 * IRQ handler. Invoke the handler thread. The receive interrupt
8393 * remains blocked.
8394 */
8398 /*
8399 * The packet processor detected no more packets. Clear the receive
8400 * interrupt and recheck for a packet packet that may have arrived
8401 * after the previous check and interrupt clear. If a packet arrived,
8402 * force another interrupt.
8403 */
8410 }
8412 /*
8413 * Receive packet thread handler. This expects to be invoked with the
8414 * receive interrupt still blocked.
8415 */
8417 {
8421 /* receive interrupt is still blocked from the IRQ handler */
8424 /*
8425 * The packet processor will only return if it detected no more
8426 * packets. Hold IRQs here so we can safely clear the interrupt and
8427 * recheck for a packet that may have arrived after the previous
8428 * check and the interrupt clear. If a packet arrived, force another
8429 * interrupt.
8430 */
8439 }
8441 /* ========================================================================= */
8444 {
8445 u64 reg;
8450 }
8453 {
8454 u64 reg;
8459 }
8462 {
8463 u64 reg;
8466 /* clear current state, set new state */
8470 }
8472 /*
8473 * Use the 8051 to read a LCB CSR.
8474 */
8476 {
8477 u32 regno;
8485 }
8487 }
8489 /* register is an index of LCB registers: (offset - base) / 8 */
8495 }
8497 /*
8498 * Provide a cache for some of the LCB registers in case the LCB is
8499 * unavailable.
8500 * (The LCB is unavailable in certain link states, for example.)
8501 */
8503 u32 off;
8504 u64 val;
8505 };
8511 };
8514 {
8517 u64 val;
8522 /* Update if we get good data */
8525 }
8526 }
8529 {
8536 }
8537 }
8541 }
8543 /*
8544 * Read an LCB CSR. Access may not be in host control, so check.
8545 * Return 0 on success, -EBUSY on failure.
8546 */
8548 {
8551 /* if up, go through the 8051 for the value */
8554 /* if going up or down, check the cache, otherwise, no access */
8559 }
8561 /* otherwise, host has access */
8564 }
8566 /*
8567 * Use the 8051 to write a LCB CSR.
8568 */
8570 {
8571 u32 regno;
8580 }
8582 }
8584 /* register is an index of LCB registers: (offset - base) / 8 */
8590 }
8592 /*
8593 * Write an LCB CSR. Access may not be in host control, so check.
8594 * Return 0 on success, -EBUSY on failure.
8595 */
8597 {
8600 /* if up, go through the 8051 for the value */
8603 /* if going up or down, no access */
8606 /* otherwise, host has access */
8609 }
8611 /*
8612 * Returns:
8613 * < 0 = Linux error, not able to get access
8614 * > 0 = 8051 command RETURN_CODE
8615 */
8618 {
8627 /* We can't send any commands to the 8051 if it's in reset */
8631 }
8633 /*
8634 * If an 8051 host command timed out previously, then the 8051 is
8635 * stuck.
8636 *
8637 * On first timeout, attempt to reset and restart the entire DC
8638 * block (including 8051). (Is this too big of a hammer?)
8639 *
8640 * If the 8051 times out a second time, the reset did not bring it
8641 * back to healthy life. In that case, fail any subsequent commands.
8642 */
8647 type);
8650 }
8653 }
8655 /*
8656 * If there is no timeout, then the 8051 command interface is
8657 * waiting for a command.
8658 */
8660 /*
8661 * When writing a LCB CSR, out_data contains the full value to
8662 * to be written, while in_data contains the relative LCB
8663 * address in 7:0. Do the work here, rather than the caller,
8664 * of distrubting the write data to where it needs to go:
8665 *
8666 * Write data
8667 * 39:00 -> in_data[47:8]
8668 * 47:40 -> DC8051_CFG_EXT_DEV_0.RETURN_CODE
8669 * 63:48 -> DC8051_CFG_EXT_DEV_0.RSP_DATA
8670 */
8673 /* must preserve COMPLETED - it is tied to hardware */
8677 DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT)
8679 DC_DC8051_CFG_EXT_DEV_0_RSP_DATA_SHIFT);
8681 }
8683 /*
8684 * Do two writes: the first to stabilize the type and req_data, the
8685 * second to activate.
8686 */
8688 << DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_SHIFT
8695 /* wait for completion, alternate: interrupt */
8709 }
8711 }
8717 /* top 16 bits are in a different register */
8722 }
8723 }
8727 /*
8728 * Clear command for next user.
8729 */
8732 fail:
8735 }
8738 {
8740 }
8744 {
8745 u64 data;
8756 }
8758 }
8760 /*
8761 * Read the 8051 firmware "registers". Use the RAM directly. Always
8762 * set the result, even on error.
8763 * Return 0 on success, -errno on failure
8764 */
8767 {
8768 u64 big_data;
8769 u32 addr;
8772 /* address start depends on the lane_id */
8776 else
8780 /* read is in 8-byte chunks, hardware will truncate the address down */
8784 /* extract the 4 bytes we want */
8787 else
8793 }
8796 }
8799 u8 continuous)
8800 {
8801 u32 frame;
8807 }
8811 {
8812 u32 frame;
8821 }
8825 {
8826 u32 frame;
8833 }
8836 u8 misc_bits,
8837 u8 flag_bits,
8838 u16 link_widths)
8839 {
8840 u32 frame;
8846 frame);
8847 }
8850 u8 device_rev)
8851 {
8852 u32 frame;
8857 }
8861 {
8862 u32 frame;
8868 }
8871 {
8872 u32 frame;
8873 u32 mask;
8877 /* Clear, then set field */
8881 frame);
8882 }
8886 {
8887 u32 frame;
8891 STS_FM_VERSION_MAJOR_MASK;
8893 STS_FM_VERSION_MINOR_MASK;
8897 STS_FM_VERSION_PATCH_MASK;
8898 }
8902 {
8903 u32 frame;
8910 }
8914 {
8915 u32 frame;
8923 }
8928 {
8929 u32 frame;
8936 }
8939 {
8940 u32 frame;
8944 }
8947 {
8949 }
8952 {
8954 }
8957 {
8958 u32 frame;
8968 }
8969 }
8972 {
8973 u32 frame;
8977 }
8980 {
8981 u32 frame;
8985 }
8992 {
8993 u32 frame;
9005 }
9008 u8 enable_lane_tx,
9009 u8 tx_polarity_inversion,
9010 u8 rx_polarity_inversion,
9011 u8 max_rate)
9012 {
9013 u32 frame;
9015 /* no need to mask, all variable sizes match field widths */
9021 }
9023 /*
9024 * Read an idle LCB message.
9025 *
9026 * Returns 0 on success, -EINVAL on error
9027 */
9029 {
9037 }
9039 /* return only the payload as we already know the type */
9042 }
9044 /*
9045 * Read an idle SMA message. To be done in response to a notification from
9046 * the 8051.
9047 *
9048 * Returns 0 on success, -EINVAL on error
9049 */
9051 {
9053 data);
9054 }
9056 /*
9057 * Send an idle LCB message.
9058 *
9059 * Returns 0 on success, -EINVAL on error
9060 */
9062 {
9071 }
9073 }
9075 /*
9076 * Send an idle SMA message.
9077 *
9078 * Returns 0 on success, -EINVAL on error
9079 */
9081 {
9082 u64 data;
9087 }
9089 /*
9090 * Initialize the LCB then do a quick link up. This may or may not be
9091 * in loopback.
9092 *
9093 * return 0 on success, -errno on error
9094 */
9096 {
9102 /* LCB_CFG_LOOPBACK.VAL = 2 */
9103 /* LCB_CFG_LANE_WIDTH.VAL = 0 */
9107 }
9109 /* start the LCBs */
9110 /* LCB_CFG_TX_FIFOS_RESET.VAL = 0 */
9113 /* simulator only loopback steps */
9115 /* LCB_CFG_RUN.EN = 1 */
9125 }
9128 /*
9129 * When doing quick linkup and not in loopback, both
9130 * sides must be done with LCB set-up before either
9131 * starts the quick linkup. Put a delay here so that
9132 * both sides can be started and have a chance to be
9133 * done with LCB set up before resuming.
9134 */
9139 }
9144 /*
9145 * State "quick" LinkUp request sets the physical link state to
9146 * LinkUp without a verify capability sequence.
9147 * This state is in simulator v37 and later.
9148 */
9161 }
9164 }
9166 /*
9167 * Do all special steps to set up loopback.
9168 */
9170 {
9173 /* all loopbacks should disable self GUID check */
9177 /*
9178 * The simulator has only one loopback option - LCB. Switch
9179 * to that option, which includes quick link up.
9180 *
9181 * Accept all valid loopback values.
9182 */
9189 }
9191 /*
9192 * SerDes loopback init sequence is handled in set_local_link_attributes
9193 */
9197 /* LCB loopback - handled at poll time */
9201 /* not supported in emulation due to emulation RTL changes */
9206 }
9208 }
9210 /* external cable loopback requires no extra steps */
9216 }
9218 /*
9219 * Translate from the OPA_LINK_WIDTH handed to us by the FM to bits
9220 * used in the Verify Capability link width attribute.
9221 */
9223 {
9228 u16 from;
9229 u16 to;
9235 };
9240 }
9242 }
9244 /*
9245 * Set link attributes before moving to polling.
9246 */
9248 {
9250 u8 enable_lane_tx;
9251 u8 tx_polarity_inversion;
9252 u8 rx_polarity_inversion;
9255 /* reset our fabric serdes to clear any lingering problems */
9258 /* set the local tx rate - need to read-modify-write */
9265 /* set the tx rate to the fastest enabled */
9268 else
9271 /* set the tx rate to all enabled */
9277 }
9289 ret);
9291 }
9293 /*
9294 * DC supports continuous updates.
9295 */
9302 /* z=1 in the next call: AU of 0 is not supported by the hardware */
9308 /*
9309 * SerDes loopback init sequence requires
9310 * setting bit 0 of MISC_CONFIG_BITS
9311 */
9321 /* let peer know who we are */
9326 set_local_link_attributes_fail:
9329 ret);
9331 }
9333 /*
9334 * Call this to start the link.
9335 * Do not do anything if the link is disabled.
9336 * Returns 0 if link is disabled, moved to polling, or the driver is not ready.
9337 */
9339 {
9340 /*
9341 * Tune the SerDes to a ballpark setting for optimal signal and bit
9342 * error rate. Needs to be done before starting the link.
9343 */
9349 __func__);
9351 }
9353 /*
9354 * FULL_MGMT_P_KEY is cleared from the pkey table, so that the
9355 * pkey table can be configured properly if the HFI unit is connected
9356 * to switch port with MgmtAllowed=NO
9357 */
9361 }
9364 {
9366 u64 mask;
9369 /*
9370 * Some QSFP cables have a quirk that asserts the IntN line as a side
9371 * effect of power up on plug-in. We ignore this false positive
9372 * interrupt until the module has finished powering up by waiting for
9373 * a minimum timeout of the module inrush initialization time of
9374 * 500 ms (SFF 8679 Table 5-6) to ensure the voltage rails in the
9375 * module have stabilized.
9376 */
9379 /*
9380 * Check for QSFP interrupt for t_init (SFF 8679 Table 8-1)
9381 */
9390 __func__);
9392 }
9394 }
9395 }
9398 {
9400 u64 mask;
9404 /*
9405 * Clear the status register to avoid an immediate interrupt
9406 * when we re-enable the IntN pin
9407 */
9409 QSFP_HFI0_INT_N);
9413 }
9415 }
9418 {
9422 /* Disable INT_N from triggering QSFP interrupts */
9425 /* Reset the QSFP */
9442 /*
9443 * Allow INT_N to trigger the QSFP interrupt to watch
9444 * for alarms and warnings
9445 */
9448 /*
9449 * After the reset, AOC transmitters are enabled by default. They need
9450 * to be turned off to complete the QSFP setup before they can be
9451 * enabled again.
9452 */
9454 }
9458 {
9464 __func__);
9469 __func__);
9471 /*
9472 * The remaining alarms/warnings don't matter if the link is down.
9473 */
9480 __func__);
9485 __func__);
9487 /* Byte 2 is vendor specific */
9492 __func__);
9497 __func__);
9502 __func__);
9507 __func__);
9512 __func__);
9517 __func__);
9522 __func__);
9527 __func__);
9532 __func__);
9537 __func__);
9542 __func__);
9547 __func__);
9549 /* Bytes 9-10 and 11-12 are reserved */
9550 /* Bytes 13-15 are vendor specific */
9553 }
9555 /* This routine will only be scheduled if the QSFP module present is asserted */
9557 {
9566 /* Sanity check */
9573 __func__);
9575 }
9577 /*
9578 * Turn DC back on after cable has been re-inserted. Up until
9579 * now, the DC has been in reset to save power.
9580 */
9588 /*
9589 * Allow INT_N to trigger the QSFP interrupt to watch
9590 * for alarms and warnings
9591 */
9595 }
9604 __func__);
9613 flags);
9614 }
9615 }
9616 }
9619 {
9625 /*
9626 * disable QSFP1 interrupts for HFI1, QSFP2 interrupts for HFI0
9627 * Qsfp1Int and Qsfp2Int are adjacent bits in the same CSR,
9628 * therefore just one of QSFP1_INT/QSFP2_INT can be used to find
9629 * the index of the appropriate CSR in the CCEIntMask CSR array
9630 */
9636 cce_int_mask);
9640 cce_int_mask);
9641 }
9644 /* Clear current status to avoid spurious interrupts */
9646 qsfp_mask);
9648 qsfp_mask);
9652 /* Handle active low nature of INT_N and MODPRST_N pins */
9657 qsfp_mask);
9658 }
9660 /*
9661 * Do a one-time initialize of the LCB block.
9662 */
9664 {
9665 /* simulator does not correctly handle LCB cclk loopback, skip */
9669 /* the DC has been reset earlier in the driver load */
9671 /* set LCB for cclk loopback on the port */
9679 }
9681 /*
9682 * Perform a test read on the QSFP. Return 0 on success, -ERRNO
9683 * on error.
9684 */
9686 {
9688 u8 status;
9690 /*
9691 * Report success if not a QSFP or, if it is a QSFP, but the cable is
9692 * not present
9693 */
9697 /* read byte 2, the status byte */
9705 }
9707 /*
9708 * Values for QSFP retry.
9709 *
9710 * Give up after 10s (20 x 500ms). The overall timeout was empirically
9711 * arrived at from experience on a large cluster.
9712 */
9713 #define MAX_QSFP_RETRIES 20
9716 /*
9717 * Try a QSFP read. If it fails, schedule a retry for later.
9718 * Called on first link activation after driver load.
9719 */
9721 {
9723 /* read failed */
9727 }
9735 }
9739 }
9741 /*
9742 * Workqueue function to start the link after a delay.
9743 */
9745 {
9749 }
9752 {
9754 u64 guid;
9765 }
9767 /* Set linkinit_reason on power up per OPA spec */
9770 /* one-time init of the LCB */
9777 }
9784 }
9788 }
9791 {
9794 /*
9795 * Shut down the link and keep it down. First turn off that the
9796 * driver wants to allow the link to be up (driver_link_ready).
9797 * Then make sure the link is not automatically restarted
9798 * (link_enabled). Cancel any pending restart. And finally
9799 * go offline.
9800 */
9811 OPA_LINKDOWN_REASON_REBOOT);
9814 /* disable the port */
9816 }
9819 {
9834 }
9837 }
9839 /*
9840 * index is the index into the receive array
9841 */
9844 {
9845 u64 reg;
9858 }
9862 reg = RCV_ARRAY_RT_WRITE_ENABLE_SMASK
9870 /*
9871 * Eager entries are written and flushed
9872 *
9873 * Expected entries are flushed every 4 writes
9874 */
9876 done:
9878 }
9881 {
9883 u32 i;
9885 /* this could be optimized */
9893 }
9917 "HFI1_IB_CFG_PORT"
9918 };
9921 {
9925 }
9928 {
9973 unimplemented:
9976 dd,
9978 __func__,
9981 }
9984 }
9986 /*
9987 * The largest MAD packet size.
9988 */
9989 #define MAX_MAD_PACKET 2048
9991 /*
9992 * Return the maximum header bytes that can go on the _wire_
9993 * for this device. This count includes the ICRC which is
9994 * not part of the packet held in memory but it is appended
9995 * by the HW.
9996 * This is dependent on the device's receive header entry size.
9997 * HFI allows this to be set per-receive context, but the
9998 * driver presently enforces a global value.
9999 */
10001 {
10002 /*
10003 * The maximum non-payload (MTU) bytes in LRH.PktLen are
10004 * the Receive Header Entry Size minus the PBC (or RHF) size
10005 * plus one DW for the ICRC appended by HW.
10006 *
10007 * dd->rcd[0].rcvhdrqentsize is in DW.
10008 * We use rcd[0] as all context will have the same value. Also,
10009 * the first kernel context would have been allocated by now so
10010 * we are guaranteed a valid value.
10011 */
10013 }
10015 /*
10016 * Set Send Length
10017 * @ppd - per port data
10018 *
10019 * Set the MTU by limiting how many DWs may be sent. The SendLenCheck*
10020 * registers compare against LRH.PktLen, so use the max bytes included
10021 * in the LRH.
10022 *
10023 * This routine changes all VL values except VL15, which it maintains at
10024 * the same value.
10025 */
10027 {
10033 SEND_LEN_CHECK1_LEN_VL15_SHIFT;
10035 u32 thres;
10044 else
10048 }
10051 /* adjust kernel credit return thresholds based on new MTUs */
10052 /* all kernel receive contexts have the same hdrqentsize */
10061 thres);
10062 }
10069 /* Adjust maximum MTU for the port in DC */
10075 DCC_CFG_PORT_CONFIG_MTU_CAP_SHIFT;
10077 }
10080 {
10086 u32 lid;
10088 /*
10089 * Program 0 in CSR if port lid is extended. This prevents
10090 * 9B packets being sent out for large lids.
10091 */
10093 c1 &= ~(DCC_CFG_PORT_CONFIG1_TARGET_DLID_SMASK
10101 /*
10102 * Iterate over all the send contexts and set their SLID check
10103 */
10105 SEND_CTXT_CHECK_SLID_MASK_SHIFT) |
10107 SEND_CTXT_CHECK_SLID_VALUE_SHIFT);
10113 }
10115 /* Now we have to do the same thing for the sdma engines */
10117 }
10120 {
10124 "VerifyCap"
10125 };
10131 }
10149 "Unable to identify preset equalization on sufficient lanes to meet the local link width policy",
10154 "Link partner completed the EstablishComm state, but the passing lanes do not meet the local link width policy",
10161 "Link partner completed the OptimizeEq state, but the passing lanes do not meet the local link width policy",
10168 "Link partner completed the VerifyCap state, but the passing lanes do not meet the local link width policy",
10174 };
10177 u32 code)
10178 {
10187 }
10189 /* describe the given last state complete frame */
10192 {
10194 u32 success;
10195 u32 state;
10196 u32 reason;
10197 u32 lanes;
10199 /*
10200 * Decode frame:
10201 * [ 0: 0] - success
10202 * [ 3: 1] - state
10203 * [ 7: 4] - next state timeout
10204 * [15: 8] - reason code
10205 * [31:16] - lanes
10206 */
10221 }
10223 /*
10224 * Read the last state complete frames and explain them. This routine
10225 * expects to be called if the link went down during link negotiation
10226 * and initialization (LNI). That is, anywhere between polling and link up.
10227 */
10229 {
10230 u32 last_local_state;
10231 u32 last_remote_state;
10236 /*
10237 * Don't report anything if there is nothing to report. A value of
10238 * 0 means the link was taken down while polling and there was no
10239 * training in-process.
10240 */
10246 }
10248 /* wait for wait_ms for LINK_TRANSFER_ACTIVE to go to 1 */
10250 {
10251 u64 reg;
10254 /* watch LCB_STS_LINK_TRANSFER_ACTIVE */
10264 }
10266 }
10268 }
10270 /* called when the logical link state is not down as it should be */
10272 {
10275 /*
10276 * Bring link up in LCB loopback
10277 */
10280 DC_LCB_CFG_IGNORE_LOST_RCLK_EN_SMASK);
10295 /*
10296 * Bring the link down again.
10297 */
10303 }
10305 /*
10306 * Helper for set_link_state(). Do not call except from that routine.
10307 * Expects ppd->hls_mutex to be held.
10308 *
10309 * @rem_reason value to be sent to the neighbor
10310 *
10311 * LinkDownReasons only set if transition succeeds.
10312 */
10314 {
10316 u32 previous_state;
10325 /* start offline transition */
10331 ret);
10333 }
10343 /* Disabling AOC transmitters */
10354 /* not fatal, but should warn */
10357 }
10358 }
10360 /*
10361 * Wait for the offline.Quiet transition if it hasn't happened yet. It
10362 * can take a while for the link to go down.
10363 */
10368 }
10370 /*
10371 * Now in charge of LCB - must be after the physical state is
10372 * offline.quiet and before host_link_state is changed.
10373 */
10377 /* make sure the logical state is also down */
10385 /*
10386 * The LNI has a mandatory wait time after the physical state
10387 * moves to Offline.Quiet. The wait time may be different
10388 * depending on how the link went down. The 8051 firmware
10389 * will observe the needed wait time and only move to ready
10390 * when that is completed. The largest of the quiet timeouts
10391 * is 6s, so wait that long and then at least 0.5s more for
10392 * other transitions, and another 0.5s for a buffer.
10393 */
10397 "After going offline, timed out waiting for the 8051 to become ready to accept host requests\n");
10398 /* state is really offline, so make it so */
10401 }
10403 /*
10404 * The state is now offline and the 8051 is ready to accept host
10405 * requests.
10406 * - change our state
10407 * - notify others if we were previously in a linkup state
10408 */
10411 /* went down while link was up */
10415 /* went down while attempting link up */
10418 /* The QSFP doesn't need to be reset on LNI failure */
10420 }
10422 /* the active link width (downgrade) is 0 on link down */
10428 }
10430 /* return the link state name */
10432 {
10447 };
10451 }
10453 /* return the link state reason name */
10455 {
10470 }
10471 }
10473 }
10475 /*
10476 * driver_pstate - convert the driver's notion of a port's
10477 * state (an HLS_*) into a physical state (a {IB,OPA}_PORTPHYSSTATE_*).
10478 * Return -1 (converted to a u32) to indicate error.
10479 */
10481 {
10506 }
10507 }
10509 /*
10510 * driver_lstate - convert the driver's notion of a port's
10511 * state (an HLS_*) into a logical state (a IB_PORT_*). Return -1
10512 * (converted to a u32) to indicate error.
10513 */
10515 {
10530 }
10531 }
10535 {
10541 }
10542 }
10544 /*
10545 * Verify if BCT for data VLs is non-zero.
10546 */
10548 {
10550 }
10552 /*
10553 * Change the physical and/or logical link state.
10554 *
10555 * Do not call this routine while inside an interrupt. It contains
10556 * calls to routines that can take multiple seconds to finish.
10557 *
10558 * Returns 0 on success, -errno on failure.
10559 */
10561 {
10573 /* interpret poll -> poll as a link bounce */
10583 /*
10584 * If we're going to a (HLS_*) link state that implies the logical
10585 * link state is neither of (IB_PORT_ARMED, IB_PORT_ACTIVE), then
10586 * reset is_sm_config_started to 0.
10587 */
10591 /*
10592 * Do nothing if the states match. Let a poll to poll link bounce
10593 * go through.
10594 */
10602 /*
10603 * Quick link up jumps from polling to here.
10604 *
10605 * Whether in normal or loopback mode, the
10606 * simulator jumps from polling to link up.
10607 * Accept that here.
10608 */
10609 /* OK */
10612 }
10614 /*
10615 * Wait for Link_Up physical state.
10616 * Physical and Logical states should already be
10617 * be transitioned to LinkUp and LinkInit respectively.
10618 */
10623 __func__);
10625 }
10631 __func__);
10633 }
10635 /* clear old transient LINKINIT_REASON code */
10638 OPA_LINKINIT_REASON_LINKUP;
10640 /* enable the port */
10645 /*
10646 * After link up, a new link width will have been set.
10647 * Update the xmit counters with regards to the new
10648 * link width.
10649 */
10664 }
10671 __func__);
10673 }
10676 /*
10677 * The simulator does not currently implement SMA messages,
10678 * so neighbor_normal is not set. Set it here when we first
10679 * move to Armed.
10680 */
10693 __func__);
10695 /* tell all engines to go running */
10700 /* Signal the IB layer that the port has went active */
10704 }
10711 /* Hand LED control to the DC */
10721 }
10726 }
10737 /* quick linkup does not go into polling */
10744 ret1);
10746 }
10747 }
10750 /*
10751 * If an error occurred above, go back to offline. The
10752 * caller may reschedule another attempt.
10753 */
10756 else
10760 /* link is disabled */
10763 /* allow any state to transition to disabled */
10765 /* must transition to offline first */
10771 }
10778 ret1);
10781 }
10786 __func__);
10788 }
10790 }
10797 /* allow any state to transition to offline */
10816 ret1);
10819 }
10830 }
10834 unexpected:
10840 done:
10847 }
10850 {
10851 u64 reg;
10859 /*
10860 * The VL Arbitrator high limit is sent in units of 4k
10861 * bytes, while HFI stores it in units of 64 bytes.
10862 */
10869 /* HFI only supports POLL as the default link down state */
10878 }
10880 /*
10881 * For link width, link width downgrade, and speed enable, always AND
10882 * the setting with what is actually supported. This has two benefits.
10883 * First, enabled can't have unsupported values, no matter what the
10884 * SM or FM might want. Second, the ALL_SUPPORTED wildcards that mean
10885 * "fill in with your supported value" have all the bits in the
10886 * field set, so simply ANDing with supported has the desired result.
10887 */
10899 /*
10900 * HFI does not follow IB specs, save this value
10901 * so we can report it, if asked.
10902 */
10906 /*
10907 * HFI does not follow IB specs, save this value
10908 * so we can report it, if asked.
10909 */
10928 }
10930 }
10932 /* begin functions related to vl arbitration table caching */
10934 {
10938 VL_ARB_LOW_PRIO_TABLE_SIZE);
10940 VL_ARB_HIGH_PRIO_TABLE_SIZE);
10942 /*
10943 * Note that we always return values directly from the
10944 * 'vl_arb_cache' (and do no CSR reads) in response to a
10945 * 'Get(VLArbTable)'. This is obviously correct after a
10946 * 'Set(VLArbTable)', since the cache will then be up to
10947 * date. But it's also correct prior to any 'Set(VLArbTable)'
10948 * since then both the cache, and the relevant h/w registers
10949 * will be zeroed.
10950 */
10954 }
10956 /*
10957 * vl_arb_lock_cache
10958 *
10959 * All other vl_arb_* functions should be called only after locking
10960 * the cache.
10961 */
10964 {
10969 }
10972 {
10974 }
10978 {
10980 }
10984 {
10986 }
10990 {
10992 }
10994 /* end functions related to vl arbitration table caching */
10998 {
11000 u64 reg;
11012 /*
11013 * Before adjusting VL arbitration weights, empty per-VL
11014 * FIFOs, otherwise a packet whose VL weight is being
11015 * set to 0 could get stuck in a FIFO with no chance to
11016 * egress.
11017 */
11022 dd,
11024 __func__);
11026 }
11029 /*
11030 * NOTE: The low priority shift and mask are used here, but
11031 * they are the same for both the low and high registers.
11032 */
11039 }
11045 err:
11049 }
11051 /*
11052 * Read one credit merge VL register.
11053 */
11056 {
11065 }
11067 /*
11068 * Read the current credit merge limits.
11069 */
11072 {
11073 u64 reg;
11076 /* not all entries are filled in */
11079 /* OPA and HFI have a 1-1 mapping */
11083 /* NOTE: assumes that VL* and VL15 CSRs are bit-wise identical */
11095 }
11098 {
11099 u64 reg;
11102 /* each register contains 16 SC->VLnt mappings, 4 bits each */
11109 }
11117 }
11119 }
11123 {
11129 }
11130 }
11133 {
11170 }
11173 u16 limit)
11174 {
11178 }
11180 /* change only the shared limit portion of SendCmGLobalCredit */
11182 {
11183 u64 reg;
11189 }
11191 /* change only the total credit limit portion of SendCmGLobalCredit */
11193 {
11194 u64 reg;
11200 }
11202 /* set the given per-VL shared limit */
11204 {
11205 u64 reg;
11206 u32 addr;
11210 else
11217 }
11219 /* set the given per-VL dedicated limit */
11221 {
11222 u64 reg;
11223 u32 addr;
11227 else
11234 }
11236 /* spin until the given per-VL status mask bits clear */
11239 {
11241 u64 reg;
11252 }
11257 /*
11258 * If this occurs, it is likely there was a credit loss on the link.
11259 * The only recovery from that is a link bounce.
11260 */
11263 }
11265 /*
11266 * The number of credits on the VLs may be changed while everything
11267 * is "live", but the following algorithm must be followed due to
11268 * how the hardware is actually implemented. In particular,
11269 * Return_Credit_Status[] is the only correct status check.
11270 *
11271 * if (reducing Global_Shared_Credit_Limit or any shared limit changing)
11272 * set Global_Shared_Credit_Limit = 0
11273 * use_all_vl = 1
11274 * mask0 = all VLs that are changing either dedicated or shared limits
11275 * set Shared_Limit[mask0] = 0
11276 * spin until Return_Credit_Status[use_all_vl ? all VL : mask0] == 0
11277 * if (changing any dedicated limit)
11278 * mask1 = all VLs that are lowering dedicated limits
11279 * lower Dedicated_Limit[mask1]
11280 * spin until Return_Credit_Status[mask1] == 0
11281 * raise Dedicated_Limits
11282 * raise Shared_Limits
11283 * raise Global_Shared_Credit_Limit
11284 *
11285 * lower = if the new limit is lower, set the limit to the new value
11286 * raise = if the new limit is higher than the current value (may be changed
11287 * earlier in the algorithm), set the new limit to the new value
11288 */
11291 {
11298 /*
11299 * A0: add the variable any_shared_limit_changing below and in the
11300 * algorithm above. If removing A0 support, it can be removed.
11301 */
11306 u16 cur_total;
11309 SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK
11310 | SEND_CM_CREDIT_USED_STATUS_VL1_RETURN_CREDIT_STATUS_SMASK
11311 | SEND_CM_CREDIT_USED_STATUS_VL2_RETURN_CREDIT_STATUS_SMASK
11312 | SEND_CM_CREDIT_USED_STATUS_VL3_RETURN_CREDIT_STATUS_SMASK
11313 | SEND_CM_CREDIT_USED_STATUS_VL4_RETURN_CREDIT_STATUS_SMASK
11314 | SEND_CM_CREDIT_USED_STATUS_VL5_RETURN_CREDIT_STATUS_SMASK
11315 | SEND_CM_CREDIT_USED_STATUS_VL6_RETURN_CREDIT_STATUS_SMASK
11316 | SEND_CM_CREDIT_USED_STATUS_VL7_RETURN_CREDIT_STATUS_SMASK
11319 #define valid_vl(idx) ((idx) < TXE_NUM_DATA_VL || (idx) == 15)
11322 /* find the new total credits, do sanity check on unused VLs */
11327 }
11334 }
11337 /* fetch the current values */
11340 /*
11341 * Create the masks we will use.
11342 */
11345 /*
11346 * NOTE: Assumes that the individual VL bits are adjacent and in
11347 * increasing order
11348 */
11349 stat_mask =
11350 SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK;
11363 this_shared_changing) {
11366 change_count++;
11367 }
11372 }
11373 }
11375 /* bracket the credit change with a total adjustment */
11379 /*
11380 * Start the credit change algorithm.
11381 */
11389 }
11398 }
11399 }
11415 }
11416 }
11420 /* now raise all dedicated that are going up */
11430 }
11431 }
11433 /* next raise all shared that are going up */
11441 }
11443 /* finally raise the global shared */
11449 /* bracket the credit change with a total adjustment */
11453 /*
11454 * Determine the actual number of operational VLS using the number of
11455 * dedicated and shared credits for each VL.
11456 */
11461 vl_count++;
11466 NULL);
11473 }
11475 }
11477 /*
11478 * Read the given fabric manager table. Return the size of the
11479 * table (in bytes) on success, and a negative error code on
11480 * failure.
11481 */
11484 {
11491 /*
11492 * OPA specifies 128 elements (of 2 bytes each), though
11493 * HFI supports only 16 elements in h/w.
11494 */
11501 /*
11502 * OPA specifies 128 elements (of 2 bytes each), though
11503 * HFI supports only 16 elements in h/w.
11504 */
11517 /* OPA specifies 128 elements, of 2 bytes each */
11522 /*
11523 * OPA specifies that this is the same size as the VL
11524 * arbitration tables (i.e., 256 bytes).
11525 */
11529 }
11531 }
11533 /*
11534 * Write the given fabric manager table.
11535 */
11537 {
11547 }
11558 }
11572 }
11574 }
11576 /*
11577 * Disable all data VLs.
11578 *
11579 * Return 0 if disabled, non-zero if the VLs cannot be disabled.
11580 */
11582 {
11589 }
11591 /*
11592 * open_fill_data_vls() - the counterpart to stop_drain_data_vls().
11593 * Just re-enables all data VLs (the "fill" part happens
11594 * automatically - the name was chosen for symmetry with
11595 * stop_drain_data_vls()).
11596 *
11597 * Return 0 if successful, non-zero if the VLs cannot be enabled.
11598 */
11600 {
11607 }
11609 /*
11610 * drain_data_vls() - assumes that disable_data_vls() has been called,
11611 * wait for occupancy (of per-VL FIFOs) for all contexts, and SDMA
11612 * engines to drop to 0.
11613 */
11615 {
11619 }
11621 /*
11622 * stop_drain_data_vls() - disable, then drain all per-VL fifos.
11623 *
11624 * Use open_fill_data_vls() to resume using data VLs. This pair is
11625 * meant to be used like this:
11626 *
11627 * stop_drain_data_vls(dd);
11628 * // do things with per-VL resources
11629 * open_fill_data_vls(dd);
11630 */
11632 {
11640 }
11642 /*
11643 * Convert a nanosecond time to a cclock count. No matter how slow
11644 * the cclock, a non-zero ns will always have a non-zero result.
11645 */
11647 {
11648 u32 cclocks;
11657 }
11659 /*
11660 * Convert a cclock count to nanoseconds. Not matter how slow
11661 * the cclock, a non-zero cclocks will always have a non-zero result.
11662 */
11664 {
11665 u32 ns;
11674 }
11676 /*
11677 * Dynamically adjust the receive interrupt timeout for a context based on
11678 * incoming packet rate.
11679 *
11680 * NOTE: Dynamic adjustment does not allow rcv_intr_count to be zero.
11681 */
11683 {
11687 /*
11688 * This algorithm doubles or halves the timeout depending on whether
11689 * the number of packets received in this interrupt were less than or
11690 * greater equal the interrupt count.
11691 *
11692 * The calculations below do not allow a steady state to be achieved.
11693 * Only at the endpoints it is possible to have an unchanging
11694 * timeout.
11695 */
11697 /*
11698 * Not enough packets arrived before the timeout, adjust
11699 * timeout downward.
11700 */
11705 /*
11706 * More than enough packets arrived before the timeout, adjust
11707 * timeout upward.
11708 */
11712 }
11715 /*
11716 * timeout cannot be larger than rcv_intr_timeout_csr which has already
11717 * been verified to be in range
11718 */
11721 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT);
11722 }
11726 {
11728 u64 reg;
11731 /*
11732 * Need to write timeout register before updating RcvHdrHead to ensure
11733 * that a new value is used when the HW decides to restart counting.
11734 */
11741 }
11748 }
11751 {
11759 else
11763 }
11765 /*
11766 * Context Control and Receive Array encoding for buffer size:
11767 * 0x0 invalid
11768 * 0x1 4 KB
11769 * 0x2 8 KB
11770 * 0x3 16 KB
11771 * 0x4 32 KB
11772 * 0x5 64 KB
11773 * 0x6 128 KB
11774 * 0x7 256 KB
11775 * 0x8 512 KB (Receive Array only)
11776 * 0x9 1 MB (Receive Array only)
11777 * 0xa 2 MB (Receive Array only)
11778 *
11779 * 0xB-0xF - reserved (Receive Array only)
11780 *
11781 *
11782 * This routine assumes that the value has already been sanity checked.
11783 */
11785 {
11797 }
11799 }
11803 {
11806 u16 ctxt;
11816 /* if the context already enabled, don't do the extra steps */
11819 /* reset the tail and hdr addresses, and sequence count */
11827 /* reset the cached receive header queue head value */
11830 /*
11831 * Zero the receive header queue so we don't get false
11832 * positives when checking the sequence number. The
11833 * sequence numbers could land exactly on the same spot.
11834 * E.g. a rcd restart before the receive header wrapped.
11835 */
11838 /* starting timeout */
11841 /* enable the context */
11844 /* clean the egr buffer size first */
11850 /* zero RcvHdrHead - set RcvHdrHead.Counter after enable */
11854 /* zero RcvEgrIndexHead */
11857 /* set eager count and base index */
11866 /*
11867 * Set TID (expected) count and base index.
11868 * rcd->expected_count is set to individual RcvArray entries,
11869 * not pairs, and the CSR takes a pair-count in groups of
11870 * four, so divide by 8.
11871 */
11881 }
11884 /*
11885 * When receive context is being disabled turn on tail
11886 * update with a dummy tail address and then disable
11887 * receive context.
11888 */
11892 /* Enabling RcvCtxtCtrl.TailUpd is intentional. */
11894 }
11897 }
11905 /* See comment on RcvCtxtCtrl.TailUpd above */
11908 }
11914 /*
11915 * In one-packet-per-eager mode, the size comes from
11916 * the RcvArray entry.
11917 */
11920 }
11935 /* work around sticky RcvCtxtStatus.BlockedRHQFull */
11949 }
11950 }
11953 /*
11954 * The interrupt timeout and count must be set after
11955 * the context is enabled to take effect.
11956 */
11957 /* set interrupt timeout */
11960 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT);
11962 /* set RcvHdrHead.Counter, zero RcvHdrHead.Head (again) */
11965 }
11968 /*
11969 * If the context has been disabled and the Tail Update has
11970 * been cleared, set the RCV_HDR_TAIL_ADDR CSR to dummy address
11971 * so it doesn't contain an address that is invalid.
11972 */
11975 }
11978 {
11991 /* Get the start of the block of counters */
11994 /*
11995 * Now go and fill in each counter in the block.
11996 */
12001 /* Nothing */
12009 CNTR_MODE_R,
12012 CNTR,
12016 val;
12017 }
12022 j++) {
12023 val =
12030 val;
12031 }
12034 CNTR_INVALID_VL,
12038 }
12039 }
12040 }
12041 }
12043 }
12045 /*
12046 * Used by sysfs to create files for hfi stats to read
12047 */
12049 {
12067 /* Nothing */
12070 }
12076 CNTR_MODE_R,
12079 CNTR,
12083 }
12086 CNTR_INVALID_VL,
12087 CNTR_MODE_R,
12091 }
12092 }
12093 }
12095 }
12098 {
12116 }
12128 }
12129 }
12133 {
12134 u64 val;
12140 }
12146 /* If its a synthetic counter there is more work we need to do */
12149 /* No need to read already saturated */
12151 }
12154 /* 32bit counters can wrap multiple times */
12161 else
12162 upper++;
12163 }
12169 /* If we rolled we are saturated */
12172 }
12173 }
12180 }
12185 {
12186 u64 val;
12191 }
12203 data);
12204 }
12207 }
12214 }
12217 {
12228 }
12231 {
12242 }
12245 {
12257 /* We do not want to bother for disabled contexts */
12259 }
12262 }
12265 {
12277 /* We do not want to bother for disabled contexts */
12279 }
12282 }
12285 {
12286 u64 cur_tx;
12287 u64 cur_rx;
12288 u64 total_flits;
12294 update_cntr_work);
12296 /*
12297 * Rather than keep beating on the CSRs pick a minimal set that we can
12298 * check to watch for potential roll over. We can do this by looking at
12299 * the number of flits sent/recv. If the total flits exceeds 32bits then
12300 * we have to iterate all the counters and update.
12301 */
12309 CNTR,
12314 /*
12315 * May not be strictly necessary to update but it won't hurt and
12316 * simplifies the logic here.
12317 */
12330 }
12331 }
12342 }
12343 }
12353 }
12354 }
12355 }
12357 /*
12358 * We want the value in the register. The goal is to keep track
12359 * of the number of "ticks" not the counter value. In other
12360 * words if the register rolls we want to notice it and go ahead
12361 * and force an update.
12362 */
12376 }
12377 }
12380 {
12385 }
12389 {
12398 /* set up the stats timer; the add_timer is done at the end */
12401 /***********************/
12402 /* per device counters */
12403 /***********************/
12405 /* size names and determine how many we have*/
12413 }
12421 /* Add ",32" for 32-bit counters */
12424 sz++;
12426 }
12433 /* Add ",32" for 32-bit counters */
12436 sz++;
12438 }
12440 /* +1 for newline. */
12442 /* Add ",32" for 32-bit counters */
12447 }
12448 }
12450 /* allocate space for the counter values */
12459 /* allocate space for the counter names */
12465 /* fill in the names */
12468 /* Nothing */
12477 /* Counter is 32 bits */
12481 }
12484 }
12492 /* Counter is 32 bits */
12496 }
12499 }
12504 /* Counter is 32 bits */
12508 }
12511 }
12512 }
12514 /*********************/
12515 /* per port counters */
12516 /*********************/
12518 /*
12519 * Go through the counters for the overflows and disable the ones we
12520 * don't need. This varies based on platform so we need to do it
12521 * dynamically here.
12522 */
12527 }
12529 /* size port counter names and determine how many we have*/
12536 }
12544 /* Add ",32" for 32-bit counters */
12547 sz++;
12549 }
12551 /* +1 for newline */
12553 /* Add ",32" for 32-bit counters */
12558 }
12559 }
12561 /* allocate space for the counter names */
12567 /* fill in port cntr names */
12579 /* Counter is 32 bits */
12583 }
12586 }
12592 /* Counter is 32 bits */
12596 }
12599 }
12600 }
12602 /* allocate per port storage for counter values */
12612 }
12614 /* CPU counters need to be allocated and zeroed */
12627 bail:
12630 }
12633 {
12638 chip_lstate);
12639 /* fall through */
12648 }
12649 }
12652 {
12653 /* look at the HFI meta-states only */
12657 chip_pstate);
12658 /* fall through */
12671 }
12672 }
12674 /* return the OPA port logical state name */
12676 {
12684 };
12688 }
12690 /* return the OPA port physical state name */
12692 {
12706 };
12710 }
12712 /**
12713 * update_statusp - Update userspace status flag
12714 * @ppd: Port data structure
12715 * @state: port state information
12716 *
12717 * Actual port status is determined by the host_link_state value
12718 * in the ppd.
12719 *
12720 * host_link_state MUST be updated before updating the user space
12721 * statusp.
12722 */
12724 {
12725 /*
12726 * Set port status flags in the page mapped into userspace
12727 * memory. Do it here to ensure a reliable state - this is
12728 * the only function called by all state handling code.
12729 * Always set the flags due to the fact that the cache value
12730 * might have been changed explicitly outside of this
12731 * function.
12732 */
12738 HFI1_STATUS_IB_READY);
12746 }
12747 }
12750 }
12752 /**
12753 * wait_logical_linkstate - wait for an IB link state change to occur
12754 * @ppd: port device
12755 * @state: the state to wait for
12756 * @msecs: the number of milliseconds to wait
12757 *
12758 * Wait up to msecs milliseconds for IB link state change to occur.
12759 * For now, take the easy polling route.
12760 * Returns 0 if state reached, otherwise -ETIMEDOUT.
12761 */
12764 {
12766 u32 new_state;
12777 state);
12779 }
12781 }
12784 }
12787 {
12793 }
12795 /*
12796 * Read the physical hardware link state and check if it matches host
12797 * drivers anticipated state.
12798 */
12800 {
12809 }
12810 }
12812 /*
12813 * wait_physical_linkstate - wait for an physical link state change to occur
12814 * @ppd: port device
12815 * @state: the state to wait for
12816 * @msecs: the number of milliseconds to wait
12817 *
12818 * Wait up to msecs milliseconds for physical link state change to occur.
12819 * Returns 0 if state reached, otherwise -ETIMEDOUT.
12820 */
12823 {
12824 u32 read_state;
12835 state);
12837 }
12839 }
12843 }
12845 /*
12846 * wait_phys_link_offline_quiet_substates - wait for any offline substate
12847 * @ppd: port device
12848 * @msecs: the number of milliseconds to wait
12849 *
12850 * Wait up to msecs milliseconds for any offline physical link
12851 * state change to occur.
12852 * Returns 0 if at least one state is reached, otherwise -ETIMEDOUT.
12853 */
12856 {
12857 u32 read_state;
12870 }
12872 }
12876 }
12878 #define CLEAR_STATIC_RATE_CONTROL_SMASK(r) \
12879 (r &= ~SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK)
12881 #define SET_STATIC_RATE_CONTROL_SMASK(r) \
12882 (r |= SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK)
12885 {
12888 u64 reg;
12893 SEND_CTXT_CHECK_ENABLE);
12896 else
12900 }
12901 }
12904 {
12906 u64 reg;
12911 __func__);
12913 }
12916 ASIC_STS_THERM_CURR_TEMP_MASK);
12918 ASIC_STS_THERM_LO_TEMP_MASK);
12920 ASIC_STS_THERM_HI_TEMP_MASK);
12922 ASIC_STS_THERM_CRIT_TEMP_MASK);
12923 /* triggers is a 3-bit value - 1 bit per trigger. */
12927 }
12929 /**
12930 * get_int_mask - get 64 bit int mask
12931 * @dd - the devdata
12932 * @i - the csr (relative to CCE_INT_MASK)
12933 *
12934 * Returns the mask with the urgent interrupt mask
12935 * bit clear for kernel receive contexts.
12936 */
12938 {
12947 /* j = 0..dd->first_dyn_alloc_ctxt - 1,k = 0..63 */
12949 /* convert to bit in mask and clear */
12951 }
12953 }
12955 /* ========================================================================= */
12957 /*
12958 * Enable/disable chip from delivering interrupts.
12959 */
12961 {
12964 /*
12965 * In HFI, the mask needs to be 1 to allow interrupts.
12966 */
12968 /* enable all interrupts but urgent on kernel contexts */
12973 }
12979 }
12980 }
12982 /*
12983 * Clear all interrupt sources on the chip.
12984 */
12986 {
13007 }
13009 /* Move to pcie.c? */
13011 {
13013 }
13015 /**
13016 * hfi1_clean_up_interrupts() - Free all IRQ resources
13017 * @dd: valid device data data structure
13018 *
13019 * Free the MSI or INTx IRQs and assoicated PCI resources,
13020 * if they have been allocated.
13021 */
13023 {
13026 /* remove irqs - must happen before disabling/turning off */
13028 /* MSI-X */
13036 }
13038 /* clean structures */
13043 /* INTx */
13047 }
13049 }
13052 }
13054 /*
13055 * Remap the interrupt source from the general handler to the given MSI-X
13056 * interrupt.
13057 */
13059 {
13060 u64 reg;
13063 /* clear from the handled mask of the general interrupt */
13071 }
13073 /* direct the chip source to the given MSI-X interrupt */
13080 }
13084 {
13085 /*
13086 * SDMA engine interrupt sources grouped by type, rather than
13087 * engine. Per-engine interrupts are as follows:
13088 * SDMA
13089 * SDMAProgress
13090 * SDMAIdle
13091 */
13093 msix_intr);
13095 msix_intr);
13097 msix_intr);
13098 }
13101 {
13108 ret);
13109 else
13112 }
13115 {
13121 /* calculate the ranges we are going to use */
13129 /* VNIC MSIx interrupts get mapped when VNIC contexts are created */
13132 /*
13133 * Sanity check - the code expects all SDMA chip source
13134 * interrupts to be in the same CSR, starting at bit 0. Verify
13135 * that this is true by checking the bit location of the start.
13136 */
13142 irq_handler_t handler;
13150 /* obtain the arguments to pci_request_irq */
13173 /*
13174 * Set the interrupt register and mask for this
13175 * context's interrupt.
13176 */
13191 }
13193 /* not in our expected range - complain, then
13194 * ignore it
13195 */
13199 }
13200 /* no argument, no interrupt */
13203 /* make sure the name is terminated */
13207 name);
13213 }
13214 /*
13215 * assign arg after pci_request_irq call, so it will be
13216 * cleaned up
13217 */
13223 }
13226 }
13229 {
13235 }
13242 }
13243 }
13246 {
13257 }
13260 {
13270 /*
13271 * Set the interrupt register and mask for this
13272 * context's interrupt.
13273 */
13282 receive_context_interrupt,
13289 }
13290 /*
13291 * assign arg after pci_request_irq call, so it will be
13292 * cleaned up
13293 */
13301 }
13302 }
13304 /*
13305 * Set the general handler to accept all interrupts, remap all
13306 * chip interrupts back to MSI-X 0.
13307 */
13309 {
13312 /* all interrupts handled by the general handler */
13316 /* all chip interrupts map to MSI-X 0 */
13319 }
13322 {
13323 u32 total;
13327 /*
13328 * Interrupt count:
13329 * 1 general, "slow path" interrupt (includes the SDMA engines
13330 * slow source, SDMACleanupDone)
13331 * N interrupts - one per used SDMA engine
13332 * M interrupt - one per kernel receive context
13333 * V interrupt - one for each VNIC context
13334 */
13337 /* ask for MSI-X interrupts */
13343 /* using INTx */
13344 /* dd->num_msix_entries already zero */
13348 /* using MSI-X, with reduced interrupts */
13355 GFP_KERNEL);
13359 }
13360 /* using MSI-X */
13363 }
13365 /* mask all interrupts */
13367 /* clear all pending interrupts */
13370 /* reset general handler mask, chip MSI-X mappings */
13375 else
13382 fail:
13385 }
13387 /*
13388 * Set up context values in dd. Sets:
13389 *
13390 * num_rcv_contexts - number of contexts being used
13391 * n_krcv_queues - number of kernel contexts
13392 * first_dyn_alloc_ctxt - first dynamically allocated context
13393 * in array of contexts
13394 * freectxts - number of free user contexts
13395 * num_send_contexts - number of PIO send contexts being used
13396 * num_vnic_contexts - number of contexts reserved for VNIC
13397 */
13399 {
13407 u32 n_usr_ctxts;
13409 /*
13410 * Kernel receive contexts:
13411 * - Context 0 - control context (VL15/multicast/error)
13412 * - Context 1 - first kernel context
13413 * - Context 2 - second kernel context
13414 * ...
13415 */
13417 /*
13418 * n_krcvqs is the sum of module parameter kernel receive
13419 * contexts, krcvqs[]. It does not include the control
13420 * context, so add that.
13421 */
13423 else
13425 /*
13426 * Every kernel receive context needs an ACK send context.
13427 * one send context is allocated for each VL{0-7} and VL15
13428 */
13433 num_kernel_contexts);
13435 }
13437 /* Accommodate VNIC contexts if possible */
13441 }
13444 /*
13445 * User contexts:
13446 * - default to 1 user context per real (non-HT) CPU core if
13447 * num_user_contexts is negative
13448 */
13451 else
13453 /*
13454 * Adjust the counts given a global max.
13455 */
13460 n_usr_ctxts);
13461 /* recalculate */
13463 }
13465 /* each user context requires an entry in the RMT */
13471 n_usr_ctxts,
13472 user_rmt_reduced);
13473 /* recalculate */
13475 }
13479 /* the first N are kernel contexts, the rest are user/vnic contexts */
13494 /*
13495 * Receive array allocation:
13496 * All RcvArray entries are divided into groups of 8. This
13497 * is required by the hardware and will speed up writes to
13498 * consecutive entries by using write-combining of the entire
13499 * cacheline.
13500 *
13501 * The number of groups are evenly divided among all contexts.
13502 * any left over groups will be given to the first N user
13503 * contexts.
13504 */
13521 }
13522 /*
13523 * PIO send contexts
13524 */
13529 dd,
13538 }
13541 }
13543 /*
13544 * Set the device/port partition key table. The MAD code
13545 * will ensure that, at least, the partial management
13546 * partition key is present in the table.
13547 */
13549 {
13557 RCV_PARTITION_KEY_PARTITION_KEY_A_MASK) <<
13559 RCV_PARTITION_KEY_PARTITION_KEY_B_SHIFT);
13560 /* Each register holds 4 PKey values. */
13565 }
13566 }
13568 /* Always enable HW pkeys check when pkeys table is set */
13570 }
13572 /*
13573 * These CSRs and memories are uninitialized on reset and must be
13574 * written before reading to set the ECC/parity bits.
13575 *
13576 * NOTE: All user context CSRs that are not mmaped write-only
13577 * (e.g. the TID flows) must be initialized even if the driver never
13578 * reads them.
13579 */
13581 {
13584 /* CceIntMap */
13588 /* SendCtxtCreditReturnAddr */
13592 /* PIO Send buffers */
13593 /* SDMA Send buffers */
13594 /*
13595 * These are not normally read, and (presently) have no method
13596 * to be read, so are not pre-initialized
13597 */
13599 /* RcvHdrAddr */
13600 /* RcvHdrTailAddr */
13601 /* RcvTidFlowTable */
13607 }
13609 /* RcvArray */
13613 /* RcvQPMapTable */
13616 }
13618 /*
13619 * Use the ctrl_bits in CceCtrl to clear the status_bits in CceStatus.
13620 */
13622 u64 ctrl_bits)
13623 {
13625 u64 reg;
13627 /* is the condition present? */
13632 /* clear the condition */
13635 /* wait for the condition to clear */
13646 }
13648 }
13649 }
13651 /* set CCE CSRs to chip reset defaults */
13653 {
13656 /* CCE_REVISION read-only */
13657 /* CCE_REVISION2 read-only */
13658 /* CCE_CTRL - bits clear automatically */
13659 /* CCE_STATUS read-only, use CceCtrl to clear */
13665 /* CCE_ERR_STATUS read-only */
13668 /* CCE_ERR_FORCE leave alone */
13672 /* CCE_PCIE_CTRL leave alone */
13676 CCE_MSIX_TABLE_UPPER_RESETCSR);
13677 }
13679 /* CCE_MSIX_PBA read-only */
13682 }
13686 /* CCE_INT_STATUS read-only */
13689 /* CCE_INT_FORCE leave alone */
13690 /* CCE_INT_BLOCKED read-only */
13691 }
13694 }
13696 /* set MISC CSRs to chip reset defaults */
13698 {
13705 }
13706 /*
13707 * MISC_CFG_SHA_PRELOAD leave alone - always reads 0 and can
13708 * only be written 128-byte chunks
13709 */
13710 /* init RSA engine to clear lingering errors */
13714 /* MISC_STS_8051_DIGEST read-only */
13715 /* MISC_STS_SBM_DIGEST read-only */
13716 /* MISC_STS_PCIE_DIGEST read-only */
13717 /* MISC_STS_FAB_DIGEST read-only */
13718 /* MISC_ERR_STATUS read-only */
13721 /* MISC_ERR_FORCE leave alone */
13722 }
13724 /* set TXE CSRs to chip reset defaults */
13726 {
13729 /*
13730 * TXE Kernel CSRs
13731 */
13734 /* SEND_CONTEXTS read-only */
13735 /* SEND_DMA_ENGINES read-only */
13736 /* SEND_PIO_MEM_SIZE read-only */
13737 /* SEND_DMA_MEM_SIZE read-only */
13740 /* SEND_PIO_ERR_STATUS read-only */
13743 /* SEND_PIO_ERR_FORCE leave alone */
13744 /* SEND_DMA_ERR_STATUS read-only */
13747 /* SEND_DMA_ERR_FORCE leave alone */
13748 /* SEND_EGRESS_ERR_STATUS read-only */
13751 /* SEND_EGRESS_ERR_FORCE leave alone */
13760 /* SEND_ERR_STATUS read-only */
13763 /* SEND_ERR_FORCE read-only */
13776 /* SEND_CM_CREDIT_USED_STATUS read-only */
13785 /* SEND_CM_CREDIT_USED_VL read-only */
13786 /* SEND_CM_CREDIT_USED_VL15 read-only */
13787 /* SEND_EGRESS_CTXT_STATUS read-only */
13788 /* SEND_EGRESS_SEND_DMA_STATUS read-only */
13790 /* SEND_EGRESS_ERR_INFO read-only */
13791 /* SEND_EGRESS_ERR_SOURCE read-only */
13793 /*
13794 * TXE Per-Context CSRs
13795 */
13809 }
13811 /*
13812 * TXE Per-SDMA CSRs
13813 */
13816 /* SEND_DMA_STATUS read-only */
13820 /* SEND_DMA_HEAD read-only */
13823 /* SEND_DMA_IDLE_CNT read-only */
13826 /* SEND_DMA_DESC_FETCHED_CNT read-only */
13827 /* SEND_DMA_ENG_ERR_STATUS read-only */
13830 /* SEND_DMA_ENG_ERR_FORCE leave alone */
13838 }
13839 }
13841 /*
13842 * Expect on entry:
13843 * o Packet ingress is disabled, i.e. RcvCtrl.RcvPortEnable == 0
13844 */
13846 {
13847 u64 reg;
13850 /*
13851 * Wait for DMA to stop: RxRbufPktPending and RxPktInProgress are
13852 * clear.
13853 */
13860 /*
13861 * Give up after 1ms - maximum wait time.
13862 *
13863 * RBuf size is 136KiB. Slowest possible is PCIe Gen1 x1 at
13864 * 250MB/s bandwidth. Lower rate to 66% for overhead to get:
13865 * 136 KB / (66% * 250MB/s) = 844us
13866 */
13872 }
13874 }
13876 /* start the init - expect RcvCtrl to be 0 */
13879 /*
13880 * Read to force the write of Rcvtrl.RxRbufInit. There is a brief
13881 * period after the write before RcvStatus.RxRbufInitDone is valid.
13882 * The delay in the first run through the loop below is sufficient and
13883 * required before the first read of RcvStatus.RxRbufInintDone.
13884 */
13887 /* wait for the init to finish */
13890 /* delay is required first time through - see above */
13896 /* give up after 100us - slowest possible at 33MHz is 73us */
13900 __func__);
13902 }
13903 }
13904 }
13906 /* set RXE CSRs to chip reset defaults */
13908 {
13911 /*
13912 * RXE Kernel CSRs
13913 */
13916 /* RCV_STATUS read-only */
13917 /* RCV_CONTEXTS read-only */
13918 /* RCV_ARRAY_CNT read-only */
13919 /* RCV_BUF_SIZE read-only */
13924 /* this is a clear-down */
13926 RCV_ERR_INFO_RCV_EXCESS_BUFFER_OVERRUN_SMASK);
13927 /* RCV_ERR_STATUS read-only */
13930 /* RCV_ERR_FORCE leave alone */
13944 /*
13945 * RXE Kernel and User Per-Context CSRs
13946 */
13948 /* kernel */
13950 /* RCV_CTXT_STATUS read-only */
13962 /* user */
13963 /* RCV_HDR_TAIL read-only */
13965 /* RCV_EGR_INDEX_TAIL read-only */
13967 /* RCV_EGR_OFFSET_TAIL read-only */
13971 }
13972 }
13973 }
13975 /*
13976 * Set sc2vl tables.
13977 *
13978 * They power on to zeros, so to avoid send context errors
13979 * they need to be set:
13980 *
13981 * SC 0-7 -> VL 0-7 (respectively)
13982 * SC 15 -> VL 15
13983 * otherwise
13984 * -> VL 0
13985 */
13987 {
13989 /* init per architecture spec, constrained by hardware capability */
13991 /* HFI maps sent packets */
14017 /* DC maps received packets */
14027 /* initialize the cached sc2vl values consistently with h/w */
14031 else
14033 }
14034 }
14036 /*
14037 * Read chip sizes and then reset parts to sane, disabled, values. We cannot
14038 * depend on the chip going through a power-on reset - a driver may be loaded
14039 * and unloaded many times.
14040 *
14041 * Do not write any CSR values to the chip in this routine - there may be
14042 * a reset following the (possible) FLR in this routine.
14043 *
14044 */
14046 {
14050 /*
14051 * Put the HFI CSRs in a known state.
14052 * Combine this with a DC reset.
14053 *
14054 * Stop the device from doing anything while we do a
14055 * reset. We know there are no other active users of
14056 * the device since we are now in charge. Turn off
14057 * off all outbound and inbound traffic and make sure
14058 * the device does not generate any interrupts.
14059 */
14061 /* disable send contexts and SDMA engines */
14067 /* disable port (turn off RXE inbound traffic) and contexts */
14071 /* mask all interrupt sources */
14075 /*
14076 * DC Reset: do a full DC reset before the register clear.
14077 * A recommended length of time to hold is one CSR read,
14078 * so reread the CceDcCtrl. Then, hold the DC in reset
14079 * across the clear.
14080 */
14085 /*
14086 * A FLR will reset the SPC core and part of the PCIe.
14087 * The parts that need to be restored have already been
14088 * saved.
14089 */
14092 /* do the FLR, the DC reset will remain */
14095 /* restore command and BARs */
14099 __func__);
14101 }
14109 __func__);
14111 }
14112 }
14119 }
14120 /* clear the DC reset */
14123 /* Set the LED off */
14126 /*
14127 * Clear the QSFP reset.
14128 * An FLR enforces a 0 on all out pins. The driver does not touch
14129 * ASIC_QSFPn_OUT otherwise. This leaves RESET_N low and
14130 * anything plugged constantly in reset, if it pays attention
14131 * to RESET_N.
14132 * Prime examples of this are optical cables. Set all pins high.
14133 * I2CCLK and I2CDAT will change per direction, and INT_N and
14134 * MODPRS_N are input only and their value is ignored.
14135 */
14140 }
14143 {
14146 /* assign link credit variables */
14152 /* enough room for 8 MAD packets plus header - 17K */
14164 }
14166 }
14169 {
14170 /* user changed the KDETH_QP */
14172 /* out of range or illegal value */
14175 }
14181 SEND_BTH_QP_KDETH_QP_SHIFT);
14185 RCV_BTH_QP_KDETH_QP_SHIFT);
14186 }
14188 /**
14189 * init_qpmap_table
14190 * @dd - device data
14191 * @first_ctxt - first context
14192 * @last_ctxt - first context
14193 *
14194 * This return sets the qpn mapping table that
14195 * is indexed by qpn[8:1].
14196 *
14197 * The routine will round robin the 256 settings
14198 * from first_ctxt to last_ctxt.
14199 *
14200 * The first/last looks ahead to having specialized
14201 * receive contexts for mgmt and bypass. Normal
14202 * verbs traffic will assumed to be on a range
14203 * of receive contexts.
14204 */
14206 u32 first_ctxt,
14207 u32 last_ctxt)
14208 {
14216 ctxt++;
14223 }
14224 }
14228 }
14233 };
14236 u8 offset;
14237 u8 pkt_type;
14238 u32 field1_off;
14239 u32 field2_off;
14240 u32 index1_off;
14241 u32 index1_width;
14242 u32 index2_off;
14243 u32 index2_width;
14244 u32 mask1;
14245 u32 value1;
14246 u32 mask2;
14247 u32 value2;
14248 };
14250 /*
14251 * Return an initialized RMT map table for users to fill in. OK if it
14252 * returns NULL, indicating no table.
14253 */
14255 {
14263 }
14266 }
14268 /*
14269 * Write the final RMT map table to the chip and free the table. OK if
14270 * table is NULL.
14271 */
14274 {
14278 /* write table to chip */
14282 /* enable RSM */
14284 }
14285 }
14287 /*
14288 * Add a receive side mapping rule.
14289 */
14292 {
14309 }
14311 /*
14312 * Clear a receive side mapping rule.
14313 */
14315 {
14319 }
14321 /* return the number of RSM map table entries that will be used for QOS */
14324 {
14329 /* is QOS active at all? */
14335 /* determine bits for qpn */
14343 /* determine bits for vl */
14346 /* reject if too much is used */
14357 no_qos:
14363 }
14365 /**
14366 * init_qos - init RX qos
14367 * @dd - device data
14368 * @rmt - RSM map table
14369 *
14370 * This routine initializes Rule 0 and the RSM map table to implement
14371 * quality of service (qos).
14372 *
14373 * If all of the limit tests succeed, qos is applied based on the array
14374 * interpretation of krcvqs where entry 0 is VL0.
14375 *
14376 * The number of vl bits (n) and the number of qpn bits (m) are computed to
14377 * feed both the RSM map table and the single rule.
14378 */
14380 {
14384 u64 reg;
14393 /* enough room in the map table? */
14398 /* add qos entries to the the RSM map table */
14406 /* generate the index the hardware will produce */
14410 /* replace default with context number */
14412 reg &= ~(RCV_RSM_MAP_TABLE_RCV_CONTEXT_A_MASK
14418 }
14420 }
14435 /* add rule 0 */
14438 /* mark RSM map entries as used */
14440 /* map everything else to the mcast/err/vl15 context */
14444 bail:
14447 }
14451 {
14453 u64 reg;
14455 u8 offset;
14457 /* there needs to be enough room in the map table */
14461 }
14463 /*
14464 * RSM will extract the destination context as an index into the
14465 * map table. The destination contexts are a sequential block
14466 * in the range first_dyn_alloc_ctxt...num_rcv_contexts-1 (inclusive).
14467 * Map entries are accessed as offset + extracted value. Adjust
14468 * the added offset so this sequence can be placed anywhere in
14469 * the table - as long as the entries themselves do not wrap.
14470 * There are only enough bits in offset for the table size, so
14471 * start with that to allow for a "negative" offset.
14472 */
14478 /* replace with identity mapping */
14485 }
14487 /*
14488 * For RSM intercept of Expected FECN packets:
14489 * o packet type 0 - expected
14490 * o match on F (bit 95), using select/match 1, and
14491 * o match on SH (bit 133), using select/match 2.
14492 *
14493 * Use index 1 to extract the 8-bit receive context from DestQP
14494 * (start at bit 64). Use that as the RSM map table index.
14495 */
14509 /* add rule 1 */
14513 }
14515 /* Initialize RSM for VNIC */
14517 {
14520 u64 reg;
14521 u32 regoff;
14528 }
14534 /* Update RSM mapping table, 32 regs, 256 entries - 1 ctx per byte */
14538 /* Update map register with vnic context */
14542 /* Wrap up vnic ctx index */
14544 /* Write back map register */
14554 }
14555 }
14557 /* Add rule for vnic */
14560 /* Match 16B packets */
14564 /* Match ETH L4 packets */
14568 /* Calc context from veswid and entropy */
14575 /* Enable RSM if not already enabled */
14577 }
14580 {
14583 /* Disable RSM if used only by vnic */
14586 }
14589 {
14591 u64 val;
14593 /* enable all receive errors */
14597 /* set up QOS, including the QPN map table */
14601 /* record number of used rsm map entries for vnic */
14605 /*
14606 * make sure RcvCtrl.RcvWcb <= PCIe Device Control
14607 * Register Max_Payload_Size (PCI_EXP_DEVCTL in Linux PCIe config
14608 * space, PciCfgCap2.MaxPayloadSize in HFI). There is only one
14609 * invalid configuration: RcvCtrl.RcvWcb set to its max of 256 and
14610 * Max_PayLoad_Size set to its minimum of 128.
14611 *
14612 * Presently, RcvCtrl.RcvWcb is not modified from its default of 0
14613 * (64 bytes). Max_Payload_Size is possibly modified upward in
14614 * tune_pcie_caps() which is called after this routine.
14615 */
14617 /* Have 16 bytes (4DW) of bypass header available in header queue */
14621 }
14624 {
14625 /* enable all CCE errors */
14627 /* enable *some* Misc errors */
14629 /* enable all DC errors, except LCB */
14632 }
14634 /*
14635 * Fill out the given AU table using the given CU. A CU is defined in terms
14636 * AUs. The table is a an encoding: given the index, how many AUs does that
14637 * represent?
14638 *
14639 * NOTE: Assumes that the register layout is the same for the
14640 * local and remote tables.
14641 */
14644 {
14649 SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE2_SHIFT |
14651 SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE3_SHIFT);
14654 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE4_SHIFT |
14656 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE5_SHIFT |
14658 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE6_SHIFT |
14660 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE7_SHIFT);
14661 }
14664 {
14666 SEND_CM_LOCAL_AU_TABLE4_TO7);
14667 }
14670 {
14672 SEND_CM_REMOTE_AU_TABLE4_TO7);
14673 }
14676 {
14679 /* enable all PIO, SDMA, general, and Egress errors */
14685 /* enable all per-context and per-SDMA engine errors */
14691 /* set the local CU to AU mapping */
14694 /*
14695 * Set reasonable default for Credit Return Timer
14696 * Don't set on Simulator - causes it to choke.
14697 */
14700 }
14703 u16 jkey)
14704 {
14705 u8 hw_ctxt;
14706 u64 reg;
14714 SEND_CTXT_CHECK_JOB_KEY_VALUE_SHIFT);
14715 /* JOB_KEY_ALLOW_PERMISSIVE is not allowed by default */
14719 /*
14720 * Enable send-side J_KEY integrity check, unless this is A0 h/w
14721 */
14726 }
14728 /* Enable J_KEY check on receive context. */
14731 RCV_KEY_CTRL_JOB_KEY_VALUE_SHIFT);
14735 }
14738 {
14739 u8 hw_ctxt;
14740 u64 reg;
14747 /*
14748 * Disable send-side J_KEY integrity check, unless this is A0 h/w.
14749 * This check would not have been enabled for A0 h/w, see
14750 * set_ctxt_jkey().
14751 */
14756 }
14757 /* Turn off the J_KEY on the receive side */
14761 }
14764 u16 pkey)
14765 {
14766 u8 hw_ctxt;
14767 u64 reg;
14774 SEND_CTXT_CHECK_PARTITION_KEY_VALUE_SHIFT;
14782 }
14785 {
14786 u8 hw_ctxt;
14787 u64 reg;
14799 }
14801 /*
14802 * Start doing the clean up the the chip. Our clean up happens in multiple
14803 * stages and this is just the first.
14804 */
14806 {
14811 }
14813 #define HFI_BASE_GUID(dev) \
14814 ((dev)->base_guid & ~(1ULL << GUID_HFI_INDEX_SHIFT))
14816 /*
14817 * Information can be shared between the two HFIs on the same ASIC
14818 * in the same OS. This function finds the peer device and sets
14819 * up a shared structure.
14820 */
14822 {
14828 /* pre-allocate the asic structure in case we are the first device */
14834 /* Find our peer device */
14840 }
14841 }
14844 /* use already allocated structure */
14850 }
14854 /* first one through - set up i2c devices */
14859 }
14861 /*
14862 * Set dd->boardname. Use a generic name if a name is not returned from
14863 * EFI variable space.
14864 *
14865 * Return 0 on success, -ENOMEM if space could not be allocated.
14866 */
14868 {
14869 /* generic board description */
14879 /* use generic description */
14883 }
14885 }
14887 /*
14888 * Check the interrupt registers to make sure that they are mapped correctly.
14889 * It is intended to help user identify any mismapping by VMM when the driver
14890 * is running in a VM. This function should only be called before interrupt
14891 * is set up properly.
14892 *
14893 * Return 0 on success, -EINVAL on failure.
14894 */
14896 {
14897 u64 reg;
14899 u64 mask;
14901 /* Clear CceIntMask[0] to avoid raising any interrupts */
14908 /* Clear all interrupt status bits */
14914 /* Set all interrupt status bits */
14920 /* Restore the interrupt mask */
14925 err_exit:
14929 }
14931 /**
14932 * Allocate and initialize the device structure for the hfi.
14933 * @dev: the pci_dev for hfi1_ib device
14934 * @ent: pci_device_id struct for this dev
14935 *
14936 * Also allocates, initializes, and returns the devdata struct for this
14937 * device instance
14938 *
14939 * This is global, and is called directly at init to set up the
14940 * chip-specific function pointers for later use.
14941 */
14944 {
14947 u64 reg;
14953 "Functional simulator"
14954 };
14964 /* init common fields */
14966 /* DC supports 4 link widths */
14972 /* start out enabling only 4X */
14976 /* link width active is 0 when link is down */
14977 /* link width downgrade active is 0 when link is down */
14984 }
14987 /* Set the default MTU. */
14991 /*
14992 * Set the initial values to reasonable default, will be set
14993 * for real when link is up.
14994 */
14998 /* initialize supported LTP CRC mode */
15000 /* initialize enabled LTP CRC mode */
15002 /* start in offline */
15005 }
15007 /*
15008 * Do remaining PCIe setup and save PCIe values in dd.
15009 * Any error printing is already done by the init code.
15010 * On return, we have the chip mapped.
15011 */
15016 /* Save PCI space registers to rewrite after device reset */
15021 /* verify that reads actually work, save revision for reset check */
15027 }
15033 /*
15034 * Check interrupt registers mapping if the driver has no access to
15035 * the upstream component. In this case, it is likely that the driver
15036 * is running in a VM.
15037 */
15042 }
15044 /*
15045 * obtain the hardware ID - NOT related to unit, which is a
15046 * software enumeration
15047 */
15051 /* the variable size will remove unwanted bits */
15058 /* speeds the hardware can support */
15060 /* speeds allowed to run at */
15062 /* give a reasonable active value, will be set on link up */
15070 /* fix up link widths for emulation _p */
15077 OPA_LINK_WIDTH_1X;
15078 }
15079 /* insure num_vls isn't larger than number of sdma engines */
15086 }
15088 /*
15089 * Convert the ns parameter to the 64 * cclocks used in the CSR.
15090 * Limit the max if larger than the field holds. If timeout is
15091 * non-zero, then the calculated field will be at least 1.
15092 *
15093 * Must be after icode is set up - the cclock rate depends
15094 * on knowing the hardware being used.
15095 */
15098 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK)
15100 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK;
15104 /* needs to be done before we look for the peer device */
15107 /* set up shared ASIC data with peer device */
15112 /* obtain chip sizes, reset chip CSRs */
15117 /* read in the PCIe link speed information */
15122 /* call before get_platform_config(), after init_chip_resources() */
15127 /* Needs to be called before hfi1_firmware_init */
15130 /* read in firmware */
15135 /*
15136 * In general, the PCIe Gen3 transition must occur after the
15137 * chip has been idled (so it won't initiate any PCIe transactions
15138 * e.g. an interrupt) and before the driver changes any registers
15139 * (the transition will reset the registers).
15140 *
15141 * In particular, place this call after:
15142 * - init_chip() - the chip will not initiate any PCIe transactions
15143 * - pcie_speeds() - reads the current link speed
15144 * - hfi1_firmware_init() - the needed firmware is ready to be
15145 * downloaded
15146 */
15151 /* start setting dd values and adjusting CSRs */
15172 /* set initial RXE CSRs */
15174 /* set initial TXE CSRs */
15176 /* set initial non-RXE, non-TXE CSRs */
15178 /* set up KDETH QP prefix in both RX and TX CSRs */
15185 /* send contexts must be set up before receive contexts */
15194 /*
15195 * Initialize aspm, to be done after gen3 transition and setting up
15196 * contexts and before enabling interrupts
15197 */
15201 /*
15202 * rcd[0] is guaranteed to be valid by this point. Also, all
15203 * context are using the same value, as per the module parameter.
15204 */
15211 /* sdma init */
15216 }
15218 /* use contexts created by hfi1_create_kctxts */
15223 /* set up LCB access - must be after set_up_interrupts() */
15226 /*
15227 * Serial number is created from the base guid:
15228 * [27:24] = base guid [38:35]
15229 * [23: 0] = base guid [23: 0]
15230 */
15255 /* The user refcount starts with one to inidicate an active device */
15260 bail_free_rcverr:
15262 bail_free_cntrs:
15264 bail_clear_intr:
15266 bail_cleanup:
15268 bail_free:
15271 bail:
15273 }
15276 u32 dw_len)
15277 {
15278 u32 delta_cycles;
15280 /* rates here are in units of 10^6 bits/sec */
15292 }
15294 /**
15295 * create_pbc - build a pbc for transmission
15296 * @flags: special case flags or-ed in built pbc
15297 * @srate: static rate
15298 * @vl: vl
15299 * @dwlen: dword length (header words + data words + pbc words)
15300 *
15301 * Create a PBC with the given flags, rate, VL, and length.
15302 *
15303 * NOTE: The PBC created will not insert any HCRC - all callers but one are
15304 * for verbs, which does not use this PSM feature. The lone other caller
15305 * is for the diagnostic interface which calls this if the user does not
15306 * supply their own PBC.
15307 */
15309 u32 dw_len)
15310 {
15316 pbc = flags
15324 }
15326 #define SBUS_THERMAL 0x4f
15327 #define SBUS_THERM_MONITOR_MODE 0x1
15329 #define THERM_FAILURE(dev, ret, reason) \
15330 dd_dev_err((dd), \
15332 (reason), (ret))
15334 /*
15335 * Initialize the thermal sensor.
15336 *
15337 * After initialization, enable polling of thermal sensor through
15338 * SBus interface. In order for this to work, the SBus Master
15339 * firmware has to be loaded due to the fact that the HW polling
15340 * logic uses SBus interrupts, which are not supported with
15341 * default firmware. Otherwise, no data will be returned through
15342 * the ASIC_STS_THERM CSR.
15343 */
15345 {
15356 }
15359 /* Disable polling of thermal readings */
15362 /* Thermal Sensor Initialization */
15363 /* Step 1: Reset the Thermal SBus Receiver */
15369 }
15370 /* Step 2: Set Reset bit in Thermal block */
15376 }
15377 /* Step 3: Write clock divider value (100MHz -> 2MHz) */
15383 }
15384 /* Step 4: Select temperature mode */
15386 WRITE_SBUS_RECEIVER,
15387 SBUS_THERM_MONITOR_MODE);
15391 }
15392 /* Step 5: De-assert block reset and start conversion */
15398 }
15399 /* Step 5.1: Wait for first conversion (21.5ms per spec) */
15402 /* Enable polling of thermal readings */
15405 /* Set initialized flag */
15410 done:
15413 }
15416 {
15418 /*
15419 * Thermal Critical Interrupt
15420 * Put the device into forced freeze mode, take link down to
15421 * offline, and put DC into reset.
15422 */
15427 /*
15428 * Shut DC down as much and as quickly as possible.
15429 *
15430 * Step 1: Take the link down to OFFLINE. This will cause the
15431 * 8051 to put the Serdes in reset. However, we don't want to
15432 * go through the entire link state machine since we want to
15433 * shutdown ASAP. Furthermore, this is not a graceful shutdown
15434 * but rather an attempt to save the chip.
15435 * Code below is almost the same as quiet_serdes() but avoids
15436 * all the extra work and the sleeps.
15437 */
15441 PLS_OFFLINE);
15442 /*
15443 * Step 2: Shutdown LCB and 8051
15444 * After shutdown, do not restore DC_CFG_RESET value.
15445 */
15447 }