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x86/topology: Update the 'cpu cores' field in /proc/cpuinfo correctly across CPU...
[cris-mirror.git] / drivers / infiniband / hw / nes / nes_utils.c
blob21b4a8373acfcaa22e6f942ffd9cd3600b51a2d5
1 /*
2 * Copyright (c) 2006 - 2011 Intel Corporation. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34 #include <linux/module.h>
35 #include <linux/moduleparam.h>
36 #include <linux/netdevice.h>
37 #include <linux/etherdevice.h>
38 #include <linux/ethtool.h>
39 #include <linux/mii.h>
40 #include <linux/if_vlan.h>
41 #include <linux/slab.h>
42 #include <linux/crc32.h>
43 #include <linux/in.h>
44 #include <linux/ip.h>
45 #include <linux/tcp.h>
46 #include <linux/init.h>
47 #include <linux/kernel.h>
48
49 #include <asm/io.h>
50 #include <asm/irq.h>
51 #include <asm/byteorder.h>
52
53 #include "nes.h"
54
55 static u16 nes_read16_eeprom(void __iomem *addr, u16 offset);
56
57 u32 mh_detected;
58 u32 mh_pauses_sent;
59
60 static u32 nes_set_pau(struct nes_device *nesdev)
61 {
62 u32 ret = 0;
63 u32 counter;
64
65 nes_write_indexed(nesdev, NES_IDX_GPR2, NES_ENABLE_PAU);
66 nes_write_indexed(nesdev, NES_IDX_GPR_TRIGGER, 1);
67
68 for (counter = 0; counter < NES_PAU_COUNTER; counter++) {
69 udelay(30);
70 if (!nes_read_indexed(nesdev, NES_IDX_GPR2)) {
71 printk(KERN_INFO PFX "PAU is supported.\n");
72 break;
73 }
74 nes_write_indexed(nesdev, NES_IDX_GPR_TRIGGER, 1);
75 }
76 if (counter == NES_PAU_COUNTER) {
77 printk(KERN_INFO PFX "PAU is not supported.\n");
78 return -EPERM;
79 }
80 return ret;
81 }
82
83 /**
84 * nes_read_eeprom_values -
85 */
86 int nes_read_eeprom_values(struct nes_device *nesdev, struct nes_adapter *nesadapter)
87 {
88 u32 mac_addr_low;
89 u16 mac_addr_high;
90 u16 eeprom_data;
91 u16 eeprom_offset;
92 u16 next_section_address;
93 u16 sw_section_ver;
94 u8 major_ver = 0;
95 u8 minor_ver = 0;
96
97 /* TODO: deal with EEPROM endian issues */
98 if (nesadapter->firmware_eeprom_offset == 0) {
99 /* Read the EEPROM Parameters */
100 eeprom_data = nes_read16_eeprom(nesdev->regs, 0);
101 nes_debug(NES_DBG_HW, "EEPROM Offset 0 = 0x%04X\n", eeprom_data);
102 eeprom_offset = 2 + (((eeprom_data & 0x007f) << 3) <<
103 ((eeprom_data & 0x0080) >> 7));
104 nes_debug(NES_DBG_HW, "Firmware Offset = 0x%04X\n", eeprom_offset);
105 nesadapter->firmware_eeprom_offset = eeprom_offset;
106 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 4);
107 if (eeprom_data != 0x5746) {
108 nes_debug(NES_DBG_HW, "Not a valid Firmware Image = 0x%04X\n", eeprom_data);
109 return -1;
110 }
111
112 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
113 nes_debug(NES_DBG_HW, "EEPROM Offset %u = 0x%04X\n",
114 eeprom_offset + 2, eeprom_data);
115 eeprom_offset += ((eeprom_data & 0x00ff) << 3) << ((eeprom_data & 0x0100) >> 8);
116 nes_debug(NES_DBG_HW, "Software Offset = 0x%04X\n", eeprom_offset);
117 nesadapter->software_eeprom_offset = eeprom_offset;
118 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 4);
119 if (eeprom_data != 0x5753) {
120 printk("Not a valid Software Image = 0x%04X\n", eeprom_data);
121 return -1;
122 }
123 sw_section_ver = nes_read16_eeprom(nesdev->regs, nesadapter->software_eeprom_offset + 6);
124 nes_debug(NES_DBG_HW, "Software section version number = 0x%04X\n",
125 sw_section_ver);
126
127 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
128 nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
129 eeprom_offset + 2, eeprom_data);
130 next_section_address = eeprom_offset + (((eeprom_data & 0x00ff) << 3) <<
131 ((eeprom_data & 0x0100) >> 8));
132 eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
133 if (eeprom_data != 0x414d) {
134 nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x414d but was 0x%04X\n",
135 eeprom_data);
136 goto no_fw_rev;
137 }
138 eeprom_offset = next_section_address;
139
140 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
141 nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
142 eeprom_offset + 2, eeprom_data);
143 next_section_address = eeprom_offset + (((eeprom_data & 0x00ff) << 3) <<
144 ((eeprom_data & 0x0100) >> 8));
145 eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
146 if (eeprom_data != 0x4f52) {
147 nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x4f52 but was 0x%04X\n",
148 eeprom_data);
149 goto no_fw_rev;
150 }
151 eeprom_offset = next_section_address;
152
153 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
154 nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
155 eeprom_offset + 2, eeprom_data);
156 next_section_address = eeprom_offset + ((eeprom_data & 0x00ff) << 3);
157 eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
158 if (eeprom_data != 0x5746) {
159 nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x5746 but was 0x%04X\n",
160 eeprom_data);
161 goto no_fw_rev;
162 }
163 eeprom_offset = next_section_address;
164
165 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
166 nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
167 eeprom_offset + 2, eeprom_data);
168 next_section_address = eeprom_offset + ((eeprom_data & 0x00ff) << 3);
169 eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
170 if (eeprom_data != 0x5753) {
171 nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x5753 but was 0x%04X\n",
172 eeprom_data);
173 goto no_fw_rev;
174 }
175 eeprom_offset = next_section_address;
176
177 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
178 nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
179 eeprom_offset + 2, eeprom_data);
180 next_section_address = eeprom_offset + ((eeprom_data & 0x00ff) << 3);
181 eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
182 if (eeprom_data != 0x414d) {
183 nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x414d but was 0x%04X\n",
184 eeprom_data);
185 goto no_fw_rev;
186 }
187 eeprom_offset = next_section_address;
188
189 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
190 nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
191 eeprom_offset + 2, eeprom_data);
192 next_section_address = eeprom_offset + ((eeprom_data & 0x00ff) << 3);
193 eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
194 if (eeprom_data != 0x464e) {
195 nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x464e but was 0x%04X\n",
196 eeprom_data);
197 goto no_fw_rev;
198 }
199 eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 8);
200 printk(PFX "Firmware version %u.%u\n", (u8)(eeprom_data>>8), (u8)eeprom_data);
201 major_ver = (u8)(eeprom_data >> 8);
202 minor_ver = (u8)(eeprom_data);
203
204 if (nes_drv_opt & NES_DRV_OPT_DISABLE_VIRT_WQ) {
205 nes_debug(NES_DBG_HW, "Virtual WQs have been disabled\n");
206 } else if (((major_ver == 2) && (minor_ver > 21)) || ((major_ver > 2) && (major_ver != 255))) {
207 nesadapter->virtwq = 1;
208 }
209 if (((major_ver == 3) && (minor_ver >= 16)) || (major_ver > 3))
210 nesadapter->send_term_ok = 1;
211
212 if (nes_drv_opt & NES_DRV_OPT_ENABLE_PAU) {
213 if (!nes_set_pau(nesdev))
214 nesadapter->allow_unaligned_fpdus = 1;
215 }
216
217 nesadapter->firmware_version = (((u32)(u8)(eeprom_data>>8)) << 16) +
218 (u32)((u8)eeprom_data);
219
220 eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 10);
221 printk(PFX "EEPROM version %u.%u\n", (u8)(eeprom_data>>8), (u8)eeprom_data);
222 nesadapter->eeprom_version = (((u32)(u8)(eeprom_data>>8)) << 16) +
223 (u32)((u8)eeprom_data);
224
225 no_fw_rev:
226 /* eeprom is valid */
227 eeprom_offset = nesadapter->software_eeprom_offset;
228 eeprom_offset += 8;
229 nesadapter->netdev_max = (u8)nes_read16_eeprom(nesdev->regs, eeprom_offset);
230 eeprom_offset += 2;
231 mac_addr_high = nes_read16_eeprom(nesdev->regs, eeprom_offset);
232 eeprom_offset += 2;
233 mac_addr_low = (u32)nes_read16_eeprom(nesdev->regs, eeprom_offset);
234 eeprom_offset += 2;
235 mac_addr_low <<= 16;
236 mac_addr_low += (u32)nes_read16_eeprom(nesdev->regs, eeprom_offset);
237 nes_debug(NES_DBG_HW, "Base MAC Address = 0x%04X%08X\n",
238 mac_addr_high, mac_addr_low);
239 nes_debug(NES_DBG_HW, "MAC Address count = %u\n", nesadapter->netdev_max);
240
241 nesadapter->mac_addr_low = mac_addr_low;
242 nesadapter->mac_addr_high = mac_addr_high;
243
244 /* Read the Phy Type array */
245 eeprom_offset += 10;
246 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
247 nesadapter->phy_type[0] = (u8)(eeprom_data >> 8);
248 nesadapter->phy_type[1] = (u8)eeprom_data;
249
250 /* Read the port array */
251 eeprom_offset += 2;
252 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
253 nesadapter->phy_type[2] = (u8)(eeprom_data >> 8);
254 nesadapter->phy_type[3] = (u8)eeprom_data;
255 /* port_count is set by soft reset reg */
256 nes_debug(NES_DBG_HW, "port_count = %u, port 0 -> %u, port 1 -> %u,"
257 " port 2 -> %u, port 3 -> %u\n",
258 nesadapter->port_count,
259 nesadapter->phy_type[0], nesadapter->phy_type[1],
260 nesadapter->phy_type[2], nesadapter->phy_type[3]);
261
262 /* Read PD config array */
263 eeprom_offset += 10;
264 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
265 nesadapter->pd_config_size[0] = eeprom_data;
266 eeprom_offset += 2;
267 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
268 nesadapter->pd_config_base[0] = eeprom_data;
269 nes_debug(NES_DBG_HW, "PD0 config, size=0x%04x, base=0x%04x\n",
270 nesadapter->pd_config_size[0], nesadapter->pd_config_base[0]);
271
272 eeprom_offset += 2;
273 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
274 nesadapter->pd_config_size[1] = eeprom_data;
275 eeprom_offset += 2;
276 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
277 nesadapter->pd_config_base[1] = eeprom_data;
278 nes_debug(NES_DBG_HW, "PD1 config, size=0x%04x, base=0x%04x\n",
279 nesadapter->pd_config_size[1], nesadapter->pd_config_base[1]);
280
281 eeprom_offset += 2;
282 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
283 nesadapter->pd_config_size[2] = eeprom_data;
284 eeprom_offset += 2;
285 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
286 nesadapter->pd_config_base[2] = eeprom_data;
287 nes_debug(NES_DBG_HW, "PD2 config, size=0x%04x, base=0x%04x\n",
288 nesadapter->pd_config_size[2], nesadapter->pd_config_base[2]);
289
290 eeprom_offset += 2;
291 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
292 nesadapter->pd_config_size[3] = eeprom_data;
293 eeprom_offset += 2;
294 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
295 nesadapter->pd_config_base[3] = eeprom_data;
296 nes_debug(NES_DBG_HW, "PD3 config, size=0x%04x, base=0x%04x\n",
297 nesadapter->pd_config_size[3], nesadapter->pd_config_base[3]);
298
299 /* Read Rx Pool Size */
300 eeprom_offset += 22; /* 46 */
301 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
302 eeprom_offset += 2;
303 nesadapter->rx_pool_size = (((u32)eeprom_data) << 16) +
304 nes_read16_eeprom(nesdev->regs, eeprom_offset);
305 nes_debug(NES_DBG_HW, "rx_pool_size = 0x%08X\n", nesadapter->rx_pool_size);
306
307 eeprom_offset += 2;
308 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
309 eeprom_offset += 2;
310 nesadapter->tx_pool_size = (((u32)eeprom_data) << 16) +
311 nes_read16_eeprom(nesdev->regs, eeprom_offset);
312 nes_debug(NES_DBG_HW, "tx_pool_size = 0x%08X\n", nesadapter->tx_pool_size);
313
314 eeprom_offset += 2;
315 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
316 eeprom_offset += 2;
317 nesadapter->rx_threshold = (((u32)eeprom_data) << 16) +
318 nes_read16_eeprom(nesdev->regs, eeprom_offset);
319 nes_debug(NES_DBG_HW, "rx_threshold = 0x%08X\n", nesadapter->rx_threshold);
320
321 eeprom_offset += 2;
322 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
323 eeprom_offset += 2;
324 nesadapter->tcp_timer_core_clk_divisor = (((u32)eeprom_data) << 16) +
325 nes_read16_eeprom(nesdev->regs, eeprom_offset);
326 nes_debug(NES_DBG_HW, "tcp_timer_core_clk_divisor = 0x%08X\n",
327 nesadapter->tcp_timer_core_clk_divisor);
328
329 eeprom_offset += 2;
330 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
331 eeprom_offset += 2;
332 nesadapter->iwarp_config = (((u32)eeprom_data) << 16) +
333 nes_read16_eeprom(nesdev->regs, eeprom_offset);
334 nes_debug(NES_DBG_HW, "iwarp_config = 0x%08X\n", nesadapter->iwarp_config);
335
336 eeprom_offset += 2;
337 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
338 eeprom_offset += 2;
339 nesadapter->cm_config = (((u32)eeprom_data) << 16) +
340 nes_read16_eeprom(nesdev->regs, eeprom_offset);
341 nes_debug(NES_DBG_HW, "cm_config = 0x%08X\n", nesadapter->cm_config);
342
343 eeprom_offset += 2;
344 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
345 eeprom_offset += 2;
346 nesadapter->sws_timer_config = (((u32)eeprom_data) << 16) +
347 nes_read16_eeprom(nesdev->regs, eeprom_offset);
348 nes_debug(NES_DBG_HW, "sws_timer_config = 0x%08X\n", nesadapter->sws_timer_config);
349
350 eeprom_offset += 2;
351 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
352 eeprom_offset += 2;
353 nesadapter->tcp_config1 = (((u32)eeprom_data) << 16) +
354 nes_read16_eeprom(nesdev->regs, eeprom_offset);
355 nes_debug(NES_DBG_HW, "tcp_config1 = 0x%08X\n", nesadapter->tcp_config1);
356
357 eeprom_offset += 2;
358 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
359 eeprom_offset += 2;
360 nesadapter->wqm_wat = (((u32)eeprom_data) << 16) +
361 nes_read16_eeprom(nesdev->regs, eeprom_offset);
362 nes_debug(NES_DBG_HW, "wqm_wat = 0x%08X\n", nesadapter->wqm_wat);
363
364 eeprom_offset += 2;
365 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
366 eeprom_offset += 2;
367 nesadapter->core_clock = (((u32)eeprom_data) << 16) +
368 nes_read16_eeprom(nesdev->regs, eeprom_offset);
369 nes_debug(NES_DBG_HW, "core_clock = 0x%08X\n", nesadapter->core_clock);
370
371 if ((sw_section_ver) && (nesadapter->hw_rev != NE020_REV)) {
372 eeprom_offset += 2;
373 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
374 nesadapter->phy_index[0] = (eeprom_data & 0xff00)>>8;
375 nesadapter->phy_index[1] = eeprom_data & 0x00ff;
376 eeprom_offset += 2;
377 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
378 nesadapter->phy_index[2] = (eeprom_data & 0xff00)>>8;
379 nesadapter->phy_index[3] = eeprom_data & 0x00ff;
380 } else {
381 nesadapter->phy_index[0] = 4;
382 nesadapter->phy_index[1] = 5;
383 nesadapter->phy_index[2] = 6;
384 nesadapter->phy_index[3] = 7;
385 }
386 nes_debug(NES_DBG_HW, "Phy address map = 0 > %u, 1 > %u, 2 > %u, 3 > %u\n",
387 nesadapter->phy_index[0],nesadapter->phy_index[1],
388 nesadapter->phy_index[2],nesadapter->phy_index[3]);
389 }
390
391 return 0;
392 }
393
394
395 /**
396 * nes_read16_eeprom
397 */
398 static u16 nes_read16_eeprom(void __iomem *addr, u16 offset)
399 {
400 writel(NES_EEPROM_READ_REQUEST + (offset >> 1),
401 (void __iomem *)addr + NES_EEPROM_COMMAND);
402
403 do {
404 } while (readl((void __iomem *)addr + NES_EEPROM_COMMAND) &
405 NES_EEPROM_READ_REQUEST);
406
407 return readw((void __iomem *)addr + NES_EEPROM_DATA);
408 }
409
410
411 /**
412 * nes_write_1G_phy_reg
413 */
414 void nes_write_1G_phy_reg(struct nes_device *nesdev, u8 phy_reg, u8 phy_addr, u16 data)
415 {
416 u32 u32temp;
417 u32 counter;
418
419 nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
420 0x50020000 | data | ((u32)phy_reg << 18) | ((u32)phy_addr << 23));
421 for (counter = 0; counter < 100 ; counter++) {
422 udelay(30);
423 u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
424 if (u32temp & 1) {
425 /* nes_debug(NES_DBG_PHY, "Phy interrupt status = 0x%X.\n", u32temp); */
426 nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
427 break;
428 }
429 }
430 if (!(u32temp & 1))
431 nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
432 u32temp);
433 }
434
435
436 /**
437 * nes_read_1G_phy_reg
438 * This routine only issues the read, the data must be read
439 * separately.
440 */
441 void nes_read_1G_phy_reg(struct nes_device *nesdev, u8 phy_reg, u8 phy_addr, u16 *data)
442 {
443 u32 u32temp;
444 u32 counter;
445
446 /* nes_debug(NES_DBG_PHY, "phy addr = %d, mac_index = %d\n",
447 phy_addr, nesdev->mac_index); */
448
449 nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
450 0x60020000 | ((u32)phy_reg << 18) | ((u32)phy_addr << 23));
451 for (counter = 0; counter < 100 ; counter++) {
452 udelay(30);
453 u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
454 if (u32temp & 1) {
455 /* nes_debug(NES_DBG_PHY, "Phy interrupt status = 0x%X.\n", u32temp); */
456 nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
457 break;
458 }
459 }
460 if (!(u32temp & 1)) {
461 nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
462 u32temp);
463 *data = 0xffff;
464 } else {
465 *data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
466 }
467 }
468
469
470 /**
471 * nes_write_10G_phy_reg
472 */
473 void nes_write_10G_phy_reg(struct nes_device *nesdev, u16 phy_addr, u8 dev_addr, u16 phy_reg,
474 u16 data)
475 {
476 u32 port_addr;
477 u32 u32temp;
478 u32 counter;
479
480 port_addr = phy_addr;
481
482 /* set address */
483 nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
484 0x00020000 | (u32)phy_reg | (((u32)dev_addr) << 18) | (((u32)port_addr) << 23));
485 for (counter = 0; counter < 100 ; counter++) {
486 udelay(30);
487 u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
488 if (u32temp & 1) {
489 nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
490 break;
491 }
492 }
493 if (!(u32temp & 1))
494 nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
495 u32temp);
496
497 /* set data */
498 nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
499 0x10020000 | (u32)data | (((u32)dev_addr) << 18) | (((u32)port_addr) << 23));
500 for (counter = 0; counter < 100 ; counter++) {
501 udelay(30);
502 u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
503 if (u32temp & 1) {
504 nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
505 break;
506 }
507 }
508 if (!(u32temp & 1))
509 nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
510 u32temp);
511 }
512
513
514 /**
515 * nes_read_10G_phy_reg
516 * This routine only issues the read, the data must be read
517 * separately.
518 */
519 void nes_read_10G_phy_reg(struct nes_device *nesdev, u8 phy_addr, u8 dev_addr, u16 phy_reg)
520 {
521 u32 port_addr;
522 u32 u32temp;
523 u32 counter;
524
525 port_addr = phy_addr;
526
527 /* set address */
528 nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
529 0x00020000 | (u32)phy_reg | (((u32)dev_addr) << 18) | (((u32)port_addr) << 23));
530 for (counter = 0; counter < 100 ; counter++) {
531 udelay(30);
532 u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
533 if (u32temp & 1) {
534 nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
535 break;
536 }
537 }
538 if (!(u32temp & 1))
539 nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
540 u32temp);
541
542 /* issue read */
543 nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
544 0x30020000 | (((u32)dev_addr) << 18) | (((u32)port_addr) << 23));
545 for (counter = 0; counter < 100 ; counter++) {
546 udelay(30);
547 u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
548 if (u32temp & 1) {
549 nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
550 break;
551 }
552 }
553 if (!(u32temp & 1))
554 nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
555 u32temp);
556 }
557
558
559 /**
560 * nes_get_cqp_request
561 */
562 struct nes_cqp_request *nes_get_cqp_request(struct nes_device *nesdev)
563 {
564 unsigned long flags;
565 struct nes_cqp_request *cqp_request = NULL;
566
567 if (!list_empty(&nesdev->cqp_avail_reqs)) {
568 spin_lock_irqsave(&nesdev->cqp.lock, flags);
569 if (!list_empty(&nesdev->cqp_avail_reqs)) {
570 cqp_request = list_entry(nesdev->cqp_avail_reqs.next,
571 struct nes_cqp_request, list);
572 list_del_init(&cqp_request->list);
573 }
574 spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
575 }
576 if (cqp_request == NULL) {
577 cqp_request = kzalloc(sizeof(struct nes_cqp_request), GFP_ATOMIC);
578 if (cqp_request) {
579 cqp_request->dynamic = 1;
580 INIT_LIST_HEAD(&cqp_request->list);
581 }
582 }
583
584 if (cqp_request) {
585 init_waitqueue_head(&cqp_request->waitq);
586 cqp_request->waiting = 0;
587 cqp_request->request_done = 0;
588 cqp_request->callback = 0;
589 init_waitqueue_head(&cqp_request->waitq);
590 nes_debug(NES_DBG_CQP, "Got cqp request %p from the available list \n",
591 cqp_request);
592 } else
593 printk(KERN_ERR PFX "%s: Could not allocated a CQP request.\n",
594 __func__);
595
596 return cqp_request;
597 }
598
599 void nes_free_cqp_request(struct nes_device *nesdev,
600 struct nes_cqp_request *cqp_request)
601 {
602 unsigned long flags;
603
604 nes_debug(NES_DBG_CQP, "CQP request %p (opcode 0x%02X) freed.\n",
605 cqp_request,
606 le32_to_cpu(cqp_request->cqp_wqe.wqe_words[NES_CQP_WQE_OPCODE_IDX]) & 0x3f);
607
608 if (cqp_request->dynamic) {
609 kfree(cqp_request);
610 } else {
611 spin_lock_irqsave(&nesdev->cqp.lock, flags);
612 list_add_tail(&cqp_request->list, &nesdev->cqp_avail_reqs);
613 spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
614 }
615 }
616
617 void nes_put_cqp_request(struct nes_device *nesdev,
618 struct nes_cqp_request *cqp_request)
619 {
620 if (atomic_dec_and_test(&cqp_request->refcount))
621 nes_free_cqp_request(nesdev, cqp_request);
622 }
623
624
625 /**
626 * nes_post_cqp_request
627 */
628 void nes_post_cqp_request(struct nes_device *nesdev,
629 struct nes_cqp_request *cqp_request)
630 {
631 struct nes_hw_cqp_wqe *cqp_wqe;
632 unsigned long flags;
633 u32 cqp_head;
634 u64 u64temp;
635 u32 opcode;
636 int ctx_index = NES_CQP_WQE_COMP_CTX_LOW_IDX;
637
638 spin_lock_irqsave(&nesdev->cqp.lock, flags);
639
640 if (((((nesdev->cqp.sq_tail+(nesdev->cqp.sq_size*2))-nesdev->cqp.sq_head) &
641 (nesdev->cqp.sq_size - 1)) != 1)
642 && (list_empty(&nesdev->cqp_pending_reqs))) {
643 cqp_head = nesdev->cqp.sq_head++;
644 nesdev->cqp.sq_head &= nesdev->cqp.sq_size-1;
645 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
646 memcpy(cqp_wqe, &cqp_request->cqp_wqe, sizeof(*cqp_wqe));
647 opcode = le32_to_cpu(cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX]);
648 if ((opcode & NES_CQP_OPCODE_MASK) == NES_CQP_DOWNLOAD_SEGMENT)
649 ctx_index = NES_CQP_WQE_DL_COMP_CTX_LOW_IDX;
650 barrier();
651 u64temp = (unsigned long)cqp_request;
652 set_wqe_64bit_value(cqp_wqe->wqe_words, ctx_index, u64temp);
653 nes_debug(NES_DBG_CQP, "CQP request (opcode 0x%02X), line 1 = 0x%08X put on CQPs SQ,"
654 " request = %p, cqp_head = %u, cqp_tail = %u, cqp_size = %u,"
655 " waiting = %d, refcount = %d.\n",
656 opcode & NES_CQP_OPCODE_MASK,
657 le32_to_cpu(cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX]), cqp_request,
658 nesdev->cqp.sq_head, nesdev->cqp.sq_tail, nesdev->cqp.sq_size,
659 cqp_request->waiting, atomic_read(&cqp_request->refcount));
660
661 barrier();
662
663 /* Ring doorbell (1 WQEs) */
664 nes_write32(nesdev->regs+NES_WQE_ALLOC, 0x01800000 | nesdev->cqp.qp_id);
665
666 barrier();
667 } else {
668 nes_debug(NES_DBG_CQP, "CQP request %p (opcode 0x%02X), line 1 = 0x%08X"
669 " put on the pending queue.\n",
670 cqp_request,
671 le32_to_cpu(cqp_request->cqp_wqe.wqe_words[NES_CQP_WQE_OPCODE_IDX])&0x3f,
672 le32_to_cpu(cqp_request->cqp_wqe.wqe_words[NES_CQP_WQE_ID_IDX]));
673 list_add_tail(&cqp_request->list, &nesdev->cqp_pending_reqs);
674 }
675
676 spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
677
678 return;
679 }
680
681 /**
682 * nes_arp_table
683 */
684 int nes_arp_table(struct nes_device *nesdev, u32 ip_addr, u8 *mac_addr, u32 action)
685 {
686 struct nes_adapter *nesadapter = nesdev->nesadapter;
687 int arp_index;
688 int err = 0;
689 __be32 tmp_addr;
690
691 for (arp_index = 0; (u32) arp_index < nesadapter->arp_table_size; arp_index++) {
692 if (nesadapter->arp_table[arp_index].ip_addr == ip_addr)
693 break;
694 }
695
696 if (action == NES_ARP_ADD) {
697 if (arp_index != nesadapter->arp_table_size) {
698 return -1;
699 }
700
701 arp_index = 0;
702 err = nes_alloc_resource(nesadapter, nesadapter->allocated_arps,
703 nesadapter->arp_table_size, (u32 *)&arp_index, &nesadapter->next_arp_index, NES_RESOURCE_ARP);
704 if (err) {
705 nes_debug(NES_DBG_NETDEV, "nes_alloc_resource returned error = %u\n", err);
706 return err;
707 }
708 nes_debug(NES_DBG_NETDEV, "ADD, arp_index=%d\n", arp_index);
709
710 nesadapter->arp_table[arp_index].ip_addr = ip_addr;
711 memcpy(nesadapter->arp_table[arp_index].mac_addr, mac_addr, ETH_ALEN);
712 return arp_index;
713 }
714
715 /* DELETE or RESOLVE */
716 if (arp_index == nesadapter->arp_table_size) {
717 tmp_addr = cpu_to_be32(ip_addr);
718 nes_debug(NES_DBG_NETDEV, "MAC for %pI4 not in ARP table - cannot %s\n",
719 &tmp_addr, action == NES_ARP_RESOLVE ? "resolve" : "delete");
720 return -1;
721 }
722
723 if (action == NES_ARP_RESOLVE) {
724 nes_debug(NES_DBG_NETDEV, "RESOLVE, arp_index=%d\n", arp_index);
725 return arp_index;
726 }
727
728 if (action == NES_ARP_DELETE) {
729 nes_debug(NES_DBG_NETDEV, "DELETE, arp_index=%d\n", arp_index);
730 nesadapter->arp_table[arp_index].ip_addr = 0;
731 eth_zero_addr(nesadapter->arp_table[arp_index].mac_addr);
732 nes_free_resource(nesadapter, nesadapter->allocated_arps, arp_index);
733 return arp_index;
734 }
735
736 return -1;
737 }
738
739
740 /**
741 * nes_mh_fix
742 */
743 void nes_mh_fix(struct timer_list *t)
744 {
745 struct nes_adapter *nesadapter = from_timer(nesadapter, t, mh_timer);
746 struct nes_device *nesdev = nesadapter->nesdev;
747 unsigned long flags;
748 struct nes_vnic *nesvnic;
749 u32 used_chunks_tx;
750 u32 temp_used_chunks_tx;
751 u32 temp_last_used_chunks_tx;
752 u32 used_chunks_mask;
753 u32 mac_tx_frames_low;
754 u32 mac_tx_frames_high;
755 u32 mac_tx_pauses;
756 u32 reset_value;
757 u32 tx_control;
758 u32 tx_config;
759 u32 tx_pause_quanta;
760 u32 rx_control;
761 u32 rx_config;
762 u32 mac_exact_match;
763 u32 mpp_debug;
764 u32 i=0;
765 u32 chunks_tx_progress = 0;
766
767 spin_lock_irqsave(&nesadapter->phy_lock, flags);
768 if ((nesadapter->mac_sw_state[0] != NES_MAC_SW_IDLE) || (nesadapter->mac_link_down[0])) {
769 spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
770 goto no_mh_work;
771 }
772 nesadapter->mac_sw_state[0] = NES_MAC_SW_MH;
773 spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
774 do {
775 mac_tx_frames_low = nes_read_indexed(nesdev, NES_IDX_MAC_TX_FRAMES_LOW);
776 mac_tx_frames_high = nes_read_indexed(nesdev, NES_IDX_MAC_TX_FRAMES_HIGH);
777 mac_tx_pauses = nes_read_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_FRAMES);
778 used_chunks_tx = nes_read_indexed(nesdev, NES_IDX_USED_CHUNKS_TX);
779 nesdev->mac_pause_frames_sent += mac_tx_pauses;
780 used_chunks_mask = 0;
781 temp_used_chunks_tx = used_chunks_tx;
782 temp_last_used_chunks_tx = nesdev->last_used_chunks_tx;
783
784 if (nesdev->netdev[0]) {
785 nesvnic = netdev_priv(nesdev->netdev[0]);
786 } else {
787 break;
788 }
789
790 for (i=0; i<4; i++) {
791 used_chunks_mask <<= 8;
792 if (nesvnic->qp_nic_index[i] != 0xff) {
793 used_chunks_mask |= 0xff;
794 if ((temp_used_chunks_tx&0xff)<(temp_last_used_chunks_tx&0xff)) {
795 chunks_tx_progress = 1;
796 }
797 }
798 temp_used_chunks_tx >>= 8;
799 temp_last_used_chunks_tx >>= 8;
800 }
801 if ((mac_tx_frames_low) || (mac_tx_frames_high) ||
802 (!(used_chunks_tx&used_chunks_mask)) ||
803 (!(nesdev->last_used_chunks_tx&used_chunks_mask)) ||
804 (chunks_tx_progress) ) {
805 nesdev->last_used_chunks_tx = used_chunks_tx;
806 break;
807 }
808 nesdev->last_used_chunks_tx = used_chunks_tx;
809 barrier();
810
811 nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONTROL, 0x00000005);
812 mh_pauses_sent++;
813 mac_tx_pauses = nes_read_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_FRAMES);
814 if (mac_tx_pauses) {
815 nesdev->mac_pause_frames_sent += mac_tx_pauses;
816 break;
817 }
818
819 tx_control = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONTROL);
820 tx_config = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONFIG);
821 tx_pause_quanta = nes_read_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_QUANTA);
822 rx_control = nes_read_indexed(nesdev, NES_IDX_MAC_RX_CONTROL);
823 rx_config = nes_read_indexed(nesdev, NES_IDX_MAC_RX_CONFIG);
824 mac_exact_match = nes_read_indexed(nesdev, NES_IDX_MAC_EXACT_MATCH_BOTTOM);
825 mpp_debug = nes_read_indexed(nesdev, NES_IDX_MPP_DEBUG);
826
827 /* one last ditch effort to avoid a false positive */
828 mac_tx_pauses = nes_read_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_FRAMES);
829 if (mac_tx_pauses) {
830 nesdev->last_mac_tx_pauses = nesdev->mac_pause_frames_sent;
831 nes_debug(NES_DBG_HW, "failsafe caught slow outbound pause\n");
832 break;
833 }
834 mh_detected++;
835
836 nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONTROL, 0x00000000);
837 nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, 0x00000000);
838 reset_value = nes_read32(nesdev->regs+NES_SOFTWARE_RESET);
839
840 nes_write32(nesdev->regs+NES_SOFTWARE_RESET, reset_value | 0x0000001d);
841
842 while (((nes_read32(nesdev->regs+NES_SOFTWARE_RESET)
843 & 0x00000040) != 0x00000040) && (i++ < 5000)) {
844 /* mdelay(1); */
845 }
846
847 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0, 0x00000008);
848 nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS0);
849
850 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP0, 0x000bdef7);
851 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_DRIVE0, 0x9ce73000);
852 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_MODE0, 0x0ff00000);
853 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_SIGDET0, 0x00000000);
854 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_BYPASS0, 0x00000000);
855 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_LOOPBACK_CONTROL0, 0x00000000);
856 if (nesadapter->OneG_Mode) {
857 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_CONTROL0, 0xf0182222);
858 } else {
859 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_CONTROL0, 0xf0042222);
860 }
861 nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_STATUS0);
862 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000ff);
863
864 nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONTROL, tx_control);
865 nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, tx_config);
866 nes_write_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_QUANTA, tx_pause_quanta);
867 nes_write_indexed(nesdev, NES_IDX_MAC_RX_CONTROL, rx_control);
868 nes_write_indexed(nesdev, NES_IDX_MAC_RX_CONFIG, rx_config);
869 nes_write_indexed(nesdev, NES_IDX_MAC_EXACT_MATCH_BOTTOM, mac_exact_match);
870 nes_write_indexed(nesdev, NES_IDX_MPP_DEBUG, mpp_debug);
871
872 } while (0);
873
874 nesadapter->mac_sw_state[0] = NES_MAC_SW_IDLE;
875 no_mh_work:
876 nesdev->nesadapter->mh_timer.expires = jiffies + (HZ/5);
877 add_timer(&nesdev->nesadapter->mh_timer);
878 }
879
880 /**
881 * nes_clc
882 */
883 void nes_clc(struct timer_list *t)
884 {
885 struct nes_adapter *nesadapter = from_timer(nesadapter, t, lc_timer);
886 unsigned long flags;
887
888 spin_lock_irqsave(&nesadapter->phy_lock, flags);
889 nesadapter->link_interrupt_count[0] = 0;
890 nesadapter->link_interrupt_count[1] = 0;
891 nesadapter->link_interrupt_count[2] = 0;
892 nesadapter->link_interrupt_count[3] = 0;
893 spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
894
895 nesadapter->lc_timer.expires = jiffies + 3600 * HZ; /* 1 hour */
896 add_timer(&nesadapter->lc_timer);
897 }
898
899
900 /**
901 * nes_dump_mem
902 */
903 void nes_dump_mem(unsigned int dump_debug_level, void *addr, int length)
904 {
905 if (!(nes_debug_level & dump_debug_level)) {
906 return;
907 }
908
909 if (length > 0x100) {
910 nes_debug(dump_debug_level, "Length truncated from %x to %x\n", length, 0x100);
911 length = 0x100;
912 }
913 nes_debug(dump_debug_level, "Address=0x%p, length=0x%x (%d)\n", addr, length, length);
914
915 print_hex_dump(KERN_ERR, PFX, DUMP_PREFIX_NONE, 16, 1, addr, length, true);
916 }
CRIS linux kernel tree