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x86/topology: Update the 'cpu cores' field in /proc/cpuinfo correctly across CPU...
[cris-mirror.git] / drivers / tty / serial / 8250 / 8250_dw.c
blobcd1b94a0f451ca2d033dcf51ee55ce39be274ee6
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Synopsys DesignWare 8250 driver.
4 *
5 * Copyright 2011 Picochip, Jamie Iles.
6 * Copyright 2013 Intel Corporation
7 *
8 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
9 * LCR is written whilst busy. If it is, then a busy detect interrupt is
10 * raised, the LCR needs to be rewritten and the uart status register read.
11 */
12 #include <linux/device.h>
13 #include <linux/io.h>
14 #include <linux/module.h>
15 #include <linux/serial_8250.h>
16 #include <linux/serial_reg.h>
17 #include <linux/of.h>
18 #include <linux/of_irq.h>
19 #include <linux/of_platform.h>
20 #include <linux/platform_device.h>
21 #include <linux/slab.h>
22 #include <linux/acpi.h>
23 #include <linux/clk.h>
24 #include <linux/reset.h>
25 #include <linux/pm_runtime.h>
26
27 #include <asm/byteorder.h>
28
29 #include "8250.h"
30
31 /* Offsets for the DesignWare specific registers */
32 #define DW_UART_USR 0x1f /* UART Status Register */
33 #define DW_UART_CPR 0xf4 /* Component Parameter Register */
34 #define DW_UART_UCV 0xf8 /* UART Component Version */
35
36 /* Component Parameter Register bits */
37 #define DW_UART_CPR_ABP_DATA_WIDTH (3 << 0)
38 #define DW_UART_CPR_AFCE_MODE (1 << 4)
39 #define DW_UART_CPR_THRE_MODE (1 << 5)
40 #define DW_UART_CPR_SIR_MODE (1 << 6)
41 #define DW_UART_CPR_SIR_LP_MODE (1 << 7)
42 #define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8)
43 #define DW_UART_CPR_FIFO_ACCESS (1 << 9)
44 #define DW_UART_CPR_FIFO_STAT (1 << 10)
45 #define DW_UART_CPR_SHADOW (1 << 11)
46 #define DW_UART_CPR_ENCODED_PARMS (1 << 12)
47 #define DW_UART_CPR_DMA_EXTRA (1 << 13)
48 #define DW_UART_CPR_FIFO_MODE (0xff << 16)
49 /* Helper for fifo size calculation */
50 #define DW_UART_CPR_FIFO_SIZE(a) (((a >> 16) & 0xff) * 16)
51
52 /* DesignWare specific register fields */
53 #define DW_UART_MCR_SIRE BIT(6)
54
55 struct dw8250_data {
56 u8 usr_reg;
57 int line;
58 int msr_mask_on;
59 int msr_mask_off;
60 struct clk *clk;
61 struct clk *pclk;
62 struct reset_control *rst;
63 struct uart_8250_dma dma;
64
65 unsigned int skip_autocfg:1;
66 unsigned int uart_16550_compatible:1;
67 };
68
69 static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
70 {
71 struct dw8250_data *d = p->private_data;
72
73 /* Override any modem control signals if needed */
74 if (offset == UART_MSR) {
75 value |= d->msr_mask_on;
76 value &= ~d->msr_mask_off;
77 }
78
79 return value;
80 }
81
82 static void dw8250_force_idle(struct uart_port *p)
83 {
84 struct uart_8250_port *up = up_to_u8250p(p);
85
86 serial8250_clear_and_reinit_fifos(up);
87 (void)p->serial_in(p, UART_RX);
88 }
89
90 static void dw8250_check_lcr(struct uart_port *p, int value)
91 {
92 void __iomem *offset = p->membase + (UART_LCR << p->regshift);
93 int tries = 1000;
94
95 /* Make sure LCR write wasn't ignored */
96 while (tries--) {
97 unsigned int lcr = p->serial_in(p, UART_LCR);
98
99 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
100 return;
101
102 dw8250_force_idle(p);
103
104 #ifdef CONFIG_64BIT
105 if (p->type == PORT_OCTEON)
106 __raw_writeq(value & 0xff, offset);
107 else
108 #endif
109 if (p->iotype == UPIO_MEM32)
110 writel(value, offset);
111 else if (p->iotype == UPIO_MEM32BE)
112 iowrite32be(value, offset);
113 else
114 writeb(value, offset);
115 }
116 /*
117 * FIXME: this deadlocks if port->lock is already held
118 * dev_err(p->dev, "Couldn't set LCR to %d\n", value);
119 */
120 }
121
122 static void dw8250_serial_out(struct uart_port *p, int offset, int value)
123 {
124 struct dw8250_data *d = p->private_data;
125
126 writeb(value, p->membase + (offset << p->regshift));
127
128 if (offset == UART_LCR && !d->uart_16550_compatible)
129 dw8250_check_lcr(p, value);
130 }
131
132 static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
133 {
134 unsigned int value = readb(p->membase + (offset << p->regshift));
135
136 return dw8250_modify_msr(p, offset, value);
137 }
138
139 #ifdef CONFIG_64BIT
140 static unsigned int dw8250_serial_inq(struct uart_port *p, int offset)
141 {
142 unsigned int value;
143
144 value = (u8)__raw_readq(p->membase + (offset << p->regshift));
145
146 return dw8250_modify_msr(p, offset, value);
147 }
148
149 static void dw8250_serial_outq(struct uart_port *p, int offset, int value)
150 {
151 struct dw8250_data *d = p->private_data;
152
153 value &= 0xff;
154 __raw_writeq(value, p->membase + (offset << p->regshift));
155 /* Read back to ensure register write ordering. */
156 __raw_readq(p->membase + (UART_LCR << p->regshift));
157
158 if (offset == UART_LCR && !d->uart_16550_compatible)
159 dw8250_check_lcr(p, value);
160 }
161 #endif /* CONFIG_64BIT */
162
163 static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
164 {
165 struct dw8250_data *d = p->private_data;
166
167 writel(value, p->membase + (offset << p->regshift));
168
169 if (offset == UART_LCR && !d->uart_16550_compatible)
170 dw8250_check_lcr(p, value);
171 }
172
173 static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
174 {
175 unsigned int value = readl(p->membase + (offset << p->regshift));
176
177 return dw8250_modify_msr(p, offset, value);
178 }
179
180 static void dw8250_serial_out32be(struct uart_port *p, int offset, int value)
181 {
182 struct dw8250_data *d = p->private_data;
183
184 iowrite32be(value, p->membase + (offset << p->regshift));
185
186 if (offset == UART_LCR && !d->uart_16550_compatible)
187 dw8250_check_lcr(p, value);
188 }
189
190 static unsigned int dw8250_serial_in32be(struct uart_port *p, int offset)
191 {
192 unsigned int value = ioread32be(p->membase + (offset << p->regshift));
193
194 return dw8250_modify_msr(p, offset, value);
195 }
196
197
198 static int dw8250_handle_irq(struct uart_port *p)
199 {
200 struct uart_8250_port *up = up_to_u8250p(p);
201 struct dw8250_data *d = p->private_data;
202 unsigned int iir = p->serial_in(p, UART_IIR);
203 unsigned int status;
204 unsigned long flags;
205
206 /*
207 * There are ways to get Designware-based UARTs into a state where
208 * they are asserting UART_IIR_RX_TIMEOUT but there is no actual
209 * data available. If we see such a case then we'll do a bogus
210 * read. If we don't do this then the "RX TIMEOUT" interrupt will
211 * fire forever.
212 *
213 * This problem has only been observed so far when not in DMA mode
214 * so we limit the workaround only to non-DMA mode.
215 */
216 if (!up->dma && ((iir & 0x3f) == UART_IIR_RX_TIMEOUT)) {
217 spin_lock_irqsave(&p->lock, flags);
218 status = p->serial_in(p, UART_LSR);
219
220 if (!(status & (UART_LSR_DR | UART_LSR_BI)))
221 (void) p->serial_in(p, UART_RX);
222
223 spin_unlock_irqrestore(&p->lock, flags);
224 }
225
226 if (serial8250_handle_irq(p, iir))
227 return 1;
228
229 if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
230 /* Clear the USR */
231 (void)p->serial_in(p, d->usr_reg);
232
233 return 1;
234 }
235
236 return 0;
237 }
238
239 static void
240 dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
241 {
242 if (!state)
243 pm_runtime_get_sync(port->dev);
244
245 serial8250_do_pm(port, state, old);
246
247 if (state)
248 pm_runtime_put_sync_suspend(port->dev);
249 }
250
251 static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,
252 struct ktermios *old)
253 {
254 unsigned int baud = tty_termios_baud_rate(termios);
255 struct dw8250_data *d = p->private_data;
256 long rate;
257 int ret;
258
259 if (IS_ERR(d->clk) || !old)
260 goto out;
261
262 clk_disable_unprepare(d->clk);
263 rate = clk_round_rate(d->clk, baud * 16);
264 if (rate < 0)
265 ret = rate;
266 else if (rate == 0)
267 ret = -ENOENT;
268 else
269 ret = clk_set_rate(d->clk, rate);
270 clk_prepare_enable(d->clk);
271
272 if (!ret)
273 p->uartclk = rate;
274
275 out:
276 p->status &= ~UPSTAT_AUTOCTS;
277 if (termios->c_cflag & CRTSCTS)
278 p->status |= UPSTAT_AUTOCTS;
279
280 serial8250_do_set_termios(p, termios, old);
281 }
282
283 static void dw8250_set_ldisc(struct uart_port *p, struct ktermios *termios)
284 {
285 struct uart_8250_port *up = up_to_u8250p(p);
286 unsigned int mcr = p->serial_in(p, UART_MCR);
287
288 if (up->capabilities & UART_CAP_IRDA) {
289 if (termios->c_line == N_IRDA)
290 mcr |= DW_UART_MCR_SIRE;
291 else
292 mcr &= ~DW_UART_MCR_SIRE;
293
294 p->serial_out(p, UART_MCR, mcr);
295 }
296 serial8250_do_set_ldisc(p, termios);
297 }
298
299 /*
300 * dw8250_fallback_dma_filter will prevent the UART from getting just any free
301 * channel on platforms that have DMA engines, but don't have any channels
302 * assigned to the UART.
303 *
304 * REVISIT: This is a work around for limitation in the DMA Engine API. Once the
305 * core problem is fixed, this function is no longer needed.
306 */
307 static bool dw8250_fallback_dma_filter(struct dma_chan *chan, void *param)
308 {
309 return false;
310 }
311
312 static bool dw8250_idma_filter(struct dma_chan *chan, void *param)
313 {
314 return param == chan->device->dev->parent;
315 }
316
317 static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
318 {
319 if (p->dev->of_node) {
320 struct device_node *np = p->dev->of_node;
321 int id;
322
323 /* get index of serial line, if found in DT aliases */
324 id = of_alias_get_id(np, "serial");
325 if (id >= 0)
326 p->line = id;
327 #ifdef CONFIG_64BIT
328 if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) {
329 p->serial_in = dw8250_serial_inq;
330 p->serial_out = dw8250_serial_outq;
331 p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
332 p->type = PORT_OCTEON;
333 data->usr_reg = 0x27;
334 data->skip_autocfg = true;
335 }
336 #endif
337 if (of_device_is_big_endian(p->dev->of_node)) {
338 p->iotype = UPIO_MEM32BE;
339 p->serial_in = dw8250_serial_in32be;
340 p->serial_out = dw8250_serial_out32be;
341 }
342 } else if (has_acpi_companion(p->dev)) {
343 const struct acpi_device_id *id;
344
345 id = acpi_match_device(p->dev->driver->acpi_match_table,
346 p->dev);
347 if (id && !strcmp(id->id, "APMC0D08")) {
348 p->iotype = UPIO_MEM32;
349 p->regshift = 2;
350 p->serial_in = dw8250_serial_in32;
351 data->uart_16550_compatible = true;
352 }
353 }
354
355 /* Platforms with iDMA */
356 if (platform_get_resource_byname(to_platform_device(p->dev),
357 IORESOURCE_MEM, "lpss_priv")) {
358 data->dma.rx_param = p->dev->parent;
359 data->dma.tx_param = p->dev->parent;
360 data->dma.fn = dw8250_idma_filter;
361 }
362 }
363
364 static void dw8250_setup_port(struct uart_port *p)
365 {
366 struct uart_8250_port *up = up_to_u8250p(p);
367 u32 reg;
368
369 /*
370 * If the Component Version Register returns zero, we know that
371 * ADDITIONAL_FEATURES are not enabled. No need to go any further.
372 */
373 if (p->iotype == UPIO_MEM32BE)
374 reg = ioread32be(p->membase + DW_UART_UCV);
375 else
376 reg = readl(p->membase + DW_UART_UCV);
377 if (!reg)
378 return;
379
380 dev_dbg(p->dev, "Designware UART version %c.%c%c\n",
381 (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
382
383 if (p->iotype == UPIO_MEM32BE)
384 reg = ioread32be(p->membase + DW_UART_CPR);
385 else
386 reg = readl(p->membase + DW_UART_CPR);
387 if (!reg)
388 return;
389
390 /* Select the type based on fifo */
391 if (reg & DW_UART_CPR_FIFO_MODE) {
392 p->type = PORT_16550A;
393 p->flags |= UPF_FIXED_TYPE;
394 p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
395 up->capabilities = UART_CAP_FIFO;
396 }
397
398 if (reg & DW_UART_CPR_AFCE_MODE)
399 up->capabilities |= UART_CAP_AFE;
400
401 if (reg & DW_UART_CPR_SIR_MODE)
402 up->capabilities |= UART_CAP_IRDA;
403 }
404
405 static int dw8250_probe(struct platform_device *pdev)
406 {
407 struct uart_8250_port uart = {};
408 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
409 int irq = platform_get_irq(pdev, 0);
410 struct uart_port *p = &uart.port;
411 struct device *dev = &pdev->dev;
412 struct dw8250_data *data;
413 int err;
414 u32 val;
415
416 if (!regs) {
417 dev_err(dev, "no registers defined\n");
418 return -EINVAL;
419 }
420
421 if (irq < 0) {
422 if (irq != -EPROBE_DEFER)
423 dev_err(dev, "cannot get irq\n");
424 return irq;
425 }
426
427 spin_lock_init(&p->lock);
428 p->mapbase = regs->start;
429 p->irq = irq;
430 p->handle_irq = dw8250_handle_irq;
431 p->pm = dw8250_do_pm;
432 p->type = PORT_8250;
433 p->flags = UPF_SHARE_IRQ | UPF_FIXED_PORT;
434 p->dev = dev;
435 p->iotype = UPIO_MEM;
436 p->serial_in = dw8250_serial_in;
437 p->serial_out = dw8250_serial_out;
438 p->set_ldisc = dw8250_set_ldisc;
439 p->set_termios = dw8250_set_termios;
440
441 p->membase = devm_ioremap(dev, regs->start, resource_size(regs));
442 if (!p->membase)
443 return -ENOMEM;
444
445 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
446 if (!data)
447 return -ENOMEM;
448
449 data->dma.fn = dw8250_fallback_dma_filter;
450 data->usr_reg = DW_UART_USR;
451 p->private_data = data;
452
453 data->uart_16550_compatible = device_property_read_bool(dev,
454 "snps,uart-16550-compatible");
455
456 err = device_property_read_u32(dev, "reg-shift", &val);
457 if (!err)
458 p->regshift = val;
459
460 err = device_property_read_u32(dev, "reg-io-width", &val);
461 if (!err && val == 4) {
462 p->iotype = UPIO_MEM32;
463 p->serial_in = dw8250_serial_in32;
464 p->serial_out = dw8250_serial_out32;
465 }
466
467 if (device_property_read_bool(dev, "dcd-override")) {
468 /* Always report DCD as active */
469 data->msr_mask_on |= UART_MSR_DCD;
470 data->msr_mask_off |= UART_MSR_DDCD;
471 }
472
473 if (device_property_read_bool(dev, "dsr-override")) {
474 /* Always report DSR as active */
475 data->msr_mask_on |= UART_MSR_DSR;
476 data->msr_mask_off |= UART_MSR_DDSR;
477 }
478
479 if (device_property_read_bool(dev, "cts-override")) {
480 /* Always report CTS as active */
481 data->msr_mask_on |= UART_MSR_CTS;
482 data->msr_mask_off |= UART_MSR_DCTS;
483 }
484
485 if (device_property_read_bool(dev, "ri-override")) {
486 /* Always report Ring indicator as inactive */
487 data->msr_mask_off |= UART_MSR_RI;
488 data->msr_mask_off |= UART_MSR_TERI;
489 }
490
491 /* Always ask for fixed clock rate from a property. */
492 device_property_read_u32(dev, "clock-frequency", &p->uartclk);
493
494 /* If there is separate baudclk, get the rate from it. */
495 data->clk = devm_clk_get(dev, "baudclk");
496 if (IS_ERR(data->clk) && PTR_ERR(data->clk) != -EPROBE_DEFER)
497 data->clk = devm_clk_get(dev, NULL);
498 if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER)
499 return -EPROBE_DEFER;
500 if (!IS_ERR_OR_NULL(data->clk)) {
501 err = clk_prepare_enable(data->clk);
502 if (err)
503 dev_warn(dev, "could not enable optional baudclk: %d\n",
504 err);
505 else
506 p->uartclk = clk_get_rate(data->clk);
507 }
508
509 /* If no clock rate is defined, fail. */
510 if (!p->uartclk) {
511 dev_err(dev, "clock rate not defined\n");
512 err = -EINVAL;
513 goto err_clk;
514 }
515
516 data->pclk = devm_clk_get(dev, "apb_pclk");
517 if (IS_ERR(data->pclk) && PTR_ERR(data->pclk) == -EPROBE_DEFER) {
518 err = -EPROBE_DEFER;
519 goto err_clk;
520 }
521 if (!IS_ERR(data->pclk)) {
522 err = clk_prepare_enable(data->pclk);
523 if (err) {
524 dev_err(dev, "could not enable apb_pclk\n");
525 goto err_clk;
526 }
527 }
528
529 data->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
530 if (IS_ERR(data->rst)) {
531 err = PTR_ERR(data->rst);
532 goto err_pclk;
533 }
534 reset_control_deassert(data->rst);
535
536 dw8250_quirks(p, data);
537
538 /* If the Busy Functionality is not implemented, don't handle it */
539 if (data->uart_16550_compatible)
540 p->handle_irq = NULL;
541
542 if (!data->skip_autocfg)
543 dw8250_setup_port(p);
544
545 /* If we have a valid fifosize, try hooking up DMA */
546 if (p->fifosize) {
547 data->dma.rxconf.src_maxburst = p->fifosize / 4;
548 data->dma.txconf.dst_maxburst = p->fifosize / 4;
549 uart.dma = &data->dma;
550 }
551
552 data->line = serial8250_register_8250_port(&uart);
553 if (data->line < 0) {
554 err = data->line;
555 goto err_reset;
556 }
557
558 platform_set_drvdata(pdev, data);
559
560 pm_runtime_set_active(dev);
561 pm_runtime_enable(dev);
562
563 return 0;
564
565 err_reset:
566 reset_control_assert(data->rst);
567
568 err_pclk:
569 if (!IS_ERR(data->pclk))
570 clk_disable_unprepare(data->pclk);
571
572 err_clk:
573 if (!IS_ERR(data->clk))
574 clk_disable_unprepare(data->clk);
575
576 return err;
577 }
578
579 static int dw8250_remove(struct platform_device *pdev)
580 {
581 struct dw8250_data *data = platform_get_drvdata(pdev);
582
583 pm_runtime_get_sync(&pdev->dev);
584
585 serial8250_unregister_port(data->line);
586
587 reset_control_assert(data->rst);
588
589 if (!IS_ERR(data->pclk))
590 clk_disable_unprepare(data->pclk);
591
592 if (!IS_ERR(data->clk))
593 clk_disable_unprepare(data->clk);
594
595 pm_runtime_disable(&pdev->dev);
596 pm_runtime_put_noidle(&pdev->dev);
597
598 return 0;
599 }
600
601 #ifdef CONFIG_PM_SLEEP
602 static int dw8250_suspend(struct device *dev)
603 {
604 struct dw8250_data *data = dev_get_drvdata(dev);
605
606 serial8250_suspend_port(data->line);
607
608 return 0;
609 }
610
611 static int dw8250_resume(struct device *dev)
612 {
613 struct dw8250_data *data = dev_get_drvdata(dev);
614
615 serial8250_resume_port(data->line);
616
617 return 0;
618 }
619 #endif /* CONFIG_PM_SLEEP */
620
621 #ifdef CONFIG_PM
622 static int dw8250_runtime_suspend(struct device *dev)
623 {
624 struct dw8250_data *data = dev_get_drvdata(dev);
625
626 if (!IS_ERR(data->clk))
627 clk_disable_unprepare(data->clk);
628
629 if (!IS_ERR(data->pclk))
630 clk_disable_unprepare(data->pclk);
631
632 return 0;
633 }
634
635 static int dw8250_runtime_resume(struct device *dev)
636 {
637 struct dw8250_data *data = dev_get_drvdata(dev);
638
639 if (!IS_ERR(data->pclk))
640 clk_prepare_enable(data->pclk);
641
642 if (!IS_ERR(data->clk))
643 clk_prepare_enable(data->clk);
644
645 return 0;
646 }
647 #endif
648
649 static const struct dev_pm_ops dw8250_pm_ops = {
650 SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)
651 SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
652 };
653
654 static const struct of_device_id dw8250_of_match[] = {
655 { .compatible = "snps,dw-apb-uart" },
656 { .compatible = "cavium,octeon-3860-uart" },
657 { /* Sentinel */ }
658 };
659 MODULE_DEVICE_TABLE(of, dw8250_of_match);
660
661 static const struct acpi_device_id dw8250_acpi_match[] = {
662 { "INT33C4", 0 },
663 { "INT33C5", 0 },
664 { "INT3434", 0 },
665 { "INT3435", 0 },
666 { "80860F0A", 0 },
667 { "8086228A", 0 },
668 { "APMC0D08", 0},
669 { "AMD0020", 0 },
670 { "AMDI0020", 0 },
671 { "HISI0031", 0 },
672 { },
673 };
674 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
675
676 static struct platform_driver dw8250_platform_driver = {
677 .driver = {
678 .name = "dw-apb-uart",
679 .pm = &dw8250_pm_ops,
680 .of_match_table = dw8250_of_match,
681 .acpi_match_table = ACPI_PTR(dw8250_acpi_match),
682 },
683 .probe = dw8250_probe,
684 .remove = dw8250_remove,
685 };
686
687 module_platform_driver(dw8250_platform_driver);
688
689 MODULE_AUTHOR("Jamie Iles");
690 MODULE_LICENSE("GPL");
691 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");
692 MODULE_ALIAS("platform:dw-apb-uart");
CRIS linux kernel tree