drivers/tty/serial/8250/8250_fintek.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *  Probe for F81216A LPC to 4 UART
   4  *
   5  *  Copyright (C) 2014-2016 Ricardo Ribalda, Qtechnology A/S
   6  */
   7 #include <linux/module.h>
   8 #include <linux/pci.h>
   9 #include <linux/pnp.h>
  10 #include <linux/kernel.h>
  11 #include <linux/serial_core.h>
  12 #include <linux/irq.h>
  13 #include  "8250.h"
  14
  15 #define ADDR_PORT 0
  16 #define DATA_PORT 1
  17 #define EXIT_KEY 0xAA
  18 #define CHIP_ID1  0x20
  19 #define CHIP_ID2  0x21
  20 #define CHIP_ID_F81865 0x0407
  21 #define CHIP_ID_F81866 0x1010
  22 #define CHIP_ID_F81216AD 0x1602
  23 #define CHIP_ID_F81216H 0x0501
  24 #define CHIP_ID_F81216 0x0802
  25 #define VENDOR_ID1 0x23
  26 #define VENDOR_ID1_VAL 0x19
  27 #define VENDOR_ID2 0x24
  28 #define VENDOR_ID2_VAL 0x34
  29 #define IO_ADDR1 0x61
  30 #define IO_ADDR2 0x60
  31 #define LDN 0x7
  32
  33 #define FINTEK_IRQ_MODE 0x70
  34 #define IRQ_SHARE       BIT(4)
  35 #define IRQ_MODE_MASK   (BIT(6) | BIT(5))
  36 #define IRQ_LEVEL_LOW   0
  37 #define IRQ_EDGE_HIGH   BIT(5)
  38
  39 /*
  40  * F81216H clock source register, the value and mask is the same with F81866,
  41  * but it's on F0h.
  42  *
  43  * Clock speeds for UART (register F0h)
  44  * 00: 1.8432MHz.
  45  * 01: 18.432MHz.
  46  * 10: 24MHz.
  47  * 11: 14.769MHz.
  48  */
  49 #define RS485  0xF0
  50 #define RTS_INVERT BIT(5)
  51 #define RS485_URA BIT(4)
  52 #define RXW4C_IRA BIT(3)
  53 #define TXW4C_IRA BIT(2)
  54
  55 #define FIFO_CTRL               0xF6
  56 #define FIFO_MODE_MASK          (BIT(1) | BIT(0))
  57 #define FIFO_MODE_128           (BIT(1) | BIT(0))
  58 #define RXFTHR_MODE_MASK        (BIT(5) | BIT(4))
  59 #define RXFTHR_MODE_4X          BIT(5)
  60
  61 #define F81216_LDN_LOW  0x0
  62 #define F81216_LDN_HIGH 0x4
  63
  64 /*
  65  * F81866 registers
  66  *
  67  * The IRQ setting mode of F81866 is not the same with F81216 series.
  68  *      Level/Low: IRQ_MODE0:0, IRQ_MODE1:0
  69  *      Edge/High: IRQ_MODE0:1, IRQ_MODE1:0
  70  *
  71  * Clock speeds for UART (register F2h)
  72  * 00: 1.8432MHz.
  73  * 01: 18.432MHz.
  74  * 10: 24MHz.
  75  * 11: 14.769MHz.
  76  */
  77 #define F81866_IRQ_MODE         0xf0
  78 #define F81866_IRQ_SHARE        BIT(0)
  79 #define F81866_IRQ_MODE0        BIT(1)
  80
  81 #define F81866_FIFO_CTRL        FIFO_CTRL
  82 #define F81866_IRQ_MODE1        BIT(3)
  83
  84 #define F81866_LDN_LOW          0x10
  85 #define F81866_LDN_HIGH         0x16
  86
  87 #define F81866_UART_CLK 0xF2
  88 #define F81866_UART_CLK_MASK (BIT(1) | BIT(0))
  89 #define F81866_UART_CLK_1_8432MHZ 0
  90 #define F81866_UART_CLK_14_769MHZ (BIT(1) | BIT(0))
  91 #define F81866_UART_CLK_18_432MHZ BIT(0)
  92 #define F81866_UART_CLK_24MHZ BIT(1)
  93
  94 struct fintek_8250 {
  95         u16 pid;
  96         u16 base_port;
  97         u8 index;
  98         u8 key;
  99 };
 100
 101 static u8 sio_read_reg(struct fintek_8250 *pdata, u8 reg)
 102 {
 103         outb(reg, pdata->base_port + ADDR_PORT);
 104         return inb(pdata->base_port + DATA_PORT);
 105 }
 106
 107 static void sio_write_reg(struct fintek_8250 *pdata, u8 reg, u8 data)
 108 {
 109         outb(reg, pdata->base_port + ADDR_PORT);
 110         outb(data, pdata->base_port + DATA_PORT);
 111 }
 112
 113 static void sio_write_mask_reg(struct fintek_8250 *pdata, u8 reg, u8 mask,
 114                                u8 data)
 115 {
 116         u8 tmp;
 117
 118         tmp = (sio_read_reg(pdata, reg) & ~mask) | (mask & data);
 119         sio_write_reg(pdata, reg, tmp);
 120 }
 121
 122 static int fintek_8250_enter_key(u16 base_port, u8 key)
 123 {
 124         if (!request_muxed_region(base_port, 2, "8250_fintek"))
 125                 return -EBUSY;
 126
 127         /* Force to deactive all SuperIO in this base_port */
 128         outb(EXIT_KEY, base_port + ADDR_PORT);
 129
 130         outb(key, base_port + ADDR_PORT);
 131         outb(key, base_port + ADDR_PORT);
 132         return 0;
 133 }
 134
 135 static void fintek_8250_exit_key(u16 base_port)
 136 {
 137
 138         outb(EXIT_KEY, base_port + ADDR_PORT);
 139         release_region(base_port + ADDR_PORT, 2);
 140 }
 141
 142 static int fintek_8250_check_id(struct fintek_8250 *pdata)
 143 {
 144         u16 chip;
 145
 146         if (sio_read_reg(pdata, VENDOR_ID1) != VENDOR_ID1_VAL)
 147                 return -ENODEV;
 148
 149         if (sio_read_reg(pdata, VENDOR_ID2) != VENDOR_ID2_VAL)
 150                 return -ENODEV;
 151
 152         chip = sio_read_reg(pdata, CHIP_ID1);
 153         chip |= sio_read_reg(pdata, CHIP_ID2) << 8;
 154
 155         switch (chip) {
 156         case CHIP_ID_F81865:
 157         case CHIP_ID_F81866:
 158         case CHIP_ID_F81216AD:
 159         case CHIP_ID_F81216H:
 160         case CHIP_ID_F81216:
 161                 break;
 162         default:
 163                 return -ENODEV;
 164         }
 165
 166         pdata->pid = chip;
 167         return 0;
 168 }
 169
 170 static int fintek_8250_get_ldn_range(struct fintek_8250 *pdata, int *min,
 171                                      int *max)
 172 {
 173         switch (pdata->pid) {
 174         case CHIP_ID_F81865:
 175         case CHIP_ID_F81866:
 176                 *min = F81866_LDN_LOW;
 177                 *max = F81866_LDN_HIGH;
 178                 return 0;
 179
 180         case CHIP_ID_F81216AD:
 181         case CHIP_ID_F81216H:
 182         case CHIP_ID_F81216:
 183                 *min = F81216_LDN_LOW;
 184                 *max = F81216_LDN_HIGH;
 185                 return 0;
 186         }
 187
 188         return -ENODEV;
 189 }
 190
 191 static int fintek_8250_rs485_config(struct uart_port *port,
 192                               struct serial_rs485 *rs485)
 193 {
 194         uint8_t config = 0;
 195         struct fintek_8250 *pdata = port->private_data;
 196
 197         if (!pdata)
 198                 return -EINVAL;
 199
 200         /* Hardware do not support same RTS level on send and receive */
 201         if (!(rs485->flags & SER_RS485_RTS_ON_SEND) ==
 202                         !(rs485->flags & SER_RS485_RTS_AFTER_SEND))
 203                 return -EINVAL;
 204
 205         if (rs485->flags & SER_RS485_ENABLED) {
 206                 memset(rs485->padding, 0, sizeof(rs485->padding));
 207                 config |= RS485_URA;
 208         } else {
 209                 memset(rs485, 0, sizeof(*rs485));
 210         }
 211
 212         rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND |
 213                         SER_RS485_RTS_AFTER_SEND;
 214
 215         /* Only the first port supports delays */
 216         if (pdata->index) {
 217                 rs485->delay_rts_before_send = 0;
 218                 rs485->delay_rts_after_send = 0;
 219         }
 220
 221         if (rs485->delay_rts_before_send) {
 222                 rs485->delay_rts_before_send = 1;
 223                 config |= TXW4C_IRA;
 224         }
 225
 226         if (rs485->delay_rts_after_send) {
 227                 rs485->delay_rts_after_send = 1;
 228                 config |= RXW4C_IRA;
 229         }
 230
 231         if (rs485->flags & SER_RS485_RTS_ON_SEND)
 232                 config |= RTS_INVERT;
 233
 234         if (fintek_8250_enter_key(pdata->base_port, pdata->key))
 235                 return -EBUSY;
 236
 237         sio_write_reg(pdata, LDN, pdata->index);
 238         sio_write_reg(pdata, RS485, config);
 239         fintek_8250_exit_key(pdata->base_port);
 240
 241         port->rs485 = *rs485;
 242
 243         return 0;
 244 }
 245
 246 static void fintek_8250_set_irq_mode(struct fintek_8250 *pdata, bool is_level)
 247 {
 248         sio_write_reg(pdata, LDN, pdata->index);
 249
 250         switch (pdata->pid) {
 251         case CHIP_ID_F81866:
 252                 sio_write_mask_reg(pdata, F81866_FIFO_CTRL, F81866_IRQ_MODE1,
 253                                    0);
 254                 /* fall through */
 255         case CHIP_ID_F81865:
 256                 sio_write_mask_reg(pdata, F81866_IRQ_MODE, F81866_IRQ_SHARE,
 257                                    F81866_IRQ_SHARE);
 258                 sio_write_mask_reg(pdata, F81866_IRQ_MODE, F81866_IRQ_MODE0,
 259                                    is_level ? 0 : F81866_IRQ_MODE0);
 260                 break;
 261
 262         case CHIP_ID_F81216AD:
 263         case CHIP_ID_F81216H:
 264         case CHIP_ID_F81216:
 265                 sio_write_mask_reg(pdata, FINTEK_IRQ_MODE, IRQ_SHARE,
 266                                    IRQ_SHARE);
 267                 sio_write_mask_reg(pdata, FINTEK_IRQ_MODE, IRQ_MODE_MASK,
 268                                    is_level ? IRQ_LEVEL_LOW : IRQ_EDGE_HIGH);
 269                 break;
 270         }
 271 }
 272
 273 static void fintek_8250_set_max_fifo(struct fintek_8250 *pdata)
 274 {
 275         switch (pdata->pid) {
 276         case CHIP_ID_F81216H: /* 128Bytes FIFO */
 277         case CHIP_ID_F81866:
 278                 sio_write_mask_reg(pdata, FIFO_CTRL,
 279                                    FIFO_MODE_MASK | RXFTHR_MODE_MASK,
 280                                    FIFO_MODE_128 | RXFTHR_MODE_4X);
 281                 break;
 282
 283         default: /* Default 16Bytes FIFO */
 284                 break;
 285         }
 286 }
 287
 288 static void fintek_8250_goto_highspeed(struct uart_8250_port *uart,
 289                               struct fintek_8250 *pdata)
 290 {
 291         sio_write_reg(pdata, LDN, pdata->index);
 292
 293         switch (pdata->pid) {
 294         case CHIP_ID_F81866: /* set uart clock for high speed serial mode */
 295                 sio_write_mask_reg(pdata, F81866_UART_CLK,
 296                         F81866_UART_CLK_MASK,
 297                         F81866_UART_CLK_14_769MHZ);
 298
 299                 uart->port.uartclk = 921600 * 16;
 300                 break;
 301         default: /* leave clock speed untouched */
 302                 break;
 303         }
 304 }
 305
 306 void fintek_8250_set_termios(struct uart_port *port, struct ktermios *termios,
 307                         struct ktermios *old)
 308 {
 309         struct fintek_8250 *pdata = port->private_data;
 310         unsigned int baud = tty_termios_baud_rate(termios);
 311         int i;
 312         u8 reg;
 313         static u32 baudrate_table[] = {115200, 921600, 1152000, 1500000};
 314         static u8 clock_table[] = { F81866_UART_CLK_1_8432MHZ,
 315                         F81866_UART_CLK_14_769MHZ, F81866_UART_CLK_18_432MHZ,
 316                         F81866_UART_CLK_24MHZ };
 317
 318         /*
 319          * We'll use serial8250_do_set_termios() for baud = 0, otherwise It'll
 320          * crash on baudrate_table[i] % baud with "division by zero".
 321          */
 322         if (!baud)
 323                 goto exit;
 324
 325         switch (pdata->pid) {
 326         case CHIP_ID_F81216H:
 327                 reg = RS485;
 328                 break;
 329         case CHIP_ID_F81866:
 330                 reg = F81866_UART_CLK;
 331                 break;
 332         default:
 333                 /* Don't change clocksource with unknown PID */
 334                 dev_warn(port->dev,
 335                         "%s: pid: %x Not support. use default set_termios.\n",
 336                         __func__, pdata->pid);
 337                 goto exit;
 338         }
 339
 340         for (i = 0; i < ARRAY_SIZE(baudrate_table); ++i) {
 341                 if (baud > baudrate_table[i] || baudrate_table[i] % baud != 0)
 342                         continue;
 343
 344                 if (port->uartclk == baudrate_table[i] * 16)
 345                         break;
 346
 347                 if (fintek_8250_enter_key(pdata->base_port, pdata->key))
 348                         continue;
 349
 350                 port->uartclk = baudrate_table[i] * 16;
 351
 352                 sio_write_reg(pdata, LDN, pdata->index);
 353                 sio_write_mask_reg(pdata, reg, F81866_UART_CLK_MASK,
 354                                 clock_table[i]);
 355
 356                 fintek_8250_exit_key(pdata->base_port);
 357                 break;
 358         }
 359
 360         if (i == ARRAY_SIZE(baudrate_table)) {
 361                 baud = tty_termios_baud_rate(old);
 362                 tty_termios_encode_baud_rate(termios, baud, baud);
 363         }
 364
 365 exit:
 366         serial8250_do_set_termios(port, termios, old);
 367 }
 368
 369 static void fintek_8250_set_termios_handler(struct uart_8250_port *uart)
 370 {
 371         struct fintek_8250 *pdata = uart->port.private_data;
 372
 373         switch (pdata->pid) {
 374         case CHIP_ID_F81216H:
 375         case CHIP_ID_F81866:
 376                 uart->port.set_termios = fintek_8250_set_termios;
 377                 break;
 378
 379         default:
 380                 break;
 381         }
 382 }
 383
 384 static int probe_setup_port(struct fintek_8250 *pdata,
 385                                         struct uart_8250_port *uart)
 386 {
 387         static const u16 addr[] = {0x4e, 0x2e};
 388         static const u8 keys[] = {0x77, 0xa0, 0x87, 0x67};
 389         struct irq_data *irq_data;
 390         bool level_mode = false;
 391         int i, j, k, min, max;
 392
 393         for (i = 0; i < ARRAY_SIZE(addr); i++) {
 394                 for (j = 0; j < ARRAY_SIZE(keys); j++) {
 395                         pdata->base_port = addr[i];
 396                         pdata->key = keys[j];
 397
 398                         if (fintek_8250_enter_key(addr[i], keys[j]))
 399                                 continue;
 400                         if (fintek_8250_check_id(pdata) ||
 401                             fintek_8250_get_ldn_range(pdata, &min, &max)) {
 402                                 fintek_8250_exit_key(addr[i]);
 403                                 continue;
 404                         }
 405
 406                         for (k = min; k < max; k++) {
 407                                 u16 aux;
 408
 409                                 sio_write_reg(pdata, LDN, k);
 410                                 aux = sio_read_reg(pdata, IO_ADDR1);
 411                                 aux |= sio_read_reg(pdata, IO_ADDR2) << 8;
 412                                 if (aux != uart->port.iobase)
 413                                         continue;
 414
 415                                 pdata->index = k;
 416
 417                                 irq_data = irq_get_irq_data(uart->port.irq);
 418                                 if (irq_data)
 419                                         level_mode =
 420                                                 irqd_is_level_type(irq_data);
 421
 422                                 fintek_8250_set_irq_mode(pdata, level_mode);
 423                                 fintek_8250_set_max_fifo(pdata);
 424                                 fintek_8250_goto_highspeed(uart, pdata);
 425
 426                                 fintek_8250_exit_key(addr[i]);
 427
 428                                 return 0;
 429                         }
 430
 431                         fintek_8250_exit_key(addr[i]);
 432                 }
 433         }
 434
 435         return -ENODEV;
 436 }
 437
 438 static void fintek_8250_set_rs485_handler(struct uart_8250_port *uart)
 439 {
 440         struct fintek_8250 *pdata = uart->port.private_data;
 441
 442         switch (pdata->pid) {
 443         case CHIP_ID_F81216AD:
 444         case CHIP_ID_F81216H:
 445         case CHIP_ID_F81866:
 446         case CHIP_ID_F81865:
 447                 uart->port.rs485_config = fintek_8250_rs485_config;
 448                 break;
 449
 450         default: /* No RS485 Auto direction functional */
 451                 break;
 452         }
 453 }
 454
 455 int fintek_8250_probe(struct uart_8250_port *uart)
 456 {
 457         struct fintek_8250 *pdata;
 458         struct fintek_8250 probe_data;
 459
 460         if (probe_setup_port(&probe_data, uart))
 461                 return -ENODEV;
 462
 463         pdata = devm_kzalloc(uart->port.dev, sizeof(*pdata), GFP_KERNEL);
 464         if (!pdata)
 465                 return -ENOMEM;
 466
 467         memcpy(pdata, &probe_data, sizeof(probe_data));
 468         uart->port.private_data = pdata;
 469         fintek_8250_set_rs485_handler(uart);
 470         fintek_8250_set_termios_handler(uart);
 471
 472         return 0;
 473 }