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x86/topology: Update the 'cpu cores' field in /proc/cpuinfo correctly across CPU...
[cris-mirror.git] / drivers / tty / serial / 8250 / 8250_omap.c
blob57f6eba47f4419b88453e1415e2b674102fc94d6
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * 8250-core based driver for the OMAP internal UART
4 *
5 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments.
6 *
7 * Copyright (C) 2014 Sebastian Andrzej Siewior
8 *
9 */
10
11 #include <linux/device.h>
12 #include <linux/io.h>
13 #include <linux/module.h>
14 #include <linux/serial_8250.h>
15 #include <linux/serial_reg.h>
16 #include <linux/tty_flip.h>
17 #include <linux/platform_device.h>
18 #include <linux/slab.h>
19 #include <linux/of.h>
20 #include <linux/of_device.h>
21 #include <linux/of_gpio.h>
22 #include <linux/of_irq.h>
23 #include <linux/delay.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/console.h>
26 #include <linux/pm_qos.h>
27 #include <linux/pm_wakeirq.h>
28 #include <linux/dma-mapping.h>
29
30 #include "8250.h"
31
32 #define DEFAULT_CLK_SPEED 48000000
33
34 #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0)
35 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1)
36 #define OMAP_DMA_TX_KICK (1 << 2)
37 /*
38 * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015.
39 * The same errata is applicable to AM335x and DRA7x processors too.
40 */
41 #define UART_ERRATA_CLOCK_DISABLE (1 << 3)
42
43 #define OMAP_UART_FCR_RX_TRIG 6
44 #define OMAP_UART_FCR_TX_TRIG 4
45
46 /* SCR register bitmasks */
47 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
48 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
49 #define OMAP_UART_SCR_TX_EMPTY (1 << 3)
50 #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1)
51 #define OMAP_UART_SCR_DMAMODE_1 (1 << 1)
52 #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0)
53
54 /* MVR register bitmasks */
55 #define OMAP_UART_MVR_SCHEME_SHIFT 30
56 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
57 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
58 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
59 #define OMAP_UART_MVR_MAJ_MASK 0x700
60 #define OMAP_UART_MVR_MAJ_SHIFT 8
61 #define OMAP_UART_MVR_MIN_MASK 0x3f
62
63 /* SYSC register bitmasks */
64 #define OMAP_UART_SYSC_SOFTRESET (1 << 1)
65
66 /* SYSS register bitmasks */
67 #define OMAP_UART_SYSS_RESETDONE (1 << 0)
68
69 #define UART_TI752_TLR_TX 0
70 #define UART_TI752_TLR_RX 4
71
72 #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2)
73 #define TRIGGER_FCR_MASK(x) (x & 3)
74
75 /* Enable XON/XOFF flow control on output */
76 #define OMAP_UART_SW_TX 0x08
77 /* Enable XON/XOFF flow control on input */
78 #define OMAP_UART_SW_RX 0x02
79
80 #define OMAP_UART_WER_MOD_WKUP 0x7f
81 #define OMAP_UART_TX_WAKEUP_EN (1 << 7)
82
83 #define TX_TRIGGER 1
84 #define RX_TRIGGER 48
85
86 #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4)
87 #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0)
88
89 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
90
91 #define OMAP_UART_REV_46 0x0406
92 #define OMAP_UART_REV_52 0x0502
93 #define OMAP_UART_REV_63 0x0603
94
95 struct omap8250_priv {
96 int line;
97 u8 habit;
98 u8 mdr1;
99 u8 efr;
100 u8 scr;
101 u8 wer;
102 u8 xon;
103 u8 xoff;
104 u8 delayed_restore;
105 u16 quot;
106
107 bool is_suspending;
108 int wakeirq;
109 int wakeups_enabled;
110 u32 latency;
111 u32 calc_latency;
112 struct pm_qos_request pm_qos_request;
113 struct work_struct qos_work;
114 struct uart_8250_dma omap8250_dma;
115 spinlock_t rx_dma_lock;
116 bool rx_dma_broken;
117 };
118
119 #ifdef CONFIG_SERIAL_8250_DMA
120 static void omap_8250_rx_dma_flush(struct uart_8250_port *p);
121 #else
122 static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { }
123 #endif
124
125 static u32 uart_read(struct uart_8250_port *up, u32 reg)
126 {
127 return readl(up->port.membase + (reg << up->port.regshift));
128 }
129
130 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
131 {
132 struct uart_8250_port *up = up_to_u8250p(port);
133 struct omap8250_priv *priv = up->port.private_data;
134 u8 lcr;
135
136 serial8250_do_set_mctrl(port, mctrl);
137
138 /*
139 * Turn off autoRTS if RTS is lowered and restore autoRTS setting
140 * if RTS is raised
141 */
142 lcr = serial_in(up, UART_LCR);
143 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
144 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
145 priv->efr |= UART_EFR_RTS;
146 else
147 priv->efr &= ~UART_EFR_RTS;
148 serial_out(up, UART_EFR, priv->efr);
149 serial_out(up, UART_LCR, lcr);
150 }
151
152 /*
153 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
154 * The access to uart register after MDR1 Access
155 * causes UART to corrupt data.
156 *
157 * Need a delay =
158 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
159 * give 10 times as much
160 */
161 static void omap_8250_mdr1_errataset(struct uart_8250_port *up,
162 struct omap8250_priv *priv)
163 {
164 u8 timeout = 255;
165 u8 old_mdr1;
166
167 old_mdr1 = serial_in(up, UART_OMAP_MDR1);
168 if (old_mdr1 == priv->mdr1)
169 return;
170
171 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
172 udelay(2);
173 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
174 UART_FCR_CLEAR_RCVR);
175 /*
176 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
177 * TX_FIFO_E bit is 1.
178 */
179 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
180 (UART_LSR_THRE | UART_LSR_DR))) {
181 timeout--;
182 if (!timeout) {
183 /* Should *never* happen. we warn and carry on */
184 dev_crit(up->port.dev, "Errata i202: timedout %x\n",
185 serial_in(up, UART_LSR));
186 break;
187 }
188 udelay(1);
189 }
190 }
191
192 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud,
193 struct omap8250_priv *priv)
194 {
195 unsigned int uartclk = port->uartclk;
196 unsigned int div_13, div_16;
197 unsigned int abs_d13, abs_d16;
198
199 /*
200 * Old custom speed handling.
201 */
202 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
203 priv->quot = port->custom_divisor & UART_DIV_MAX;
204 /*
205 * I assume that nobody is using this. But hey, if somebody
206 * would like to specify the divisor _and_ the mode then the
207 * driver is ready and waiting for it.
208 */
209 if (port->custom_divisor & (1 << 16))
210 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
211 else
212 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
213 return;
214 }
215 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud);
216 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud);
217
218 if (!div_13)
219 div_13 = 1;
220 if (!div_16)
221 div_16 = 1;
222
223 abs_d13 = abs(baud - uartclk / 13 / div_13);
224 abs_d16 = abs(baud - uartclk / 16 / div_16);
225
226 if (abs_d13 >= abs_d16) {
227 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
228 priv->quot = div_16;
229 } else {
230 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
231 priv->quot = div_13;
232 }
233 }
234
235 static void omap8250_update_scr(struct uart_8250_port *up,
236 struct omap8250_priv *priv)
237 {
238 u8 old_scr;
239
240 old_scr = serial_in(up, UART_OMAP_SCR);
241 if (old_scr == priv->scr)
242 return;
243
244 /*
245 * The manual recommends not to enable the DMA mode selector in the SCR
246 * (instead of the FCR) register _and_ selecting the DMA mode as one
247 * register write because this may lead to malfunction.
248 */
249 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK)
250 serial_out(up, UART_OMAP_SCR,
251 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK);
252 serial_out(up, UART_OMAP_SCR, priv->scr);
253 }
254
255 static void omap8250_update_mdr1(struct uart_8250_port *up,
256 struct omap8250_priv *priv)
257 {
258 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS)
259 omap_8250_mdr1_errataset(up, priv);
260 else
261 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
262 }
263
264 static void omap8250_restore_regs(struct uart_8250_port *up)
265 {
266 struct omap8250_priv *priv = up->port.private_data;
267 struct uart_8250_dma *dma = up->dma;
268
269 if (dma && dma->tx_running) {
270 /*
271 * TCSANOW requests the change to occur immediately however if
272 * we have a TX-DMA operation in progress then it has been
273 * observed that it might stall and never complete. Therefore we
274 * delay DMA completes to prevent this hang from happen.
275 */
276 priv->delayed_restore = 1;
277 return;
278 }
279
280 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
281 serial_out(up, UART_EFR, UART_EFR_ECB);
282
283 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
284 serial8250_out_MCR(up, UART_MCR_TCRTLR);
285 serial_out(up, UART_FCR, up->fcr);
286
287 omap8250_update_scr(up, priv);
288
289 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
290
291 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) |
292 OMAP_UART_TCR_HALT(52));
293 serial_out(up, UART_TI752_TLR,
294 TRIGGER_TLR_MASK(TX_TRIGGER) << UART_TI752_TLR_TX |
295 TRIGGER_TLR_MASK(RX_TRIGGER) << UART_TI752_TLR_RX);
296
297 serial_out(up, UART_LCR, 0);
298
299 /* drop TCR + TLR access, we setup XON/XOFF later */
300 serial8250_out_MCR(up, up->mcr);
301 serial_out(up, UART_IER, up->ier);
302
303 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
304 serial_dl_write(up, priv->quot);
305
306 serial_out(up, UART_EFR, priv->efr);
307
308 /* Configure flow control */
309 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
310 serial_out(up, UART_XON1, priv->xon);
311 serial_out(up, UART_XOFF1, priv->xoff);
312
313 serial_out(up, UART_LCR, up->lcr);
314
315 omap8250_update_mdr1(up, priv);
316
317 up->port.ops->set_mctrl(&up->port, up->port.mctrl);
318 }
319
320 /*
321 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have
322 * some differences in how we want to handle flow control.
323 */
324 static void omap_8250_set_termios(struct uart_port *port,
325 struct ktermios *termios,
326 struct ktermios *old)
327 {
328 struct uart_8250_port *up = up_to_u8250p(port);
329 struct omap8250_priv *priv = up->port.private_data;
330 unsigned char cval = 0;
331 unsigned int baud;
332
333 switch (termios->c_cflag & CSIZE) {
334 case CS5:
335 cval = UART_LCR_WLEN5;
336 break;
337 case CS6:
338 cval = UART_LCR_WLEN6;
339 break;
340 case CS7:
341 cval = UART_LCR_WLEN7;
342 break;
343 default:
344 case CS8:
345 cval = UART_LCR_WLEN8;
346 break;
347 }
348
349 if (termios->c_cflag & CSTOPB)
350 cval |= UART_LCR_STOP;
351 if (termios->c_cflag & PARENB)
352 cval |= UART_LCR_PARITY;
353 if (!(termios->c_cflag & PARODD))
354 cval |= UART_LCR_EPAR;
355 if (termios->c_cflag & CMSPAR)
356 cval |= UART_LCR_SPAR;
357
358 /*
359 * Ask the core to calculate the divisor for us.
360 */
361 baud = uart_get_baud_rate(port, termios, old,
362 port->uartclk / 16 / UART_DIV_MAX,
363 port->uartclk / 13);
364 omap_8250_get_divisor(port, baud, priv);
365
366 /*
367 * Ok, we're now changing the port state. Do it with
368 * interrupts disabled.
369 */
370 pm_runtime_get_sync(port->dev);
371 spin_lock_irq(&port->lock);
372
373 /*
374 * Update the per-port timeout.
375 */
376 uart_update_timeout(port, termios->c_cflag, baud);
377
378 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
379 if (termios->c_iflag & INPCK)
380 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
381 if (termios->c_iflag & (IGNBRK | PARMRK))
382 up->port.read_status_mask |= UART_LSR_BI;
383
384 /*
385 * Characters to ignore
386 */
387 up->port.ignore_status_mask = 0;
388 if (termios->c_iflag & IGNPAR)
389 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
390 if (termios->c_iflag & IGNBRK) {
391 up->port.ignore_status_mask |= UART_LSR_BI;
392 /*
393 * If we're ignoring parity and break indicators,
394 * ignore overruns too (for real raw support).
395 */
396 if (termios->c_iflag & IGNPAR)
397 up->port.ignore_status_mask |= UART_LSR_OE;
398 }
399
400 /*
401 * ignore all characters if CREAD is not set
402 */
403 if ((termios->c_cflag & CREAD) == 0)
404 up->port.ignore_status_mask |= UART_LSR_DR;
405
406 /*
407 * Modem status interrupts
408 */
409 up->ier &= ~UART_IER_MSI;
410 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
411 up->ier |= UART_IER_MSI;
412
413 up->lcr = cval;
414 /* Up to here it was mostly serial8250_do_set_termios() */
415
416 /*
417 * We enable TRIG_GRANU for RX and TX and additionally we set
418 * SCR_TX_EMPTY bit. The result is the following:
419 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt.
420 * - less than RX_TRIGGER number of bytes will also cause an interrupt
421 * once the UART decides that there no new bytes arriving.
422 * - Once THRE is enabled, the interrupt will be fired once the FIFO is
423 * empty - the trigger level is ignored here.
424 *
425 * Once DMA is enabled:
426 * - UART will assert the TX DMA line once there is room for TX_TRIGGER
427 * bytes in the TX FIFO. On each assert the DMA engine will move
428 * TX_TRIGGER bytes into the FIFO.
429 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in
430 * the FIFO and move RX_TRIGGER bytes.
431 * This is because threshold and trigger values are the same.
432 */
433 up->fcr = UART_FCR_ENABLE_FIFO;
434 up->fcr |= TRIGGER_FCR_MASK(TX_TRIGGER) << OMAP_UART_FCR_TX_TRIG;
435 up->fcr |= TRIGGER_FCR_MASK(RX_TRIGGER) << OMAP_UART_FCR_RX_TRIG;
436
437 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY |
438 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK;
439
440 if (up->dma)
441 priv->scr |= OMAP_UART_SCR_DMAMODE_1 |
442 OMAP_UART_SCR_DMAMODE_CTL;
443
444 priv->xon = termios->c_cc[VSTART];
445 priv->xoff = termios->c_cc[VSTOP];
446
447 priv->efr = 0;
448 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
449
450 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
451 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
452 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
453 priv->efr |= UART_EFR_CTS;
454 } else if (up->port.flags & UPF_SOFT_FLOW) {
455 /*
456 * OMAP rx s/w flow control is borked; the transmitter remains
457 * stuck off even if rx flow control is subsequently disabled
458 */
459
460 /*
461 * IXOFF Flag:
462 * Enable XON/XOFF flow control on output.
463 * Transmit XON1, XOFF1
464 */
465 if (termios->c_iflag & IXOFF) {
466 up->port.status |= UPSTAT_AUTOXOFF;
467 priv->efr |= OMAP_UART_SW_TX;
468 }
469 }
470 omap8250_restore_regs(up);
471
472 spin_unlock_irq(&up->port.lock);
473 pm_runtime_mark_last_busy(port->dev);
474 pm_runtime_put_autosuspend(port->dev);
475
476 /* calculate wakeup latency constraint */
477 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud;
478 priv->latency = priv->calc_latency;
479
480 schedule_work(&priv->qos_work);
481
482 /* Don't rewrite B0 */
483 if (tty_termios_baud_rate(termios))
484 tty_termios_encode_baud_rate(termios, baud, baud);
485 }
486
487 /* same as 8250 except that we may have extra flow bits set in EFR */
488 static void omap_8250_pm(struct uart_port *port, unsigned int state,
489 unsigned int oldstate)
490 {
491 struct uart_8250_port *up = up_to_u8250p(port);
492 u8 efr;
493
494 pm_runtime_get_sync(port->dev);
495 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
496 efr = serial_in(up, UART_EFR);
497 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
498 serial_out(up, UART_LCR, 0);
499
500 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
501 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
502 serial_out(up, UART_EFR, efr);
503 serial_out(up, UART_LCR, 0);
504
505 pm_runtime_mark_last_busy(port->dev);
506 pm_runtime_put_autosuspend(port->dev);
507 }
508
509 static void omap_serial_fill_features_erratas(struct uart_8250_port *up,
510 struct omap8250_priv *priv)
511 {
512 u32 mvr, scheme;
513 u16 revision, major, minor;
514
515 mvr = uart_read(up, UART_OMAP_MVER);
516
517 /* Check revision register scheme */
518 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
519
520 switch (scheme) {
521 case 0: /* Legacy Scheme: OMAP2/3 */
522 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
523 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
524 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
525 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
526 break;
527 case 1:
528 /* New Scheme: OMAP4+ */
529 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
530 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
531 OMAP_UART_MVR_MAJ_SHIFT;
532 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
533 break;
534 default:
535 dev_warn(up->port.dev,
536 "Unknown revision, defaulting to highest\n");
537 /* highest possible revision */
538 major = 0xff;
539 minor = 0xff;
540 }
541 /* normalize revision for the driver */
542 revision = UART_BUILD_REVISION(major, minor);
543
544 switch (revision) {
545 case OMAP_UART_REV_46:
546 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS;
547 break;
548 case OMAP_UART_REV_52:
549 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
550 OMAP_UART_WER_HAS_TX_WAKEUP;
551 break;
552 case OMAP_UART_REV_63:
553 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
554 OMAP_UART_WER_HAS_TX_WAKEUP;
555 break;
556 default:
557 break;
558 }
559 }
560
561 static void omap8250_uart_qos_work(struct work_struct *work)
562 {
563 struct omap8250_priv *priv;
564
565 priv = container_of(work, struct omap8250_priv, qos_work);
566 pm_qos_update_request(&priv->pm_qos_request, priv->latency);
567 }
568
569 #ifdef CONFIG_SERIAL_8250_DMA
570 static int omap_8250_dma_handle_irq(struct uart_port *port);
571 #endif
572
573 static irqreturn_t omap8250_irq(int irq, void *dev_id)
574 {
575 struct uart_port *port = dev_id;
576 struct uart_8250_port *up = up_to_u8250p(port);
577 unsigned int iir;
578 int ret;
579
580 #ifdef CONFIG_SERIAL_8250_DMA
581 if (up->dma) {
582 ret = omap_8250_dma_handle_irq(port);
583 return IRQ_RETVAL(ret);
584 }
585 #endif
586
587 serial8250_rpm_get(up);
588 iir = serial_port_in(port, UART_IIR);
589 ret = serial8250_handle_irq(port, iir);
590 serial8250_rpm_put(up);
591
592 return IRQ_RETVAL(ret);
593 }
594
595 static int omap_8250_startup(struct uart_port *port)
596 {
597 struct uart_8250_port *up = up_to_u8250p(port);
598 struct omap8250_priv *priv = port->private_data;
599 int ret;
600
601 if (priv->wakeirq) {
602 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq);
603 if (ret)
604 return ret;
605 }
606
607 pm_runtime_get_sync(port->dev);
608
609 up->mcr = 0;
610 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
611
612 serial_out(up, UART_LCR, UART_LCR_WLEN8);
613
614 up->lsr_saved_flags = 0;
615 up->msr_saved_flags = 0;
616
617 /* Disable DMA for console UART */
618 if (uart_console(port))
619 up->dma = NULL;
620
621 if (up->dma) {
622 ret = serial8250_request_dma(up);
623 if (ret) {
624 dev_warn_ratelimited(port->dev,
625 "failed to request DMA\n");
626 up->dma = NULL;
627 }
628 }
629
630 ret = request_irq(port->irq, omap8250_irq, IRQF_SHARED,
631 dev_name(port->dev), port);
632 if (ret < 0)
633 goto err;
634
635 up->ier = UART_IER_RLSI | UART_IER_RDI;
636 serial_out(up, UART_IER, up->ier);
637
638 #ifdef CONFIG_PM
639 up->capabilities |= UART_CAP_RPM;
640 #endif
641
642 /* Enable module level wake up */
643 priv->wer = OMAP_UART_WER_MOD_WKUP;
644 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP)
645 priv->wer |= OMAP_UART_TX_WAKEUP_EN;
646 serial_out(up, UART_OMAP_WER, priv->wer);
647
648 if (up->dma)
649 up->dma->rx_dma(up);
650
651 pm_runtime_mark_last_busy(port->dev);
652 pm_runtime_put_autosuspend(port->dev);
653 return 0;
654 err:
655 pm_runtime_mark_last_busy(port->dev);
656 pm_runtime_put_autosuspend(port->dev);
657 dev_pm_clear_wake_irq(port->dev);
658 return ret;
659 }
660
661 static void omap_8250_shutdown(struct uart_port *port)
662 {
663 struct uart_8250_port *up = up_to_u8250p(port);
664 struct omap8250_priv *priv = port->private_data;
665
666 flush_work(&priv->qos_work);
667 if (up->dma)
668 omap_8250_rx_dma_flush(up);
669
670 pm_runtime_get_sync(port->dev);
671
672 serial_out(up, UART_OMAP_WER, 0);
673
674 up->ier = 0;
675 serial_out(up, UART_IER, 0);
676
677 if (up->dma)
678 serial8250_release_dma(up);
679
680 /*
681 * Disable break condition and FIFOs
682 */
683 if (up->lcr & UART_LCR_SBC)
684 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC);
685 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
686
687 pm_runtime_mark_last_busy(port->dev);
688 pm_runtime_put_autosuspend(port->dev);
689 free_irq(port->irq, port);
690 dev_pm_clear_wake_irq(port->dev);
691 }
692
693 static void omap_8250_throttle(struct uart_port *port)
694 {
695 struct uart_8250_port *up = up_to_u8250p(port);
696 unsigned long flags;
697
698 pm_runtime_get_sync(port->dev);
699
700 spin_lock_irqsave(&port->lock, flags);
701 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
702 serial_out(up, UART_IER, up->ier);
703 spin_unlock_irqrestore(&port->lock, flags);
704
705 pm_runtime_mark_last_busy(port->dev);
706 pm_runtime_put_autosuspend(port->dev);
707 }
708
709 static int omap_8250_rs485_config(struct uart_port *port,
710 struct serial_rs485 *rs485)
711 {
712 struct uart_8250_port *up = up_to_u8250p(port);
713
714 /* Clamp the delays to [0, 100ms] */
715 rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
716 rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U);
717
718 port->rs485 = *rs485;
719
720 /*
721 * Both serial8250_em485_init and serial8250_em485_destroy
722 * are idempotent
723 */
724 if (rs485->flags & SER_RS485_ENABLED) {
725 int ret = serial8250_em485_init(up);
726
727 if (ret) {
728 rs485->flags &= ~SER_RS485_ENABLED;
729 port->rs485.flags &= ~SER_RS485_ENABLED;
730 }
731 return ret;
732 }
733
734 serial8250_em485_destroy(up);
735
736 return 0;
737 }
738
739 static void omap_8250_unthrottle(struct uart_port *port)
740 {
741 struct uart_8250_port *up = up_to_u8250p(port);
742 unsigned long flags;
743
744 pm_runtime_get_sync(port->dev);
745
746 spin_lock_irqsave(&port->lock, flags);
747 up->ier |= UART_IER_RLSI | UART_IER_RDI;
748 serial_out(up, UART_IER, up->ier);
749 spin_unlock_irqrestore(&port->lock, flags);
750
751 pm_runtime_mark_last_busy(port->dev);
752 pm_runtime_put_autosuspend(port->dev);
753 }
754
755 #ifdef CONFIG_SERIAL_8250_DMA
756 static int omap_8250_rx_dma(struct uart_8250_port *p);
757
758 static void __dma_rx_do_complete(struct uart_8250_port *p)
759 {
760 struct omap8250_priv *priv = p->port.private_data;
761 struct uart_8250_dma *dma = p->dma;
762 struct tty_port *tty_port = &p->port.state->port;
763 struct dma_tx_state state;
764 int count;
765 unsigned long flags;
766 int ret;
767
768 spin_lock_irqsave(&priv->rx_dma_lock, flags);
769
770 if (!dma->rx_running)
771 goto unlock;
772
773 dma->rx_running = 0;
774 dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
775
776 count = dma->rx_size - state.residue;
777
778 ret = tty_insert_flip_string(tty_port, dma->rx_buf, count);
779
780 p->port.icount.rx += ret;
781 p->port.icount.buf_overrun += count - ret;
782 unlock:
783 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
784
785 tty_flip_buffer_push(tty_port);
786 }
787
788 static void __dma_rx_complete(void *param)
789 {
790 struct uart_8250_port *p = param;
791 struct uart_8250_dma *dma = p->dma;
792 struct dma_tx_state state;
793 unsigned long flags;
794
795 spin_lock_irqsave(&p->port.lock, flags);
796
797 /*
798 * If the tx status is not DMA_COMPLETE, then this is a delayed
799 * completion callback. A previous RX timeout flush would have
800 * already pushed the data, so exit.
801 */
802 if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) !=
803 DMA_COMPLETE) {
804 spin_unlock_irqrestore(&p->port.lock, flags);
805 return;
806 }
807 __dma_rx_do_complete(p);
808 omap_8250_rx_dma(p);
809
810 spin_unlock_irqrestore(&p->port.lock, flags);
811 }
812
813 static void omap_8250_rx_dma_flush(struct uart_8250_port *p)
814 {
815 struct omap8250_priv *priv = p->port.private_data;
816 struct uart_8250_dma *dma = p->dma;
817 struct dma_tx_state state;
818 unsigned long flags;
819 int ret;
820
821 spin_lock_irqsave(&priv->rx_dma_lock, flags);
822
823 if (!dma->rx_running) {
824 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
825 return;
826 }
827
828 ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
829 if (ret == DMA_IN_PROGRESS) {
830 ret = dmaengine_pause(dma->rxchan);
831 if (WARN_ON_ONCE(ret))
832 priv->rx_dma_broken = true;
833 }
834 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
835
836 __dma_rx_do_complete(p);
837 dmaengine_terminate_all(dma->rxchan);
838 }
839
840 static int omap_8250_rx_dma(struct uart_8250_port *p)
841 {
842 struct omap8250_priv *priv = p->port.private_data;
843 struct uart_8250_dma *dma = p->dma;
844 int err = 0;
845 struct dma_async_tx_descriptor *desc;
846 unsigned long flags;
847
848 if (priv->rx_dma_broken)
849 return -EINVAL;
850
851 spin_lock_irqsave(&priv->rx_dma_lock, flags);
852
853 if (dma->rx_running)
854 goto out;
855
856 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
857 dma->rx_size, DMA_DEV_TO_MEM,
858 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
859 if (!desc) {
860 err = -EBUSY;
861 goto out;
862 }
863
864 dma->rx_running = 1;
865 desc->callback = __dma_rx_complete;
866 desc->callback_param = p;
867
868 dma->rx_cookie = dmaengine_submit(desc);
869
870 dma_async_issue_pending(dma->rxchan);
871 out:
872 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
873 return err;
874 }
875
876 static int omap_8250_tx_dma(struct uart_8250_port *p);
877
878 static void omap_8250_dma_tx_complete(void *param)
879 {
880 struct uart_8250_port *p = param;
881 struct uart_8250_dma *dma = p->dma;
882 struct circ_buf *xmit = &p->port.state->xmit;
883 unsigned long flags;
884 bool en_thri = false;
885 struct omap8250_priv *priv = p->port.private_data;
886
887 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr,
888 UART_XMIT_SIZE, DMA_TO_DEVICE);
889
890 spin_lock_irqsave(&p->port.lock, flags);
891
892 dma->tx_running = 0;
893
894 xmit->tail += dma->tx_size;
895 xmit->tail &= UART_XMIT_SIZE - 1;
896 p->port.icount.tx += dma->tx_size;
897
898 if (priv->delayed_restore) {
899 priv->delayed_restore = 0;
900 omap8250_restore_regs(p);
901 }
902
903 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
904 uart_write_wakeup(&p->port);
905
906 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) {
907 int ret;
908
909 ret = omap_8250_tx_dma(p);
910 if (ret)
911 en_thri = true;
912
913 } else if (p->capabilities & UART_CAP_RPM) {
914 en_thri = true;
915 }
916
917 if (en_thri) {
918 dma->tx_err = 1;
919 p->ier |= UART_IER_THRI;
920 serial_port_out(&p->port, UART_IER, p->ier);
921 }
922
923 spin_unlock_irqrestore(&p->port.lock, flags);
924 }
925
926 static int omap_8250_tx_dma(struct uart_8250_port *p)
927 {
928 struct uart_8250_dma *dma = p->dma;
929 struct omap8250_priv *priv = p->port.private_data;
930 struct circ_buf *xmit = &p->port.state->xmit;
931 struct dma_async_tx_descriptor *desc;
932 unsigned int skip_byte = 0;
933 int ret;
934
935 if (dma->tx_running)
936 return 0;
937 if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) {
938
939 /*
940 * Even if no data, we need to return an error for the two cases
941 * below so serial8250_tx_chars() is invoked and properly clears
942 * THRI and/or runtime suspend.
943 */
944 if (dma->tx_err || p->capabilities & UART_CAP_RPM) {
945 ret = -EBUSY;
946 goto err;
947 }
948 if (p->ier & UART_IER_THRI) {
949 p->ier &= ~UART_IER_THRI;
950 serial_out(p, UART_IER, p->ier);
951 }
952 return 0;
953 }
954
955 dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
956 if (priv->habit & OMAP_DMA_TX_KICK) {
957 u8 tx_lvl;
958
959 /*
960 * We need to put the first byte into the FIFO in order to start
961 * the DMA transfer. For transfers smaller than four bytes we
962 * don't bother doing DMA at all. It seem not matter if there
963 * are still bytes in the FIFO from the last transfer (in case
964 * we got here directly from omap_8250_dma_tx_complete()). Bytes
965 * leaving the FIFO seem not to trigger the DMA transfer. It is
966 * really the byte that we put into the FIFO.
967 * If the FIFO is already full then we most likely got here from
968 * omap_8250_dma_tx_complete(). And this means the DMA engine
969 * just completed its work. We don't have to wait the complete
970 * 86us at 115200,8n1 but around 60us (not to mention lower
971 * baudrates). So in that case we take the interrupt and try
972 * again with an empty FIFO.
973 */
974 tx_lvl = serial_in(p, UART_OMAP_TX_LVL);
975 if (tx_lvl == p->tx_loadsz) {
976 ret = -EBUSY;
977 goto err;
978 }
979 if (dma->tx_size < 4) {
980 ret = -EINVAL;
981 goto err;
982 }
983 skip_byte = 1;
984 }
985
986 desc = dmaengine_prep_slave_single(dma->txchan,
987 dma->tx_addr + xmit->tail + skip_byte,
988 dma->tx_size - skip_byte, DMA_MEM_TO_DEV,
989 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
990 if (!desc) {
991 ret = -EBUSY;
992 goto err;
993 }
994
995 dma->tx_running = 1;
996
997 desc->callback = omap_8250_dma_tx_complete;
998 desc->callback_param = p;
999
1000 dma->tx_cookie = dmaengine_submit(desc);
1001
1002 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr,
1003 UART_XMIT_SIZE, DMA_TO_DEVICE);
1004
1005 dma_async_issue_pending(dma->txchan);
1006 if (dma->tx_err)
1007 dma->tx_err = 0;
1008
1009 if (p->ier & UART_IER_THRI) {
1010 p->ier &= ~UART_IER_THRI;
1011 serial_out(p, UART_IER, p->ier);
1012 }
1013 if (skip_byte)
1014 serial_out(p, UART_TX, xmit->buf[xmit->tail]);
1015 return 0;
1016 err:
1017 dma->tx_err = 1;
1018 return ret;
1019 }
1020
1021 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1022 {
1023 switch (iir & 0x3f) {
1024 case UART_IIR_RLSI:
1025 case UART_IIR_RX_TIMEOUT:
1026 case UART_IIR_RDI:
1027 omap_8250_rx_dma_flush(up);
1028 return true;
1029 }
1030 return omap_8250_rx_dma(up);
1031 }
1032
1033 /*
1034 * This is mostly serial8250_handle_irq(). We have a slightly different DMA
1035 * hoook for RX/TX and need different logic for them in the ISR. Therefore we
1036 * use the default routine in the non-DMA case and this one for with DMA.
1037 */
1038 static int omap_8250_dma_handle_irq(struct uart_port *port)
1039 {
1040 struct uart_8250_port *up = up_to_u8250p(port);
1041 unsigned char status;
1042 unsigned long flags;
1043 u8 iir;
1044
1045 serial8250_rpm_get(up);
1046
1047 iir = serial_port_in(port, UART_IIR);
1048 if (iir & UART_IIR_NO_INT) {
1049 serial8250_rpm_put(up);
1050 return 0;
1051 }
1052
1053 spin_lock_irqsave(&port->lock, flags);
1054
1055 status = serial_port_in(port, UART_LSR);
1056
1057 if (status & (UART_LSR_DR | UART_LSR_BI)) {
1058 if (handle_rx_dma(up, iir)) {
1059 status = serial8250_rx_chars(up, status);
1060 omap_8250_rx_dma(up);
1061 }
1062 }
1063 serial8250_modem_status(up);
1064 if (status & UART_LSR_THRE && up->dma->tx_err) {
1065 if (uart_tx_stopped(&up->port) ||
1066 uart_circ_empty(&up->port.state->xmit)) {
1067 up->dma->tx_err = 0;
1068 serial8250_tx_chars(up);
1069 } else {
1070 /*
1071 * try again due to an earlier failer which
1072 * might have been resolved by now.
1073 */
1074 if (omap_8250_tx_dma(up))
1075 serial8250_tx_chars(up);
1076 }
1077 }
1078
1079 spin_unlock_irqrestore(&port->lock, flags);
1080 serial8250_rpm_put(up);
1081 return 1;
1082 }
1083
1084 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param)
1085 {
1086 return false;
1087 }
1088
1089 #else
1090
1091 static inline int omap_8250_rx_dma(struct uart_8250_port *p)
1092 {
1093 return -EINVAL;
1094 }
1095 #endif
1096
1097 static int omap8250_no_handle_irq(struct uart_port *port)
1098 {
1099 /* IRQ has not been requested but handling irq? */
1100 WARN_ONCE(1, "Unexpected irq handling before port startup\n");
1101 return 0;
1102 }
1103
1104 static const u8 am3352_habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE;
1105 static const u8 dra742_habit = UART_ERRATA_CLOCK_DISABLE;
1106
1107 static const struct of_device_id omap8250_dt_ids[] = {
1108 { .compatible = "ti,omap2-uart" },
1109 { .compatible = "ti,omap3-uart" },
1110 { .compatible = "ti,omap4-uart" },
1111 { .compatible = "ti,am3352-uart", .data = &am3352_habit, },
1112 { .compatible = "ti,am4372-uart", .data = &am3352_habit, },
1113 { .compatible = "ti,dra742-uart", .data = &dra742_habit, },
1114 {},
1115 };
1116 MODULE_DEVICE_TABLE(of, omap8250_dt_ids);
1117
1118 static int omap8250_probe(struct platform_device *pdev)
1119 {
1120 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1121 struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1122 struct omap8250_priv *priv;
1123 struct uart_8250_port up;
1124 int ret;
1125 void __iomem *membase;
1126
1127 if (!regs || !irq) {
1128 dev_err(&pdev->dev, "missing registers or irq\n");
1129 return -EINVAL;
1130 }
1131
1132 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1133 if (!priv)
1134 return -ENOMEM;
1135
1136 membase = devm_ioremap_nocache(&pdev->dev, regs->start,
1137 resource_size(regs));
1138 if (!membase)
1139 return -ENODEV;
1140
1141 memset(&up, 0, sizeof(up));
1142 up.port.dev = &pdev->dev;
1143 up.port.mapbase = regs->start;
1144 up.port.membase = membase;
1145 up.port.irq = irq->start;
1146 /*
1147 * It claims to be 16C750 compatible however it is a little different.
1148 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to
1149 * have) is enabled via EFR instead of MCR. The type is set here 8250
1150 * just to get things going. UNKNOWN does not work for a few reasons and
1151 * we don't need our own type since we don't use 8250's set_termios()
1152 * or pm callback.
1153 */
1154 up.port.type = PORT_8250;
1155 up.port.iotype = UPIO_MEM;
1156 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW |
1157 UPF_HARD_FLOW;
1158 up.port.private_data = priv;
1159
1160 up.port.regshift = 2;
1161 up.port.fifosize = 64;
1162 up.tx_loadsz = 64;
1163 up.capabilities = UART_CAP_FIFO;
1164 #ifdef CONFIG_PM
1165 /*
1166 * Runtime PM is mostly transparent. However to do it right we need to a
1167 * TX empty interrupt before we can put the device to auto idle. So if
1168 * PM is not enabled we don't add that flag and can spare that one extra
1169 * interrupt in the TX path.
1170 */
1171 up.capabilities |= UART_CAP_RPM;
1172 #endif
1173 up.port.set_termios = omap_8250_set_termios;
1174 up.port.set_mctrl = omap8250_set_mctrl;
1175 up.port.pm = omap_8250_pm;
1176 up.port.startup = omap_8250_startup;
1177 up.port.shutdown = omap_8250_shutdown;
1178 up.port.throttle = omap_8250_throttle;
1179 up.port.unthrottle = omap_8250_unthrottle;
1180 up.port.rs485_config = omap_8250_rs485_config;
1181
1182 if (pdev->dev.of_node) {
1183 const struct of_device_id *id;
1184
1185 ret = of_alias_get_id(pdev->dev.of_node, "serial");
1186
1187 of_property_read_u32(pdev->dev.of_node, "clock-frequency",
1188 &up.port.uartclk);
1189 priv->wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1190
1191 id = of_match_device(of_match_ptr(omap8250_dt_ids), &pdev->dev);
1192 if (id && id->data)
1193 priv->habit |= *(u8 *)id->data;
1194 } else {
1195 ret = pdev->id;
1196 }
1197 if (ret < 0) {
1198 dev_err(&pdev->dev, "failed to get alias/pdev id\n");
1199 return ret;
1200 }
1201 up.port.line = ret;
1202
1203 if (!up.port.uartclk) {
1204 up.port.uartclk = DEFAULT_CLK_SPEED;
1205 dev_warn(&pdev->dev,
1206 "No clock speed specified: using default: %d\n",
1207 DEFAULT_CLK_SPEED);
1208 }
1209
1210 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1211 priv->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1212 pm_qos_add_request(&priv->pm_qos_request, PM_QOS_CPU_DMA_LATENCY,
1213 priv->latency);
1214 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work);
1215
1216 spin_lock_init(&priv->rx_dma_lock);
1217
1218 device_init_wakeup(&pdev->dev, true);
1219 pm_runtime_use_autosuspend(&pdev->dev);
1220 pm_runtime_set_autosuspend_delay(&pdev->dev, -1);
1221
1222 pm_runtime_irq_safe(&pdev->dev);
1223 pm_runtime_enable(&pdev->dev);
1224
1225 pm_runtime_get_sync(&pdev->dev);
1226
1227 omap_serial_fill_features_erratas(&up, priv);
1228 up.port.handle_irq = omap8250_no_handle_irq;
1229 #ifdef CONFIG_SERIAL_8250_DMA
1230 if (pdev->dev.of_node) {
1231 /*
1232 * Oh DMA support. If there are no DMA properties in the DT then
1233 * we will fall back to a generic DMA channel which does not
1234 * really work here. To ensure that we do not get a generic DMA
1235 * channel assigned, we have the the_no_dma_filter_fn() here.
1236 * To avoid "failed to request DMA" messages we check for DMA
1237 * properties in DT.
1238 */
1239 ret = of_property_count_strings(pdev->dev.of_node, "dma-names");
1240 if (ret == 2) {
1241 up.dma = &priv->omap8250_dma;
1242 priv->omap8250_dma.fn = the_no_dma_filter_fn;
1243 priv->omap8250_dma.tx_dma = omap_8250_tx_dma;
1244 priv->omap8250_dma.rx_dma = omap_8250_rx_dma;
1245 priv->omap8250_dma.rx_size = RX_TRIGGER;
1246 priv->omap8250_dma.rxconf.src_maxburst = RX_TRIGGER;
1247 priv->omap8250_dma.txconf.dst_maxburst = TX_TRIGGER;
1248 }
1249 }
1250 #endif
1251 ret = serial8250_register_8250_port(&up);
1252 if (ret < 0) {
1253 dev_err(&pdev->dev, "unable to register 8250 port\n");
1254 goto err;
1255 }
1256 priv->line = ret;
1257 platform_set_drvdata(pdev, priv);
1258 pm_runtime_mark_last_busy(&pdev->dev);
1259 pm_runtime_put_autosuspend(&pdev->dev);
1260 return 0;
1261 err:
1262 pm_runtime_dont_use_autosuspend(&pdev->dev);
1263 pm_runtime_put_sync(&pdev->dev);
1264 pm_runtime_disable(&pdev->dev);
1265 return ret;
1266 }
1267
1268 static int omap8250_remove(struct platform_device *pdev)
1269 {
1270 struct omap8250_priv *priv = platform_get_drvdata(pdev);
1271
1272 pm_runtime_dont_use_autosuspend(&pdev->dev);
1273 pm_runtime_put_sync(&pdev->dev);
1274 pm_runtime_disable(&pdev->dev);
1275 serial8250_unregister_port(priv->line);
1276 pm_qos_remove_request(&priv->pm_qos_request);
1277 device_init_wakeup(&pdev->dev, false);
1278 return 0;
1279 }
1280
1281 #ifdef CONFIG_PM_SLEEP
1282 static int omap8250_prepare(struct device *dev)
1283 {
1284 struct omap8250_priv *priv = dev_get_drvdata(dev);
1285
1286 if (!priv)
1287 return 0;
1288 priv->is_suspending = true;
1289 return 0;
1290 }
1291
1292 static void omap8250_complete(struct device *dev)
1293 {
1294 struct omap8250_priv *priv = dev_get_drvdata(dev);
1295
1296 if (!priv)
1297 return;
1298 priv->is_suspending = false;
1299 }
1300
1301 static int omap8250_suspend(struct device *dev)
1302 {
1303 struct omap8250_priv *priv = dev_get_drvdata(dev);
1304
1305 serial8250_suspend_port(priv->line);
1306 flush_work(&priv->qos_work);
1307 return 0;
1308 }
1309
1310 static int omap8250_resume(struct device *dev)
1311 {
1312 struct omap8250_priv *priv = dev_get_drvdata(dev);
1313
1314 serial8250_resume_port(priv->line);
1315 return 0;
1316 }
1317 #else
1318 #define omap8250_prepare NULL
1319 #define omap8250_complete NULL
1320 #endif
1321
1322 #ifdef CONFIG_PM
1323 static int omap8250_lost_context(struct uart_8250_port *up)
1324 {
1325 u32 val;
1326
1327 val = serial_in(up, UART_OMAP_SCR);
1328 /*
1329 * If we lose context, then SCR is set to its reset value of zero.
1330 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1,
1331 * among other bits, to never set the register back to zero again.
1332 */
1333 if (!val)
1334 return 1;
1335 return 0;
1336 }
1337
1338 /* TODO: in future, this should happen via API in drivers/reset/ */
1339 static int omap8250_soft_reset(struct device *dev)
1340 {
1341 struct omap8250_priv *priv = dev_get_drvdata(dev);
1342 struct uart_8250_port *up = serial8250_get_port(priv->line);
1343 int timeout = 100;
1344 int sysc;
1345 int syss;
1346
1347 sysc = serial_in(up, UART_OMAP_SYSC);
1348
1349 /* softreset the UART */
1350 sysc |= OMAP_UART_SYSC_SOFTRESET;
1351 serial_out(up, UART_OMAP_SYSC, sysc);
1352
1353 /* By experiments, 1us enough for reset complete on AM335x */
1354 do {
1355 udelay(1);
1356 syss = serial_in(up, UART_OMAP_SYSS);
1357 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE));
1358
1359 if (!timeout) {
1360 dev_err(dev, "timed out waiting for reset done\n");
1361 return -ETIMEDOUT;
1362 }
1363
1364 return 0;
1365 }
1366
1367 static int omap8250_runtime_suspend(struct device *dev)
1368 {
1369 struct omap8250_priv *priv = dev_get_drvdata(dev);
1370 struct uart_8250_port *up;
1371
1372 /* In case runtime-pm tries this before we are setup */
1373 if (!priv)
1374 return 0;
1375
1376 up = serial8250_get_port(priv->line);
1377 /*
1378 * When using 'no_console_suspend', the console UART must not be
1379 * suspended. Since driver suspend is managed by runtime suspend,
1380 * preventing runtime suspend (by returning error) will keep device
1381 * active during suspend.
1382 */
1383 if (priv->is_suspending && !console_suspend_enabled) {
1384 if (uart_console(&up->port))
1385 return -EBUSY;
1386 }
1387
1388 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) {
1389 int ret;
1390
1391 ret = omap8250_soft_reset(dev);
1392 if (ret)
1393 return ret;
1394
1395 /* Restore to UART mode after reset (for wakeup) */
1396 omap8250_update_mdr1(up, priv);
1397 }
1398
1399 if (up->dma && up->dma->rxchan)
1400 omap_8250_rx_dma_flush(up);
1401
1402 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1403 schedule_work(&priv->qos_work);
1404
1405 return 0;
1406 }
1407
1408 static int omap8250_runtime_resume(struct device *dev)
1409 {
1410 struct omap8250_priv *priv = dev_get_drvdata(dev);
1411 struct uart_8250_port *up;
1412
1413 /* In case runtime-pm tries this before we are setup */
1414 if (!priv)
1415 return 0;
1416
1417 up = serial8250_get_port(priv->line);
1418
1419 if (omap8250_lost_context(up))
1420 omap8250_restore_regs(up);
1421
1422 if (up->dma && up->dma->rxchan)
1423 omap_8250_rx_dma(up);
1424
1425 priv->latency = priv->calc_latency;
1426 schedule_work(&priv->qos_work);
1427 return 0;
1428 }
1429 #endif
1430
1431 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP
1432 static int __init omap8250_console_fixup(void)
1433 {
1434 char *omap_str;
1435 char *options;
1436 u8 idx;
1437
1438 if (strstr(boot_command_line, "console=ttyS"))
1439 /* user set a ttyS based name for the console */
1440 return 0;
1441
1442 omap_str = strstr(boot_command_line, "console=ttyO");
1443 if (!omap_str)
1444 /* user did not set ttyO based console, so we don't care */
1445 return 0;
1446
1447 omap_str += 12;
1448 if ('0' <= *omap_str && *omap_str <= '9')
1449 idx = *omap_str - '0';
1450 else
1451 return 0;
1452
1453 omap_str++;
1454 if (omap_str[0] == ',') {
1455 omap_str++;
1456 options = omap_str;
1457 } else {
1458 options = NULL;
1459 }
1460
1461 add_preferred_console("ttyS", idx, options);
1462 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n",
1463 idx, idx);
1464 pr_err("This ensures that you still see kernel messages. Please\n");
1465 pr_err("update your kernel commandline.\n");
1466 return 0;
1467 }
1468 console_initcall(omap8250_console_fixup);
1469 #endif
1470
1471 static const struct dev_pm_ops omap8250_dev_pm_ops = {
1472 SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume)
1473 SET_RUNTIME_PM_OPS(omap8250_runtime_suspend,
1474 omap8250_runtime_resume, NULL)
1475 .prepare = omap8250_prepare,
1476 .complete = omap8250_complete,
1477 };
1478
1479 static struct platform_driver omap8250_platform_driver = {
1480 .driver = {
1481 .name = "omap8250",
1482 .pm = &omap8250_dev_pm_ops,
1483 .of_match_table = omap8250_dt_ids,
1484 },
1485 .probe = omap8250_probe,
1486 .remove = omap8250_remove,
1487 };
1488 module_platform_driver(omap8250_platform_driver);
1489
1490 MODULE_AUTHOR("Sebastian Andrzej Siewior");
1491 MODULE_DESCRIPTION("OMAP 8250 Driver");
1492 MODULE_LICENSE("GPL v2");
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