?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
x86/topology: Update the 'cpu cores' field in /proc/cpuinfo correctly across CPU...
[cris-mirror.git] / drivers / tty / serial / bfin_sport_uart.c
blob4ccca5d22f4fc0a7f09a6d5262c7910e946245fa
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Blackfin On-Chip Sport Emulated UART Driver
4 *
5 * Copyright 2006-2009 Analog Devices Inc.
6 *
7 * Enter bugs at http://blackfin.uclinux.org/
8 */
9
10 /*
11 * This driver and the hardware supported are in term of EE-191 of ADI.
12 * http://www.analog.com/static/imported-files/application_notes/EE191.pdf
13 * This application note describe how to implement a UART on a Sharc DSP,
14 * but this driver is implemented on Blackfin Processor.
15 * Transmit Frame Sync is not used by this driver to transfer data out.
16 */
17
18 /* #define DEBUG */
19
20 #define DRV_NAME "bfin-sport-uart"
21 #define DEVICE_NAME "ttySS"
22 #define pr_fmt(fmt) DRV_NAME ": " fmt
23
24 #include <linux/module.h>
25 #include <linux/ioport.h>
26 #include <linux/io.h>
27 #include <linux/init.h>
28 #include <linux/console.h>
29 #include <linux/sysrq.h>
30 #include <linux/slab.h>
31 #include <linux/platform_device.h>
32 #include <linux/tty.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial_core.h>
35 #include <linux/gpio.h>
36
37 #include <asm/bfin_sport.h>
38 #include <asm/delay.h>
39 #include <asm/portmux.h>
40
41 #include "bfin_sport_uart.h"
42
43 struct sport_uart_port {
44 struct uart_port port;
45 int err_irq;
46 unsigned short csize;
47 unsigned short rxmask;
48 unsigned short txmask1;
49 unsigned short txmask2;
50 unsigned char stopb;
51 /* unsigned char parib; */
52 #ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
53 int cts_pin;
54 int rts_pin;
55 #endif
56 };
57
58 static int sport_uart_tx_chars(struct sport_uart_port *up);
59 static void sport_stop_tx(struct uart_port *port);
60
61 static inline void tx_one_byte(struct sport_uart_port *up, unsigned int value)
62 {
63 pr_debug("%s value:%x, mask1=0x%x, mask2=0x%x\n", __func__, value,
64 up->txmask1, up->txmask2);
65
66 /* Place Start and Stop bits */
67 __asm__ __volatile__ (
68 "%[val] <<= 1;"
69 "%[val] = %[val] & %[mask1];"
70 "%[val] = %[val] | %[mask2];"
71 : [val]"+d"(value)
72 : [mask1]"d"(up->txmask1), [mask2]"d"(up->txmask2)
73 : "ASTAT"
74 );
75 pr_debug("%s value:%x\n", __func__, value);
76
77 SPORT_PUT_TX(up, value);
78 }
79
80 static inline unsigned char rx_one_byte(struct sport_uart_port *up)
81 {
82 unsigned int value;
83 unsigned char extract;
84 u32 tmp_mask1, tmp_mask2, tmp_shift, tmp;
85
86 if ((up->csize + up->stopb) > 7)
87 value = SPORT_GET_RX32(up);
88 else
89 value = SPORT_GET_RX(up);
90
91 pr_debug("%s value:%x, cs=%d, mask=0x%x\n", __func__, value,
92 up->csize, up->rxmask);
93
94 /* Extract data */
95 __asm__ __volatile__ (
96 "%[extr] = 0;"
97 "%[mask1] = %[rxmask];"
98 "%[mask2] = 0x0200(Z);"
99 "%[shift] = 0;"
100 "LSETUP(.Lloop_s, .Lloop_e) LC0 = %[lc];"
101 ".Lloop_s:"
102 "%[tmp] = extract(%[val], %[mask1].L)(Z);"
103 "%[tmp] <<= %[shift];"
104 "%[extr] = %[extr] | %[tmp];"
105 "%[mask1] = %[mask1] - %[mask2];"
106 ".Lloop_e:"
107 "%[shift] += 1;"
108 : [extr]"=&d"(extract), [shift]"=&d"(tmp_shift), [tmp]"=&d"(tmp),
109 [mask1]"=&d"(tmp_mask1), [mask2]"=&d"(tmp_mask2)
110 : [val]"d"(value), [rxmask]"d"(up->rxmask), [lc]"a"(up->csize)
111 : "ASTAT", "LB0", "LC0", "LT0"
112 );
113
114 pr_debug(" extract:%x\n", extract);
115 return extract;
116 }
117
118 static int sport_uart_setup(struct sport_uart_port *up, int size, int baud_rate)
119 {
120 int tclkdiv, rclkdiv;
121 unsigned int sclk = get_sclk();
122
123 /* Set TCR1 and TCR2, TFSR is not enabled for uart */
124 SPORT_PUT_TCR1(up, (LATFS | ITFS | TFSR | TLSBIT | ITCLK));
125 SPORT_PUT_TCR2(up, size + 1);
126 pr_debug("%s TCR1:%x, TCR2:%x\n", __func__, SPORT_GET_TCR1(up), SPORT_GET_TCR2(up));
127
128 /* Set RCR1 and RCR2 */
129 SPORT_PUT_RCR1(up, (RCKFE | LARFS | LRFS | RFSR | IRCLK));
130 SPORT_PUT_RCR2(up, (size + 1) * 2 - 1);
131 pr_debug("%s RCR1:%x, RCR2:%x\n", __func__, SPORT_GET_RCR1(up), SPORT_GET_RCR2(up));
132
133 tclkdiv = sclk / (2 * baud_rate) - 1;
134 /* The actual uart baud rate of devices vary between +/-2%. The sport
135 * RX sample rate should be faster than the double of the worst case,
136 * otherwise, wrong data are received. So, set sport RX clock to be
137 * 3% faster.
138 */
139 rclkdiv = sclk / (2 * baud_rate * 2 * 97 / 100) - 1;
140 SPORT_PUT_TCLKDIV(up, tclkdiv);
141 SPORT_PUT_RCLKDIV(up, rclkdiv);
142 SSYNC();
143 pr_debug("%s sclk:%d, baud_rate:%d, tclkdiv:%d, rclkdiv:%d\n",
144 __func__, sclk, baud_rate, tclkdiv, rclkdiv);
145
146 return 0;
147 }
148
149 static irqreturn_t sport_uart_rx_irq(int irq, void *dev_id)
150 {
151 struct sport_uart_port *up = dev_id;
152 struct tty_port *port = &up->port.state->port;
153 unsigned int ch;
154
155 spin_lock(&up->port.lock);
156
157 while (SPORT_GET_STAT(up) & RXNE) {
158 ch = rx_one_byte(up);
159 up->port.icount.rx++;
160
161 if (!uart_handle_sysrq_char(&up->port, ch))
162 tty_insert_flip_char(port, ch, TTY_NORMAL);
163 }
164
165 spin_unlock(&up->port.lock);
166
167 /* XXX this won't deadlock with lowlat? */
168 tty_flip_buffer_push(port);
169
170 return IRQ_HANDLED;
171 }
172
173 static irqreturn_t sport_uart_tx_irq(int irq, void *dev_id)
174 {
175 struct sport_uart_port *up = dev_id;
176
177 spin_lock(&up->port.lock);
178 sport_uart_tx_chars(up);
179 spin_unlock(&up->port.lock);
180
181 return IRQ_HANDLED;
182 }
183
184 static irqreturn_t sport_uart_err_irq(int irq, void *dev_id)
185 {
186 struct sport_uart_port *up = dev_id;
187 unsigned int stat = SPORT_GET_STAT(up);
188
189 spin_lock(&up->port.lock);
190
191 /* Overflow in RX FIFO */
192 if (stat & ROVF) {
193 up->port.icount.overrun++;
194 tty_insert_flip_char(&up->port.state->port, 0, TTY_OVERRUN);
195 SPORT_PUT_STAT(up, ROVF); /* Clear ROVF bit */
196 }
197 /* These should not happen */
198 if (stat & (TOVF | TUVF | RUVF)) {
199 pr_err("SPORT Error:%s %s %s\n",
200 (stat & TOVF) ? "TX overflow" : "",
201 (stat & TUVF) ? "TX underflow" : "",
202 (stat & RUVF) ? "RX underflow" : "");
203 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
204 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN);
205 }
206 SSYNC();
207
208 spin_unlock(&up->port.lock);
209 /* XXX we don't push the overrun bit to TTY? */
210
211 return IRQ_HANDLED;
212 }
213
214 #ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
215 static unsigned int sport_get_mctrl(struct uart_port *port)
216 {
217 struct sport_uart_port *up = (struct sport_uart_port *)port;
218 if (up->cts_pin < 0)
219 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
220
221 /* CTS PIN is negative assertive. */
222 if (SPORT_UART_GET_CTS(up))
223 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
224 else
225 return TIOCM_DSR | TIOCM_CAR;
226 }
227
228 static void sport_set_mctrl(struct uart_port *port, unsigned int mctrl)
229 {
230 struct sport_uart_port *up = (struct sport_uart_port *)port;
231 if (up->rts_pin < 0)
232 return;
233
234 /* RTS PIN is negative assertive. */
235 if (mctrl & TIOCM_RTS)
236 SPORT_UART_ENABLE_RTS(up);
237 else
238 SPORT_UART_DISABLE_RTS(up);
239 }
240
241 /*
242 * Handle any change of modem status signal.
243 */
244 static irqreturn_t sport_mctrl_cts_int(int irq, void *dev_id)
245 {
246 struct sport_uart_port *up = (struct sport_uart_port *)dev_id;
247 unsigned int status;
248
249 status = sport_get_mctrl(&up->port);
250 uart_handle_cts_change(&up->port, status & TIOCM_CTS);
251
252 return IRQ_HANDLED;
253 }
254 #else
255 static unsigned int sport_get_mctrl(struct uart_port *port)
256 {
257 pr_debug("%s enter\n", __func__);
258 return TIOCM_CTS | TIOCM_CD | TIOCM_DSR;
259 }
260
261 static void sport_set_mctrl(struct uart_port *port, unsigned int mctrl)
262 {
263 pr_debug("%s enter\n", __func__);
264 }
265 #endif
266
267 /* Reqeust IRQ, Setup clock */
268 static int sport_startup(struct uart_port *port)
269 {
270 struct sport_uart_port *up = (struct sport_uart_port *)port;
271 int ret;
272
273 pr_debug("%s enter\n", __func__);
274 ret = request_irq(up->port.irq, sport_uart_rx_irq, 0,
275 "SPORT_UART_RX", up);
276 if (ret) {
277 dev_err(port->dev, "unable to request SPORT RX interrupt\n");
278 return ret;
279 }
280
281 ret = request_irq(up->port.irq+1, sport_uart_tx_irq, 0,
282 "SPORT_UART_TX", up);
283 if (ret) {
284 dev_err(port->dev, "unable to request SPORT TX interrupt\n");
285 goto fail1;
286 }
287
288 ret = request_irq(up->err_irq, sport_uart_err_irq, 0,
289 "SPORT_UART_STATUS", up);
290 if (ret) {
291 dev_err(port->dev, "unable to request SPORT status interrupt\n");
292 goto fail2;
293 }
294
295 #ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
296 if (up->cts_pin >= 0) {
297 if (request_irq(gpio_to_irq(up->cts_pin),
298 sport_mctrl_cts_int,
299 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
300 0, "BFIN_SPORT_UART_CTS", up)) {
301 up->cts_pin = -1;
302 dev_info(port->dev, "Unable to attach BlackFin UART over SPORT CTS interrupt. So, disable it.\n");
303 }
304 }
305 if (up->rts_pin >= 0) {
306 if (gpio_request(up->rts_pin, DRV_NAME)) {
307 dev_info(port->dev, "fail to request RTS PIN at GPIO_%d\n", up->rts_pin);
308 up->rts_pin = -1;
309 } else
310 gpio_direction_output(up->rts_pin, 0);
311 }
312 #endif
313
314 return 0;
315 fail2:
316 free_irq(up->port.irq+1, up);
317 fail1:
318 free_irq(up->port.irq, up);
319
320 return ret;
321 }
322
323 /*
324 * sport_uart_tx_chars
325 *
326 * ret 1 means need to enable sport.
327 * ret 0 means do nothing.
328 */
329 static int sport_uart_tx_chars(struct sport_uart_port *up)
330 {
331 struct circ_buf *xmit = &up->port.state->xmit;
332
333 if (SPORT_GET_STAT(up) & TXF)
334 return 0;
335
336 if (up->port.x_char) {
337 tx_one_byte(up, up->port.x_char);
338 up->port.icount.tx++;
339 up->port.x_char = 0;
340 return 1;
341 }
342
343 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
344 /* The waiting loop to stop SPORT TX from TX interrupt is
345 * too long. This may block SPORT RX interrupts and cause
346 * RX FIFO overflow. So, do stop sport TX only after the last
347 * char in TX FIFO is moved into the shift register.
348 */
349 if (SPORT_GET_STAT(up) & TXHRE)
350 sport_stop_tx(&up->port);
351 return 0;
352 }
353
354 while(!(SPORT_GET_STAT(up) & TXF) && !uart_circ_empty(xmit)) {
355 tx_one_byte(up, xmit->buf[xmit->tail]);
356 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE -1);
357 up->port.icount.tx++;
358 }
359
360 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
361 uart_write_wakeup(&up->port);
362
363 return 1;
364 }
365
366 static unsigned int sport_tx_empty(struct uart_port *port)
367 {
368 struct sport_uart_port *up = (struct sport_uart_port *)port;
369 unsigned int stat;
370
371 stat = SPORT_GET_STAT(up);
372 pr_debug("%s stat:%04x\n", __func__, stat);
373 if (stat & TXHRE) {
374 return TIOCSER_TEMT;
375 } else
376 return 0;
377 }
378
379 static void sport_stop_tx(struct uart_port *port)
380 {
381 struct sport_uart_port *up = (struct sport_uart_port *)port;
382
383 pr_debug("%s enter\n", __func__);
384
385 if (!(SPORT_GET_TCR1(up) & TSPEN))
386 return;
387
388 /* Although the hold register is empty, last byte is still in shift
389 * register and not sent out yet. So, put a dummy data into TX FIFO.
390 * Then, sport tx stops when last byte is shift out and the dummy
391 * data is moved into the shift register.
392 */
393 SPORT_PUT_TX(up, 0xffff);
394 while (!(SPORT_GET_STAT(up) & TXHRE))
395 cpu_relax();
396
397 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
398 SSYNC();
399
400 return;
401 }
402
403 static void sport_start_tx(struct uart_port *port)
404 {
405 struct sport_uart_port *up = (struct sport_uart_port *)port;
406
407 pr_debug("%s enter\n", __func__);
408
409 /* Write data into SPORT FIFO before enable SPROT to transmit */
410 if (sport_uart_tx_chars(up)) {
411 /* Enable transmit, then an interrupt will generated */
412 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
413 SSYNC();
414 }
415
416 pr_debug("%s exit\n", __func__);
417 }
418
419 static void sport_stop_rx(struct uart_port *port)
420 {
421 struct sport_uart_port *up = (struct sport_uart_port *)port;
422
423 pr_debug("%s enter\n", __func__);
424 /* Disable sport to stop rx */
425 SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN));
426 SSYNC();
427 }
428
429 static void sport_break_ctl(struct uart_port *port, int break_state)
430 {
431 pr_debug("%s enter\n", __func__);
432 }
433
434 static void sport_shutdown(struct uart_port *port)
435 {
436 struct sport_uart_port *up = (struct sport_uart_port *)port;
437
438 dev_dbg(port->dev, "%s enter\n", __func__);
439
440 /* Disable sport */
441 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
442 SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN));
443 SSYNC();
444
445 free_irq(up->port.irq, up);
446 free_irq(up->port.irq+1, up);
447 free_irq(up->err_irq, up);
448 #ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
449 if (up->cts_pin >= 0)
450 free_irq(gpio_to_irq(up->cts_pin), up);
451 if (up->rts_pin >= 0)
452 gpio_free(up->rts_pin);
453 #endif
454 }
455
456 static const char *sport_type(struct uart_port *port)
457 {
458 struct sport_uart_port *up = (struct sport_uart_port *)port;
459
460 pr_debug("%s enter\n", __func__);
461 return up->port.type == PORT_BFIN_SPORT ? "BFIN-SPORT-UART" : NULL;
462 }
463
464 static void sport_release_port(struct uart_port *port)
465 {
466 pr_debug("%s enter\n", __func__);
467 }
468
469 static int sport_request_port(struct uart_port *port)
470 {
471 pr_debug("%s enter\n", __func__);
472 return 0;
473 }
474
475 static void sport_config_port(struct uart_port *port, int flags)
476 {
477 struct sport_uart_port *up = (struct sport_uart_port *)port;
478
479 pr_debug("%s enter\n", __func__);
480 up->port.type = PORT_BFIN_SPORT;
481 }
482
483 static int sport_verify_port(struct uart_port *port, struct serial_struct *ser)
484 {
485 pr_debug("%s enter\n", __func__);
486 return 0;
487 }
488
489 static void sport_set_termios(struct uart_port *port,
490 struct ktermios *termios, struct ktermios *old)
491 {
492 struct sport_uart_port *up = (struct sport_uart_port *)port;
493 unsigned long flags;
494 int i;
495
496 pr_debug("%s enter, c_cflag:%08x\n", __func__, termios->c_cflag);
497
498 #ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
499 if (old == NULL && up->cts_pin != -1)
500 termios->c_cflag |= CRTSCTS;
501 else if (up->cts_pin == -1)
502 termios->c_cflag &= ~CRTSCTS;
503 #endif
504
505 switch (termios->c_cflag & CSIZE) {
506 case CS8:
507 up->csize = 8;
508 break;
509 case CS7:
510 up->csize = 7;
511 break;
512 case CS6:
513 up->csize = 6;
514 break;
515 case CS5:
516 up->csize = 5;
517 break;
518 default:
519 pr_warn("requested word length not supported\n");
520 break;
521 }
522
523 if (termios->c_cflag & CSTOPB) {
524 up->stopb = 1;
525 }
526 if (termios->c_cflag & PARENB) {
527 pr_warn("PAREN bit is not supported yet\n");
528 /* up->parib = 1; */
529 }
530
531 spin_lock_irqsave(&up->port.lock, flags);
532
533 port->read_status_mask = 0;
534
535 /*
536 * Characters to ignore
537 */
538 port->ignore_status_mask = 0;
539
540 /* RX extract mask */
541 up->rxmask = 0x01 | (((up->csize + up->stopb) * 2 - 1) << 0x8);
542 /* TX masks, 8 bit data and 1 bit stop for example:
543 * mask1 = b#0111111110
544 * mask2 = b#1000000000
545 */
546 for (i = 0, up->txmask1 = 0; i < up->csize; i++)
547 up->txmask1 |= (1<<i);
548 up->txmask2 = (1<<i);
549 if (up->stopb) {
550 ++i;
551 up->txmask2 |= (1<<i);
552 }
553 up->txmask1 <<= 1;
554 up->txmask2 <<= 1;
555 /* uart baud rate */
556 port->uartclk = uart_get_baud_rate(port, termios, old, 0, get_sclk()/16);
557
558 /* Disable UART */
559 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
560 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN);
561
562 sport_uart_setup(up, up->csize + up->stopb, port->uartclk);
563
564 /* driver TX line high after config, one dummy data is
565 * necessary to stop sport after shift one byte
566 */
567 SPORT_PUT_TX(up, 0xffff);
568 SPORT_PUT_TX(up, 0xffff);
569 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
570 SSYNC();
571 while (!(SPORT_GET_STAT(up) & TXHRE))
572 cpu_relax();
573 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
574 SSYNC();
575
576 /* Port speed changed, update the per-port timeout. */
577 uart_update_timeout(port, termios->c_cflag, port->uartclk);
578
579 /* Enable sport rx */
580 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) | RSPEN);
581 SSYNC();
582
583 spin_unlock_irqrestore(&up->port.lock, flags);
584 }
585
586 static const struct uart_ops sport_uart_ops = {
587 .tx_empty = sport_tx_empty,
588 .set_mctrl = sport_set_mctrl,
589 .get_mctrl = sport_get_mctrl,
590 .stop_tx = sport_stop_tx,
591 .start_tx = sport_start_tx,
592 .stop_rx = sport_stop_rx,
593 .break_ctl = sport_break_ctl,
594 .startup = sport_startup,
595 .shutdown = sport_shutdown,
596 .set_termios = sport_set_termios,
597 .type = sport_type,
598 .release_port = sport_release_port,
599 .request_port = sport_request_port,
600 .config_port = sport_config_port,
601 .verify_port = sport_verify_port,
602 };
603
604 #define BFIN_SPORT_UART_MAX_PORTS 4
605
606 static struct sport_uart_port *bfin_sport_uart_ports[BFIN_SPORT_UART_MAX_PORTS];
607
608 #ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
609 #define CLASS_BFIN_SPORT_CONSOLE "bfin-sport-console"
610
611 static int __init
612 sport_uart_console_setup(struct console *co, char *options)
613 {
614 struct sport_uart_port *up;
615 int baud = 57600;
616 int bits = 8;
617 int parity = 'n';
618 # ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
619 int flow = 'r';
620 # else
621 int flow = 'n';
622 # endif
623
624 /* Check whether an invalid uart number has been specified */
625 if (co->index < 0 || co->index >= BFIN_SPORT_UART_MAX_PORTS)
626 return -ENODEV;
627
628 up = bfin_sport_uart_ports[co->index];
629 if (!up)
630 return -ENODEV;
631
632 if (options)
633 uart_parse_options(options, &baud, &parity, &bits, &flow);
634
635 return uart_set_options(&up->port, co, baud, parity, bits, flow);
636 }
637
638 static void sport_uart_console_putchar(struct uart_port *port, int ch)
639 {
640 struct sport_uart_port *up = (struct sport_uart_port *)port;
641
642 while (SPORT_GET_STAT(up) & TXF)
643 barrier();
644
645 tx_one_byte(up, ch);
646 }
647
648 /*
649 * Interrupts are disabled on entering
650 */
651 static void
652 sport_uart_console_write(struct console *co, const char *s, unsigned int count)
653 {
654 struct sport_uart_port *up = bfin_sport_uart_ports[co->index];
655 unsigned long flags;
656
657 spin_lock_irqsave(&up->port.lock, flags);
658
659 if (SPORT_GET_TCR1(up) & TSPEN)
660 uart_console_write(&up->port, s, count, sport_uart_console_putchar);
661 else {
662 /* dummy data to start sport */
663 while (SPORT_GET_STAT(up) & TXF)
664 barrier();
665 SPORT_PUT_TX(up, 0xffff);
666 /* Enable transmit, then an interrupt will generated */
667 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
668 SSYNC();
669
670 uart_console_write(&up->port, s, count, sport_uart_console_putchar);
671
672 /* Although the hold register is empty, last byte is still in shift
673 * register and not sent out yet. So, put a dummy data into TX FIFO.
674 * Then, sport tx stops when last byte is shift out and the dummy
675 * data is moved into the shift register.
676 */
677 while (SPORT_GET_STAT(up) & TXF)
678 barrier();
679 SPORT_PUT_TX(up, 0xffff);
680 while (!(SPORT_GET_STAT(up) & TXHRE))
681 barrier();
682
683 /* Stop sport tx transfer */
684 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
685 SSYNC();
686 }
687
688 spin_unlock_irqrestore(&up->port.lock, flags);
689 }
690
691 static struct uart_driver sport_uart_reg;
692
693 static struct console sport_uart_console = {
694 .name = DEVICE_NAME,
695 .write = sport_uart_console_write,
696 .device = uart_console_device,
697 .setup = sport_uart_console_setup,
698 .flags = CON_PRINTBUFFER,
699 .index = -1,
700 .data = &sport_uart_reg,
701 };
702
703 #define SPORT_UART_CONSOLE (&sport_uart_console)
704 #else
705 #define SPORT_UART_CONSOLE NULL
706 #endif /* CONFIG_SERIAL_BFIN_SPORT_CONSOLE */
707
708
709 static struct uart_driver sport_uart_reg = {
710 .owner = THIS_MODULE,
711 .driver_name = DRV_NAME,
712 .dev_name = DEVICE_NAME,
713 .major = 204,
714 .minor = 84,
715 .nr = BFIN_SPORT_UART_MAX_PORTS,
716 .cons = SPORT_UART_CONSOLE,
717 };
718
719 #ifdef CONFIG_PM
720 static int sport_uart_suspend(struct device *dev)
721 {
722 struct sport_uart_port *sport = dev_get_drvdata(dev);
723
724 dev_dbg(dev, "%s enter\n", __func__);
725 if (sport)
726 uart_suspend_port(&sport_uart_reg, &sport->port);
727
728 return 0;
729 }
730
731 static int sport_uart_resume(struct device *dev)
732 {
733 struct sport_uart_port *sport = dev_get_drvdata(dev);
734
735 dev_dbg(dev, "%s enter\n", __func__);
736 if (sport)
737 uart_resume_port(&sport_uart_reg, &sport->port);
738
739 return 0;
740 }
741
742 static const struct dev_pm_ops bfin_sport_uart_dev_pm_ops = {
743 .suspend = sport_uart_suspend,
744 .resume = sport_uart_resume,
745 };
746 #endif
747
748 static int sport_uart_probe(struct platform_device *pdev)
749 {
750 struct resource *res;
751 struct sport_uart_port *sport;
752 int ret = 0;
753
754 dev_dbg(&pdev->dev, "%s enter\n", __func__);
755
756 if (pdev->id < 0 || pdev->id >= BFIN_SPORT_UART_MAX_PORTS) {
757 dev_err(&pdev->dev, "Wrong sport uart platform device id.\n");
758 return -ENOENT;
759 }
760
761 if (bfin_sport_uart_ports[pdev->id] == NULL) {
762 bfin_sport_uart_ports[pdev->id] =
763 kzalloc(sizeof(struct sport_uart_port), GFP_KERNEL);
764 sport = bfin_sport_uart_ports[pdev->id];
765 if (!sport) {
766 dev_err(&pdev->dev,
767 "Fail to malloc sport_uart_port\n");
768 return -ENOMEM;
769 }
770
771 ret = peripheral_request_list(dev_get_platdata(&pdev->dev),
772 DRV_NAME);
773 if (ret) {
774 dev_err(&pdev->dev,
775 "Fail to request SPORT peripherals\n");
776 goto out_error_free_mem;
777 }
778
779 spin_lock_init(&sport->port.lock);
780 sport->port.fifosize = SPORT_TX_FIFO_SIZE,
781 sport->port.ops = &sport_uart_ops;
782 sport->port.line = pdev->id;
783 sport->port.iotype = UPIO_MEM;
784 sport->port.flags = UPF_BOOT_AUTOCONF;
785
786 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
787 if (res == NULL) {
788 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
789 ret = -ENOENT;
790 goto out_error_free_peripherals;
791 }
792
793 sport->port.membase = ioremap(res->start, resource_size(res));
794 if (!sport->port.membase) {
795 dev_err(&pdev->dev, "Cannot map sport IO\n");
796 ret = -ENXIO;
797 goto out_error_free_peripherals;
798 }
799 sport->port.mapbase = res->start;
800
801 sport->port.irq = platform_get_irq(pdev, 0);
802 if ((int)sport->port.irq < 0) {
803 dev_err(&pdev->dev, "No sport RX/TX IRQ specified\n");
804 ret = -ENOENT;
805 goto out_error_unmap;
806 }
807
808 sport->err_irq = platform_get_irq(pdev, 1);
809 if (sport->err_irq < 0) {
810 dev_err(&pdev->dev, "No sport status IRQ specified\n");
811 ret = -ENOENT;
812 goto out_error_unmap;
813 }
814 #ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
815 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
816 if (res == NULL)
817 sport->cts_pin = -1;
818 else
819 sport->cts_pin = res->start;
820
821 res = platform_get_resource(pdev, IORESOURCE_IO, 1);
822 if (res == NULL)
823 sport->rts_pin = -1;
824 else
825 sport->rts_pin = res->start;
826 #endif
827 }
828
829 #ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
830 if (!is_early_platform_device(pdev)) {
831 #endif
832 sport = bfin_sport_uart_ports[pdev->id];
833 sport->port.dev = &pdev->dev;
834 dev_set_drvdata(&pdev->dev, sport);
835 ret = uart_add_one_port(&sport_uart_reg, &sport->port);
836 #ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
837 }
838 #endif
839 if (!ret)
840 return 0;
841
842 if (sport) {
843 out_error_unmap:
844 iounmap(sport->port.membase);
845 out_error_free_peripherals:
846 peripheral_free_list(dev_get_platdata(&pdev->dev));
847 out_error_free_mem:
848 kfree(sport);
849 bfin_sport_uart_ports[pdev->id] = NULL;
850 }
851
852 return ret;
853 }
854
855 static int sport_uart_remove(struct platform_device *pdev)
856 {
857 struct sport_uart_port *sport = platform_get_drvdata(pdev);
858
859 dev_dbg(&pdev->dev, "%s enter\n", __func__);
860 dev_set_drvdata(&pdev->dev, NULL);
861
862 if (sport) {
863 uart_remove_one_port(&sport_uart_reg, &sport->port);
864 iounmap(sport->port.membase);
865 peripheral_free_list(dev_get_platdata(&pdev->dev));
866 kfree(sport);
867 bfin_sport_uart_ports[pdev->id] = NULL;
868 }
869
870 return 0;
871 }
872
873 static struct platform_driver sport_uart_driver = {
874 .probe = sport_uart_probe,
875 .remove = sport_uart_remove,
876 .driver = {
877 .name = DRV_NAME,
878 #ifdef CONFIG_PM
879 .pm = &bfin_sport_uart_dev_pm_ops,
880 #endif
881 },
882 };
883
884 #ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
885 static struct early_platform_driver early_sport_uart_driver __initdata = {
886 .class_str = CLASS_BFIN_SPORT_CONSOLE,
887 .pdrv = &sport_uart_driver,
888 .requested_id = EARLY_PLATFORM_ID_UNSET,
889 };
890
891 static int __init sport_uart_rs_console_init(void)
892 {
893 early_platform_driver_register(&early_sport_uart_driver, DRV_NAME);
894
895 early_platform_driver_probe(CLASS_BFIN_SPORT_CONSOLE,
896 BFIN_SPORT_UART_MAX_PORTS, 0);
897
898 register_console(&sport_uart_console);
899
900 return 0;
901 }
902 console_initcall(sport_uart_rs_console_init);
903 #endif
904
905 static int __init sport_uart_init(void)
906 {
907 int ret;
908
909 pr_info("Blackfin uart over sport driver\n");
910
911 ret = uart_register_driver(&sport_uart_reg);
912 if (ret) {
913 pr_err("failed to register %s:%d\n",
914 sport_uart_reg.driver_name, ret);
915 return ret;
916 }
917
918 ret = platform_driver_register(&sport_uart_driver);
919 if (ret) {
920 pr_err("failed to register sport uart driver:%d\n", ret);
921 uart_unregister_driver(&sport_uart_reg);
922 }
923
924 return ret;
925 }
926 module_init(sport_uart_init);
927
928 static void __exit sport_uart_exit(void)
929 {
930 platform_driver_unregister(&sport_uart_driver);
931 uart_unregister_driver(&sport_uart_reg);
932 }
933 module_exit(sport_uart_exit);
934
935 MODULE_AUTHOR("Sonic Zhang, Roy Huang");
936 MODULE_DESCRIPTION("Blackfin serial over SPORT driver");
937 MODULE_LICENSE("GPL");
CRIS linux kernel tree