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kvm,mips: Fix potential swait_active() races
[cris-mirror.git] / drivers / iommu / amd_iommu.c
blob4ad7e5e31943db7b1d1d90850fac652fbfeb8ed6
1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/acpi.h>
23 #include <linux/amba/bus.h>
24 #include <linux/platform_device.h>
25 #include <linux/pci-ats.h>
26 #include <linux/bitmap.h>
27 #include <linux/slab.h>
28 #include <linux/debugfs.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/iommu-helper.h>
32 #include <linux/iommu.h>
33 #include <linux/delay.h>
34 #include <linux/amd-iommu.h>
35 #include <linux/notifier.h>
36 #include <linux/export.h>
37 #include <linux/irq.h>
38 #include <linux/msi.h>
39 #include <linux/dma-contiguous.h>
40 #include <linux/irqdomain.h>
41 #include <linux/percpu.h>
42 #include <linux/iova.h>
43 #include <asm/irq_remapping.h>
44 #include <asm/io_apic.h>
45 #include <asm/apic.h>
46 #include <asm/hw_irq.h>
47 #include <asm/msidef.h>
48 #include <asm/proto.h>
49 #include <asm/iommu.h>
50 #include <asm/gart.h>
51 #include <asm/dma.h>
52
53 #include "amd_iommu_proto.h"
54 #include "amd_iommu_types.h"
55 #include "irq_remapping.h"
56
57 #define AMD_IOMMU_MAPPING_ERROR 0
58
59 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
60
61 #define LOOP_TIMEOUT 100000
62
63 /* IO virtual address start page frame number */
64 #define IOVA_START_PFN (1)
65 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
66 #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
67
68 /* Reserved IOVA ranges */
69 #define MSI_RANGE_START (0xfee00000)
70 #define MSI_RANGE_END (0xfeefffff)
71 #define HT_RANGE_START (0xfd00000000ULL)
72 #define HT_RANGE_END (0xffffffffffULL)
73
74 /*
75 * This bitmap is used to advertise the page sizes our hardware support
76 * to the IOMMU core, which will then use this information to split
77 * physically contiguous memory regions it is mapping into page sizes
78 * that we support.
79 *
80 * 512GB Pages are not supported due to a hardware bug
81 */
82 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
83
84 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
85
86 /* List of all available dev_data structures */
87 static LIST_HEAD(dev_data_list);
88 static DEFINE_SPINLOCK(dev_data_list_lock);
89
90 LIST_HEAD(ioapic_map);
91 LIST_HEAD(hpet_map);
92 LIST_HEAD(acpihid_map);
93
94 /*
95 * Domain for untranslated devices - only allocated
96 * if iommu=pt passed on kernel cmd line.
97 */
98 const struct iommu_ops amd_iommu_ops;
99
100 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
101 int amd_iommu_max_glx_val = -1;
102
103 static const struct dma_map_ops amd_iommu_dma_ops;
104
105 /*
106 * This struct contains device specific data for the IOMMU
107 */
108 struct iommu_dev_data {
109 struct list_head list; /* For domain->dev_list */
110 struct list_head dev_data_list; /* For global dev_data_list */
111 struct protection_domain *domain; /* Domain the device is bound to */
112 u16 devid; /* PCI Device ID */
113 u16 alias; /* Alias Device ID */
114 bool iommu_v2; /* Device can make use of IOMMUv2 */
115 bool passthrough; /* Device is identity mapped */
116 struct {
117 bool enabled;
118 int qdep;
119 } ats; /* ATS state */
120 bool pri_tlp; /* PASID TLB required for
121 PPR completions */
122 u32 errata; /* Bitmap for errata to apply */
123 bool use_vapic; /* Enable device to use vapic mode */
124
125 struct ratelimit_state rs; /* Ratelimit IOPF messages */
126 };
127
128 /*
129 * general struct to manage commands send to an IOMMU
130 */
131 struct iommu_cmd {
132 u32 data[4];
133 };
134
135 struct kmem_cache *amd_iommu_irq_cache;
136
137 static void update_domain(struct protection_domain *domain);
138 static int protection_domain_init(struct protection_domain *domain);
139 static void detach_device(struct device *dev);
140
141 #define FLUSH_QUEUE_SIZE 256
142
143 struct flush_queue_entry {
144 unsigned long iova_pfn;
145 unsigned long pages;
146 u64 counter; /* Flush counter when this entry was added to the queue */
147 };
148
149 struct flush_queue {
150 struct flush_queue_entry *entries;
151 unsigned head, tail;
152 spinlock_t lock;
153 };
154
155 /*
156 * Data container for a dma_ops specific protection domain
157 */
158 struct dma_ops_domain {
159 /* generic protection domain information */
160 struct protection_domain domain;
161
162 /* IOVA RB-Tree */
163 struct iova_domain iovad;
164
165 struct flush_queue __percpu *flush_queue;
166
167 /*
168 * We need two counter here to be race-free wrt. IOTLB flushing and
169 * adding entries to the flush queue.
170 *
171 * The flush_start_cnt is incremented _before_ the IOTLB flush starts.
172 * New entries added to the flush ring-buffer get their 'counter' value
173 * from here. This way we can make sure that entries added to the queue
174 * (or other per-cpu queues of the same domain) while the TLB is about
175 * to be flushed are not considered to be flushed already.
176 */
177 atomic64_t flush_start_cnt;
178
179 /*
180 * The flush_finish_cnt is incremented when an IOTLB flush is complete.
181 * This value is always smaller than flush_start_cnt. The queue_add
182 * function frees all IOVAs that have a counter value smaller than
183 * flush_finish_cnt. This makes sure that we only free IOVAs that are
184 * flushed out of the IOTLB of the domain.
185 */
186 atomic64_t flush_finish_cnt;
187
188 /*
189 * Timer to make sure we don't keep IOVAs around unflushed
190 * for too long
191 */
192 struct timer_list flush_timer;
193 atomic_t flush_timer_on;
194 };
195
196 static struct iova_domain reserved_iova_ranges;
197 static struct lock_class_key reserved_rbtree_key;
198
199 /****************************************************************************
200 *
201 * Helper functions
202 *
203 ****************************************************************************/
204
205 static inline int match_hid_uid(struct device *dev,
206 struct acpihid_map_entry *entry)
207 {
208 const char *hid, *uid;
209
210 hid = acpi_device_hid(ACPI_COMPANION(dev));
211 uid = acpi_device_uid(ACPI_COMPANION(dev));
212
213 if (!hid || !(*hid))
214 return -ENODEV;
215
216 if (!uid || !(*uid))
217 return strcmp(hid, entry->hid);
218
219 if (!(*entry->uid))
220 return strcmp(hid, entry->hid);
221
222 return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid));
223 }
224
225 static inline u16 get_pci_device_id(struct device *dev)
226 {
227 struct pci_dev *pdev = to_pci_dev(dev);
228
229 return PCI_DEVID(pdev->bus->number, pdev->devfn);
230 }
231
232 static inline int get_acpihid_device_id(struct device *dev,
233 struct acpihid_map_entry **entry)
234 {
235 struct acpihid_map_entry *p;
236
237 list_for_each_entry(p, &acpihid_map, list) {
238 if (!match_hid_uid(dev, p)) {
239 if (entry)
240 *entry = p;
241 return p->devid;
242 }
243 }
244 return -EINVAL;
245 }
246
247 static inline int get_device_id(struct device *dev)
248 {
249 int devid;
250
251 if (dev_is_pci(dev))
252 devid = get_pci_device_id(dev);
253 else
254 devid = get_acpihid_device_id(dev, NULL);
255
256 return devid;
257 }
258
259 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
260 {
261 return container_of(dom, struct protection_domain, domain);
262 }
263
264 static struct dma_ops_domain* to_dma_ops_domain(struct protection_domain *domain)
265 {
266 BUG_ON(domain->flags != PD_DMA_OPS_MASK);
267 return container_of(domain, struct dma_ops_domain, domain);
268 }
269
270 static struct iommu_dev_data *alloc_dev_data(u16 devid)
271 {
272 struct iommu_dev_data *dev_data;
273 unsigned long flags;
274
275 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
276 if (!dev_data)
277 return NULL;
278
279 dev_data->devid = devid;
280
281 spin_lock_irqsave(&dev_data_list_lock, flags);
282 list_add_tail(&dev_data->dev_data_list, &dev_data_list);
283 spin_unlock_irqrestore(&dev_data_list_lock, flags);
284
285 ratelimit_default_init(&dev_data->rs);
286
287 return dev_data;
288 }
289
290 static struct iommu_dev_data *search_dev_data(u16 devid)
291 {
292 struct iommu_dev_data *dev_data;
293 unsigned long flags;
294
295 spin_lock_irqsave(&dev_data_list_lock, flags);
296 list_for_each_entry(dev_data, &dev_data_list, dev_data_list) {
297 if (dev_data->devid == devid)
298 goto out_unlock;
299 }
300
301 dev_data = NULL;
302
303 out_unlock:
304 spin_unlock_irqrestore(&dev_data_list_lock, flags);
305
306 return dev_data;
307 }
308
309 static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
310 {
311 *(u16 *)data = alias;
312 return 0;
313 }
314
315 static u16 get_alias(struct device *dev)
316 {
317 struct pci_dev *pdev = to_pci_dev(dev);
318 u16 devid, ivrs_alias, pci_alias;
319
320 /* The callers make sure that get_device_id() does not fail here */
321 devid = get_device_id(dev);
322 ivrs_alias = amd_iommu_alias_table[devid];
323 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
324
325 if (ivrs_alias == pci_alias)
326 return ivrs_alias;
327
328 /*
329 * DMA alias showdown
330 *
331 * The IVRS is fairly reliable in telling us about aliases, but it
332 * can't know about every screwy device. If we don't have an IVRS
333 * reported alias, use the PCI reported alias. In that case we may
334 * still need to initialize the rlookup and dev_table entries if the
335 * alias is to a non-existent device.
336 */
337 if (ivrs_alias == devid) {
338 if (!amd_iommu_rlookup_table[pci_alias]) {
339 amd_iommu_rlookup_table[pci_alias] =
340 amd_iommu_rlookup_table[devid];
341 memcpy(amd_iommu_dev_table[pci_alias].data,
342 amd_iommu_dev_table[devid].data,
343 sizeof(amd_iommu_dev_table[pci_alias].data));
344 }
345
346 return pci_alias;
347 }
348
349 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
350 "for device %s[%04x:%04x], kernel reported alias "
351 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
352 PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device,
353 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
354 PCI_FUNC(pci_alias));
355
356 /*
357 * If we don't have a PCI DMA alias and the IVRS alias is on the same
358 * bus, then the IVRS table may know about a quirk that we don't.
359 */
360 if (pci_alias == devid &&
361 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
362 pci_add_dma_alias(pdev, ivrs_alias & 0xff);
363 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
364 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias),
365 dev_name(dev));
366 }
367
368 return ivrs_alias;
369 }
370
371 static struct iommu_dev_data *find_dev_data(u16 devid)
372 {
373 struct iommu_dev_data *dev_data;
374
375 dev_data = search_dev_data(devid);
376
377 if (dev_data == NULL)
378 dev_data = alloc_dev_data(devid);
379
380 return dev_data;
381 }
382
383 static struct iommu_dev_data *get_dev_data(struct device *dev)
384 {
385 return dev->archdata.iommu;
386 }
387
388 /*
389 * Find or create an IOMMU group for a acpihid device.
390 */
391 static struct iommu_group *acpihid_device_group(struct device *dev)
392 {
393 struct acpihid_map_entry *p, *entry = NULL;
394 int devid;
395
396 devid = get_acpihid_device_id(dev, &entry);
397 if (devid < 0)
398 return ERR_PTR(devid);
399
400 list_for_each_entry(p, &acpihid_map, list) {
401 if ((devid == p->devid) && p->group)
402 entry->group = p->group;
403 }
404
405 if (!entry->group)
406 entry->group = generic_device_group(dev);
407 else
408 iommu_group_ref_get(entry->group);
409
410 return entry->group;
411 }
412
413 static bool pci_iommuv2_capable(struct pci_dev *pdev)
414 {
415 static const int caps[] = {
416 PCI_EXT_CAP_ID_ATS,
417 PCI_EXT_CAP_ID_PRI,
418 PCI_EXT_CAP_ID_PASID,
419 };
420 int i, pos;
421
422 for (i = 0; i < 3; ++i) {
423 pos = pci_find_ext_capability(pdev, caps[i]);
424 if (pos == 0)
425 return false;
426 }
427
428 return true;
429 }
430
431 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
432 {
433 struct iommu_dev_data *dev_data;
434
435 dev_data = get_dev_data(&pdev->dev);
436
437 return dev_data->errata & (1 << erratum) ? true : false;
438 }
439
440 /*
441 * This function checks if the driver got a valid device from the caller to
442 * avoid dereferencing invalid pointers.
443 */
444 static bool check_device(struct device *dev)
445 {
446 int devid;
447
448 if (!dev || !dev->dma_mask)
449 return false;
450
451 devid = get_device_id(dev);
452 if (devid < 0)
453 return false;
454
455 /* Out of our scope? */
456 if (devid > amd_iommu_last_bdf)
457 return false;
458
459 if (amd_iommu_rlookup_table[devid] == NULL)
460 return false;
461
462 return true;
463 }
464
465 static void init_iommu_group(struct device *dev)
466 {
467 struct iommu_group *group;
468
469 group = iommu_group_get_for_dev(dev);
470 if (IS_ERR(group))
471 return;
472
473 iommu_group_put(group);
474 }
475
476 static int iommu_init_device(struct device *dev)
477 {
478 struct iommu_dev_data *dev_data;
479 struct amd_iommu *iommu;
480 int devid;
481
482 if (dev->archdata.iommu)
483 return 0;
484
485 devid = get_device_id(dev);
486 if (devid < 0)
487 return devid;
488
489 iommu = amd_iommu_rlookup_table[devid];
490
491 dev_data = find_dev_data(devid);
492 if (!dev_data)
493 return -ENOMEM;
494
495 dev_data->alias = get_alias(dev);
496
497 if (dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
498 struct amd_iommu *iommu;
499
500 iommu = amd_iommu_rlookup_table[dev_data->devid];
501 dev_data->iommu_v2 = iommu->is_iommu_v2;
502 }
503
504 dev->archdata.iommu = dev_data;
505
506 iommu_device_link(&iommu->iommu, dev);
507
508 return 0;
509 }
510
511 static void iommu_ignore_device(struct device *dev)
512 {
513 u16 alias;
514 int devid;
515
516 devid = get_device_id(dev);
517 if (devid < 0)
518 return;
519
520 alias = get_alias(dev);
521
522 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
523 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
524
525 amd_iommu_rlookup_table[devid] = NULL;
526 amd_iommu_rlookup_table[alias] = NULL;
527 }
528
529 static void iommu_uninit_device(struct device *dev)
530 {
531 struct iommu_dev_data *dev_data;
532 struct amd_iommu *iommu;
533 int devid;
534
535 devid = get_device_id(dev);
536 if (devid < 0)
537 return;
538
539 iommu = amd_iommu_rlookup_table[devid];
540
541 dev_data = search_dev_data(devid);
542 if (!dev_data)
543 return;
544
545 if (dev_data->domain)
546 detach_device(dev);
547
548 iommu_device_unlink(&iommu->iommu, dev);
549
550 iommu_group_remove_device(dev);
551
552 /* Remove dma-ops */
553 dev->dma_ops = NULL;
554
555 /*
556 * We keep dev_data around for unplugged devices and reuse it when the
557 * device is re-plugged - not doing so would introduce a ton of races.
558 */
559 }
560
561 /****************************************************************************
562 *
563 * Interrupt handling functions
564 *
565 ****************************************************************************/
566
567 static void dump_dte_entry(u16 devid)
568 {
569 int i;
570
571 for (i = 0; i < 4; ++i)
572 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
573 amd_iommu_dev_table[devid].data[i]);
574 }
575
576 static void dump_command(unsigned long phys_addr)
577 {
578 struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr);
579 int i;
580
581 for (i = 0; i < 4; ++i)
582 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
583 }
584
585 static void amd_iommu_report_page_fault(u16 devid, u16 domain_id,
586 u64 address, int flags)
587 {
588 struct iommu_dev_data *dev_data = NULL;
589 struct pci_dev *pdev;
590
591 pdev = pci_get_bus_and_slot(PCI_BUS_NUM(devid), devid & 0xff);
592 if (pdev)
593 dev_data = get_dev_data(&pdev->dev);
594
595 if (dev_data && __ratelimit(&dev_data->rs)) {
596 dev_err(&pdev->dev, "AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%016llx flags=0x%04x]\n",
597 domain_id, address, flags);
598 } else if (printk_ratelimit()) {
599 pr_err("AMD-Vi: Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%016llx flags=0x%04x]\n",
600 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
601 domain_id, address, flags);
602 }
603
604 if (pdev)
605 pci_dev_put(pdev);
606 }
607
608 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
609 {
610 int type, devid, domid, flags;
611 volatile u32 *event = __evt;
612 int count = 0;
613 u64 address;
614
615 retry:
616 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
617 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
618 domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
619 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
620 address = (u64)(((u64)event[3]) << 32) | event[2];
621
622 if (type == 0) {
623 /* Did we hit the erratum? */
624 if (++count == LOOP_TIMEOUT) {
625 pr_err("AMD-Vi: No event written to event log\n");
626 return;
627 }
628 udelay(1);
629 goto retry;
630 }
631
632 if (type == EVENT_TYPE_IO_FAULT) {
633 amd_iommu_report_page_fault(devid, domid, address, flags);
634 return;
635 } else {
636 printk(KERN_ERR "AMD-Vi: Event logged [");
637 }
638
639 switch (type) {
640 case EVENT_TYPE_ILL_DEV:
641 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
642 "address=0x%016llx flags=0x%04x]\n",
643 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
644 address, flags);
645 dump_dte_entry(devid);
646 break;
647 case EVENT_TYPE_DEV_TAB_ERR:
648 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
649 "address=0x%016llx flags=0x%04x]\n",
650 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
651 address, flags);
652 break;
653 case EVENT_TYPE_PAGE_TAB_ERR:
654 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
655 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
656 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
657 domid, address, flags);
658 break;
659 case EVENT_TYPE_ILL_CMD:
660 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
661 dump_command(address);
662 break;
663 case EVENT_TYPE_CMD_HARD_ERR:
664 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
665 "flags=0x%04x]\n", address, flags);
666 break;
667 case EVENT_TYPE_IOTLB_INV_TO:
668 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
669 "address=0x%016llx]\n",
670 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
671 address);
672 break;
673 case EVENT_TYPE_INV_DEV_REQ:
674 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
675 "address=0x%016llx flags=0x%04x]\n",
676 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
677 address, flags);
678 break;
679 default:
680 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
681 }
682
683 memset(__evt, 0, 4 * sizeof(u32));
684 }
685
686 static void iommu_poll_events(struct amd_iommu *iommu)
687 {
688 u32 head, tail;
689
690 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
691 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
692
693 while (head != tail) {
694 iommu_print_event(iommu, iommu->evt_buf + head);
695 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
696 }
697
698 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
699 }
700
701 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
702 {
703 struct amd_iommu_fault fault;
704
705 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
706 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
707 return;
708 }
709
710 fault.address = raw[1];
711 fault.pasid = PPR_PASID(raw[0]);
712 fault.device_id = PPR_DEVID(raw[0]);
713 fault.tag = PPR_TAG(raw[0]);
714 fault.flags = PPR_FLAGS(raw[0]);
715
716 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
717 }
718
719 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
720 {
721 u32 head, tail;
722
723 if (iommu->ppr_log == NULL)
724 return;
725
726 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
727 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
728
729 while (head != tail) {
730 volatile u64 *raw;
731 u64 entry[2];
732 int i;
733
734 raw = (u64 *)(iommu->ppr_log + head);
735
736 /*
737 * Hardware bug: Interrupt may arrive before the entry is
738 * written to memory. If this happens we need to wait for the
739 * entry to arrive.
740 */
741 for (i = 0; i < LOOP_TIMEOUT; ++i) {
742 if (PPR_REQ_TYPE(raw[0]) != 0)
743 break;
744 udelay(1);
745 }
746
747 /* Avoid memcpy function-call overhead */
748 entry[0] = raw[0];
749 entry[1] = raw[1];
750
751 /*
752 * To detect the hardware bug we need to clear the entry
753 * back to zero.
754 */
755 raw[0] = raw[1] = 0UL;
756
757 /* Update head pointer of hardware ring-buffer */
758 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
759 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
760
761 /* Handle PPR entry */
762 iommu_handle_ppr_entry(iommu, entry);
763
764 /* Refresh ring-buffer information */
765 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
766 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
767 }
768 }
769
770 #ifdef CONFIG_IRQ_REMAP
771 static int (*iommu_ga_log_notifier)(u32);
772
773 int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
774 {
775 iommu_ga_log_notifier = notifier;
776
777 return 0;
778 }
779 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
780
781 static void iommu_poll_ga_log(struct amd_iommu *iommu)
782 {
783 u32 head, tail, cnt = 0;
784
785 if (iommu->ga_log == NULL)
786 return;
787
788 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
789 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
790
791 while (head != tail) {
792 volatile u64 *raw;
793 u64 log_entry;
794
795 raw = (u64 *)(iommu->ga_log + head);
796 cnt++;
797
798 /* Avoid memcpy function-call overhead */
799 log_entry = *raw;
800
801 /* Update head pointer of hardware ring-buffer */
802 head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
803 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
804
805 /* Handle GA entry */
806 switch (GA_REQ_TYPE(log_entry)) {
807 case GA_GUEST_NR:
808 if (!iommu_ga_log_notifier)
809 break;
810
811 pr_debug("AMD-Vi: %s: devid=%#x, ga_tag=%#x\n",
812 __func__, GA_DEVID(log_entry),
813 GA_TAG(log_entry));
814
815 if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
816 pr_err("AMD-Vi: GA log notifier failed.\n");
817 break;
818 default:
819 break;
820 }
821 }
822 }
823 #endif /* CONFIG_IRQ_REMAP */
824
825 #define AMD_IOMMU_INT_MASK \
826 (MMIO_STATUS_EVT_INT_MASK | \
827 MMIO_STATUS_PPR_INT_MASK | \
828 MMIO_STATUS_GALOG_INT_MASK)
829
830 irqreturn_t amd_iommu_int_thread(int irq, void *data)
831 {
832 struct amd_iommu *iommu = (struct amd_iommu *) data;
833 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
834
835 while (status & AMD_IOMMU_INT_MASK) {
836 /* Enable EVT and PPR and GA interrupts again */
837 writel(AMD_IOMMU_INT_MASK,
838 iommu->mmio_base + MMIO_STATUS_OFFSET);
839
840 if (status & MMIO_STATUS_EVT_INT_MASK) {
841 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
842 iommu_poll_events(iommu);
843 }
844
845 if (status & MMIO_STATUS_PPR_INT_MASK) {
846 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
847 iommu_poll_ppr_log(iommu);
848 }
849
850 #ifdef CONFIG_IRQ_REMAP
851 if (status & MMIO_STATUS_GALOG_INT_MASK) {
852 pr_devel("AMD-Vi: Processing IOMMU GA Log\n");
853 iommu_poll_ga_log(iommu);
854 }
855 #endif
856
857 /*
858 * Hardware bug: ERBT1312
859 * When re-enabling interrupt (by writing 1
860 * to clear the bit), the hardware might also try to set
861 * the interrupt bit in the event status register.
862 * In this scenario, the bit will be set, and disable
863 * subsequent interrupts.
864 *
865 * Workaround: The IOMMU driver should read back the
866 * status register and check if the interrupt bits are cleared.
867 * If not, driver will need to go through the interrupt handler
868 * again and re-clear the bits
869 */
870 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
871 }
872 return IRQ_HANDLED;
873 }
874
875 irqreturn_t amd_iommu_int_handler(int irq, void *data)
876 {
877 return IRQ_WAKE_THREAD;
878 }
879
880 /****************************************************************************
881 *
882 * IOMMU command queuing functions
883 *
884 ****************************************************************************/
885
886 static int wait_on_sem(volatile u64 *sem)
887 {
888 int i = 0;
889
890 while (*sem == 0 && i < LOOP_TIMEOUT) {
891 udelay(1);
892 i += 1;
893 }
894
895 if (i == LOOP_TIMEOUT) {
896 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
897 return -EIO;
898 }
899
900 return 0;
901 }
902
903 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
904 struct iommu_cmd *cmd)
905 {
906 u8 *target;
907
908 target = iommu->cmd_buf + iommu->cmd_buf_tail;
909
910 iommu->cmd_buf_tail += sizeof(*cmd);
911 iommu->cmd_buf_tail %= CMD_BUFFER_SIZE;
912
913 /* Copy command to buffer */
914 memcpy(target, cmd, sizeof(*cmd));
915
916 /* Tell the IOMMU about it */
917 writel(iommu->cmd_buf_tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
918 }
919
920 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
921 {
922 u64 paddr = iommu_virt_to_phys((void *)address);
923
924 WARN_ON(address & 0x7ULL);
925
926 memset(cmd, 0, sizeof(*cmd));
927 cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK;
928 cmd->data[1] = upper_32_bits(paddr);
929 cmd->data[2] = 1;
930 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
931 }
932
933 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
934 {
935 memset(cmd, 0, sizeof(*cmd));
936 cmd->data[0] = devid;
937 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
938 }
939
940 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
941 size_t size, u16 domid, int pde)
942 {
943 u64 pages;
944 bool s;
945
946 pages = iommu_num_pages(address, size, PAGE_SIZE);
947 s = false;
948
949 if (pages > 1) {
950 /*
951 * If we have to flush more than one page, flush all
952 * TLB entries for this domain
953 */
954 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
955 s = true;
956 }
957
958 address &= PAGE_MASK;
959
960 memset(cmd, 0, sizeof(*cmd));
961 cmd->data[1] |= domid;
962 cmd->data[2] = lower_32_bits(address);
963 cmd->data[3] = upper_32_bits(address);
964 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
965 if (s) /* size bit - we flush more than one 4kb page */
966 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
967 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
968 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
969 }
970
971 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
972 u64 address, size_t size)
973 {
974 u64 pages;
975 bool s;
976
977 pages = iommu_num_pages(address, size, PAGE_SIZE);
978 s = false;
979
980 if (pages > 1) {
981 /*
982 * If we have to flush more than one page, flush all
983 * TLB entries for this domain
984 */
985 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
986 s = true;
987 }
988
989 address &= PAGE_MASK;
990
991 memset(cmd, 0, sizeof(*cmd));
992 cmd->data[0] = devid;
993 cmd->data[0] |= (qdep & 0xff) << 24;
994 cmd->data[1] = devid;
995 cmd->data[2] = lower_32_bits(address);
996 cmd->data[3] = upper_32_bits(address);
997 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
998 if (s)
999 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
1000 }
1001
1002 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
1003 u64 address, bool size)
1004 {
1005 memset(cmd, 0, sizeof(*cmd));
1006
1007 address &= ~(0xfffULL);
1008
1009 cmd->data[0] = pasid;
1010 cmd->data[1] = domid;
1011 cmd->data[2] = lower_32_bits(address);
1012 cmd->data[3] = upper_32_bits(address);
1013 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
1014 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
1015 if (size)
1016 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
1017 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
1018 }
1019
1020 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
1021 int qdep, u64 address, bool size)
1022 {
1023 memset(cmd, 0, sizeof(*cmd));
1024
1025 address &= ~(0xfffULL);
1026
1027 cmd->data[0] = devid;
1028 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
1029 cmd->data[0] |= (qdep & 0xff) << 24;
1030 cmd->data[1] = devid;
1031 cmd->data[1] |= (pasid & 0xff) << 16;
1032 cmd->data[2] = lower_32_bits(address);
1033 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
1034 cmd->data[3] = upper_32_bits(address);
1035 if (size)
1036 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
1037 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
1038 }
1039
1040 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
1041 int status, int tag, bool gn)
1042 {
1043 memset(cmd, 0, sizeof(*cmd));
1044
1045 cmd->data[0] = devid;
1046 if (gn) {
1047 cmd->data[1] = pasid;
1048 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
1049 }
1050 cmd->data[3] = tag & 0x1ff;
1051 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
1052
1053 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
1054 }
1055
1056 static void build_inv_all(struct iommu_cmd *cmd)
1057 {
1058 memset(cmd, 0, sizeof(*cmd));
1059 CMD_SET_TYPE(cmd, CMD_INV_ALL);
1060 }
1061
1062 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
1063 {
1064 memset(cmd, 0, sizeof(*cmd));
1065 cmd->data[0] = devid;
1066 CMD_SET_TYPE(cmd, CMD_INV_IRT);
1067 }
1068
1069 /*
1070 * Writes the command to the IOMMUs command buffer and informs the
1071 * hardware about the new command.
1072 */
1073 static int __iommu_queue_command_sync(struct amd_iommu *iommu,
1074 struct iommu_cmd *cmd,
1075 bool sync)
1076 {
1077 unsigned int count = 0;
1078 u32 left, next_tail;
1079
1080 next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
1081 again:
1082 left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE;
1083
1084 if (left <= 0x20) {
1085 /* Skip udelay() the first time around */
1086 if (count++) {
1087 if (count == LOOP_TIMEOUT) {
1088 pr_err("AMD-Vi: Command buffer timeout\n");
1089 return -EIO;
1090 }
1091
1092 udelay(1);
1093 }
1094
1095 /* Update head and recheck remaining space */
1096 iommu->cmd_buf_head = readl(iommu->mmio_base +
1097 MMIO_CMD_HEAD_OFFSET);
1098
1099 goto again;
1100 }
1101
1102 copy_cmd_to_buffer(iommu, cmd);
1103
1104 /* Do we need to make sure all commands are processed? */
1105 iommu->need_sync = sync;
1106
1107 return 0;
1108 }
1109
1110 static int iommu_queue_command_sync(struct amd_iommu *iommu,
1111 struct iommu_cmd *cmd,
1112 bool sync)
1113 {
1114 unsigned long flags;
1115 int ret;
1116
1117 spin_lock_irqsave(&iommu->lock, flags);
1118 ret = __iommu_queue_command_sync(iommu, cmd, sync);
1119 spin_unlock_irqrestore(&iommu->lock, flags);
1120
1121 return ret;
1122 }
1123
1124 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1125 {
1126 return iommu_queue_command_sync(iommu, cmd, true);
1127 }
1128
1129 /*
1130 * This function queues a completion wait command into the command
1131 * buffer of an IOMMU
1132 */
1133 static int iommu_completion_wait(struct amd_iommu *iommu)
1134 {
1135 struct iommu_cmd cmd;
1136 unsigned long flags;
1137 int ret;
1138
1139 if (!iommu->need_sync)
1140 return 0;
1141
1142
1143 build_completion_wait(&cmd, (u64)&iommu->cmd_sem);
1144
1145 spin_lock_irqsave(&iommu->lock, flags);
1146
1147 iommu->cmd_sem = 0;
1148
1149 ret = __iommu_queue_command_sync(iommu, &cmd, false);
1150 if (ret)
1151 goto out_unlock;
1152
1153 ret = wait_on_sem(&iommu->cmd_sem);
1154
1155 out_unlock:
1156 spin_unlock_irqrestore(&iommu->lock, flags);
1157
1158 return ret;
1159 }
1160
1161 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1162 {
1163 struct iommu_cmd cmd;
1164
1165 build_inv_dte(&cmd, devid);
1166
1167 return iommu_queue_command(iommu, &cmd);
1168 }
1169
1170 static void iommu_flush_dte_all(struct amd_iommu *iommu)
1171 {
1172 u32 devid;
1173
1174 for (devid = 0; devid <= 0xffff; ++devid)
1175 iommu_flush_dte(iommu, devid);
1176
1177 iommu_completion_wait(iommu);
1178 }
1179
1180 /*
1181 * This function uses heavy locking and may disable irqs for some time. But
1182 * this is no issue because it is only called during resume.
1183 */
1184 static void iommu_flush_tlb_all(struct amd_iommu *iommu)
1185 {
1186 u32 dom_id;
1187
1188 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1189 struct iommu_cmd cmd;
1190 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1191 dom_id, 1);
1192 iommu_queue_command(iommu, &cmd);
1193 }
1194
1195 iommu_completion_wait(iommu);
1196 }
1197
1198 static void iommu_flush_all(struct amd_iommu *iommu)
1199 {
1200 struct iommu_cmd cmd;
1201
1202 build_inv_all(&cmd);
1203
1204 iommu_queue_command(iommu, &cmd);
1205 iommu_completion_wait(iommu);
1206 }
1207
1208 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1209 {
1210 struct iommu_cmd cmd;
1211
1212 build_inv_irt(&cmd, devid);
1213
1214 iommu_queue_command(iommu, &cmd);
1215 }
1216
1217 static void iommu_flush_irt_all(struct amd_iommu *iommu)
1218 {
1219 u32 devid;
1220
1221 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1222 iommu_flush_irt(iommu, devid);
1223
1224 iommu_completion_wait(iommu);
1225 }
1226
1227 void iommu_flush_all_caches(struct amd_iommu *iommu)
1228 {
1229 if (iommu_feature(iommu, FEATURE_IA)) {
1230 iommu_flush_all(iommu);
1231 } else {
1232 iommu_flush_dte_all(iommu);
1233 iommu_flush_irt_all(iommu);
1234 iommu_flush_tlb_all(iommu);
1235 }
1236 }
1237
1238 /*
1239 * Command send function for flushing on-device TLB
1240 */
1241 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1242 u64 address, size_t size)
1243 {
1244 struct amd_iommu *iommu;
1245 struct iommu_cmd cmd;
1246 int qdep;
1247
1248 qdep = dev_data->ats.qdep;
1249 iommu = amd_iommu_rlookup_table[dev_data->devid];
1250
1251 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1252
1253 return iommu_queue_command(iommu, &cmd);
1254 }
1255
1256 /*
1257 * Command send function for invalidating a device table entry
1258 */
1259 static int device_flush_dte(struct iommu_dev_data *dev_data)
1260 {
1261 struct amd_iommu *iommu;
1262 u16 alias;
1263 int ret;
1264
1265 iommu = amd_iommu_rlookup_table[dev_data->devid];
1266 alias = dev_data->alias;
1267
1268 ret = iommu_flush_dte(iommu, dev_data->devid);
1269 if (!ret && alias != dev_data->devid)
1270 ret = iommu_flush_dte(iommu, alias);
1271 if (ret)
1272 return ret;
1273
1274 if (dev_data->ats.enabled)
1275 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1276
1277 return ret;
1278 }
1279
1280 /*
1281 * TLB invalidation function which is called from the mapping functions.
1282 * It invalidates a single PTE if the range to flush is within a single
1283 * page. Otherwise it flushes the whole TLB of the IOMMU.
1284 */
1285 static void __domain_flush_pages(struct protection_domain *domain,
1286 u64 address, size_t size, int pde)
1287 {
1288 struct iommu_dev_data *dev_data;
1289 struct iommu_cmd cmd;
1290 int ret = 0, i;
1291
1292 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1293
1294 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1295 if (!domain->dev_iommu[i])
1296 continue;
1297
1298 /*
1299 * Devices of this domain are behind this IOMMU
1300 * We need a TLB flush
1301 */
1302 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1303 }
1304
1305 list_for_each_entry(dev_data, &domain->dev_list, list) {
1306
1307 if (!dev_data->ats.enabled)
1308 continue;
1309
1310 ret |= device_flush_iotlb(dev_data, address, size);
1311 }
1312
1313 WARN_ON(ret);
1314 }
1315
1316 static void domain_flush_pages(struct protection_domain *domain,
1317 u64 address, size_t size)
1318 {
1319 __domain_flush_pages(domain, address, size, 0);
1320 }
1321
1322 /* Flush the whole IO/TLB for a given protection domain */
1323 static void domain_flush_tlb(struct protection_domain *domain)
1324 {
1325 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1326 }
1327
1328 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1329 static void domain_flush_tlb_pde(struct protection_domain *domain)
1330 {
1331 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1332 }
1333
1334 static void domain_flush_complete(struct protection_domain *domain)
1335 {
1336 int i;
1337
1338 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1339 if (domain && !domain->dev_iommu[i])
1340 continue;
1341
1342 /*
1343 * Devices of this domain are behind this IOMMU
1344 * We need to wait for completion of all commands.
1345 */
1346 iommu_completion_wait(amd_iommus[i]);
1347 }
1348 }
1349
1350
1351 /*
1352 * This function flushes the DTEs for all devices in domain
1353 */
1354 static void domain_flush_devices(struct protection_domain *domain)
1355 {
1356 struct iommu_dev_data *dev_data;
1357
1358 list_for_each_entry(dev_data, &domain->dev_list, list)
1359 device_flush_dte(dev_data);
1360 }
1361
1362 /****************************************************************************
1363 *
1364 * The functions below are used the create the page table mappings for
1365 * unity mapped regions.
1366 *
1367 ****************************************************************************/
1368
1369 /*
1370 * This function is used to add another level to an IO page table. Adding
1371 * another level increases the size of the address space by 9 bits to a size up
1372 * to 64 bits.
1373 */
1374 static bool increase_address_space(struct protection_domain *domain,
1375 gfp_t gfp)
1376 {
1377 u64 *pte;
1378
1379 if (domain->mode == PAGE_MODE_6_LEVEL)
1380 /* address space already 64 bit large */
1381 return false;
1382
1383 pte = (void *)get_zeroed_page(gfp);
1384 if (!pte)
1385 return false;
1386
1387 *pte = PM_LEVEL_PDE(domain->mode,
1388 iommu_virt_to_phys(domain->pt_root));
1389 domain->pt_root = pte;
1390 domain->mode += 1;
1391 domain->updated = true;
1392
1393 return true;
1394 }
1395
1396 static u64 *alloc_pte(struct protection_domain *domain,
1397 unsigned long address,
1398 unsigned long page_size,
1399 u64 **pte_page,
1400 gfp_t gfp)
1401 {
1402 int level, end_lvl;
1403 u64 *pte, *page;
1404
1405 BUG_ON(!is_power_of_2(page_size));
1406
1407 while (address > PM_LEVEL_SIZE(domain->mode))
1408 increase_address_space(domain, gfp);
1409
1410 level = domain->mode - 1;
1411 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1412 address = PAGE_SIZE_ALIGN(address, page_size);
1413 end_lvl = PAGE_SIZE_LEVEL(page_size);
1414
1415 while (level > end_lvl) {
1416 u64 __pte, __npte;
1417
1418 __pte = *pte;
1419
1420 if (!IOMMU_PTE_PRESENT(__pte)) {
1421 page = (u64 *)get_zeroed_page(gfp);
1422 if (!page)
1423 return NULL;
1424
1425 __npte = PM_LEVEL_PDE(level, iommu_virt_to_phys(page));
1426
1427 /* pte could have been changed somewhere. */
1428 if (cmpxchg64(pte, __pte, __npte) != __pte) {
1429 free_page((unsigned long)page);
1430 continue;
1431 }
1432 }
1433
1434 /* No level skipping support yet */
1435 if (PM_PTE_LEVEL(*pte) != level)
1436 return NULL;
1437
1438 level -= 1;
1439
1440 pte = IOMMU_PTE_PAGE(*pte);
1441
1442 if (pte_page && level == end_lvl)
1443 *pte_page = pte;
1444
1445 pte = &pte[PM_LEVEL_INDEX(level, address)];
1446 }
1447
1448 return pte;
1449 }
1450
1451 /*
1452 * This function checks if there is a PTE for a given dma address. If
1453 * there is one, it returns the pointer to it.
1454 */
1455 static u64 *fetch_pte(struct protection_domain *domain,
1456 unsigned long address,
1457 unsigned long *page_size)
1458 {
1459 int level;
1460 u64 *pte;
1461
1462 if (address > PM_LEVEL_SIZE(domain->mode))
1463 return NULL;
1464
1465 level = domain->mode - 1;
1466 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1467 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1468
1469 while (level > 0) {
1470
1471 /* Not Present */
1472 if (!IOMMU_PTE_PRESENT(*pte))
1473 return NULL;
1474
1475 /* Large PTE */
1476 if (PM_PTE_LEVEL(*pte) == 7 ||
1477 PM_PTE_LEVEL(*pte) == 0)
1478 break;
1479
1480 /* No level skipping support yet */
1481 if (PM_PTE_LEVEL(*pte) != level)
1482 return NULL;
1483
1484 level -= 1;
1485
1486 /* Walk to the next level */
1487 pte = IOMMU_PTE_PAGE(*pte);
1488 pte = &pte[PM_LEVEL_INDEX(level, address)];
1489 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1490 }
1491
1492 if (PM_PTE_LEVEL(*pte) == 0x07) {
1493 unsigned long pte_mask;
1494
1495 /*
1496 * If we have a series of large PTEs, make
1497 * sure to return a pointer to the first one.
1498 */
1499 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1500 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1501 pte = (u64 *)(((unsigned long)pte) & pte_mask);
1502 }
1503
1504 return pte;
1505 }
1506
1507 /*
1508 * Generic mapping functions. It maps a physical address into a DMA
1509 * address space. It allocates the page table pages if necessary.
1510 * In the future it can be extended to a generic mapping function
1511 * supporting all features of AMD IOMMU page tables like level skipping
1512 * and full 64 bit address spaces.
1513 */
1514 static int iommu_map_page(struct protection_domain *dom,
1515 unsigned long bus_addr,
1516 unsigned long phys_addr,
1517 unsigned long page_size,
1518 int prot,
1519 gfp_t gfp)
1520 {
1521 u64 __pte, *pte;
1522 int i, count;
1523
1524 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1525 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1526
1527 if (!(prot & IOMMU_PROT_MASK))
1528 return -EINVAL;
1529
1530 count = PAGE_SIZE_PTE_COUNT(page_size);
1531 pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp);
1532
1533 if (!pte)
1534 return -ENOMEM;
1535
1536 for (i = 0; i < count; ++i)
1537 if (IOMMU_PTE_PRESENT(pte[i]))
1538 return -EBUSY;
1539
1540 if (count > 1) {
1541 __pte = PAGE_SIZE_PTE(__sme_set(phys_addr), page_size);
1542 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
1543 } else
1544 __pte = __sme_set(phys_addr) | IOMMU_PTE_P | IOMMU_PTE_FC;
1545
1546 if (prot & IOMMU_PROT_IR)
1547 __pte |= IOMMU_PTE_IR;
1548 if (prot & IOMMU_PROT_IW)
1549 __pte |= IOMMU_PTE_IW;
1550
1551 for (i = 0; i < count; ++i)
1552 pte[i] = __pte;
1553
1554 update_domain(dom);
1555
1556 return 0;
1557 }
1558
1559 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1560 unsigned long bus_addr,
1561 unsigned long page_size)
1562 {
1563 unsigned long long unmapped;
1564 unsigned long unmap_size;
1565 u64 *pte;
1566
1567 BUG_ON(!is_power_of_2(page_size));
1568
1569 unmapped = 0;
1570
1571 while (unmapped < page_size) {
1572
1573 pte = fetch_pte(dom, bus_addr, &unmap_size);
1574
1575 if (pte) {
1576 int i, count;
1577
1578 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1579 for (i = 0; i < count; i++)
1580 pte[i] = 0ULL;
1581 }
1582
1583 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1584 unmapped += unmap_size;
1585 }
1586
1587 BUG_ON(unmapped && !is_power_of_2(unmapped));
1588
1589 return unmapped;
1590 }
1591
1592 /****************************************************************************
1593 *
1594 * The next functions belong to the address allocator for the dma_ops
1595 * interface functions.
1596 *
1597 ****************************************************************************/
1598
1599
1600 static unsigned long dma_ops_alloc_iova(struct device *dev,
1601 struct dma_ops_domain *dma_dom,
1602 unsigned int pages, u64 dma_mask)
1603 {
1604 unsigned long pfn = 0;
1605
1606 pages = __roundup_pow_of_two(pages);
1607
1608 if (dma_mask > DMA_BIT_MASK(32))
1609 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1610 IOVA_PFN(DMA_BIT_MASK(32)));
1611
1612 if (!pfn)
1613 pfn = alloc_iova_fast(&dma_dom->iovad, pages, IOVA_PFN(dma_mask));
1614
1615 return (pfn << PAGE_SHIFT);
1616 }
1617
1618 static void dma_ops_free_iova(struct dma_ops_domain *dma_dom,
1619 unsigned long address,
1620 unsigned int pages)
1621 {
1622 pages = __roundup_pow_of_two(pages);
1623 address >>= PAGE_SHIFT;
1624
1625 free_iova_fast(&dma_dom->iovad, address, pages);
1626 }
1627
1628 /****************************************************************************
1629 *
1630 * The next functions belong to the domain allocation. A domain is
1631 * allocated for every IOMMU as the default domain. If device isolation
1632 * is enabled, every device get its own domain. The most important thing
1633 * about domains is the page table mapping the DMA address space they
1634 * contain.
1635 *
1636 ****************************************************************************/
1637
1638 /*
1639 * This function adds a protection domain to the global protection domain list
1640 */
1641 static void add_domain_to_list(struct protection_domain *domain)
1642 {
1643 unsigned long flags;
1644
1645 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1646 list_add(&domain->list, &amd_iommu_pd_list);
1647 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1648 }
1649
1650 /*
1651 * This function removes a protection domain to the global
1652 * protection domain list
1653 */
1654 static void del_domain_from_list(struct protection_domain *domain)
1655 {
1656 unsigned long flags;
1657
1658 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1659 list_del(&domain->list);
1660 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1661 }
1662
1663 static u16 domain_id_alloc(void)
1664 {
1665 unsigned long flags;
1666 int id;
1667
1668 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1669 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1670 BUG_ON(id == 0);
1671 if (id > 0 && id < MAX_DOMAIN_ID)
1672 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1673 else
1674 id = 0;
1675 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1676
1677 return id;
1678 }
1679
1680 static void domain_id_free(int id)
1681 {
1682 unsigned long flags;
1683
1684 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1685 if (id > 0 && id < MAX_DOMAIN_ID)
1686 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1687 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1688 }
1689
1690 #define DEFINE_FREE_PT_FN(LVL, FN) \
1691 static void free_pt_##LVL (unsigned long __pt) \
1692 { \
1693 unsigned long p; \
1694 u64 *pt; \
1695 int i; \
1696 \
1697 pt = (u64 *)__pt; \
1698 \
1699 for (i = 0; i < 512; ++i) { \
1700 /* PTE present? */ \
1701 if (!IOMMU_PTE_PRESENT(pt[i])) \
1702 continue; \
1703 \
1704 /* Large PTE? */ \
1705 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1706 PM_PTE_LEVEL(pt[i]) == 7) \
1707 continue; \
1708 \
1709 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1710 FN(p); \
1711 } \
1712 free_page((unsigned long)pt); \
1713 }
1714
1715 DEFINE_FREE_PT_FN(l2, free_page)
1716 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1717 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1718 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1719 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1720
1721 static void free_pagetable(struct protection_domain *domain)
1722 {
1723 unsigned long root = (unsigned long)domain->pt_root;
1724
1725 switch (domain->mode) {
1726 case PAGE_MODE_NONE:
1727 break;
1728 case PAGE_MODE_1_LEVEL:
1729 free_page(root);
1730 break;
1731 case PAGE_MODE_2_LEVEL:
1732 free_pt_l2(root);
1733 break;
1734 case PAGE_MODE_3_LEVEL:
1735 free_pt_l3(root);
1736 break;
1737 case PAGE_MODE_4_LEVEL:
1738 free_pt_l4(root);
1739 break;
1740 case PAGE_MODE_5_LEVEL:
1741 free_pt_l5(root);
1742 break;
1743 case PAGE_MODE_6_LEVEL:
1744 free_pt_l6(root);
1745 break;
1746 default:
1747 BUG();
1748 }
1749 }
1750
1751 static void free_gcr3_tbl_level1(u64 *tbl)
1752 {
1753 u64 *ptr;
1754 int i;
1755
1756 for (i = 0; i < 512; ++i) {
1757 if (!(tbl[i] & GCR3_VALID))
1758 continue;
1759
1760 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1761
1762 free_page((unsigned long)ptr);
1763 }
1764 }
1765
1766 static void free_gcr3_tbl_level2(u64 *tbl)
1767 {
1768 u64 *ptr;
1769 int i;
1770
1771 for (i = 0; i < 512; ++i) {
1772 if (!(tbl[i] & GCR3_VALID))
1773 continue;
1774
1775 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1776
1777 free_gcr3_tbl_level1(ptr);
1778 }
1779 }
1780
1781 static void free_gcr3_table(struct protection_domain *domain)
1782 {
1783 if (domain->glx == 2)
1784 free_gcr3_tbl_level2(domain->gcr3_tbl);
1785 else if (domain->glx == 1)
1786 free_gcr3_tbl_level1(domain->gcr3_tbl);
1787 else
1788 BUG_ON(domain->glx != 0);
1789
1790 free_page((unsigned long)domain->gcr3_tbl);
1791 }
1792
1793 static void dma_ops_domain_free_flush_queue(struct dma_ops_domain *dom)
1794 {
1795 int cpu;
1796
1797 for_each_possible_cpu(cpu) {
1798 struct flush_queue *queue;
1799
1800 queue = per_cpu_ptr(dom->flush_queue, cpu);
1801 kfree(queue->entries);
1802 }
1803
1804 free_percpu(dom->flush_queue);
1805
1806 dom->flush_queue = NULL;
1807 }
1808
1809 static int dma_ops_domain_alloc_flush_queue(struct dma_ops_domain *dom)
1810 {
1811 int cpu;
1812
1813 atomic64_set(&dom->flush_start_cnt, 0);
1814 atomic64_set(&dom->flush_finish_cnt, 0);
1815
1816 dom->flush_queue = alloc_percpu(struct flush_queue);
1817 if (!dom->flush_queue)
1818 return -ENOMEM;
1819
1820 /* First make sure everything is cleared */
1821 for_each_possible_cpu(cpu) {
1822 struct flush_queue *queue;
1823
1824 queue = per_cpu_ptr(dom->flush_queue, cpu);
1825 queue->head = 0;
1826 queue->tail = 0;
1827 queue->entries = NULL;
1828 }
1829
1830 /* Now start doing the allocation */
1831 for_each_possible_cpu(cpu) {
1832 struct flush_queue *queue;
1833
1834 queue = per_cpu_ptr(dom->flush_queue, cpu);
1835 queue->entries = kzalloc(FLUSH_QUEUE_SIZE * sizeof(*queue->entries),
1836 GFP_KERNEL);
1837 if (!queue->entries) {
1838 dma_ops_domain_free_flush_queue(dom);
1839 return -ENOMEM;
1840 }
1841
1842 spin_lock_init(&queue->lock);
1843 }
1844
1845 return 0;
1846 }
1847
1848 static void dma_ops_domain_flush_tlb(struct dma_ops_domain *dom)
1849 {
1850 atomic64_inc(&dom->flush_start_cnt);
1851 domain_flush_tlb(&dom->domain);
1852 domain_flush_complete(&dom->domain);
1853 atomic64_inc(&dom->flush_finish_cnt);
1854 }
1855
1856 static inline bool queue_ring_full(struct flush_queue *queue)
1857 {
1858 assert_spin_locked(&queue->lock);
1859
1860 return (((queue->tail + 1) % FLUSH_QUEUE_SIZE) == queue->head);
1861 }
1862
1863 #define queue_ring_for_each(i, q) \
1864 for (i = (q)->head; i != (q)->tail; i = (i + 1) % FLUSH_QUEUE_SIZE)
1865
1866 static inline unsigned queue_ring_add(struct flush_queue *queue)
1867 {
1868 unsigned idx = queue->tail;
1869
1870 assert_spin_locked(&queue->lock);
1871 queue->tail = (idx + 1) % FLUSH_QUEUE_SIZE;
1872
1873 return idx;
1874 }
1875
1876 static inline void queue_ring_remove_head(struct flush_queue *queue)
1877 {
1878 assert_spin_locked(&queue->lock);
1879 queue->head = (queue->head + 1) % FLUSH_QUEUE_SIZE;
1880 }
1881
1882 static void queue_ring_free_flushed(struct dma_ops_domain *dom,
1883 struct flush_queue *queue)
1884 {
1885 u64 counter = atomic64_read(&dom->flush_finish_cnt);
1886 int idx;
1887
1888 queue_ring_for_each(idx, queue) {
1889 /*
1890 * This assumes that counter values in the ring-buffer are
1891 * monotonously rising.
1892 */
1893 if (queue->entries[idx].counter >= counter)
1894 break;
1895
1896 free_iova_fast(&dom->iovad,
1897 queue->entries[idx].iova_pfn,
1898 queue->entries[idx].pages);
1899
1900 queue_ring_remove_head(queue);
1901 }
1902 }
1903
1904 static void queue_add(struct dma_ops_domain *dom,
1905 unsigned long address, unsigned long pages)
1906 {
1907 struct flush_queue *queue;
1908 unsigned long flags;
1909 int idx;
1910
1911 pages = __roundup_pow_of_two(pages);
1912 address >>= PAGE_SHIFT;
1913
1914 queue = get_cpu_ptr(dom->flush_queue);
1915 spin_lock_irqsave(&queue->lock, flags);
1916
1917 /*
1918 * First remove the enries from the ring-buffer that are already
1919 * flushed to make the below queue_ring_full() check less likely
1920 */
1921 queue_ring_free_flushed(dom, queue);
1922
1923 /*
1924 * When ring-queue is full, flush the entries from the IOTLB so
1925 * that we can free all entries with queue_ring_free_flushed()
1926 * below.
1927 */
1928 if (queue_ring_full(queue)) {
1929 dma_ops_domain_flush_tlb(dom);
1930 queue_ring_free_flushed(dom, queue);
1931 }
1932
1933 idx = queue_ring_add(queue);
1934
1935 queue->entries[idx].iova_pfn = address;
1936 queue->entries[idx].pages = pages;
1937 queue->entries[idx].counter = atomic64_read(&dom->flush_start_cnt);
1938
1939 spin_unlock_irqrestore(&queue->lock, flags);
1940
1941 if (atomic_cmpxchg(&dom->flush_timer_on, 0, 1) == 0)
1942 mod_timer(&dom->flush_timer, jiffies + msecs_to_jiffies(10));
1943
1944 put_cpu_ptr(dom->flush_queue);
1945 }
1946
1947 static void queue_flush_timeout(unsigned long data)
1948 {
1949 struct dma_ops_domain *dom = (struct dma_ops_domain *)data;
1950 int cpu;
1951
1952 atomic_set(&dom->flush_timer_on, 0);
1953
1954 dma_ops_domain_flush_tlb(dom);
1955
1956 for_each_possible_cpu(cpu) {
1957 struct flush_queue *queue;
1958 unsigned long flags;
1959
1960 queue = per_cpu_ptr(dom->flush_queue, cpu);
1961 spin_lock_irqsave(&queue->lock, flags);
1962 queue_ring_free_flushed(dom, queue);
1963 spin_unlock_irqrestore(&queue->lock, flags);
1964 }
1965 }
1966
1967 /*
1968 * Free a domain, only used if something went wrong in the
1969 * allocation path and we need to free an already allocated page table
1970 */
1971 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1972 {
1973 if (!dom)
1974 return;
1975
1976 del_domain_from_list(&dom->domain);
1977
1978 if (timer_pending(&dom->flush_timer))
1979 del_timer(&dom->flush_timer);
1980
1981 dma_ops_domain_free_flush_queue(dom);
1982
1983 put_iova_domain(&dom->iovad);
1984
1985 free_pagetable(&dom->domain);
1986
1987 if (dom->domain.id)
1988 domain_id_free(dom->domain.id);
1989
1990 kfree(dom);
1991 }
1992
1993 /*
1994 * Allocates a new protection domain usable for the dma_ops functions.
1995 * It also initializes the page table and the address allocator data
1996 * structures required for the dma_ops interface
1997 */
1998 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1999 {
2000 struct dma_ops_domain *dma_dom;
2001
2002 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
2003 if (!dma_dom)
2004 return NULL;
2005
2006 if (protection_domain_init(&dma_dom->domain))
2007 goto free_dma_dom;
2008
2009 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
2010 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2011 dma_dom->domain.flags = PD_DMA_OPS_MASK;
2012 if (!dma_dom->domain.pt_root)
2013 goto free_dma_dom;
2014
2015 init_iova_domain(&dma_dom->iovad, PAGE_SIZE,
2016 IOVA_START_PFN, DMA_32BIT_PFN);
2017
2018 /* Initialize reserved ranges */
2019 copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad);
2020
2021 if (dma_ops_domain_alloc_flush_queue(dma_dom))
2022 goto free_dma_dom;
2023
2024 setup_timer(&dma_dom->flush_timer, queue_flush_timeout,
2025 (unsigned long)dma_dom);
2026
2027 atomic_set(&dma_dom->flush_timer_on, 0);
2028
2029 add_domain_to_list(&dma_dom->domain);
2030
2031 return dma_dom;
2032
2033 free_dma_dom:
2034 dma_ops_domain_free(dma_dom);
2035
2036 return NULL;
2037 }
2038
2039 /*
2040 * little helper function to check whether a given protection domain is a
2041 * dma_ops domain
2042 */
2043 static bool dma_ops_domain(struct protection_domain *domain)
2044 {
2045 return domain->flags & PD_DMA_OPS_MASK;
2046 }
2047
2048 static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
2049 {
2050 u64 pte_root = 0;
2051 u64 flags = 0;
2052
2053 if (domain->mode != PAGE_MODE_NONE)
2054 pte_root = iommu_virt_to_phys(domain->pt_root);
2055
2056 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
2057 << DEV_ENTRY_MODE_SHIFT;
2058 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
2059
2060 flags = amd_iommu_dev_table[devid].data[1];
2061
2062 if (ats)
2063 flags |= DTE_FLAG_IOTLB;
2064
2065 if (domain->flags & PD_IOMMUV2_MASK) {
2066 u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
2067 u64 glx = domain->glx;
2068 u64 tmp;
2069
2070 pte_root |= DTE_FLAG_GV;
2071 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
2072
2073 /* First mask out possible old values for GCR3 table */
2074 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
2075 flags &= ~tmp;
2076
2077 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
2078 flags &= ~tmp;
2079
2080 /* Encode GCR3 table into DTE */
2081 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
2082 pte_root |= tmp;
2083
2084 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
2085 flags |= tmp;
2086
2087 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
2088 flags |= tmp;
2089 }
2090
2091
2092 flags &= ~(DTE_FLAG_SA | 0xffffULL);
2093 flags |= domain->id;
2094
2095 amd_iommu_dev_table[devid].data[1] = flags;
2096 amd_iommu_dev_table[devid].data[0] = pte_root;
2097 }
2098
2099 static void clear_dte_entry(u16 devid)
2100 {
2101 /* remove entry from the device table seen by the hardware */
2102 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
2103 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
2104
2105 amd_iommu_apply_erratum_63(devid);
2106 }
2107
2108 static void do_attach(struct iommu_dev_data *dev_data,
2109 struct protection_domain *domain)
2110 {
2111 struct amd_iommu *iommu;
2112 u16 alias;
2113 bool ats;
2114
2115 iommu = amd_iommu_rlookup_table[dev_data->devid];
2116 alias = dev_data->alias;
2117 ats = dev_data->ats.enabled;
2118
2119 /* Update data structures */
2120 dev_data->domain = domain;
2121 list_add(&dev_data->list, &domain->dev_list);
2122
2123 /* Do reference counting */
2124 domain->dev_iommu[iommu->index] += 1;
2125 domain->dev_cnt += 1;
2126
2127 /* Update device table */
2128 set_dte_entry(dev_data->devid, domain, ats);
2129 if (alias != dev_data->devid)
2130 set_dte_entry(alias, domain, ats);
2131
2132 device_flush_dte(dev_data);
2133 }
2134
2135 static void do_detach(struct iommu_dev_data *dev_data)
2136 {
2137 struct amd_iommu *iommu;
2138 u16 alias;
2139
2140 /*
2141 * First check if the device is still attached. It might already
2142 * be detached from its domain because the generic
2143 * iommu_detach_group code detached it and we try again here in
2144 * our alias handling.
2145 */
2146 if (!dev_data->domain)
2147 return;
2148
2149 iommu = amd_iommu_rlookup_table[dev_data->devid];
2150 alias = dev_data->alias;
2151
2152 /* decrease reference counters */
2153 dev_data->domain->dev_iommu[iommu->index] -= 1;
2154 dev_data->domain->dev_cnt -= 1;
2155
2156 /* Update data structures */
2157 dev_data->domain = NULL;
2158 list_del(&dev_data->list);
2159 clear_dte_entry(dev_data->devid);
2160 if (alias != dev_data->devid)
2161 clear_dte_entry(alias);
2162
2163 /* Flush the DTE entry */
2164 device_flush_dte(dev_data);
2165 }
2166
2167 /*
2168 * If a device is not yet associated with a domain, this function does
2169 * assigns it visible for the hardware
2170 */
2171 static int __attach_device(struct iommu_dev_data *dev_data,
2172 struct protection_domain *domain)
2173 {
2174 int ret;
2175
2176 /*
2177 * Must be called with IRQs disabled. Warn here to detect early
2178 * when its not.
2179 */
2180 WARN_ON(!irqs_disabled());
2181
2182 /* lock domain */
2183 spin_lock(&domain->lock);
2184
2185 ret = -EBUSY;
2186 if (dev_data->domain != NULL)
2187 goto out_unlock;
2188
2189 /* Attach alias group root */
2190 do_attach(dev_data, domain);
2191
2192 ret = 0;
2193
2194 out_unlock:
2195
2196 /* ready */
2197 spin_unlock(&domain->lock);
2198
2199 return ret;
2200 }
2201
2202
2203 static void pdev_iommuv2_disable(struct pci_dev *pdev)
2204 {
2205 pci_disable_ats(pdev);
2206 pci_disable_pri(pdev);
2207 pci_disable_pasid(pdev);
2208 }
2209
2210 /* FIXME: Change generic reset-function to do the same */
2211 static int pri_reset_while_enabled(struct pci_dev *pdev)
2212 {
2213 u16 control;
2214 int pos;
2215
2216 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2217 if (!pos)
2218 return -EINVAL;
2219
2220 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
2221 control |= PCI_PRI_CTRL_RESET;
2222 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
2223
2224 return 0;
2225 }
2226
2227 static int pdev_iommuv2_enable(struct pci_dev *pdev)
2228 {
2229 bool reset_enable;
2230 int reqs, ret;
2231
2232 /* FIXME: Hardcode number of outstanding requests for now */
2233 reqs = 32;
2234 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2235 reqs = 1;
2236 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2237
2238 /* Only allow access to user-accessible pages */
2239 ret = pci_enable_pasid(pdev, 0);
2240 if (ret)
2241 goto out_err;
2242
2243 /* First reset the PRI state of the device */
2244 ret = pci_reset_pri(pdev);
2245 if (ret)
2246 goto out_err;
2247
2248 /* Enable PRI */
2249 ret = pci_enable_pri(pdev, reqs);
2250 if (ret)
2251 goto out_err;
2252
2253 if (reset_enable) {
2254 ret = pri_reset_while_enabled(pdev);
2255 if (ret)
2256 goto out_err;
2257 }
2258
2259 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2260 if (ret)
2261 goto out_err;
2262
2263 return 0;
2264
2265 out_err:
2266 pci_disable_pri(pdev);
2267 pci_disable_pasid(pdev);
2268
2269 return ret;
2270 }
2271
2272 /* FIXME: Move this to PCI code */
2273 #define PCI_PRI_TLP_OFF (1 << 15)
2274
2275 static bool pci_pri_tlp_required(struct pci_dev *pdev)
2276 {
2277 u16 status;
2278 int pos;
2279
2280 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2281 if (!pos)
2282 return false;
2283
2284 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
2285
2286 return (status & PCI_PRI_TLP_OFF) ? true : false;
2287 }
2288
2289 /*
2290 * If a device is not yet associated with a domain, this function
2291 * assigns it visible for the hardware
2292 */
2293 static int attach_device(struct device *dev,
2294 struct protection_domain *domain)
2295 {
2296 struct pci_dev *pdev;
2297 struct iommu_dev_data *dev_data;
2298 unsigned long flags;
2299 int ret;
2300
2301 dev_data = get_dev_data(dev);
2302
2303 if (!dev_is_pci(dev))
2304 goto skip_ats_check;
2305
2306 pdev = to_pci_dev(dev);
2307 if (domain->flags & PD_IOMMUV2_MASK) {
2308 if (!dev_data->passthrough)
2309 return -EINVAL;
2310
2311 if (dev_data->iommu_v2) {
2312 if (pdev_iommuv2_enable(pdev) != 0)
2313 return -EINVAL;
2314
2315 dev_data->ats.enabled = true;
2316 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2317 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2318 }
2319 } else if (amd_iommu_iotlb_sup &&
2320 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2321 dev_data->ats.enabled = true;
2322 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2323 }
2324
2325 skip_ats_check:
2326 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2327 ret = __attach_device(dev_data, domain);
2328 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2329
2330 /*
2331 * We might boot into a crash-kernel here. The crashed kernel
2332 * left the caches in the IOMMU dirty. So we have to flush
2333 * here to evict all dirty stuff.
2334 */
2335 domain_flush_tlb_pde(domain);
2336
2337 return ret;
2338 }
2339
2340 /*
2341 * Removes a device from a protection domain (unlocked)
2342 */
2343 static void __detach_device(struct iommu_dev_data *dev_data)
2344 {
2345 struct protection_domain *domain;
2346
2347 /*
2348 * Must be called with IRQs disabled. Warn here to detect early
2349 * when its not.
2350 */
2351 WARN_ON(!irqs_disabled());
2352
2353 if (WARN_ON(!dev_data->domain))
2354 return;
2355
2356 domain = dev_data->domain;
2357
2358 spin_lock(&domain->lock);
2359
2360 do_detach(dev_data);
2361
2362 spin_unlock(&domain->lock);
2363 }
2364
2365 /*
2366 * Removes a device from a protection domain (with devtable_lock held)
2367 */
2368 static void detach_device(struct device *dev)
2369 {
2370 struct protection_domain *domain;
2371 struct iommu_dev_data *dev_data;
2372 unsigned long flags;
2373
2374 dev_data = get_dev_data(dev);
2375 domain = dev_data->domain;
2376
2377 /* lock device table */
2378 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2379 __detach_device(dev_data);
2380 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2381
2382 if (!dev_is_pci(dev))
2383 return;
2384
2385 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
2386 pdev_iommuv2_disable(to_pci_dev(dev));
2387 else if (dev_data->ats.enabled)
2388 pci_disable_ats(to_pci_dev(dev));
2389
2390 dev_data->ats.enabled = false;
2391 }
2392
2393 static int amd_iommu_add_device(struct device *dev)
2394 {
2395 struct iommu_dev_data *dev_data;
2396 struct iommu_domain *domain;
2397 struct amd_iommu *iommu;
2398 int ret, devid;
2399
2400 if (!check_device(dev) || get_dev_data(dev))
2401 return 0;
2402
2403 devid = get_device_id(dev);
2404 if (devid < 0)
2405 return devid;
2406
2407 iommu = amd_iommu_rlookup_table[devid];
2408
2409 ret = iommu_init_device(dev);
2410 if (ret) {
2411 if (ret != -ENOTSUPP)
2412 pr_err("Failed to initialize device %s - trying to proceed anyway\n",
2413 dev_name(dev));
2414
2415 iommu_ignore_device(dev);
2416 dev->dma_ops = &nommu_dma_ops;
2417 goto out;
2418 }
2419 init_iommu_group(dev);
2420
2421 dev_data = get_dev_data(dev);
2422
2423 BUG_ON(!dev_data);
2424
2425 if (iommu_pass_through || dev_data->iommu_v2)
2426 iommu_request_dm_for_dev(dev);
2427
2428 /* Domains are initialized for this device - have a look what we ended up with */
2429 domain = iommu_get_domain_for_dev(dev);
2430 if (domain->type == IOMMU_DOMAIN_IDENTITY)
2431 dev_data->passthrough = true;
2432 else
2433 dev->dma_ops = &amd_iommu_dma_ops;
2434
2435 out:
2436 iommu_completion_wait(iommu);
2437
2438 return 0;
2439 }
2440
2441 static void amd_iommu_remove_device(struct device *dev)
2442 {
2443 struct amd_iommu *iommu;
2444 int devid;
2445
2446 if (!check_device(dev))
2447 return;
2448
2449 devid = get_device_id(dev);
2450 if (devid < 0)
2451 return;
2452
2453 iommu = amd_iommu_rlookup_table[devid];
2454
2455 iommu_uninit_device(dev);
2456 iommu_completion_wait(iommu);
2457 }
2458
2459 static struct iommu_group *amd_iommu_device_group(struct device *dev)
2460 {
2461 if (dev_is_pci(dev))
2462 return pci_device_group(dev);
2463
2464 return acpihid_device_group(dev);
2465 }
2466
2467 /*****************************************************************************
2468 *
2469 * The next functions belong to the dma_ops mapping/unmapping code.
2470 *
2471 *****************************************************************************/
2472
2473 /*
2474 * In the dma_ops path we only have the struct device. This function
2475 * finds the corresponding IOMMU, the protection domain and the
2476 * requestor id for a given device.
2477 * If the device is not yet associated with a domain this is also done
2478 * in this function.
2479 */
2480 static struct protection_domain *get_domain(struct device *dev)
2481 {
2482 struct protection_domain *domain;
2483
2484 if (!check_device(dev))
2485 return ERR_PTR(-EINVAL);
2486
2487 domain = get_dev_data(dev)->domain;
2488 if (!dma_ops_domain(domain))
2489 return ERR_PTR(-EBUSY);
2490
2491 return domain;
2492 }
2493
2494 static void update_device_table(struct protection_domain *domain)
2495 {
2496 struct iommu_dev_data *dev_data;
2497
2498 list_for_each_entry(dev_data, &domain->dev_list, list) {
2499 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
2500
2501 if (dev_data->devid == dev_data->alias)
2502 continue;
2503
2504 /* There is an alias, update device table entry for it */
2505 set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled);
2506 }
2507 }
2508
2509 static void update_domain(struct protection_domain *domain)
2510 {
2511 if (!domain->updated)
2512 return;
2513
2514 update_device_table(domain);
2515
2516 domain_flush_devices(domain);
2517 domain_flush_tlb_pde(domain);
2518
2519 domain->updated = false;
2520 }
2521
2522 static int dir2prot(enum dma_data_direction direction)
2523 {
2524 if (direction == DMA_TO_DEVICE)
2525 return IOMMU_PROT_IR;
2526 else if (direction == DMA_FROM_DEVICE)
2527 return IOMMU_PROT_IW;
2528 else if (direction == DMA_BIDIRECTIONAL)
2529 return IOMMU_PROT_IW | IOMMU_PROT_IR;
2530 else
2531 return 0;
2532 }
2533 /*
2534 * This function contains common code for mapping of a physically
2535 * contiguous memory region into DMA address space. It is used by all
2536 * mapping functions provided with this IOMMU driver.
2537 * Must be called with the domain lock held.
2538 */
2539 static dma_addr_t __map_single(struct device *dev,
2540 struct dma_ops_domain *dma_dom,
2541 phys_addr_t paddr,
2542 size_t size,
2543 enum dma_data_direction direction,
2544 u64 dma_mask)
2545 {
2546 dma_addr_t offset = paddr & ~PAGE_MASK;
2547 dma_addr_t address, start, ret;
2548 unsigned int pages;
2549 int prot = 0;
2550 int i;
2551
2552 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2553 paddr &= PAGE_MASK;
2554
2555 address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask);
2556 if (address == AMD_IOMMU_MAPPING_ERROR)
2557 goto out;
2558
2559 prot = dir2prot(direction);
2560
2561 start = address;
2562 for (i = 0; i < pages; ++i) {
2563 ret = iommu_map_page(&dma_dom->domain, start, paddr,
2564 PAGE_SIZE, prot, GFP_ATOMIC);
2565 if (ret)
2566 goto out_unmap;
2567
2568 paddr += PAGE_SIZE;
2569 start += PAGE_SIZE;
2570 }
2571 address += offset;
2572
2573 if (unlikely(amd_iommu_np_cache)) {
2574 domain_flush_pages(&dma_dom->domain, address, size);
2575 domain_flush_complete(&dma_dom->domain);
2576 }
2577
2578 out:
2579 return address;
2580
2581 out_unmap:
2582
2583 for (--i; i >= 0; --i) {
2584 start -= PAGE_SIZE;
2585 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2586 }
2587
2588 domain_flush_tlb(&dma_dom->domain);
2589 domain_flush_complete(&dma_dom->domain);
2590
2591 dma_ops_free_iova(dma_dom, address, pages);
2592
2593 return AMD_IOMMU_MAPPING_ERROR;
2594 }
2595
2596 /*
2597 * Does the reverse of the __map_single function. Must be called with
2598 * the domain lock held too
2599 */
2600 static void __unmap_single(struct dma_ops_domain *dma_dom,
2601 dma_addr_t dma_addr,
2602 size_t size,
2603 int dir)
2604 {
2605 dma_addr_t flush_addr;
2606 dma_addr_t i, start;
2607 unsigned int pages;
2608
2609 flush_addr = dma_addr;
2610 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2611 dma_addr &= PAGE_MASK;
2612 start = dma_addr;
2613
2614 for (i = 0; i < pages; ++i) {
2615 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2616 start += PAGE_SIZE;
2617 }
2618
2619 if (amd_iommu_unmap_flush) {
2620 dma_ops_free_iova(dma_dom, dma_addr, pages);
2621 domain_flush_tlb(&dma_dom->domain);
2622 domain_flush_complete(&dma_dom->domain);
2623 } else {
2624 queue_add(dma_dom, dma_addr, pages);
2625 }
2626 }
2627
2628 /*
2629 * The exported map_single function for dma_ops.
2630 */
2631 static dma_addr_t map_page(struct device *dev, struct page *page,
2632 unsigned long offset, size_t size,
2633 enum dma_data_direction dir,
2634 unsigned long attrs)
2635 {
2636 phys_addr_t paddr = page_to_phys(page) + offset;
2637 struct protection_domain *domain;
2638 struct dma_ops_domain *dma_dom;
2639 u64 dma_mask;
2640
2641 domain = get_domain(dev);
2642 if (PTR_ERR(domain) == -EINVAL)
2643 return (dma_addr_t)paddr;
2644 else if (IS_ERR(domain))
2645 return AMD_IOMMU_MAPPING_ERROR;
2646
2647 dma_mask = *dev->dma_mask;
2648 dma_dom = to_dma_ops_domain(domain);
2649
2650 return __map_single(dev, dma_dom, paddr, size, dir, dma_mask);
2651 }
2652
2653 /*
2654 * The exported unmap_single function for dma_ops.
2655 */
2656 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2657 enum dma_data_direction dir, unsigned long attrs)
2658 {
2659 struct protection_domain *domain;
2660 struct dma_ops_domain *dma_dom;
2661
2662 domain = get_domain(dev);
2663 if (IS_ERR(domain))
2664 return;
2665
2666 dma_dom = to_dma_ops_domain(domain);
2667
2668 __unmap_single(dma_dom, dma_addr, size, dir);
2669 }
2670
2671 static int sg_num_pages(struct device *dev,
2672 struct scatterlist *sglist,
2673 int nelems)
2674 {
2675 unsigned long mask, boundary_size;
2676 struct scatterlist *s;
2677 int i, npages = 0;
2678
2679 mask = dma_get_seg_boundary(dev);
2680 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
2681 1UL << (BITS_PER_LONG - PAGE_SHIFT);
2682
2683 for_each_sg(sglist, s, nelems, i) {
2684 int p, n;
2685
2686 s->dma_address = npages << PAGE_SHIFT;
2687 p = npages % boundary_size;
2688 n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2689 if (p + n > boundary_size)
2690 npages += boundary_size - p;
2691 npages += n;
2692 }
2693
2694 return npages;
2695 }
2696
2697 /*
2698 * The exported map_sg function for dma_ops (handles scatter-gather
2699 * lists).
2700 */
2701 static int map_sg(struct device *dev, struct scatterlist *sglist,
2702 int nelems, enum dma_data_direction direction,
2703 unsigned long attrs)
2704 {
2705 int mapped_pages = 0, npages = 0, prot = 0, i;
2706 struct protection_domain *domain;
2707 struct dma_ops_domain *dma_dom;
2708 struct scatterlist *s;
2709 unsigned long address;
2710 u64 dma_mask;
2711
2712 domain = get_domain(dev);
2713 if (IS_ERR(domain))
2714 return 0;
2715
2716 dma_dom = to_dma_ops_domain(domain);
2717 dma_mask = *dev->dma_mask;
2718
2719 npages = sg_num_pages(dev, sglist, nelems);
2720
2721 address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask);
2722 if (address == AMD_IOMMU_MAPPING_ERROR)
2723 goto out_err;
2724
2725 prot = dir2prot(direction);
2726
2727 /* Map all sg entries */
2728 for_each_sg(sglist, s, nelems, i) {
2729 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2730
2731 for (j = 0; j < pages; ++j) {
2732 unsigned long bus_addr, phys_addr;
2733 int ret;
2734
2735 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2736 phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT);
2737 ret = iommu_map_page(domain, bus_addr, phys_addr, PAGE_SIZE, prot, GFP_ATOMIC);
2738 if (ret)
2739 goto out_unmap;
2740
2741 mapped_pages += 1;
2742 }
2743 }
2744
2745 /* Everything is mapped - write the right values into s->dma_address */
2746 for_each_sg(sglist, s, nelems, i) {
2747 s->dma_address += address + s->offset;
2748 s->dma_length = s->length;
2749 }
2750
2751 return nelems;
2752
2753 out_unmap:
2754 pr_err("%s: IOMMU mapping error in map_sg (io-pages: %d)\n",
2755 dev_name(dev), npages);
2756
2757 for_each_sg(sglist, s, nelems, i) {
2758 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2759
2760 for (j = 0; j < pages; ++j) {
2761 unsigned long bus_addr;
2762
2763 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2764 iommu_unmap_page(domain, bus_addr, PAGE_SIZE);
2765
2766 if (--mapped_pages)
2767 goto out_free_iova;
2768 }
2769 }
2770
2771 out_free_iova:
2772 free_iova_fast(&dma_dom->iovad, address, npages);
2773
2774 out_err:
2775 return 0;
2776 }
2777
2778 /*
2779 * The exported map_sg function for dma_ops (handles scatter-gather
2780 * lists).
2781 */
2782 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2783 int nelems, enum dma_data_direction dir,
2784 unsigned long attrs)
2785 {
2786 struct protection_domain *domain;
2787 struct dma_ops_domain *dma_dom;
2788 unsigned long startaddr;
2789 int npages = 2;
2790
2791 domain = get_domain(dev);
2792 if (IS_ERR(domain))
2793 return;
2794
2795 startaddr = sg_dma_address(sglist) & PAGE_MASK;
2796 dma_dom = to_dma_ops_domain(domain);
2797 npages = sg_num_pages(dev, sglist, nelems);
2798
2799 __unmap_single(dma_dom, startaddr, npages << PAGE_SHIFT, dir);
2800 }
2801
2802 /*
2803 * The exported alloc_coherent function for dma_ops.
2804 */
2805 static void *alloc_coherent(struct device *dev, size_t size,
2806 dma_addr_t *dma_addr, gfp_t flag,
2807 unsigned long attrs)
2808 {
2809 u64 dma_mask = dev->coherent_dma_mask;
2810 struct protection_domain *domain;
2811 struct dma_ops_domain *dma_dom;
2812 struct page *page;
2813
2814 domain = get_domain(dev);
2815 if (PTR_ERR(domain) == -EINVAL) {
2816 page = alloc_pages(flag, get_order(size));
2817 *dma_addr = page_to_phys(page);
2818 return page_address(page);
2819 } else if (IS_ERR(domain))
2820 return NULL;
2821
2822 dma_dom = to_dma_ops_domain(domain);
2823 size = PAGE_ALIGN(size);
2824 dma_mask = dev->coherent_dma_mask;
2825 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2826 flag |= __GFP_ZERO;
2827
2828 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2829 if (!page) {
2830 if (!gfpflags_allow_blocking(flag))
2831 return NULL;
2832
2833 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2834 get_order(size), flag);
2835 if (!page)
2836 return NULL;
2837 }
2838
2839 if (!dma_mask)
2840 dma_mask = *dev->dma_mask;
2841
2842 *dma_addr = __map_single(dev, dma_dom, page_to_phys(page),
2843 size, DMA_BIDIRECTIONAL, dma_mask);
2844
2845 if (*dma_addr == AMD_IOMMU_MAPPING_ERROR)
2846 goto out_free;
2847
2848 return page_address(page);
2849
2850 out_free:
2851
2852 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2853 __free_pages(page, get_order(size));
2854
2855 return NULL;
2856 }
2857
2858 /*
2859 * The exported free_coherent function for dma_ops.
2860 */
2861 static void free_coherent(struct device *dev, size_t size,
2862 void *virt_addr, dma_addr_t dma_addr,
2863 unsigned long attrs)
2864 {
2865 struct protection_domain *domain;
2866 struct dma_ops_domain *dma_dom;
2867 struct page *page;
2868
2869 page = virt_to_page(virt_addr);
2870 size = PAGE_ALIGN(size);
2871
2872 domain = get_domain(dev);
2873 if (IS_ERR(domain))
2874 goto free_mem;
2875
2876 dma_dom = to_dma_ops_domain(domain);
2877
2878 __unmap_single(dma_dom, dma_addr, size, DMA_BIDIRECTIONAL);
2879
2880 free_mem:
2881 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2882 __free_pages(page, get_order(size));
2883 }
2884
2885 /*
2886 * This function is called by the DMA layer to find out if we can handle a
2887 * particular device. It is part of the dma_ops.
2888 */
2889 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2890 {
2891 if (!x86_dma_supported(dev, mask))
2892 return 0;
2893 return check_device(dev);
2894 }
2895
2896 static int amd_iommu_mapping_error(struct device *dev, dma_addr_t dma_addr)
2897 {
2898 return dma_addr == AMD_IOMMU_MAPPING_ERROR;
2899 }
2900
2901 static const struct dma_map_ops amd_iommu_dma_ops = {
2902 .alloc = alloc_coherent,
2903 .free = free_coherent,
2904 .map_page = map_page,
2905 .unmap_page = unmap_page,
2906 .map_sg = map_sg,
2907 .unmap_sg = unmap_sg,
2908 .dma_supported = amd_iommu_dma_supported,
2909 .mapping_error = amd_iommu_mapping_error,
2910 };
2911
2912 static int init_reserved_iova_ranges(void)
2913 {
2914 struct pci_dev *pdev = NULL;
2915 struct iova *val;
2916
2917 init_iova_domain(&reserved_iova_ranges, PAGE_SIZE,
2918 IOVA_START_PFN, DMA_32BIT_PFN);
2919
2920 lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock,
2921 &reserved_rbtree_key);
2922
2923 /* MSI memory range */
2924 val = reserve_iova(&reserved_iova_ranges,
2925 IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END));
2926 if (!val) {
2927 pr_err("Reserving MSI range failed\n");
2928 return -ENOMEM;
2929 }
2930
2931 /* HT memory range */
2932 val = reserve_iova(&reserved_iova_ranges,
2933 IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END));
2934 if (!val) {
2935 pr_err("Reserving HT range failed\n");
2936 return -ENOMEM;
2937 }
2938
2939 /*
2940 * Memory used for PCI resources
2941 * FIXME: Check whether we can reserve the PCI-hole completly
2942 */
2943 for_each_pci_dev(pdev) {
2944 int i;
2945
2946 for (i = 0; i < PCI_NUM_RESOURCES; ++i) {
2947 struct resource *r = &pdev->resource[i];
2948
2949 if (!(r->flags & IORESOURCE_MEM))
2950 continue;
2951
2952 val = reserve_iova(&reserved_iova_ranges,
2953 IOVA_PFN(r->start),
2954 IOVA_PFN(r->end));
2955 if (!val) {
2956 pr_err("Reserve pci-resource range failed\n");
2957 return -ENOMEM;
2958 }
2959 }
2960 }
2961
2962 return 0;
2963 }
2964
2965 int __init amd_iommu_init_api(void)
2966 {
2967 int ret, err = 0;
2968
2969 ret = iova_cache_get();
2970 if (ret)
2971 return ret;
2972
2973 ret = init_reserved_iova_ranges();
2974 if (ret)
2975 return ret;
2976
2977 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2978 if (err)
2979 return err;
2980 #ifdef CONFIG_ARM_AMBA
2981 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
2982 if (err)
2983 return err;
2984 #endif
2985 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
2986 if (err)
2987 return err;
2988
2989 return 0;
2990 }
2991
2992 int __init amd_iommu_init_dma_ops(void)
2993 {
2994 swiotlb = iommu_pass_through ? 1 : 0;
2995 iommu_detected = 1;
2996
2997 /*
2998 * In case we don't initialize SWIOTLB (actually the common case
2999 * when AMD IOMMU is enabled), make sure there are global
3000 * dma_ops set as a fall-back for devices not handled by this
3001 * driver (for example non-PCI devices).
3002 */
3003 if (!swiotlb)
3004 dma_ops = &nommu_dma_ops;
3005
3006 if (amd_iommu_unmap_flush)
3007 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
3008 else
3009 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
3010
3011 return 0;
3012
3013 }
3014
3015 /*****************************************************************************
3016 *
3017 * The following functions belong to the exported interface of AMD IOMMU
3018 *
3019 * This interface allows access to lower level functions of the IOMMU
3020 * like protection domain handling and assignement of devices to domains
3021 * which is not possible with the dma_ops interface.
3022 *
3023 *****************************************************************************/
3024
3025 static void cleanup_domain(struct protection_domain *domain)
3026 {
3027 struct iommu_dev_data *entry;
3028 unsigned long flags;
3029
3030 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3031
3032 while (!list_empty(&domain->dev_list)) {
3033 entry = list_first_entry(&domain->dev_list,
3034 struct iommu_dev_data, list);
3035 __detach_device(entry);
3036 }
3037
3038 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3039 }
3040
3041 static void protection_domain_free(struct protection_domain *domain)
3042 {
3043 if (!domain)
3044 return;
3045
3046 del_domain_from_list(domain);
3047
3048 if (domain->id)
3049 domain_id_free(domain->id);
3050
3051 kfree(domain);
3052 }
3053
3054 static int protection_domain_init(struct protection_domain *domain)
3055 {
3056 spin_lock_init(&domain->lock);
3057 mutex_init(&domain->api_lock);
3058 domain->id = domain_id_alloc();
3059 if (!domain->id)
3060 return -ENOMEM;
3061 INIT_LIST_HEAD(&domain->dev_list);
3062
3063 return 0;
3064 }
3065
3066 static struct protection_domain *protection_domain_alloc(void)
3067 {
3068 struct protection_domain *domain;
3069
3070 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
3071 if (!domain)
3072 return NULL;
3073
3074 if (protection_domain_init(domain))
3075 goto out_err;
3076
3077 add_domain_to_list(domain);
3078
3079 return domain;
3080
3081 out_err:
3082 kfree(domain);
3083
3084 return NULL;
3085 }
3086
3087 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
3088 {
3089 struct protection_domain *pdomain;
3090 struct dma_ops_domain *dma_domain;
3091
3092 switch (type) {
3093 case IOMMU_DOMAIN_UNMANAGED:
3094 pdomain = protection_domain_alloc();
3095 if (!pdomain)
3096 return NULL;
3097
3098 pdomain->mode = PAGE_MODE_3_LEVEL;
3099 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
3100 if (!pdomain->pt_root) {
3101 protection_domain_free(pdomain);
3102 return NULL;
3103 }
3104
3105 pdomain->domain.geometry.aperture_start = 0;
3106 pdomain->domain.geometry.aperture_end = ~0ULL;
3107 pdomain->domain.geometry.force_aperture = true;
3108
3109 break;
3110 case IOMMU_DOMAIN_DMA:
3111 dma_domain = dma_ops_domain_alloc();
3112 if (!dma_domain) {
3113 pr_err("AMD-Vi: Failed to allocate\n");
3114 return NULL;
3115 }
3116 pdomain = &dma_domain->domain;
3117 break;
3118 case IOMMU_DOMAIN_IDENTITY:
3119 pdomain = protection_domain_alloc();
3120 if (!pdomain)
3121 return NULL;
3122
3123 pdomain->mode = PAGE_MODE_NONE;
3124 break;
3125 default:
3126 return NULL;
3127 }
3128
3129 return &pdomain->domain;
3130 }
3131
3132 static void amd_iommu_domain_free(struct iommu_domain *dom)
3133 {
3134 struct protection_domain *domain;
3135 struct dma_ops_domain *dma_dom;
3136
3137 domain = to_pdomain(dom);
3138
3139 if (domain->dev_cnt > 0)
3140 cleanup_domain(domain);
3141
3142 BUG_ON(domain->dev_cnt != 0);
3143
3144 if (!dom)
3145 return;
3146
3147 switch (dom->type) {
3148 case IOMMU_DOMAIN_DMA:
3149 /* Now release the domain */
3150 dma_dom = to_dma_ops_domain(domain);
3151 dma_ops_domain_free(dma_dom);
3152 break;
3153 default:
3154 if (domain->mode != PAGE_MODE_NONE)
3155 free_pagetable(domain);
3156
3157 if (domain->flags & PD_IOMMUV2_MASK)
3158 free_gcr3_table(domain);
3159
3160 protection_domain_free(domain);
3161 break;
3162 }
3163 }
3164
3165 static void amd_iommu_detach_device(struct iommu_domain *dom,
3166 struct device *dev)
3167 {
3168 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3169 struct amd_iommu *iommu;
3170 int devid;
3171
3172 if (!check_device(dev))
3173 return;
3174
3175 devid = get_device_id(dev);
3176 if (devid < 0)
3177 return;
3178
3179 if (dev_data->domain != NULL)
3180 detach_device(dev);
3181
3182 iommu = amd_iommu_rlookup_table[devid];
3183 if (!iommu)
3184 return;
3185
3186 #ifdef CONFIG_IRQ_REMAP
3187 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
3188 (dom->type == IOMMU_DOMAIN_UNMANAGED))
3189 dev_data->use_vapic = 0;
3190 #endif
3191
3192 iommu_completion_wait(iommu);
3193 }
3194
3195 static int amd_iommu_attach_device(struct iommu_domain *dom,
3196 struct device *dev)
3197 {
3198 struct protection_domain *domain = to_pdomain(dom);
3199 struct iommu_dev_data *dev_data;
3200 struct amd_iommu *iommu;
3201 int ret;
3202
3203 if (!check_device(dev))
3204 return -EINVAL;
3205
3206 dev_data = dev->archdata.iommu;
3207
3208 iommu = amd_iommu_rlookup_table[dev_data->devid];
3209 if (!iommu)
3210 return -EINVAL;
3211
3212 if (dev_data->domain)
3213 detach_device(dev);
3214
3215 ret = attach_device(dev, domain);
3216
3217 #ifdef CONFIG_IRQ_REMAP
3218 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
3219 if (dom->type == IOMMU_DOMAIN_UNMANAGED)
3220 dev_data->use_vapic = 1;
3221 else
3222 dev_data->use_vapic = 0;
3223 }
3224 #endif
3225
3226 iommu_completion_wait(iommu);
3227
3228 return ret;
3229 }
3230
3231 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3232 phys_addr_t paddr, size_t page_size, int iommu_prot)
3233 {
3234 struct protection_domain *domain = to_pdomain(dom);
3235 int prot = 0;
3236 int ret;
3237
3238 if (domain->mode == PAGE_MODE_NONE)
3239 return -EINVAL;
3240
3241 if (iommu_prot & IOMMU_READ)
3242 prot |= IOMMU_PROT_IR;
3243 if (iommu_prot & IOMMU_WRITE)
3244 prot |= IOMMU_PROT_IW;
3245
3246 mutex_lock(&domain->api_lock);
3247 ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL);
3248 mutex_unlock(&domain->api_lock);
3249
3250 return ret;
3251 }
3252
3253 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3254 size_t page_size)
3255 {
3256 struct protection_domain *domain = to_pdomain(dom);
3257 size_t unmap_size;
3258
3259 if (domain->mode == PAGE_MODE_NONE)
3260 return -EINVAL;
3261
3262 mutex_lock(&domain->api_lock);
3263 unmap_size = iommu_unmap_page(domain, iova, page_size);
3264 mutex_unlock(&domain->api_lock);
3265
3266 domain_flush_tlb_pde(domain);
3267
3268 return unmap_size;
3269 }
3270
3271 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3272 dma_addr_t iova)
3273 {
3274 struct protection_domain *domain = to_pdomain(dom);
3275 unsigned long offset_mask, pte_pgsize;
3276 u64 *pte, __pte;
3277
3278 if (domain->mode == PAGE_MODE_NONE)
3279 return iova;
3280
3281 pte = fetch_pte(domain, iova, &pte_pgsize);
3282
3283 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3284 return 0;
3285
3286 offset_mask = pte_pgsize - 1;
3287 __pte = *pte & PM_ADDR_MASK;
3288
3289 return (__pte & ~offset_mask) | (iova & offset_mask);
3290 }
3291
3292 static bool amd_iommu_capable(enum iommu_cap cap)
3293 {
3294 switch (cap) {
3295 case IOMMU_CAP_CACHE_COHERENCY:
3296 return true;
3297 case IOMMU_CAP_INTR_REMAP:
3298 return (irq_remapping_enabled == 1);
3299 case IOMMU_CAP_NOEXEC:
3300 return false;
3301 }
3302
3303 return false;
3304 }
3305
3306 static void amd_iommu_get_resv_regions(struct device *dev,
3307 struct list_head *head)
3308 {
3309 struct iommu_resv_region *region;
3310 struct unity_map_entry *entry;
3311 int devid;
3312
3313 devid = get_device_id(dev);
3314 if (devid < 0)
3315 return;
3316
3317 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
3318 size_t length;
3319 int prot = 0;
3320
3321 if (devid < entry->devid_start || devid > entry->devid_end)
3322 continue;
3323
3324 length = entry->address_end - entry->address_start;
3325 if (entry->prot & IOMMU_PROT_IR)
3326 prot |= IOMMU_READ;
3327 if (entry->prot & IOMMU_PROT_IW)
3328 prot |= IOMMU_WRITE;
3329
3330 region = iommu_alloc_resv_region(entry->address_start,
3331 length, prot,
3332 IOMMU_RESV_DIRECT);
3333 if (!region) {
3334 pr_err("Out of memory allocating dm-regions for %s\n",
3335 dev_name(dev));
3336 return;
3337 }
3338 list_add_tail(&region->list, head);
3339 }
3340
3341 region = iommu_alloc_resv_region(MSI_RANGE_START,
3342 MSI_RANGE_END - MSI_RANGE_START + 1,
3343 0, IOMMU_RESV_MSI);
3344 if (!region)
3345 return;
3346 list_add_tail(&region->list, head);
3347
3348 region = iommu_alloc_resv_region(HT_RANGE_START,
3349 HT_RANGE_END - HT_RANGE_START + 1,
3350 0, IOMMU_RESV_RESERVED);
3351 if (!region)
3352 return;
3353 list_add_tail(&region->list, head);
3354 }
3355
3356 static void amd_iommu_put_resv_regions(struct device *dev,
3357 struct list_head *head)
3358 {
3359 struct iommu_resv_region *entry, *next;
3360
3361 list_for_each_entry_safe(entry, next, head, list)
3362 kfree(entry);
3363 }
3364
3365 static void amd_iommu_apply_resv_region(struct device *dev,
3366 struct iommu_domain *domain,
3367 struct iommu_resv_region *region)
3368 {
3369 struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain));
3370 unsigned long start, end;
3371
3372 start = IOVA_PFN(region->start);
3373 end = IOVA_PFN(region->start + region->length);
3374
3375 WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL);
3376 }
3377
3378 const struct iommu_ops amd_iommu_ops = {
3379 .capable = amd_iommu_capable,
3380 .domain_alloc = amd_iommu_domain_alloc,
3381 .domain_free = amd_iommu_domain_free,
3382 .attach_dev = amd_iommu_attach_device,
3383 .detach_dev = amd_iommu_detach_device,
3384 .map = amd_iommu_map,
3385 .unmap = amd_iommu_unmap,
3386 .map_sg = default_iommu_map_sg,
3387 .iova_to_phys = amd_iommu_iova_to_phys,
3388 .add_device = amd_iommu_add_device,
3389 .remove_device = amd_iommu_remove_device,
3390 .device_group = amd_iommu_device_group,
3391 .get_resv_regions = amd_iommu_get_resv_regions,
3392 .put_resv_regions = amd_iommu_put_resv_regions,
3393 .apply_resv_region = amd_iommu_apply_resv_region,
3394 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3395 };
3396
3397 /*****************************************************************************
3398 *
3399 * The next functions do a basic initialization of IOMMU for pass through
3400 * mode
3401 *
3402 * In passthrough mode the IOMMU is initialized and enabled but not used for
3403 * DMA-API translation.
3404 *
3405 *****************************************************************************/
3406
3407 /* IOMMUv2 specific functions */
3408 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3409 {
3410 return atomic_notifier_chain_register(&ppr_notifier, nb);
3411 }
3412 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3413
3414 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3415 {
3416 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3417 }
3418 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3419
3420 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3421 {
3422 struct protection_domain *domain = to_pdomain(dom);
3423 unsigned long flags;
3424
3425 spin_lock_irqsave(&domain->lock, flags);
3426
3427 /* Update data structure */
3428 domain->mode = PAGE_MODE_NONE;
3429 domain->updated = true;
3430
3431 /* Make changes visible to IOMMUs */
3432 update_domain(domain);
3433
3434 /* Page-table is not visible to IOMMU anymore, so free it */
3435 free_pagetable(domain);
3436
3437 spin_unlock_irqrestore(&domain->lock, flags);
3438 }
3439 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3440
3441 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3442 {
3443 struct protection_domain *domain = to_pdomain(dom);
3444 unsigned long flags;
3445 int levels, ret;
3446
3447 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3448 return -EINVAL;
3449
3450 /* Number of GCR3 table levels required */
3451 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3452 levels += 1;
3453
3454 if (levels > amd_iommu_max_glx_val)
3455 return -EINVAL;
3456
3457 spin_lock_irqsave(&domain->lock, flags);
3458
3459 /*
3460 * Save us all sanity checks whether devices already in the
3461 * domain support IOMMUv2. Just force that the domain has no
3462 * devices attached when it is switched into IOMMUv2 mode.
3463 */
3464 ret = -EBUSY;
3465 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3466 goto out;
3467
3468 ret = -ENOMEM;
3469 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3470 if (domain->gcr3_tbl == NULL)
3471 goto out;
3472
3473 domain->glx = levels;
3474 domain->flags |= PD_IOMMUV2_MASK;
3475 domain->updated = true;
3476
3477 update_domain(domain);
3478
3479 ret = 0;
3480
3481 out:
3482 spin_unlock_irqrestore(&domain->lock, flags);
3483
3484 return ret;
3485 }
3486 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3487
3488 static int __flush_pasid(struct protection_domain *domain, int pasid,
3489 u64 address, bool size)
3490 {
3491 struct iommu_dev_data *dev_data;
3492 struct iommu_cmd cmd;
3493 int i, ret;
3494
3495 if (!(domain->flags & PD_IOMMUV2_MASK))
3496 return -EINVAL;
3497
3498 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3499
3500 /*
3501 * IOMMU TLB needs to be flushed before Device TLB to
3502 * prevent device TLB refill from IOMMU TLB
3503 */
3504 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
3505 if (domain->dev_iommu[i] == 0)
3506 continue;
3507
3508 ret = iommu_queue_command(amd_iommus[i], &cmd);
3509 if (ret != 0)
3510 goto out;
3511 }
3512
3513 /* Wait until IOMMU TLB flushes are complete */
3514 domain_flush_complete(domain);
3515
3516 /* Now flush device TLBs */
3517 list_for_each_entry(dev_data, &domain->dev_list, list) {
3518 struct amd_iommu *iommu;
3519 int qdep;
3520
3521 /*
3522 There might be non-IOMMUv2 capable devices in an IOMMUv2
3523 * domain.
3524 */
3525 if (!dev_data->ats.enabled)
3526 continue;
3527
3528 qdep = dev_data->ats.qdep;
3529 iommu = amd_iommu_rlookup_table[dev_data->devid];
3530
3531 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3532 qdep, address, size);
3533
3534 ret = iommu_queue_command(iommu, &cmd);
3535 if (ret != 0)
3536 goto out;
3537 }
3538
3539 /* Wait until all device TLBs are flushed */
3540 domain_flush_complete(domain);
3541
3542 ret = 0;
3543
3544 out:
3545
3546 return ret;
3547 }
3548
3549 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3550 u64 address)
3551 {
3552 return __flush_pasid(domain, pasid, address, false);
3553 }
3554
3555 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3556 u64 address)
3557 {
3558 struct protection_domain *domain = to_pdomain(dom);
3559 unsigned long flags;
3560 int ret;
3561
3562 spin_lock_irqsave(&domain->lock, flags);
3563 ret = __amd_iommu_flush_page(domain, pasid, address);
3564 spin_unlock_irqrestore(&domain->lock, flags);
3565
3566 return ret;
3567 }
3568 EXPORT_SYMBOL(amd_iommu_flush_page);
3569
3570 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3571 {
3572 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3573 true);
3574 }
3575
3576 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3577 {
3578 struct protection_domain *domain = to_pdomain(dom);
3579 unsigned long flags;
3580 int ret;
3581
3582 spin_lock_irqsave(&domain->lock, flags);
3583 ret = __amd_iommu_flush_tlb(domain, pasid);
3584 spin_unlock_irqrestore(&domain->lock, flags);
3585
3586 return ret;
3587 }
3588 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3589
3590 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3591 {
3592 int index;
3593 u64 *pte;
3594
3595 while (true) {
3596
3597 index = (pasid >> (9 * level)) & 0x1ff;
3598 pte = &root[index];
3599
3600 if (level == 0)
3601 break;
3602
3603 if (!(*pte & GCR3_VALID)) {
3604 if (!alloc)
3605 return NULL;
3606
3607 root = (void *)get_zeroed_page(GFP_ATOMIC);
3608 if (root == NULL)
3609 return NULL;
3610
3611 *pte = iommu_virt_to_phys(root) | GCR3_VALID;
3612 }
3613
3614 root = iommu_phys_to_virt(*pte & PAGE_MASK);
3615
3616 level -= 1;
3617 }
3618
3619 return pte;
3620 }
3621
3622 static int __set_gcr3(struct protection_domain *domain, int pasid,
3623 unsigned long cr3)
3624 {
3625 u64 *pte;
3626
3627 if (domain->mode != PAGE_MODE_NONE)
3628 return -EINVAL;
3629
3630 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3631 if (pte == NULL)
3632 return -ENOMEM;
3633
3634 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3635
3636 return __amd_iommu_flush_tlb(domain, pasid);
3637 }
3638
3639 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3640 {
3641 u64 *pte;
3642
3643 if (domain->mode != PAGE_MODE_NONE)
3644 return -EINVAL;
3645
3646 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3647 if (pte == NULL)
3648 return 0;
3649
3650 *pte = 0;
3651
3652 return __amd_iommu_flush_tlb(domain, pasid);
3653 }
3654
3655 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3656 unsigned long cr3)
3657 {
3658 struct protection_domain *domain = to_pdomain(dom);
3659 unsigned long flags;
3660 int ret;
3661
3662 spin_lock_irqsave(&domain->lock, flags);
3663 ret = __set_gcr3(domain, pasid, cr3);
3664 spin_unlock_irqrestore(&domain->lock, flags);
3665
3666 return ret;
3667 }
3668 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3669
3670 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3671 {
3672 struct protection_domain *domain = to_pdomain(dom);
3673 unsigned long flags;
3674 int ret;
3675
3676 spin_lock_irqsave(&domain->lock, flags);
3677 ret = __clear_gcr3(domain, pasid);
3678 spin_unlock_irqrestore(&domain->lock, flags);
3679
3680 return ret;
3681 }
3682 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3683
3684 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3685 int status, int tag)
3686 {
3687 struct iommu_dev_data *dev_data;
3688 struct amd_iommu *iommu;
3689 struct iommu_cmd cmd;
3690
3691 dev_data = get_dev_data(&pdev->dev);
3692 iommu = amd_iommu_rlookup_table[dev_data->devid];
3693
3694 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3695 tag, dev_data->pri_tlp);
3696
3697 return iommu_queue_command(iommu, &cmd);
3698 }
3699 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3700
3701 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3702 {
3703 struct protection_domain *pdomain;
3704
3705 pdomain = get_domain(&pdev->dev);
3706 if (IS_ERR(pdomain))
3707 return NULL;
3708
3709 /* Only return IOMMUv2 domains */
3710 if (!(pdomain->flags & PD_IOMMUV2_MASK))
3711 return NULL;
3712
3713 return &pdomain->domain;
3714 }
3715 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3716
3717 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3718 {
3719 struct iommu_dev_data *dev_data;
3720
3721 if (!amd_iommu_v2_supported())
3722 return;
3723
3724 dev_data = get_dev_data(&pdev->dev);
3725 dev_data->errata |= (1 << erratum);
3726 }
3727 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3728
3729 int amd_iommu_device_info(struct pci_dev *pdev,
3730 struct amd_iommu_device_info *info)
3731 {
3732 int max_pasids;
3733 int pos;
3734
3735 if (pdev == NULL || info == NULL)
3736 return -EINVAL;
3737
3738 if (!amd_iommu_v2_supported())
3739 return -EINVAL;
3740
3741 memset(info, 0, sizeof(*info));
3742
3743 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3744 if (pos)
3745 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3746
3747 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3748 if (pos)
3749 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3750
3751 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3752 if (pos) {
3753 int features;
3754
3755 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3756 max_pasids = min(max_pasids, (1 << 20));
3757
3758 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3759 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3760
3761 features = pci_pasid_features(pdev);
3762 if (features & PCI_PASID_CAP_EXEC)
3763 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3764 if (features & PCI_PASID_CAP_PRIV)
3765 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3766 }
3767
3768 return 0;
3769 }
3770 EXPORT_SYMBOL(amd_iommu_device_info);
3771
3772 #ifdef CONFIG_IRQ_REMAP
3773
3774 /*****************************************************************************
3775 *
3776 * Interrupt Remapping Implementation
3777 *
3778 *****************************************************************************/
3779
3780 static struct irq_chip amd_ir_chip;
3781
3782 #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
3783 #define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
3784 #define DTE_IRQ_TABLE_LEN (8ULL << 1)
3785 #define DTE_IRQ_REMAP_ENABLE 1ULL
3786
3787 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3788 {
3789 u64 dte;
3790
3791 dte = amd_iommu_dev_table[devid].data[2];
3792 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3793 dte |= iommu_virt_to_phys(table->table);
3794 dte |= DTE_IRQ_REMAP_INTCTL;
3795 dte |= DTE_IRQ_TABLE_LEN;
3796 dte |= DTE_IRQ_REMAP_ENABLE;
3797
3798 amd_iommu_dev_table[devid].data[2] = dte;
3799 }
3800
3801 static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic)
3802 {
3803 struct irq_remap_table *table = NULL;
3804 struct amd_iommu *iommu;
3805 unsigned long flags;
3806 u16 alias;
3807
3808 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3809
3810 iommu = amd_iommu_rlookup_table[devid];
3811 if (!iommu)
3812 goto out_unlock;
3813
3814 table = irq_lookup_table[devid];
3815 if (table)
3816 goto out_unlock;
3817
3818 alias = amd_iommu_alias_table[devid];
3819 table = irq_lookup_table[alias];
3820 if (table) {
3821 irq_lookup_table[devid] = table;
3822 set_dte_irq_entry(devid, table);
3823 iommu_flush_dte(iommu, devid);
3824 goto out;
3825 }
3826
3827 /* Nothing there yet, allocate new irq remapping table */
3828 table = kzalloc(sizeof(*table), GFP_ATOMIC);
3829 if (!table)
3830 goto out_unlock;
3831
3832 /* Initialize table spin-lock */
3833 spin_lock_init(&table->lock);
3834
3835 if (ioapic)
3836 /* Keep the first 32 indexes free for IOAPIC interrupts */
3837 table->min_index = 32;
3838
3839 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC);
3840 if (!table->table) {
3841 kfree(table);
3842 table = NULL;
3843 goto out_unlock;
3844 }
3845
3846 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3847 memset(table->table, 0,
3848 MAX_IRQS_PER_TABLE * sizeof(u32));
3849 else
3850 memset(table->table, 0,
3851 (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
3852
3853 if (ioapic) {
3854 int i;
3855
3856 for (i = 0; i < 32; ++i)
3857 iommu->irte_ops->set_allocated(table, i);
3858 }
3859
3860 irq_lookup_table[devid] = table;
3861 set_dte_irq_entry(devid, table);
3862 iommu_flush_dte(iommu, devid);
3863 if (devid != alias) {
3864 irq_lookup_table[alias] = table;
3865 set_dte_irq_entry(alias, table);
3866 iommu_flush_dte(iommu, alias);
3867 }
3868
3869 out:
3870 iommu_completion_wait(iommu);
3871
3872 out_unlock:
3873 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3874
3875 return table;
3876 }
3877
3878 static int alloc_irq_index(u16 devid, int count)
3879 {
3880 struct irq_remap_table *table;
3881 unsigned long flags;
3882 int index, c;
3883 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3884
3885 if (!iommu)
3886 return -ENODEV;
3887
3888 table = get_irq_table(devid, false);
3889 if (!table)
3890 return -ENODEV;
3891
3892 spin_lock_irqsave(&table->lock, flags);
3893
3894 /* Scan table for free entries */
3895 for (c = 0, index = table->min_index;
3896 index < MAX_IRQS_PER_TABLE;
3897 ++index) {
3898 if (!iommu->irte_ops->is_allocated(table, index))
3899 c += 1;
3900 else
3901 c = 0;
3902
3903 if (c == count) {
3904 for (; c != 0; --c)
3905 iommu->irte_ops->set_allocated(table, index - c + 1);
3906
3907 index -= count - 1;
3908 goto out;
3909 }
3910 }
3911
3912 index = -ENOSPC;
3913
3914 out:
3915 spin_unlock_irqrestore(&table->lock, flags);
3916
3917 return index;
3918 }
3919
3920 static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
3921 struct amd_ir_data *data)
3922 {
3923 struct irq_remap_table *table;
3924 struct amd_iommu *iommu;
3925 unsigned long flags;
3926 struct irte_ga *entry;
3927
3928 iommu = amd_iommu_rlookup_table[devid];
3929 if (iommu == NULL)
3930 return -EINVAL;
3931
3932 table = get_irq_table(devid, false);
3933 if (!table)
3934 return -ENOMEM;
3935
3936 spin_lock_irqsave(&table->lock, flags);
3937
3938 entry = (struct irte_ga *)table->table;
3939 entry = &entry[index];
3940 entry->lo.fields_remap.valid = 0;
3941 entry->hi.val = irte->hi.val;
3942 entry->lo.val = irte->lo.val;
3943 entry->lo.fields_remap.valid = 1;
3944 if (data)
3945 data->ref = entry;
3946
3947 spin_unlock_irqrestore(&table->lock, flags);
3948
3949 iommu_flush_irt(iommu, devid);
3950 iommu_completion_wait(iommu);
3951
3952 return 0;
3953 }
3954
3955 static int modify_irte(u16 devid, int index, union irte *irte)
3956 {
3957 struct irq_remap_table *table;
3958 struct amd_iommu *iommu;
3959 unsigned long flags;
3960
3961 iommu = amd_iommu_rlookup_table[devid];
3962 if (iommu == NULL)
3963 return -EINVAL;
3964
3965 table = get_irq_table(devid, false);
3966 if (!table)
3967 return -ENOMEM;
3968
3969 spin_lock_irqsave(&table->lock, flags);
3970 table->table[index] = irte->val;
3971 spin_unlock_irqrestore(&table->lock, flags);
3972
3973 iommu_flush_irt(iommu, devid);
3974 iommu_completion_wait(iommu);
3975
3976 return 0;
3977 }
3978
3979 static void free_irte(u16 devid, int index)
3980 {
3981 struct irq_remap_table *table;
3982 struct amd_iommu *iommu;
3983 unsigned long flags;
3984
3985 iommu = amd_iommu_rlookup_table[devid];
3986 if (iommu == NULL)
3987 return;
3988
3989 table = get_irq_table(devid, false);
3990 if (!table)
3991 return;
3992
3993 spin_lock_irqsave(&table->lock, flags);
3994 iommu->irte_ops->clear_allocated(table, index);
3995 spin_unlock_irqrestore(&table->lock, flags);
3996
3997 iommu_flush_irt(iommu, devid);
3998 iommu_completion_wait(iommu);
3999 }
4000
4001 static void irte_prepare(void *entry,
4002 u32 delivery_mode, u32 dest_mode,
4003 u8 vector, u32 dest_apicid, int devid)
4004 {
4005 union irte *irte = (union irte *) entry;
4006
4007 irte->val = 0;
4008 irte->fields.vector = vector;
4009 irte->fields.int_type = delivery_mode;
4010 irte->fields.destination = dest_apicid;
4011 irte->fields.dm = dest_mode;
4012 irte->fields.valid = 1;
4013 }
4014
4015 static void irte_ga_prepare(void *entry,
4016 u32 delivery_mode, u32 dest_mode,
4017 u8 vector, u32 dest_apicid, int devid)
4018 {
4019 struct irte_ga *irte = (struct irte_ga *) entry;
4020
4021 irte->lo.val = 0;
4022 irte->hi.val = 0;
4023 irte->lo.fields_remap.int_type = delivery_mode;
4024 irte->lo.fields_remap.dm = dest_mode;
4025 irte->hi.fields.vector = vector;
4026 irte->lo.fields_remap.destination = dest_apicid;
4027 irte->lo.fields_remap.valid = 1;
4028 }
4029
4030 static void irte_activate(void *entry, u16 devid, u16 index)
4031 {
4032 union irte *irte = (union irte *) entry;
4033
4034 irte->fields.valid = 1;
4035 modify_irte(devid, index, irte);
4036 }
4037
4038 static void irte_ga_activate(void *entry, u16 devid, u16 index)
4039 {
4040 struct irte_ga *irte = (struct irte_ga *) entry;
4041
4042 irte->lo.fields_remap.valid = 1;
4043 modify_irte_ga(devid, index, irte, NULL);
4044 }
4045
4046 static void irte_deactivate(void *entry, u16 devid, u16 index)
4047 {
4048 union irte *irte = (union irte *) entry;
4049
4050 irte->fields.valid = 0;
4051 modify_irte(devid, index, irte);
4052 }
4053
4054 static void irte_ga_deactivate(void *entry, u16 devid, u16 index)
4055 {
4056 struct irte_ga *irte = (struct irte_ga *) entry;
4057
4058 irte->lo.fields_remap.valid = 0;
4059 modify_irte_ga(devid, index, irte, NULL);
4060 }
4061
4062 static void irte_set_affinity(void *entry, u16 devid, u16 index,
4063 u8 vector, u32 dest_apicid)
4064 {
4065 union irte *irte = (union irte *) entry;
4066
4067 irte->fields.vector = vector;
4068 irte->fields.destination = dest_apicid;
4069 modify_irte(devid, index, irte);
4070 }
4071
4072 static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
4073 u8 vector, u32 dest_apicid)
4074 {
4075 struct irte_ga *irte = (struct irte_ga *) entry;
4076 struct iommu_dev_data *dev_data = search_dev_data(devid);
4077
4078 if (!dev_data || !dev_data->use_vapic ||
4079 !irte->lo.fields_remap.guest_mode) {
4080 irte->hi.fields.vector = vector;
4081 irte->lo.fields_remap.destination = dest_apicid;
4082 modify_irte_ga(devid, index, irte, NULL);
4083 }
4084 }
4085
4086 #define IRTE_ALLOCATED (~1U)
4087 static void irte_set_allocated(struct irq_remap_table *table, int index)
4088 {
4089 table->table[index] = IRTE_ALLOCATED;
4090 }
4091
4092 static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
4093 {
4094 struct irte_ga *ptr = (struct irte_ga *)table->table;
4095 struct irte_ga *irte = &ptr[index];
4096
4097 memset(&irte->lo.val, 0, sizeof(u64));
4098 memset(&irte->hi.val, 0, sizeof(u64));
4099 irte->hi.fields.vector = 0xff;
4100 }
4101
4102 static bool irte_is_allocated(struct irq_remap_table *table, int index)
4103 {
4104 union irte *ptr = (union irte *)table->table;
4105 union irte *irte = &ptr[index];
4106
4107 return irte->val != 0;
4108 }
4109
4110 static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
4111 {
4112 struct irte_ga *ptr = (struct irte_ga *)table->table;
4113 struct irte_ga *irte = &ptr[index];
4114
4115 return irte->hi.fields.vector != 0;
4116 }
4117
4118 static void irte_clear_allocated(struct irq_remap_table *table, int index)
4119 {
4120 table->table[index] = 0;
4121 }
4122
4123 static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
4124 {
4125 struct irte_ga *ptr = (struct irte_ga *)table->table;
4126 struct irte_ga *irte = &ptr[index];
4127
4128 memset(&irte->lo.val, 0, sizeof(u64));
4129 memset(&irte->hi.val, 0, sizeof(u64));
4130 }
4131
4132 static int get_devid(struct irq_alloc_info *info)
4133 {
4134 int devid = -1;
4135
4136 switch (info->type) {
4137 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4138 devid = get_ioapic_devid(info->ioapic_id);
4139 break;
4140 case X86_IRQ_ALLOC_TYPE_HPET:
4141 devid = get_hpet_devid(info->hpet_id);
4142 break;
4143 case X86_IRQ_ALLOC_TYPE_MSI:
4144 case X86_IRQ_ALLOC_TYPE_MSIX:
4145 devid = get_device_id(&info->msi_dev->dev);
4146 break;
4147 default:
4148 BUG_ON(1);
4149 break;
4150 }
4151
4152 return devid;
4153 }
4154
4155 static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
4156 {
4157 struct amd_iommu *iommu;
4158 int devid;
4159
4160 if (!info)
4161 return NULL;
4162
4163 devid = get_devid(info);
4164 if (devid >= 0) {
4165 iommu = amd_iommu_rlookup_table[devid];
4166 if (iommu)
4167 return iommu->ir_domain;
4168 }
4169
4170 return NULL;
4171 }
4172
4173 static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
4174 {
4175 struct amd_iommu *iommu;
4176 int devid;
4177
4178 if (!info)
4179 return NULL;
4180
4181 switch (info->type) {
4182 case X86_IRQ_ALLOC_TYPE_MSI:
4183 case X86_IRQ_ALLOC_TYPE_MSIX:
4184 devid = get_device_id(&info->msi_dev->dev);
4185 if (devid < 0)
4186 return NULL;
4187
4188 iommu = amd_iommu_rlookup_table[devid];
4189 if (iommu)
4190 return iommu->msi_domain;
4191 break;
4192 default:
4193 break;
4194 }
4195
4196 return NULL;
4197 }
4198
4199 struct irq_remap_ops amd_iommu_irq_ops = {
4200 .prepare = amd_iommu_prepare,
4201 .enable = amd_iommu_enable,
4202 .disable = amd_iommu_disable,
4203 .reenable = amd_iommu_reenable,
4204 .enable_faulting = amd_iommu_enable_faulting,
4205 .get_ir_irq_domain = get_ir_irq_domain,
4206 .get_irq_domain = get_irq_domain,
4207 };
4208
4209 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
4210 struct irq_cfg *irq_cfg,
4211 struct irq_alloc_info *info,
4212 int devid, int index, int sub_handle)
4213 {
4214 struct irq_2_irte *irte_info = &data->irq_2_irte;
4215 struct msi_msg *msg = &data->msi_entry;
4216 struct IO_APIC_route_entry *entry;
4217 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
4218
4219 if (!iommu)
4220 return;
4221
4222 data->irq_2_irte.devid = devid;
4223 data->irq_2_irte.index = index + sub_handle;
4224 iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode,
4225 apic->irq_dest_mode, irq_cfg->vector,
4226 irq_cfg->dest_apicid, devid);
4227
4228 switch (info->type) {
4229 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4230 /* Setup IOAPIC entry */
4231 entry = info->ioapic_entry;
4232 info->ioapic_entry = NULL;
4233 memset(entry, 0, sizeof(*entry));
4234 entry->vector = index;
4235 entry->mask = 0;
4236 entry->trigger = info->ioapic_trigger;
4237 entry->polarity = info->ioapic_polarity;
4238 /* Mask level triggered irqs. */
4239 if (info->ioapic_trigger)
4240 entry->mask = 1;
4241 break;
4242
4243 case X86_IRQ_ALLOC_TYPE_HPET:
4244 case X86_IRQ_ALLOC_TYPE_MSI:
4245 case X86_IRQ_ALLOC_TYPE_MSIX:
4246 msg->address_hi = MSI_ADDR_BASE_HI;
4247 msg->address_lo = MSI_ADDR_BASE_LO;
4248 msg->data = irte_info->index;
4249 break;
4250
4251 default:
4252 BUG_ON(1);
4253 break;
4254 }
4255 }
4256
4257 struct amd_irte_ops irte_32_ops = {
4258 .prepare = irte_prepare,
4259 .activate = irte_activate,
4260 .deactivate = irte_deactivate,
4261 .set_affinity = irte_set_affinity,
4262 .set_allocated = irte_set_allocated,
4263 .is_allocated = irte_is_allocated,
4264 .clear_allocated = irte_clear_allocated,
4265 };
4266
4267 struct amd_irte_ops irte_128_ops = {
4268 .prepare = irte_ga_prepare,
4269 .activate = irte_ga_activate,
4270 .deactivate = irte_ga_deactivate,
4271 .set_affinity = irte_ga_set_affinity,
4272 .set_allocated = irte_ga_set_allocated,
4273 .is_allocated = irte_ga_is_allocated,
4274 .clear_allocated = irte_ga_clear_allocated,
4275 };
4276
4277 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
4278 unsigned int nr_irqs, void *arg)
4279 {
4280 struct irq_alloc_info *info = arg;
4281 struct irq_data *irq_data;
4282 struct amd_ir_data *data = NULL;
4283 struct irq_cfg *cfg;
4284 int i, ret, devid;
4285 int index = -1;
4286
4287 if (!info)
4288 return -EINVAL;
4289 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
4290 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
4291 return -EINVAL;
4292
4293 /*
4294 * With IRQ remapping enabled, don't need contiguous CPU vectors
4295 * to support multiple MSI interrupts.
4296 */
4297 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
4298 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
4299
4300 devid = get_devid(info);
4301 if (devid < 0)
4302 return -EINVAL;
4303
4304 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
4305 if (ret < 0)
4306 return ret;
4307
4308 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
4309 if (get_irq_table(devid, true))
4310 index = info->ioapic_pin;
4311 else
4312 ret = -ENOMEM;
4313 } else {
4314 index = alloc_irq_index(devid, nr_irqs);
4315 }
4316 if (index < 0) {
4317 pr_warn("Failed to allocate IRTE\n");
4318 ret = index;
4319 goto out_free_parent;
4320 }
4321
4322 for (i = 0; i < nr_irqs; i++) {
4323 irq_data = irq_domain_get_irq_data(domain, virq + i);
4324 cfg = irqd_cfg(irq_data);
4325 if (!irq_data || !cfg) {
4326 ret = -EINVAL;
4327 goto out_free_data;
4328 }
4329
4330 ret = -ENOMEM;
4331 data = kzalloc(sizeof(*data), GFP_KERNEL);
4332 if (!data)
4333 goto out_free_data;
4334
4335 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
4336 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
4337 else
4338 data->entry = kzalloc(sizeof(struct irte_ga),
4339 GFP_KERNEL);
4340 if (!data->entry) {
4341 kfree(data);
4342 goto out_free_data;
4343 }
4344
4345 irq_data->hwirq = (devid << 16) + i;
4346 irq_data->chip_data = data;
4347 irq_data->chip = &amd_ir_chip;
4348 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
4349 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
4350 }
4351
4352 return 0;
4353
4354 out_free_data:
4355 for (i--; i >= 0; i--) {
4356 irq_data = irq_domain_get_irq_data(domain, virq + i);
4357 if (irq_data)
4358 kfree(irq_data->chip_data);
4359 }
4360 for (i = 0; i < nr_irqs; i++)
4361 free_irte(devid, index + i);
4362 out_free_parent:
4363 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4364 return ret;
4365 }
4366
4367 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
4368 unsigned int nr_irqs)
4369 {
4370 struct irq_2_irte *irte_info;
4371 struct irq_data *irq_data;
4372 struct amd_ir_data *data;
4373 int i;
4374
4375 for (i = 0; i < nr_irqs; i++) {
4376 irq_data = irq_domain_get_irq_data(domain, virq + i);
4377 if (irq_data && irq_data->chip_data) {
4378 data = irq_data->chip_data;
4379 irte_info = &data->irq_2_irte;
4380 free_irte(irte_info->devid, irte_info->index);
4381 kfree(data->entry);
4382 kfree(data);
4383 }
4384 }
4385 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4386 }
4387
4388 static void irq_remapping_activate(struct irq_domain *domain,
4389 struct irq_data *irq_data)
4390 {
4391 struct amd_ir_data *data = irq_data->chip_data;
4392 struct irq_2_irte *irte_info = &data->irq_2_irte;
4393 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4394
4395 if (iommu)
4396 iommu->irte_ops->activate(data->entry, irte_info->devid,
4397 irte_info->index);
4398 }
4399
4400 static void irq_remapping_deactivate(struct irq_domain *domain,
4401 struct irq_data *irq_data)
4402 {
4403 struct amd_ir_data *data = irq_data->chip_data;
4404 struct irq_2_irte *irte_info = &data->irq_2_irte;
4405 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4406
4407 if (iommu)
4408 iommu->irte_ops->deactivate(data->entry, irte_info->devid,
4409 irte_info->index);
4410 }
4411
4412 static const struct irq_domain_ops amd_ir_domain_ops = {
4413 .alloc = irq_remapping_alloc,
4414 .free = irq_remapping_free,
4415 .activate = irq_remapping_activate,
4416 .deactivate = irq_remapping_deactivate,
4417 };
4418
4419 static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
4420 {
4421 struct amd_iommu *iommu;
4422 struct amd_iommu_pi_data *pi_data = vcpu_info;
4423 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
4424 struct amd_ir_data *ir_data = data->chip_data;
4425 struct irte_ga *irte = (struct irte_ga *) ir_data->entry;
4426 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4427 struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid);
4428
4429 /* Note:
4430 * This device has never been set up for guest mode.
4431 * we should not modify the IRTE
4432 */
4433 if (!dev_data || !dev_data->use_vapic)
4434 return 0;
4435
4436 pi_data->ir_data = ir_data;
4437
4438 /* Note:
4439 * SVM tries to set up for VAPIC mode, but we are in
4440 * legacy mode. So, we force legacy mode instead.
4441 */
4442 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
4443 pr_debug("AMD-Vi: %s: Fall back to using intr legacy remap\n",
4444 __func__);
4445 pi_data->is_guest_mode = false;
4446 }
4447
4448 iommu = amd_iommu_rlookup_table[irte_info->devid];
4449 if (iommu == NULL)
4450 return -EINVAL;
4451
4452 pi_data->prev_ga_tag = ir_data->cached_ga_tag;
4453 if (pi_data->is_guest_mode) {
4454 /* Setting */
4455 irte->hi.fields.ga_root_ptr = (pi_data->base >> 12);
4456 irte->hi.fields.vector = vcpu_pi_info->vector;
4457 irte->lo.fields_vapic.ga_log_intr = 1;
4458 irte->lo.fields_vapic.guest_mode = 1;
4459 irte->lo.fields_vapic.ga_tag = pi_data->ga_tag;
4460
4461 ir_data->cached_ga_tag = pi_data->ga_tag;
4462 } else {
4463 /* Un-Setting */
4464 struct irq_cfg *cfg = irqd_cfg(data);
4465
4466 irte->hi.val = 0;
4467 irte->lo.val = 0;
4468 irte->hi.fields.vector = cfg->vector;
4469 irte->lo.fields_remap.guest_mode = 0;
4470 irte->lo.fields_remap.destination = cfg->dest_apicid;
4471 irte->lo.fields_remap.int_type = apic->irq_delivery_mode;
4472 irte->lo.fields_remap.dm = apic->irq_dest_mode;
4473
4474 /*
4475 * This communicates the ga_tag back to the caller
4476 * so that it can do all the necessary clean up.
4477 */
4478 ir_data->cached_ga_tag = 0;
4479 }
4480
4481 return modify_irte_ga(irte_info->devid, irte_info->index, irte, ir_data);
4482 }
4483
4484 static int amd_ir_set_affinity(struct irq_data *data,
4485 const struct cpumask *mask, bool force)
4486 {
4487 struct amd_ir_data *ir_data = data->chip_data;
4488 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4489 struct irq_cfg *cfg = irqd_cfg(data);
4490 struct irq_data *parent = data->parent_data;
4491 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4492 int ret;
4493
4494 if (!iommu)
4495 return -ENODEV;
4496
4497 ret = parent->chip->irq_set_affinity(parent, mask, force);
4498 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
4499 return ret;
4500
4501 /*
4502 * Atomically updates the IRTE with the new destination, vector
4503 * and flushes the interrupt entry cache.
4504 */
4505 iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid,
4506 irte_info->index, cfg->vector, cfg->dest_apicid);
4507
4508 /*
4509 * After this point, all the interrupts will start arriving
4510 * at the new destination. So, time to cleanup the previous
4511 * vector allocation.
4512 */
4513 send_cleanup_vector(cfg);
4514
4515 return IRQ_SET_MASK_OK_DONE;
4516 }
4517
4518 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
4519 {
4520 struct amd_ir_data *ir_data = irq_data->chip_data;
4521
4522 *msg = ir_data->msi_entry;
4523 }
4524
4525 static struct irq_chip amd_ir_chip = {
4526 .name = "AMD-IR",
4527 .irq_ack = ir_ack_apic_edge,
4528 .irq_set_affinity = amd_ir_set_affinity,
4529 .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity,
4530 .irq_compose_msi_msg = ir_compose_msi_msg,
4531 };
4532
4533 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4534 {
4535 struct fwnode_handle *fn;
4536
4537 fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index);
4538 if (!fn)
4539 return -ENOMEM;
4540 iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu);
4541 irq_domain_free_fwnode(fn);
4542 if (!iommu->ir_domain)
4543 return -ENOMEM;
4544
4545 iommu->ir_domain->parent = arch_get_ir_parent_domain();
4546 iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain,
4547 "AMD-IR-MSI",
4548 iommu->index);
4549 return 0;
4550 }
4551
4552 int amd_iommu_update_ga(int cpu, bool is_run, void *data)
4553 {
4554 unsigned long flags;
4555 struct amd_iommu *iommu;
4556 struct irq_remap_table *irt;
4557 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4558 int devid = ir_data->irq_2_irte.devid;
4559 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4560 struct irte_ga *ref = (struct irte_ga *) ir_data->ref;
4561
4562 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4563 !ref || !entry || !entry->lo.fields_vapic.guest_mode)
4564 return 0;
4565
4566 iommu = amd_iommu_rlookup_table[devid];
4567 if (!iommu)
4568 return -ENODEV;
4569
4570 irt = get_irq_table(devid, false);
4571 if (!irt)
4572 return -ENODEV;
4573
4574 spin_lock_irqsave(&irt->lock, flags);
4575
4576 if (ref->lo.fields_vapic.guest_mode) {
4577 if (cpu >= 0)
4578 ref->lo.fields_vapic.destination = cpu;
4579 ref->lo.fields_vapic.is_run = is_run;
4580 barrier();
4581 }
4582
4583 spin_unlock_irqrestore(&irt->lock, flags);
4584
4585 iommu_flush_irt(iommu, devid);
4586 iommu_completion_wait(iommu);
4587 return 0;
4588 }
4589 EXPORT_SYMBOL(amd_iommu_update_ga);
4590 #endif
CRIS linux kernel tree