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Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[cris-mirror.git] / drivers / mmc / host / davinci_mmc.c
blob693144e7427b1d9fefbe37c2dd936b602dab2af7
1 /*
2 * davinci_mmc.c - TI DaVinci MMC/SD/SDIO driver
3 *
4 * Copyright (C) 2006 Texas Instruments.
5 * Original author: Purushotam Kumar
6 * Copyright (C) 2009 David Brownell
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23 #include <linux/module.h>
24 #include <linux/ioport.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/err.h>
28 #include <linux/cpufreq.h>
29 #include <linux/mmc/host.h>
30 #include <linux/io.h>
31 #include <linux/irq.h>
32 #include <linux/delay.h>
33 #include <linux/dmaengine.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/edma.h>
36 #include <linux/mmc/mmc.h>
37 #include <linux/of.h>
38 #include <linux/of_device.h>
39
40 #include <linux/platform_data/edma.h>
41 #include <linux/platform_data/mmc-davinci.h>
42
43 /*
44 * Register Definitions
45 */
46 #define DAVINCI_MMCCTL 0x00 /* Control Register */
47 #define DAVINCI_MMCCLK 0x04 /* Memory Clock Control Register */
48 #define DAVINCI_MMCST0 0x08 /* Status Register 0 */
49 #define DAVINCI_MMCST1 0x0C /* Status Register 1 */
50 #define DAVINCI_MMCIM 0x10 /* Interrupt Mask Register */
51 #define DAVINCI_MMCTOR 0x14 /* Response Time-Out Register */
52 #define DAVINCI_MMCTOD 0x18 /* Data Read Time-Out Register */
53 #define DAVINCI_MMCBLEN 0x1C /* Block Length Register */
54 #define DAVINCI_MMCNBLK 0x20 /* Number of Blocks Register */
55 #define DAVINCI_MMCNBLC 0x24 /* Number of Blocks Counter Register */
56 #define DAVINCI_MMCDRR 0x28 /* Data Receive Register */
57 #define DAVINCI_MMCDXR 0x2C /* Data Transmit Register */
58 #define DAVINCI_MMCCMD 0x30 /* Command Register */
59 #define DAVINCI_MMCARGHL 0x34 /* Argument Register */
60 #define DAVINCI_MMCRSP01 0x38 /* Response Register 0 and 1 */
61 #define DAVINCI_MMCRSP23 0x3C /* Response Register 0 and 1 */
62 #define DAVINCI_MMCRSP45 0x40 /* Response Register 0 and 1 */
63 #define DAVINCI_MMCRSP67 0x44 /* Response Register 0 and 1 */
64 #define DAVINCI_MMCDRSP 0x48 /* Data Response Register */
65 #define DAVINCI_MMCETOK 0x4C
66 #define DAVINCI_MMCCIDX 0x50 /* Command Index Register */
67 #define DAVINCI_MMCCKC 0x54
68 #define DAVINCI_MMCTORC 0x58
69 #define DAVINCI_MMCTODC 0x5C
70 #define DAVINCI_MMCBLNC 0x60
71 #define DAVINCI_SDIOCTL 0x64
72 #define DAVINCI_SDIOST0 0x68
73 #define DAVINCI_SDIOIEN 0x6C
74 #define DAVINCI_SDIOIST 0x70
75 #define DAVINCI_MMCFIFOCTL 0x74 /* FIFO Control Register */
76
77 /* DAVINCI_MMCCTL definitions */
78 #define MMCCTL_DATRST (1 << 0)
79 #define MMCCTL_CMDRST (1 << 1)
80 #define MMCCTL_WIDTH_8_BIT (1 << 8)
81 #define MMCCTL_WIDTH_4_BIT (1 << 2)
82 #define MMCCTL_DATEG_DISABLED (0 << 6)
83 #define MMCCTL_DATEG_RISING (1 << 6)
84 #define MMCCTL_DATEG_FALLING (2 << 6)
85 #define MMCCTL_DATEG_BOTH (3 << 6)
86 #define MMCCTL_PERMDR_LE (0 << 9)
87 #define MMCCTL_PERMDR_BE (1 << 9)
88 #define MMCCTL_PERMDX_LE (0 << 10)
89 #define MMCCTL_PERMDX_BE (1 << 10)
90
91 /* DAVINCI_MMCCLK definitions */
92 #define MMCCLK_CLKEN (1 << 8)
93 #define MMCCLK_CLKRT_MASK (0xFF << 0)
94
95 /* IRQ bit definitions, for DAVINCI_MMCST0 and DAVINCI_MMCIM */
96 #define MMCST0_DATDNE BIT(0) /* data done */
97 #define MMCST0_BSYDNE BIT(1) /* busy done */
98 #define MMCST0_RSPDNE BIT(2) /* command done */
99 #define MMCST0_TOUTRD BIT(3) /* data read timeout */
100 #define MMCST0_TOUTRS BIT(4) /* command response timeout */
101 #define MMCST0_CRCWR BIT(5) /* data write CRC error */
102 #define MMCST0_CRCRD BIT(6) /* data read CRC error */
103 #define MMCST0_CRCRS BIT(7) /* command response CRC error */
104 #define MMCST0_DXRDY BIT(9) /* data transmit ready (fifo empty) */
105 #define MMCST0_DRRDY BIT(10) /* data receive ready (data in fifo)*/
106 #define MMCST0_DATED BIT(11) /* DAT3 edge detect */
107 #define MMCST0_TRNDNE BIT(12) /* transfer done */
108
109 /* DAVINCI_MMCST1 definitions */
110 #define MMCST1_BUSY (1 << 0)
111
112 /* DAVINCI_MMCCMD definitions */
113 #define MMCCMD_CMD_MASK (0x3F << 0)
114 #define MMCCMD_PPLEN (1 << 7)
115 #define MMCCMD_BSYEXP (1 << 8)
116 #define MMCCMD_RSPFMT_MASK (3 << 9)
117 #define MMCCMD_RSPFMT_NONE (0 << 9)
118 #define MMCCMD_RSPFMT_R1456 (1 << 9)
119 #define MMCCMD_RSPFMT_R2 (2 << 9)
120 #define MMCCMD_RSPFMT_R3 (3 << 9)
121 #define MMCCMD_DTRW (1 << 11)
122 #define MMCCMD_STRMTP (1 << 12)
123 #define MMCCMD_WDATX (1 << 13)
124 #define MMCCMD_INITCK (1 << 14)
125 #define MMCCMD_DCLR (1 << 15)
126 #define MMCCMD_DMATRIG (1 << 16)
127
128 /* DAVINCI_MMCFIFOCTL definitions */
129 #define MMCFIFOCTL_FIFORST (1 << 0)
130 #define MMCFIFOCTL_FIFODIR_WR (1 << 1)
131 #define MMCFIFOCTL_FIFODIR_RD (0 << 1)
132 #define MMCFIFOCTL_FIFOLEV (1 << 2) /* 0 = 128 bits, 1 = 256 bits */
133 #define MMCFIFOCTL_ACCWD_4 (0 << 3) /* access width of 4 bytes */
134 #define MMCFIFOCTL_ACCWD_3 (1 << 3) /* access width of 3 bytes */
135 #define MMCFIFOCTL_ACCWD_2 (2 << 3) /* access width of 2 bytes */
136 #define MMCFIFOCTL_ACCWD_1 (3 << 3) /* access width of 1 byte */
137
138 /* DAVINCI_SDIOST0 definitions */
139 #define SDIOST0_DAT1_HI BIT(0)
140
141 /* DAVINCI_SDIOIEN definitions */
142 #define SDIOIEN_IOINTEN BIT(0)
143
144 /* DAVINCI_SDIOIST definitions */
145 #define SDIOIST_IOINT BIT(0)
146
147 /* MMCSD Init clock in Hz in opendrain mode */
148 #define MMCSD_INIT_CLOCK 200000
149
150 /*
151 * One scatterlist dma "segment" is at most MAX_CCNT rw_threshold units,
152 * and we handle up to MAX_NR_SG segments. MMC_BLOCK_BOUNCE kicks in only
153 * for drivers with max_segs == 1, making the segments bigger (64KB)
154 * than the page or two that's otherwise typical. nr_sg (passed from
155 * platform data) == 16 gives at least the same throughput boost, using
156 * EDMA transfer linkage instead of spending CPU time copying pages.
157 */
158 #define MAX_CCNT ((1 << 16) - 1)
159
160 #define MAX_NR_SG 16
161
162 static unsigned rw_threshold = 32;
163 module_param(rw_threshold, uint, S_IRUGO);
164 MODULE_PARM_DESC(rw_threshold,
165 "Read/Write threshold. Default = 32");
166
167 static unsigned poll_threshold = 128;
168 module_param(poll_threshold, uint, S_IRUGO);
169 MODULE_PARM_DESC(poll_threshold,
170 "Polling transaction size threshold. Default = 128");
171
172 static unsigned poll_loopcount = 32;
173 module_param(poll_loopcount, uint, S_IRUGO);
174 MODULE_PARM_DESC(poll_loopcount,
175 "Maximum polling loop count. Default = 32");
176
177 static unsigned __initdata use_dma = 1;
178 module_param(use_dma, uint, 0);
179 MODULE_PARM_DESC(use_dma, "Whether to use DMA or not. Default = 1");
180
181 struct mmc_davinci_host {
182 struct mmc_command *cmd;
183 struct mmc_data *data;
184 struct mmc_host *mmc;
185 struct clk *clk;
186 unsigned int mmc_input_clk;
187 void __iomem *base;
188 struct resource *mem_res;
189 int mmc_irq, sdio_irq;
190 unsigned char bus_mode;
191
192 #define DAVINCI_MMC_DATADIR_NONE 0
193 #define DAVINCI_MMC_DATADIR_READ 1
194 #define DAVINCI_MMC_DATADIR_WRITE 2
195 unsigned char data_dir;
196
197 /* buffer is used during PIO of one scatterlist segment, and
198 * is updated along with buffer_bytes_left. bytes_left applies
199 * to all N blocks of the PIO transfer.
200 */
201 u8 *buffer;
202 u32 buffer_bytes_left;
203 u32 bytes_left;
204
205 u32 rxdma, txdma;
206 struct dma_chan *dma_tx;
207 struct dma_chan *dma_rx;
208 bool use_dma;
209 bool do_dma;
210 bool sdio_int;
211 bool active_request;
212
213 /* For PIO we walk scatterlists one segment at a time. */
214 unsigned int sg_len;
215 struct scatterlist *sg;
216
217 /* Version of the MMC/SD controller */
218 u8 version;
219 /* for ns in one cycle calculation */
220 unsigned ns_in_one_cycle;
221 /* Number of sg segments */
222 u8 nr_sg;
223 #ifdef CONFIG_CPU_FREQ
224 struct notifier_block freq_transition;
225 #endif
226 };
227
228 static irqreturn_t mmc_davinci_irq(int irq, void *dev_id);
229
230 /* PIO only */
231 static void mmc_davinci_sg_to_buf(struct mmc_davinci_host *host)
232 {
233 host->buffer_bytes_left = sg_dma_len(host->sg);
234 host->buffer = sg_virt(host->sg);
235 if (host->buffer_bytes_left > host->bytes_left)
236 host->buffer_bytes_left = host->bytes_left;
237 }
238
239 static void davinci_fifo_data_trans(struct mmc_davinci_host *host,
240 unsigned int n)
241 {
242 u8 *p;
243 unsigned int i;
244
245 if (host->buffer_bytes_left == 0) {
246 host->sg = sg_next(host->data->sg);
247 mmc_davinci_sg_to_buf(host);
248 }
249
250 p = host->buffer;
251 if (n > host->buffer_bytes_left)
252 n = host->buffer_bytes_left;
253 host->buffer_bytes_left -= n;
254 host->bytes_left -= n;
255
256 /* NOTE: we never transfer more than rw_threshold bytes
257 * to/from the fifo here; there's no I/O overlap.
258 * This also assumes that access width( i.e. ACCWD) is 4 bytes
259 */
260 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) {
261 for (i = 0; i < (n >> 2); i++) {
262 writel(*((u32 *)p), host->base + DAVINCI_MMCDXR);
263 p = p + 4;
264 }
265 if (n & 3) {
266 iowrite8_rep(host->base + DAVINCI_MMCDXR, p, (n & 3));
267 p = p + (n & 3);
268 }
269 } else {
270 for (i = 0; i < (n >> 2); i++) {
271 *((u32 *)p) = readl(host->base + DAVINCI_MMCDRR);
272 p = p + 4;
273 }
274 if (n & 3) {
275 ioread8_rep(host->base + DAVINCI_MMCDRR, p, (n & 3));
276 p = p + (n & 3);
277 }
278 }
279 host->buffer = p;
280 }
281
282 static void mmc_davinci_start_command(struct mmc_davinci_host *host,
283 struct mmc_command *cmd)
284 {
285 u32 cmd_reg = 0;
286 u32 im_val;
287
288 dev_dbg(mmc_dev(host->mmc), "CMD%d, arg 0x%08x%s\n",
289 cmd->opcode, cmd->arg,
290 ({ char *s;
291 switch (mmc_resp_type(cmd)) {
292 case MMC_RSP_R1:
293 s = ", R1/R5/R6/R7 response";
294 break;
295 case MMC_RSP_R1B:
296 s = ", R1b response";
297 break;
298 case MMC_RSP_R2:
299 s = ", R2 response";
300 break;
301 case MMC_RSP_R3:
302 s = ", R3/R4 response";
303 break;
304 default:
305 s = ", (R? response)";
306 break;
307 }; s; }));
308 host->cmd = cmd;
309
310 switch (mmc_resp_type(cmd)) {
311 case MMC_RSP_R1B:
312 /* There's some spec confusion about when R1B is
313 * allowed, but if the card doesn't issue a BUSY
314 * then it's harmless for us to allow it.
315 */
316 cmd_reg |= MMCCMD_BSYEXP;
317 /* FALLTHROUGH */
318 case MMC_RSP_R1: /* 48 bits, CRC */
319 cmd_reg |= MMCCMD_RSPFMT_R1456;
320 break;
321 case MMC_RSP_R2: /* 136 bits, CRC */
322 cmd_reg |= MMCCMD_RSPFMT_R2;
323 break;
324 case MMC_RSP_R3: /* 48 bits, no CRC */
325 cmd_reg |= MMCCMD_RSPFMT_R3;
326 break;
327 default:
328 cmd_reg |= MMCCMD_RSPFMT_NONE;
329 dev_dbg(mmc_dev(host->mmc), "unknown resp_type %04x\n",
330 mmc_resp_type(cmd));
331 break;
332 }
333
334 /* Set command index */
335 cmd_reg |= cmd->opcode;
336
337 /* Enable EDMA transfer triggers */
338 if (host->do_dma)
339 cmd_reg |= MMCCMD_DMATRIG;
340
341 if (host->version == MMC_CTLR_VERSION_2 && host->data != NULL &&
342 host->data_dir == DAVINCI_MMC_DATADIR_READ)
343 cmd_reg |= MMCCMD_DMATRIG;
344
345 /* Setting whether command involves data transfer or not */
346 if (cmd->data)
347 cmd_reg |= MMCCMD_WDATX;
348
349 /* Setting whether data read or write */
350 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE)
351 cmd_reg |= MMCCMD_DTRW;
352
353 if (host->bus_mode == MMC_BUSMODE_PUSHPULL)
354 cmd_reg |= MMCCMD_PPLEN;
355
356 /* set Command timeout */
357 writel(0x1FFF, host->base + DAVINCI_MMCTOR);
358
359 /* Enable interrupt (calculate here, defer until FIFO is stuffed). */
360 im_val = MMCST0_RSPDNE | MMCST0_CRCRS | MMCST0_TOUTRS;
361 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) {
362 im_val |= MMCST0_DATDNE | MMCST0_CRCWR;
363
364 if (!host->do_dma)
365 im_val |= MMCST0_DXRDY;
366 } else if (host->data_dir == DAVINCI_MMC_DATADIR_READ) {
367 im_val |= MMCST0_DATDNE | MMCST0_CRCRD | MMCST0_TOUTRD;
368
369 if (!host->do_dma)
370 im_val |= MMCST0_DRRDY;
371 }
372
373 /*
374 * Before non-DMA WRITE commands the controller needs priming:
375 * FIFO should be populated with 32 bytes i.e. whatever is the FIFO size
376 */
377 if (!host->do_dma && (host->data_dir == DAVINCI_MMC_DATADIR_WRITE))
378 davinci_fifo_data_trans(host, rw_threshold);
379
380 writel(cmd->arg, host->base + DAVINCI_MMCARGHL);
381 writel(cmd_reg, host->base + DAVINCI_MMCCMD);
382
383 host->active_request = true;
384
385 if (!host->do_dma && host->bytes_left <= poll_threshold) {
386 u32 count = poll_loopcount;
387
388 while (host->active_request && count--) {
389 mmc_davinci_irq(0, host);
390 cpu_relax();
391 }
392 }
393
394 if (host->active_request)
395 writel(im_val, host->base + DAVINCI_MMCIM);
396 }
397
398 /*----------------------------------------------------------------------*/
399
400 /* DMA infrastructure */
401
402 static void davinci_abort_dma(struct mmc_davinci_host *host)
403 {
404 struct dma_chan *sync_dev;
405
406 if (host->data_dir == DAVINCI_MMC_DATADIR_READ)
407 sync_dev = host->dma_rx;
408 else
409 sync_dev = host->dma_tx;
410
411 dmaengine_terminate_all(sync_dev);
412 }
413
414 static int mmc_davinci_send_dma_request(struct mmc_davinci_host *host,
415 struct mmc_data *data)
416 {
417 struct dma_chan *chan;
418 struct dma_async_tx_descriptor *desc;
419 int ret = 0;
420
421 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) {
422 struct dma_slave_config dma_tx_conf = {
423 .direction = DMA_MEM_TO_DEV,
424 .dst_addr = host->mem_res->start + DAVINCI_MMCDXR,
425 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
426 .dst_maxburst =
427 rw_threshold / DMA_SLAVE_BUSWIDTH_4_BYTES,
428 };
429 chan = host->dma_tx;
430 dmaengine_slave_config(host->dma_tx, &dma_tx_conf);
431
432 desc = dmaengine_prep_slave_sg(host->dma_tx,
433 data->sg,
434 host->sg_len,
435 DMA_MEM_TO_DEV,
436 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
437 if (!desc) {
438 dev_dbg(mmc_dev(host->mmc),
439 "failed to allocate DMA TX descriptor");
440 ret = -1;
441 goto out;
442 }
443 } else {
444 struct dma_slave_config dma_rx_conf = {
445 .direction = DMA_DEV_TO_MEM,
446 .src_addr = host->mem_res->start + DAVINCI_MMCDRR,
447 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
448 .src_maxburst =
449 rw_threshold / DMA_SLAVE_BUSWIDTH_4_BYTES,
450 };
451 chan = host->dma_rx;
452 dmaengine_slave_config(host->dma_rx, &dma_rx_conf);
453
454 desc = dmaengine_prep_slave_sg(host->dma_rx,
455 data->sg,
456 host->sg_len,
457 DMA_DEV_TO_MEM,
458 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
459 if (!desc) {
460 dev_dbg(mmc_dev(host->mmc),
461 "failed to allocate DMA RX descriptor");
462 ret = -1;
463 goto out;
464 }
465 }
466
467 dmaengine_submit(desc);
468 dma_async_issue_pending(chan);
469
470 out:
471 return ret;
472 }
473
474 static int mmc_davinci_start_dma_transfer(struct mmc_davinci_host *host,
475 struct mmc_data *data)
476 {
477 int i;
478 int mask = rw_threshold - 1;
479 int ret = 0;
480
481 host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
482 ((data->flags & MMC_DATA_WRITE)
483 ? DMA_TO_DEVICE
484 : DMA_FROM_DEVICE));
485
486 /* no individual DMA segment should need a partial FIFO */
487 for (i = 0; i < host->sg_len; i++) {
488 if (sg_dma_len(data->sg + i) & mask) {
489 dma_unmap_sg(mmc_dev(host->mmc),
490 data->sg, data->sg_len,
491 (data->flags & MMC_DATA_WRITE)
492 ? DMA_TO_DEVICE
493 : DMA_FROM_DEVICE);
494 return -1;
495 }
496 }
497
498 host->do_dma = 1;
499 ret = mmc_davinci_send_dma_request(host, data);
500
501 return ret;
502 }
503
504 static void __init_or_module
505 davinci_release_dma_channels(struct mmc_davinci_host *host)
506 {
507 if (!host->use_dma)
508 return;
509
510 dma_release_channel(host->dma_tx);
511 dma_release_channel(host->dma_rx);
512 }
513
514 static int __init davinci_acquire_dma_channels(struct mmc_davinci_host *host)
515 {
516 int r;
517 dma_cap_mask_t mask;
518
519 dma_cap_zero(mask);
520 dma_cap_set(DMA_SLAVE, mask);
521
522 host->dma_tx =
523 dma_request_slave_channel_compat(mask, edma_filter_fn,
524 &host->txdma, mmc_dev(host->mmc), "tx");
525 if (!host->dma_tx) {
526 dev_err(mmc_dev(host->mmc), "Can't get dma_tx channel\n");
527 return -ENODEV;
528 }
529
530 host->dma_rx =
531 dma_request_slave_channel_compat(mask, edma_filter_fn,
532 &host->rxdma, mmc_dev(host->mmc), "rx");
533 if (!host->dma_rx) {
534 dev_err(mmc_dev(host->mmc), "Can't get dma_rx channel\n");
535 r = -ENODEV;
536 goto free_master_write;
537 }
538
539 return 0;
540
541 free_master_write:
542 dma_release_channel(host->dma_tx);
543
544 return r;
545 }
546
547 /*----------------------------------------------------------------------*/
548
549 static void
550 mmc_davinci_prepare_data(struct mmc_davinci_host *host, struct mmc_request *req)
551 {
552 int fifo_lev = (rw_threshold == 32) ? MMCFIFOCTL_FIFOLEV : 0;
553 int timeout;
554 struct mmc_data *data = req->data;
555
556 if (host->version == MMC_CTLR_VERSION_2)
557 fifo_lev = (rw_threshold == 64) ? MMCFIFOCTL_FIFOLEV : 0;
558
559 host->data = data;
560 if (data == NULL) {
561 host->data_dir = DAVINCI_MMC_DATADIR_NONE;
562 writel(0, host->base + DAVINCI_MMCBLEN);
563 writel(0, host->base + DAVINCI_MMCNBLK);
564 return;
565 }
566
567 dev_dbg(mmc_dev(host->mmc), "%s, %d blocks of %d bytes\n",
568 (data->flags & MMC_DATA_WRITE) ? "write" : "read",
569 data->blocks, data->blksz);
570 dev_dbg(mmc_dev(host->mmc), " DTO %d cycles + %d ns\n",
571 data->timeout_clks, data->timeout_ns);
572 timeout = data->timeout_clks +
573 (data->timeout_ns / host->ns_in_one_cycle);
574 if (timeout > 0xffff)
575 timeout = 0xffff;
576
577 writel(timeout, host->base + DAVINCI_MMCTOD);
578 writel(data->blocks, host->base + DAVINCI_MMCNBLK);
579 writel(data->blksz, host->base + DAVINCI_MMCBLEN);
580
581 /* Configure the FIFO */
582 if (data->flags & MMC_DATA_WRITE) {
583 host->data_dir = DAVINCI_MMC_DATADIR_WRITE;
584 writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR | MMCFIFOCTL_FIFORST,
585 host->base + DAVINCI_MMCFIFOCTL);
586 writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR,
587 host->base + DAVINCI_MMCFIFOCTL);
588 } else {
589 host->data_dir = DAVINCI_MMC_DATADIR_READ;
590 writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD | MMCFIFOCTL_FIFORST,
591 host->base + DAVINCI_MMCFIFOCTL);
592 writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD,
593 host->base + DAVINCI_MMCFIFOCTL);
594 }
595
596 host->buffer = NULL;
597 host->bytes_left = data->blocks * data->blksz;
598
599 /* For now we try to use DMA whenever we won't need partial FIFO
600 * reads or writes, either for the whole transfer (as tested here)
601 * or for any individual scatterlist segment (tested when we call
602 * start_dma_transfer).
603 *
604 * While we *could* change that, unusual block sizes are rarely
605 * used. The occasional fallback to PIO should't hurt.
606 */
607 if (host->use_dma && (host->bytes_left & (rw_threshold - 1)) == 0
608 && mmc_davinci_start_dma_transfer(host, data) == 0) {
609 /* zero this to ensure we take no PIO paths */
610 host->bytes_left = 0;
611 } else {
612 /* Revert to CPU Copy */
613 host->sg_len = data->sg_len;
614 host->sg = host->data->sg;
615 mmc_davinci_sg_to_buf(host);
616 }
617 }
618
619 static void mmc_davinci_request(struct mmc_host *mmc, struct mmc_request *req)
620 {
621 struct mmc_davinci_host *host = mmc_priv(mmc);
622 unsigned long timeout = jiffies + msecs_to_jiffies(900);
623 u32 mmcst1 = 0;
624
625 /* Card may still be sending BUSY after a previous operation,
626 * typically some kind of write. If so, we can't proceed yet.
627 */
628 while (time_before(jiffies, timeout)) {
629 mmcst1 = readl(host->base + DAVINCI_MMCST1);
630 if (!(mmcst1 & MMCST1_BUSY))
631 break;
632 cpu_relax();
633 }
634 if (mmcst1 & MMCST1_BUSY) {
635 dev_err(mmc_dev(host->mmc), "still BUSY? bad ... \n");
636 req->cmd->error = -ETIMEDOUT;
637 mmc_request_done(mmc, req);
638 return;
639 }
640
641 host->do_dma = 0;
642 mmc_davinci_prepare_data(host, req);
643 mmc_davinci_start_command(host, req->cmd);
644 }
645
646 static unsigned int calculate_freq_for_card(struct mmc_davinci_host *host,
647 unsigned int mmc_req_freq)
648 {
649 unsigned int mmc_freq = 0, mmc_pclk = 0, mmc_push_pull_divisor = 0;
650
651 mmc_pclk = host->mmc_input_clk;
652 if (mmc_req_freq && mmc_pclk > (2 * mmc_req_freq))
653 mmc_push_pull_divisor = ((unsigned int)mmc_pclk
654 / (2 * mmc_req_freq)) - 1;
655 else
656 mmc_push_pull_divisor = 0;
657
658 mmc_freq = (unsigned int)mmc_pclk
659 / (2 * (mmc_push_pull_divisor + 1));
660
661 if (mmc_freq > mmc_req_freq)
662 mmc_push_pull_divisor = mmc_push_pull_divisor + 1;
663 /* Convert ns to clock cycles */
664 if (mmc_req_freq <= 400000)
665 host->ns_in_one_cycle = (1000000) / (((mmc_pclk
666 / (2 * (mmc_push_pull_divisor + 1)))/1000));
667 else
668 host->ns_in_one_cycle = (1000000) / (((mmc_pclk
669 / (2 * (mmc_push_pull_divisor + 1)))/1000000));
670
671 return mmc_push_pull_divisor;
672 }
673
674 static void calculate_clk_divider(struct mmc_host *mmc, struct mmc_ios *ios)
675 {
676 unsigned int open_drain_freq = 0, mmc_pclk = 0;
677 unsigned int mmc_push_pull_freq = 0;
678 struct mmc_davinci_host *host = mmc_priv(mmc);
679
680 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
681 u32 temp;
682
683 /* Ignoring the init clock value passed for fixing the inter
684 * operability with different cards.
685 */
686 open_drain_freq = ((unsigned int)mmc_pclk
687 / (2 * MMCSD_INIT_CLOCK)) - 1;
688
689 if (open_drain_freq > 0xFF)
690 open_drain_freq = 0xFF;
691
692 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK;
693 temp |= open_drain_freq;
694 writel(temp, host->base + DAVINCI_MMCCLK);
695
696 /* Convert ns to clock cycles */
697 host->ns_in_one_cycle = (1000000) / (MMCSD_INIT_CLOCK/1000);
698 } else {
699 u32 temp;
700 mmc_push_pull_freq = calculate_freq_for_card(host, ios->clock);
701
702 if (mmc_push_pull_freq > 0xFF)
703 mmc_push_pull_freq = 0xFF;
704
705 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKEN;
706 writel(temp, host->base + DAVINCI_MMCCLK);
707
708 udelay(10);
709
710 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK;
711 temp |= mmc_push_pull_freq;
712 writel(temp, host->base + DAVINCI_MMCCLK);
713
714 writel(temp | MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK);
715
716 udelay(10);
717 }
718 }
719
720 static void mmc_davinci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
721 {
722 struct mmc_davinci_host *host = mmc_priv(mmc);
723 struct platform_device *pdev = to_platform_device(mmc->parent);
724 struct davinci_mmc_config *config = pdev->dev.platform_data;
725
726 dev_dbg(mmc_dev(host->mmc),
727 "clock %dHz busmode %d powermode %d Vdd %04x\n",
728 ios->clock, ios->bus_mode, ios->power_mode,
729 ios->vdd);
730
731 switch (ios->power_mode) {
732 case MMC_POWER_OFF:
733 if (config && config->set_power)
734 config->set_power(pdev->id, false);
735 break;
736 case MMC_POWER_UP:
737 if (config && config->set_power)
738 config->set_power(pdev->id, true);
739 break;
740 }
741
742 switch (ios->bus_width) {
743 case MMC_BUS_WIDTH_8:
744 dev_dbg(mmc_dev(host->mmc), "Enabling 8 bit mode\n");
745 writel((readl(host->base + DAVINCI_MMCCTL) &
746 ~MMCCTL_WIDTH_4_BIT) | MMCCTL_WIDTH_8_BIT,
747 host->base + DAVINCI_MMCCTL);
748 break;
749 case MMC_BUS_WIDTH_4:
750 dev_dbg(mmc_dev(host->mmc), "Enabling 4 bit mode\n");
751 if (host->version == MMC_CTLR_VERSION_2)
752 writel((readl(host->base + DAVINCI_MMCCTL) &
753 ~MMCCTL_WIDTH_8_BIT) | MMCCTL_WIDTH_4_BIT,
754 host->base + DAVINCI_MMCCTL);
755 else
756 writel(readl(host->base + DAVINCI_MMCCTL) |
757 MMCCTL_WIDTH_4_BIT,
758 host->base + DAVINCI_MMCCTL);
759 break;
760 case MMC_BUS_WIDTH_1:
761 dev_dbg(mmc_dev(host->mmc), "Enabling 1 bit mode\n");
762 if (host->version == MMC_CTLR_VERSION_2)
763 writel(readl(host->base + DAVINCI_MMCCTL) &
764 ~(MMCCTL_WIDTH_8_BIT | MMCCTL_WIDTH_4_BIT),
765 host->base + DAVINCI_MMCCTL);
766 else
767 writel(readl(host->base + DAVINCI_MMCCTL) &
768 ~MMCCTL_WIDTH_4_BIT,
769 host->base + DAVINCI_MMCCTL);
770 break;
771 }
772
773 calculate_clk_divider(mmc, ios);
774
775 host->bus_mode = ios->bus_mode;
776 if (ios->power_mode == MMC_POWER_UP) {
777 unsigned long timeout = jiffies + msecs_to_jiffies(50);
778 bool lose = true;
779
780 /* Send clock cycles, poll completion */
781 writel(0, host->base + DAVINCI_MMCARGHL);
782 writel(MMCCMD_INITCK, host->base + DAVINCI_MMCCMD);
783 while (time_before(jiffies, timeout)) {
784 u32 tmp = readl(host->base + DAVINCI_MMCST0);
785
786 if (tmp & MMCST0_RSPDNE) {
787 lose = false;
788 break;
789 }
790 cpu_relax();
791 }
792 if (lose)
793 dev_warn(mmc_dev(host->mmc), "powerup timeout\n");
794 }
795
796 /* FIXME on power OFF, reset things ... */
797 }
798
799 static void
800 mmc_davinci_xfer_done(struct mmc_davinci_host *host, struct mmc_data *data)
801 {
802 host->data = NULL;
803
804 if (host->mmc->caps & MMC_CAP_SDIO_IRQ) {
805 /*
806 * SDIO Interrupt Detection work-around as suggested by
807 * Davinci Errata (TMS320DM355 Silicon Revision 1.1 Errata
808 * 2.1.6): Signal SDIO interrupt only if it is enabled by core
809 */
810 if (host->sdio_int && !(readl(host->base + DAVINCI_SDIOST0) &
811 SDIOST0_DAT1_HI)) {
812 writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST);
813 mmc_signal_sdio_irq(host->mmc);
814 }
815 }
816
817 if (host->do_dma) {
818 davinci_abort_dma(host);
819
820 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
821 (data->flags & MMC_DATA_WRITE)
822 ? DMA_TO_DEVICE
823 : DMA_FROM_DEVICE);
824 host->do_dma = false;
825 }
826 host->data_dir = DAVINCI_MMC_DATADIR_NONE;
827
828 if (!data->stop || (host->cmd && host->cmd->error)) {
829 mmc_request_done(host->mmc, data->mrq);
830 writel(0, host->base + DAVINCI_MMCIM);
831 host->active_request = false;
832 } else
833 mmc_davinci_start_command(host, data->stop);
834 }
835
836 static void mmc_davinci_cmd_done(struct mmc_davinci_host *host,
837 struct mmc_command *cmd)
838 {
839 host->cmd = NULL;
840
841 if (cmd->flags & MMC_RSP_PRESENT) {
842 if (cmd->flags & MMC_RSP_136) {
843 /* response type 2 */
844 cmd->resp[3] = readl(host->base + DAVINCI_MMCRSP01);
845 cmd->resp[2] = readl(host->base + DAVINCI_MMCRSP23);
846 cmd->resp[1] = readl(host->base + DAVINCI_MMCRSP45);
847 cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67);
848 } else {
849 /* response types 1, 1b, 3, 4, 5, 6 */
850 cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67);
851 }
852 }
853
854 if (host->data == NULL || cmd->error) {
855 if (cmd->error == -ETIMEDOUT)
856 cmd->mrq->cmd->retries = 0;
857 mmc_request_done(host->mmc, cmd->mrq);
858 writel(0, host->base + DAVINCI_MMCIM);
859 host->active_request = false;
860 }
861 }
862
863 static inline void mmc_davinci_reset_ctrl(struct mmc_davinci_host *host,
864 int val)
865 {
866 u32 temp;
867
868 temp = readl(host->base + DAVINCI_MMCCTL);
869 if (val) /* reset */
870 temp |= MMCCTL_CMDRST | MMCCTL_DATRST;
871 else /* enable */
872 temp &= ~(MMCCTL_CMDRST | MMCCTL_DATRST);
873
874 writel(temp, host->base + DAVINCI_MMCCTL);
875 udelay(10);
876 }
877
878 static void
879 davinci_abort_data(struct mmc_davinci_host *host, struct mmc_data *data)
880 {
881 mmc_davinci_reset_ctrl(host, 1);
882 mmc_davinci_reset_ctrl(host, 0);
883 }
884
885 static irqreturn_t mmc_davinci_sdio_irq(int irq, void *dev_id)
886 {
887 struct mmc_davinci_host *host = dev_id;
888 unsigned int status;
889
890 status = readl(host->base + DAVINCI_SDIOIST);
891 if (status & SDIOIST_IOINT) {
892 dev_dbg(mmc_dev(host->mmc),
893 "SDIO interrupt status %x\n", status);
894 writel(status | SDIOIST_IOINT, host->base + DAVINCI_SDIOIST);
895 mmc_signal_sdio_irq(host->mmc);
896 }
897 return IRQ_HANDLED;
898 }
899
900 static irqreturn_t mmc_davinci_irq(int irq, void *dev_id)
901 {
902 struct mmc_davinci_host *host = (struct mmc_davinci_host *)dev_id;
903 unsigned int status, qstatus;
904 int end_command = 0;
905 int end_transfer = 0;
906 struct mmc_data *data = host->data;
907
908 if (host->cmd == NULL && host->data == NULL) {
909 status = readl(host->base + DAVINCI_MMCST0);
910 dev_dbg(mmc_dev(host->mmc),
911 "Spurious interrupt 0x%04x\n", status);
912 /* Disable the interrupt from mmcsd */
913 writel(0, host->base + DAVINCI_MMCIM);
914 return IRQ_NONE;
915 }
916
917 status = readl(host->base + DAVINCI_MMCST0);
918 qstatus = status;
919
920 /* handle FIFO first when using PIO for data.
921 * bytes_left will decrease to zero as I/O progress and status will
922 * read zero over iteration because this controller status
923 * register(MMCST0) reports any status only once and it is cleared
924 * by read. So, it is not unbouned loop even in the case of
925 * non-dma.
926 */
927 if (host->bytes_left && (status & (MMCST0_DXRDY | MMCST0_DRRDY))) {
928 unsigned long im_val;
929
930 /*
931 * If interrupts fire during the following loop, they will be
932 * handled by the handler, but the PIC will still buffer these.
933 * As a result, the handler will be called again to serve these
934 * needlessly. In order to avoid these spurious interrupts,
935 * keep interrupts masked during the loop.
936 */
937 im_val = readl(host->base + DAVINCI_MMCIM);
938 writel(0, host->base + DAVINCI_MMCIM);
939
940 do {
941 davinci_fifo_data_trans(host, rw_threshold);
942 status = readl(host->base + DAVINCI_MMCST0);
943 qstatus |= status;
944 } while (host->bytes_left &&
945 (status & (MMCST0_DXRDY | MMCST0_DRRDY)));
946
947 /*
948 * If an interrupt is pending, it is assumed it will fire when
949 * it is unmasked. This assumption is also taken when the MMCIM
950 * is first set. Otherwise, writing to MMCIM after reading the
951 * status is race-prone.
952 */
953 writel(im_val, host->base + DAVINCI_MMCIM);
954 }
955
956 if (qstatus & MMCST0_DATDNE) {
957 /* All blocks sent/received, and CRC checks passed */
958 if (data != NULL) {
959 if ((host->do_dma == 0) && (host->bytes_left > 0)) {
960 /* if datasize < rw_threshold
961 * no RX ints are generated
962 */
963 davinci_fifo_data_trans(host, host->bytes_left);
964 }
965 end_transfer = 1;
966 data->bytes_xfered = data->blocks * data->blksz;
967 } else {
968 dev_err(mmc_dev(host->mmc),
969 "DATDNE with no host->data\n");
970 }
971 }
972
973 if (qstatus & MMCST0_TOUTRD) {
974 /* Read data timeout */
975 data->error = -ETIMEDOUT;
976 end_transfer = 1;
977
978 dev_dbg(mmc_dev(host->mmc),
979 "read data timeout, status %x\n",
980 qstatus);
981
982 davinci_abort_data(host, data);
983 }
984
985 if (qstatus & (MMCST0_CRCWR | MMCST0_CRCRD)) {
986 /* Data CRC error */
987 data->error = -EILSEQ;
988 end_transfer = 1;
989
990 /* NOTE: this controller uses CRCWR to report both CRC
991 * errors and timeouts (on writes). MMCDRSP values are
992 * only weakly documented, but 0x9f was clearly a timeout
993 * case and the two three-bit patterns in various SD specs
994 * (101, 010) aren't part of it ...
995 */
996 if (qstatus & MMCST0_CRCWR) {
997 u32 temp = readb(host->base + DAVINCI_MMCDRSP);
998
999 if (temp == 0x9f)
1000 data->error = -ETIMEDOUT;
1001 }
1002 dev_dbg(mmc_dev(host->mmc), "data %s %s error\n",
1003 (qstatus & MMCST0_CRCWR) ? "write" : "read",
1004 (data->error == -ETIMEDOUT) ? "timeout" : "CRC");
1005
1006 davinci_abort_data(host, data);
1007 }
1008
1009 if (qstatus & MMCST0_TOUTRS) {
1010 /* Command timeout */
1011 if (host->cmd) {
1012 dev_dbg(mmc_dev(host->mmc),
1013 "CMD%d timeout, status %x\n",
1014 host->cmd->opcode, qstatus);
1015 host->cmd->error = -ETIMEDOUT;
1016 if (data) {
1017 end_transfer = 1;
1018 davinci_abort_data(host, data);
1019 } else
1020 end_command = 1;
1021 }
1022 }
1023
1024 if (qstatus & MMCST0_CRCRS) {
1025 /* Command CRC error */
1026 dev_dbg(mmc_dev(host->mmc), "Command CRC error\n");
1027 if (host->cmd) {
1028 host->cmd->error = -EILSEQ;
1029 end_command = 1;
1030 }
1031 }
1032
1033 if (qstatus & MMCST0_RSPDNE) {
1034 /* End of command phase */
1035 end_command = (int) host->cmd;
1036 }
1037
1038 if (end_command)
1039 mmc_davinci_cmd_done(host, host->cmd);
1040 if (end_transfer)
1041 mmc_davinci_xfer_done(host, data);
1042 return IRQ_HANDLED;
1043 }
1044
1045 static int mmc_davinci_get_cd(struct mmc_host *mmc)
1046 {
1047 struct platform_device *pdev = to_platform_device(mmc->parent);
1048 struct davinci_mmc_config *config = pdev->dev.platform_data;
1049
1050 if (!config || !config->get_cd)
1051 return -ENOSYS;
1052 return config->get_cd(pdev->id);
1053 }
1054
1055 static int mmc_davinci_get_ro(struct mmc_host *mmc)
1056 {
1057 struct platform_device *pdev = to_platform_device(mmc->parent);
1058 struct davinci_mmc_config *config = pdev->dev.platform_data;
1059
1060 if (!config || !config->get_ro)
1061 return -ENOSYS;
1062 return config->get_ro(pdev->id);
1063 }
1064
1065 static void mmc_davinci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1066 {
1067 struct mmc_davinci_host *host = mmc_priv(mmc);
1068
1069 if (enable) {
1070 if (!(readl(host->base + DAVINCI_SDIOST0) & SDIOST0_DAT1_HI)) {
1071 writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST);
1072 mmc_signal_sdio_irq(host->mmc);
1073 } else {
1074 host->sdio_int = true;
1075 writel(readl(host->base + DAVINCI_SDIOIEN) |
1076 SDIOIEN_IOINTEN, host->base + DAVINCI_SDIOIEN);
1077 }
1078 } else {
1079 host->sdio_int = false;
1080 writel(readl(host->base + DAVINCI_SDIOIEN) & ~SDIOIEN_IOINTEN,
1081 host->base + DAVINCI_SDIOIEN);
1082 }
1083 }
1084
1085 static struct mmc_host_ops mmc_davinci_ops = {
1086 .request = mmc_davinci_request,
1087 .set_ios = mmc_davinci_set_ios,
1088 .get_cd = mmc_davinci_get_cd,
1089 .get_ro = mmc_davinci_get_ro,
1090 .enable_sdio_irq = mmc_davinci_enable_sdio_irq,
1091 };
1092
1093 /*----------------------------------------------------------------------*/
1094
1095 #ifdef CONFIG_CPU_FREQ
1096 static int mmc_davinci_cpufreq_transition(struct notifier_block *nb,
1097 unsigned long val, void *data)
1098 {
1099 struct mmc_davinci_host *host;
1100 unsigned int mmc_pclk;
1101 struct mmc_host *mmc;
1102 unsigned long flags;
1103
1104 host = container_of(nb, struct mmc_davinci_host, freq_transition);
1105 mmc = host->mmc;
1106 mmc_pclk = clk_get_rate(host->clk);
1107
1108 if (val == CPUFREQ_POSTCHANGE) {
1109 spin_lock_irqsave(&mmc->lock, flags);
1110 host->mmc_input_clk = mmc_pclk;
1111 calculate_clk_divider(mmc, &mmc->ios);
1112 spin_unlock_irqrestore(&mmc->lock, flags);
1113 }
1114
1115 return 0;
1116 }
1117
1118 static inline int mmc_davinci_cpufreq_register(struct mmc_davinci_host *host)
1119 {
1120 host->freq_transition.notifier_call = mmc_davinci_cpufreq_transition;
1121
1122 return cpufreq_register_notifier(&host->freq_transition,
1123 CPUFREQ_TRANSITION_NOTIFIER);
1124 }
1125
1126 static inline void mmc_davinci_cpufreq_deregister(struct mmc_davinci_host *host)
1127 {
1128 cpufreq_unregister_notifier(&host->freq_transition,
1129 CPUFREQ_TRANSITION_NOTIFIER);
1130 }
1131 #else
1132 static inline int mmc_davinci_cpufreq_register(struct mmc_davinci_host *host)
1133 {
1134 return 0;
1135 }
1136
1137 static inline void mmc_davinci_cpufreq_deregister(struct mmc_davinci_host *host)
1138 {
1139 }
1140 #endif
1141 static void __init init_mmcsd_host(struct mmc_davinci_host *host)
1142 {
1143
1144 mmc_davinci_reset_ctrl(host, 1);
1145
1146 writel(0, host->base + DAVINCI_MMCCLK);
1147 writel(MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK);
1148
1149 writel(0x1FFF, host->base + DAVINCI_MMCTOR);
1150 writel(0xFFFF, host->base + DAVINCI_MMCTOD);
1151
1152 mmc_davinci_reset_ctrl(host, 0);
1153 }
1154
1155 static const struct platform_device_id davinci_mmc_devtype[] = {
1156 {
1157 .name = "dm6441-mmc",
1158 .driver_data = MMC_CTLR_VERSION_1,
1159 }, {
1160 .name = "da830-mmc",
1161 .driver_data = MMC_CTLR_VERSION_2,
1162 },
1163 {},
1164 };
1165 MODULE_DEVICE_TABLE(platform, davinci_mmc_devtype);
1166
1167 static const struct of_device_id davinci_mmc_dt_ids[] = {
1168 {
1169 .compatible = "ti,dm6441-mmc",
1170 .data = &davinci_mmc_devtype[MMC_CTLR_VERSION_1],
1171 },
1172 {
1173 .compatible = "ti,da830-mmc",
1174 .data = &davinci_mmc_devtype[MMC_CTLR_VERSION_2],
1175 },
1176 {},
1177 };
1178 MODULE_DEVICE_TABLE(of, davinci_mmc_dt_ids);
1179
1180 static struct davinci_mmc_config
1181 *mmc_parse_pdata(struct platform_device *pdev)
1182 {
1183 struct device_node *np;
1184 struct davinci_mmc_config *pdata = pdev->dev.platform_data;
1185 const struct of_device_id *match =
1186 of_match_device(davinci_mmc_dt_ids, &pdev->dev);
1187 u32 data;
1188
1189 np = pdev->dev.of_node;
1190 if (!np)
1191 return pdata;
1192
1193 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1194 if (!pdata) {
1195 dev_err(&pdev->dev, "Failed to allocate memory for struct davinci_mmc_config\n");
1196 goto nodata;
1197 }
1198
1199 if (match)
1200 pdev->id_entry = match->data;
1201
1202 if (of_property_read_u32(np, "max-frequency", &pdata->max_freq))
1203 dev_info(&pdev->dev, "'max-frequency' property not specified, defaulting to 25MHz\n");
1204
1205 of_property_read_u32(np, "bus-width", &data);
1206 switch (data) {
1207 case 1:
1208 case 4:
1209 case 8:
1210 pdata->wires = data;
1211 break;
1212 default:
1213 pdata->wires = 1;
1214 dev_info(&pdev->dev, "Unsupported buswidth, defaulting to 1 bit\n");
1215 }
1216 nodata:
1217 return pdata;
1218 }
1219
1220 static int __init davinci_mmcsd_probe(struct platform_device *pdev)
1221 {
1222 struct davinci_mmc_config *pdata = NULL;
1223 struct mmc_davinci_host *host = NULL;
1224 struct mmc_host *mmc = NULL;
1225 struct resource *r, *mem = NULL;
1226 int ret = 0, irq = 0;
1227 size_t mem_size;
1228 const struct platform_device_id *id_entry;
1229
1230 pdata = mmc_parse_pdata(pdev);
1231 if (pdata == NULL) {
1232 dev_err(&pdev->dev, "Couldn't get platform data\n");
1233 return -ENOENT;
1234 }
1235
1236 ret = -ENODEV;
1237 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1238 irq = platform_get_irq(pdev, 0);
1239 if (!r || irq == NO_IRQ)
1240 goto out;
1241
1242 ret = -EBUSY;
1243 mem_size = resource_size(r);
1244 mem = request_mem_region(r->start, mem_size, pdev->name);
1245 if (!mem)
1246 goto out;
1247
1248 ret = -ENOMEM;
1249 mmc = mmc_alloc_host(sizeof(struct mmc_davinci_host), &pdev->dev);
1250 if (!mmc)
1251 goto out;
1252
1253 host = mmc_priv(mmc);
1254 host->mmc = mmc; /* Important */
1255
1256 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1257 if (!r)
1258 dev_warn(&pdev->dev, "RX DMA resource not specified\n");
1259 else
1260 host->rxdma = r->start;
1261
1262 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1263 if (!r)
1264 dev_warn(&pdev->dev, "TX DMA resource not specified\n");
1265 else
1266 host->txdma = r->start;
1267
1268 host->mem_res = mem;
1269 host->base = ioremap(mem->start, mem_size);
1270 if (!host->base)
1271 goto out;
1272
1273 ret = -ENXIO;
1274 host->clk = clk_get(&pdev->dev, "MMCSDCLK");
1275 if (IS_ERR(host->clk)) {
1276 ret = PTR_ERR(host->clk);
1277 goto out;
1278 }
1279 clk_enable(host->clk);
1280 host->mmc_input_clk = clk_get_rate(host->clk);
1281
1282 init_mmcsd_host(host);
1283
1284 if (pdata->nr_sg)
1285 host->nr_sg = pdata->nr_sg - 1;
1286
1287 if (host->nr_sg > MAX_NR_SG || !host->nr_sg)
1288 host->nr_sg = MAX_NR_SG;
1289
1290 host->use_dma = use_dma;
1291 host->mmc_irq = irq;
1292 host->sdio_irq = platform_get_irq(pdev, 1);
1293
1294 if (host->use_dma && davinci_acquire_dma_channels(host) != 0)
1295 host->use_dma = 0;
1296
1297 /* REVISIT: someday, support IRQ-driven card detection. */
1298 mmc->caps |= MMC_CAP_NEEDS_POLL;
1299 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
1300
1301 if (pdata && (pdata->wires == 4 || pdata->wires == 0))
1302 mmc->caps |= MMC_CAP_4_BIT_DATA;
1303
1304 if (pdata && (pdata->wires == 8))
1305 mmc->caps |= (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA);
1306
1307 id_entry = platform_get_device_id(pdev);
1308 if (id_entry)
1309 host->version = id_entry->driver_data;
1310
1311 mmc->ops = &mmc_davinci_ops;
1312 mmc->f_min = 312500;
1313 mmc->f_max = 25000000;
1314 if (pdata && pdata->max_freq)
1315 mmc->f_max = pdata->max_freq;
1316 if (pdata && pdata->caps)
1317 mmc->caps |= pdata->caps;
1318 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1319
1320 /* With no iommu coalescing pages, each phys_seg is a hw_seg.
1321 * Each hw_seg uses one EDMA parameter RAM slot, always one
1322 * channel and then usually some linked slots.
1323 */
1324 mmc->max_segs = MAX_NR_SG;
1325
1326 /* EDMA limit per hw segment (one or two MBytes) */
1327 mmc->max_seg_size = MAX_CCNT * rw_threshold;
1328
1329 /* MMC/SD controller limits for multiblock requests */
1330 mmc->max_blk_size = 4095; /* BLEN is 12 bits */
1331 mmc->max_blk_count = 65535; /* NBLK is 16 bits */
1332 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1333
1334 dev_dbg(mmc_dev(host->mmc), "max_segs=%d\n", mmc->max_segs);
1335 dev_dbg(mmc_dev(host->mmc), "max_blk_size=%d\n", mmc->max_blk_size);
1336 dev_dbg(mmc_dev(host->mmc), "max_req_size=%d\n", mmc->max_req_size);
1337 dev_dbg(mmc_dev(host->mmc), "max_seg_size=%d\n", mmc->max_seg_size);
1338
1339 platform_set_drvdata(pdev, host);
1340
1341 ret = mmc_davinci_cpufreq_register(host);
1342 if (ret) {
1343 dev_err(&pdev->dev, "failed to register cpufreq\n");
1344 goto cpu_freq_fail;
1345 }
1346
1347 ret = mmc_add_host(mmc);
1348 if (ret < 0)
1349 goto out;
1350
1351 ret = request_irq(irq, mmc_davinci_irq, 0, mmc_hostname(mmc), host);
1352 if (ret)
1353 goto out;
1354
1355 if (host->sdio_irq >= 0) {
1356 ret = request_irq(host->sdio_irq, mmc_davinci_sdio_irq, 0,
1357 mmc_hostname(mmc), host);
1358 if (!ret)
1359 mmc->caps |= MMC_CAP_SDIO_IRQ;
1360 }
1361
1362 rename_region(mem, mmc_hostname(mmc));
1363
1364 dev_info(mmc_dev(host->mmc), "Using %s, %d-bit mode\n",
1365 host->use_dma ? "DMA" : "PIO",
1366 (mmc->caps & MMC_CAP_4_BIT_DATA) ? 4 : 1);
1367
1368 return 0;
1369
1370 out:
1371 mmc_davinci_cpufreq_deregister(host);
1372 cpu_freq_fail:
1373 if (host) {
1374 davinci_release_dma_channels(host);
1375
1376 if (host->clk) {
1377 clk_disable(host->clk);
1378 clk_put(host->clk);
1379 }
1380
1381 if (host->base)
1382 iounmap(host->base);
1383 }
1384
1385 if (mmc)
1386 mmc_free_host(mmc);
1387
1388 if (mem)
1389 release_resource(mem);
1390
1391 dev_dbg(&pdev->dev, "probe err %d\n", ret);
1392
1393 return ret;
1394 }
1395
1396 static int __exit davinci_mmcsd_remove(struct platform_device *pdev)
1397 {
1398 struct mmc_davinci_host *host = platform_get_drvdata(pdev);
1399
1400 if (host) {
1401 mmc_davinci_cpufreq_deregister(host);
1402
1403 mmc_remove_host(host->mmc);
1404 free_irq(host->mmc_irq, host);
1405 if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
1406 free_irq(host->sdio_irq, host);
1407
1408 davinci_release_dma_channels(host);
1409
1410 clk_disable(host->clk);
1411 clk_put(host->clk);
1412
1413 iounmap(host->base);
1414
1415 release_resource(host->mem_res);
1416
1417 mmc_free_host(host->mmc);
1418 }
1419
1420 return 0;
1421 }
1422
1423 #ifdef CONFIG_PM
1424 static int davinci_mmcsd_suspend(struct device *dev)
1425 {
1426 struct platform_device *pdev = to_platform_device(dev);
1427 struct mmc_davinci_host *host = platform_get_drvdata(pdev);
1428
1429 writel(0, host->base + DAVINCI_MMCIM);
1430 mmc_davinci_reset_ctrl(host, 1);
1431 clk_disable(host->clk);
1432
1433 return 0;
1434 }
1435
1436 static int davinci_mmcsd_resume(struct device *dev)
1437 {
1438 struct platform_device *pdev = to_platform_device(dev);
1439 struct mmc_davinci_host *host = platform_get_drvdata(pdev);
1440
1441 clk_enable(host->clk);
1442 mmc_davinci_reset_ctrl(host, 0);
1443
1444 return 0;
1445 }
1446
1447 static const struct dev_pm_ops davinci_mmcsd_pm = {
1448 .suspend = davinci_mmcsd_suspend,
1449 .resume = davinci_mmcsd_resume,
1450 };
1451
1452 #define davinci_mmcsd_pm_ops (&davinci_mmcsd_pm)
1453 #else
1454 #define davinci_mmcsd_pm_ops NULL
1455 #endif
1456
1457 static struct platform_driver davinci_mmcsd_driver = {
1458 .driver = {
1459 .name = "davinci_mmc",
1460 .pm = davinci_mmcsd_pm_ops,
1461 .of_match_table = davinci_mmc_dt_ids,
1462 },
1463 .remove = __exit_p(davinci_mmcsd_remove),
1464 .id_table = davinci_mmc_devtype,
1465 };
1466
1467 module_platform_driver_probe(davinci_mmcsd_driver, davinci_mmcsd_probe);
1468
1469 MODULE_AUTHOR("Texas Instruments India");
1470 MODULE_LICENSE("GPL");
1471 MODULE_DESCRIPTION("MMC/SD driver for Davinci MMC controller");
1472 MODULE_ALIAS("platform:davinci_mmc");
1473
CRIS linux kernel tree