?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[cris-mirror.git] / drivers / mmc / host / omap_hsmmc.c
blobf9ac3bb5d617c38702b979839d9dc119e7f149a6
1 /*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/debugfs.h>
22 #include <linux/dmaengine.h>
23 #include <linux/seq_file.h>
24 #include <linux/sizes.h>
25 #include <linux/interrupt.h>
26 #include <linux/delay.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/platform_device.h>
29 #include <linux/timer.h>
30 #include <linux/clk.h>
31 #include <linux/of.h>
32 #include <linux/of_irq.h>
33 #include <linux/of_gpio.h>
34 #include <linux/of_device.h>
35 #include <linux/omap-dmaengine.h>
36 #include <linux/mmc/host.h>
37 #include <linux/mmc/core.h>
38 #include <linux/mmc/mmc.h>
39 #include <linux/mmc/slot-gpio.h>
40 #include <linux/io.h>
41 #include <linux/irq.h>
42 #include <linux/gpio.h>
43 #include <linux/regulator/consumer.h>
44 #include <linux/pinctrl/consumer.h>
45 #include <linux/pm_runtime.h>
46 #include <linux/pm_wakeirq.h>
47 #include <linux/platform_data/hsmmc-omap.h>
48
49 /* OMAP HSMMC Host Controller Registers */
50 #define OMAP_HSMMC_SYSSTATUS 0x0014
51 #define OMAP_HSMMC_CON 0x002C
52 #define OMAP_HSMMC_SDMASA 0x0100
53 #define OMAP_HSMMC_BLK 0x0104
54 #define OMAP_HSMMC_ARG 0x0108
55 #define OMAP_HSMMC_CMD 0x010C
56 #define OMAP_HSMMC_RSP10 0x0110
57 #define OMAP_HSMMC_RSP32 0x0114
58 #define OMAP_HSMMC_RSP54 0x0118
59 #define OMAP_HSMMC_RSP76 0x011C
60 #define OMAP_HSMMC_DATA 0x0120
61 #define OMAP_HSMMC_PSTATE 0x0124
62 #define OMAP_HSMMC_HCTL 0x0128
63 #define OMAP_HSMMC_SYSCTL 0x012C
64 #define OMAP_HSMMC_STAT 0x0130
65 #define OMAP_HSMMC_IE 0x0134
66 #define OMAP_HSMMC_ISE 0x0138
67 #define OMAP_HSMMC_AC12 0x013C
68 #define OMAP_HSMMC_CAPA 0x0140
69
70 #define VS18 (1 << 26)
71 #define VS30 (1 << 25)
72 #define HSS (1 << 21)
73 #define SDVS18 (0x5 << 9)
74 #define SDVS30 (0x6 << 9)
75 #define SDVS33 (0x7 << 9)
76 #define SDVS_MASK 0x00000E00
77 #define SDVSCLR 0xFFFFF1FF
78 #define SDVSDET 0x00000400
79 #define AUTOIDLE 0x1
80 #define SDBP (1 << 8)
81 #define DTO 0xe
82 #define ICE 0x1
83 #define ICS 0x2
84 #define CEN (1 << 2)
85 #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */
86 #define CLKD_MASK 0x0000FFC0
87 #define CLKD_SHIFT 6
88 #define DTO_MASK 0x000F0000
89 #define DTO_SHIFT 16
90 #define INIT_STREAM (1 << 1)
91 #define ACEN_ACMD23 (2 << 2)
92 #define DP_SELECT (1 << 21)
93 #define DDIR (1 << 4)
94 #define DMAE 0x1
95 #define MSBS (1 << 5)
96 #define BCE (1 << 1)
97 #define FOUR_BIT (1 << 1)
98 #define HSPE (1 << 2)
99 #define IWE (1 << 24)
100 #define DDR (1 << 19)
101 #define CLKEXTFREE (1 << 16)
102 #define CTPL (1 << 11)
103 #define DW8 (1 << 5)
104 #define OD 0x1
105 #define STAT_CLEAR 0xFFFFFFFF
106 #define INIT_STREAM_CMD 0x00000000
107 #define DUAL_VOLT_OCR_BIT 7
108 #define SRC (1 << 25)
109 #define SRD (1 << 26)
110 #define SOFTRESET (1 << 1)
111
112 /* PSTATE */
113 #define DLEV_DAT(x) (1 << (20 + (x)))
114
115 /* Interrupt masks for IE and ISE register */
116 #define CC_EN (1 << 0)
117 #define TC_EN (1 << 1)
118 #define BWR_EN (1 << 4)
119 #define BRR_EN (1 << 5)
120 #define CIRQ_EN (1 << 8)
121 #define ERR_EN (1 << 15)
122 #define CTO_EN (1 << 16)
123 #define CCRC_EN (1 << 17)
124 #define CEB_EN (1 << 18)
125 #define CIE_EN (1 << 19)
126 #define DTO_EN (1 << 20)
127 #define DCRC_EN (1 << 21)
128 #define DEB_EN (1 << 22)
129 #define ACE_EN (1 << 24)
130 #define CERR_EN (1 << 28)
131 #define BADA_EN (1 << 29)
132
133 #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\
134 DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \
135 BRR_EN | BWR_EN | TC_EN | CC_EN)
136
137 #define CNI (1 << 7)
138 #define ACIE (1 << 4)
139 #define ACEB (1 << 3)
140 #define ACCE (1 << 2)
141 #define ACTO (1 << 1)
142 #define ACNE (1 << 0)
143
144 #define MMC_AUTOSUSPEND_DELAY 100
145 #define MMC_TIMEOUT_MS 20 /* 20 mSec */
146 #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */
147 #define OMAP_MMC_MIN_CLOCK 400000
148 #define OMAP_MMC_MAX_CLOCK 52000000
149 #define DRIVER_NAME "omap_hsmmc"
150
151 #define VDD_1V8 1800000 /* 180000 uV */
152 #define VDD_3V0 3000000 /* 300000 uV */
153 #define VDD_165_195 (ffs(MMC_VDD_165_195) - 1)
154
155 /*
156 * One controller can have multiple slots, like on some omap boards using
157 * omap.c controller driver. Luckily this is not currently done on any known
158 * omap_hsmmc.c device.
159 */
160 #define mmc_pdata(host) host->pdata
161
162 /*
163 * MMC Host controller read/write API's
164 */
165 #define OMAP_HSMMC_READ(base, reg) \
166 __raw_readl((base) + OMAP_HSMMC_##reg)
167
168 #define OMAP_HSMMC_WRITE(base, reg, val) \
169 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
170
171 struct omap_hsmmc_next {
172 unsigned int dma_len;
173 s32 cookie;
174 };
175
176 struct omap_hsmmc_host {
177 struct device *dev;
178 struct mmc_host *mmc;
179 struct mmc_request *mrq;
180 struct mmc_command *cmd;
181 struct mmc_data *data;
182 struct clk *fclk;
183 struct clk *dbclk;
184 struct regulator *pbias;
185 bool pbias_enabled;
186 void __iomem *base;
187 int vqmmc_enabled;
188 resource_size_t mapbase;
189 spinlock_t irq_lock; /* Prevent races with irq handler */
190 unsigned int dma_len;
191 unsigned int dma_sg_idx;
192 unsigned char bus_mode;
193 unsigned char power_mode;
194 int suspended;
195 u32 con;
196 u32 hctl;
197 u32 sysctl;
198 u32 capa;
199 int irq;
200 int wake_irq;
201 int use_dma, dma_ch;
202 struct dma_chan *tx_chan;
203 struct dma_chan *rx_chan;
204 int response_busy;
205 int context_loss;
206 int protect_card;
207 int reqs_blocked;
208 int req_in_progress;
209 unsigned long clk_rate;
210 unsigned int flags;
211 #define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */
212 #define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */
213 struct omap_hsmmc_next next_data;
214 struct omap_hsmmc_platform_data *pdata;
215
216 /* return MMC cover switch state, can be NULL if not supported.
217 *
218 * possible return values:
219 * 0 - closed
220 * 1 - open
221 */
222 int (*get_cover_state)(struct device *dev);
223
224 int (*card_detect)(struct device *dev);
225 };
226
227 struct omap_mmc_of_data {
228 u32 reg_offset;
229 u8 controller_flags;
230 };
231
232 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host);
233
234 static int omap_hsmmc_card_detect(struct device *dev)
235 {
236 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
237
238 return mmc_gpio_get_cd(host->mmc);
239 }
240
241 static int omap_hsmmc_get_cover_state(struct device *dev)
242 {
243 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
244
245 return mmc_gpio_get_cd(host->mmc);
246 }
247
248 static int omap_hsmmc_enable_supply(struct mmc_host *mmc)
249 {
250 int ret;
251 struct omap_hsmmc_host *host = mmc_priv(mmc);
252 struct mmc_ios *ios = &mmc->ios;
253
254 if (mmc->supply.vmmc) {
255 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
256 if (ret)
257 return ret;
258 }
259
260 /* Enable interface voltage rail, if needed */
261 if (mmc->supply.vqmmc && !host->vqmmc_enabled) {
262 ret = regulator_enable(mmc->supply.vqmmc);
263 if (ret) {
264 dev_err(mmc_dev(mmc), "vmmc_aux reg enable failed\n");
265 goto err_vqmmc;
266 }
267 host->vqmmc_enabled = 1;
268 }
269
270 return 0;
271
272 err_vqmmc:
273 if (mmc->supply.vmmc)
274 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
275
276 return ret;
277 }
278
279 static int omap_hsmmc_disable_supply(struct mmc_host *mmc)
280 {
281 int ret;
282 int status;
283 struct omap_hsmmc_host *host = mmc_priv(mmc);
284
285 if (mmc->supply.vqmmc && host->vqmmc_enabled) {
286 ret = regulator_disable(mmc->supply.vqmmc);
287 if (ret) {
288 dev_err(mmc_dev(mmc), "vmmc_aux reg disable failed\n");
289 return ret;
290 }
291 host->vqmmc_enabled = 0;
292 }
293
294 if (mmc->supply.vmmc) {
295 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
296 if (ret)
297 goto err_set_ocr;
298 }
299
300 return 0;
301
302 err_set_ocr:
303 if (mmc->supply.vqmmc) {
304 status = regulator_enable(mmc->supply.vqmmc);
305 if (status)
306 dev_err(mmc_dev(mmc), "vmmc_aux re-enable failed\n");
307 }
308
309 return ret;
310 }
311
312 static int omap_hsmmc_set_pbias(struct omap_hsmmc_host *host, bool power_on,
313 int vdd)
314 {
315 int ret;
316
317 if (!host->pbias)
318 return 0;
319
320 if (power_on) {
321 if (vdd <= VDD_165_195)
322 ret = regulator_set_voltage(host->pbias, VDD_1V8,
323 VDD_1V8);
324 else
325 ret = regulator_set_voltage(host->pbias, VDD_3V0,
326 VDD_3V0);
327 if (ret < 0) {
328 dev_err(host->dev, "pbias set voltage fail\n");
329 return ret;
330 }
331
332 if (host->pbias_enabled == 0) {
333 ret = regulator_enable(host->pbias);
334 if (ret) {
335 dev_err(host->dev, "pbias reg enable fail\n");
336 return ret;
337 }
338 host->pbias_enabled = 1;
339 }
340 } else {
341 if (host->pbias_enabled == 1) {
342 ret = regulator_disable(host->pbias);
343 if (ret) {
344 dev_err(host->dev, "pbias reg disable fail\n");
345 return ret;
346 }
347 host->pbias_enabled = 0;
348 }
349 }
350
351 return 0;
352 }
353
354 static int omap_hsmmc_set_power(struct device *dev, int power_on, int vdd)
355 {
356 struct omap_hsmmc_host *host =
357 platform_get_drvdata(to_platform_device(dev));
358 struct mmc_host *mmc = host->mmc;
359 int ret = 0;
360
361 if (mmc_pdata(host)->set_power)
362 return mmc_pdata(host)->set_power(dev, power_on, vdd);
363
364 /*
365 * If we don't see a Vcc regulator, assume it's a fixed
366 * voltage always-on regulator.
367 */
368 if (!mmc->supply.vmmc)
369 return 0;
370
371 if (mmc_pdata(host)->before_set_reg)
372 mmc_pdata(host)->before_set_reg(dev, power_on, vdd);
373
374 ret = omap_hsmmc_set_pbias(host, false, 0);
375 if (ret)
376 return ret;
377
378 /*
379 * Assume Vcc regulator is used only to power the card ... OMAP
380 * VDDS is used to power the pins, optionally with a transceiver to
381 * support cards using voltages other than VDDS (1.8V nominal). When a
382 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
383 *
384 * In some cases this regulator won't support enable/disable;
385 * e.g. it's a fixed rail for a WLAN chip.
386 *
387 * In other cases vcc_aux switches interface power. Example, for
388 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
389 * chips/cards need an interface voltage rail too.
390 */
391 if (power_on) {
392 ret = omap_hsmmc_enable_supply(mmc);
393 if (ret)
394 return ret;
395
396 ret = omap_hsmmc_set_pbias(host, true, vdd);
397 if (ret)
398 goto err_set_voltage;
399 } else {
400 ret = omap_hsmmc_disable_supply(mmc);
401 if (ret)
402 return ret;
403 }
404
405 if (mmc_pdata(host)->after_set_reg)
406 mmc_pdata(host)->after_set_reg(dev, power_on, vdd);
407
408 return 0;
409
410 err_set_voltage:
411 omap_hsmmc_disable_supply(mmc);
412
413 return ret;
414 }
415
416 static int omap_hsmmc_disable_boot_regulator(struct regulator *reg)
417 {
418 int ret;
419
420 if (!reg)
421 return 0;
422
423 if (regulator_is_enabled(reg)) {
424 ret = regulator_enable(reg);
425 if (ret)
426 return ret;
427
428 ret = regulator_disable(reg);
429 if (ret)
430 return ret;
431 }
432
433 return 0;
434 }
435
436 static int omap_hsmmc_disable_boot_regulators(struct omap_hsmmc_host *host)
437 {
438 struct mmc_host *mmc = host->mmc;
439 int ret;
440
441 /*
442 * disable regulators enabled during boot and get the usecount
443 * right so that regulators can be enabled/disabled by checking
444 * the return value of regulator_is_enabled
445 */
446 ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vmmc);
447 if (ret) {
448 dev_err(host->dev, "fail to disable boot enabled vmmc reg\n");
449 return ret;
450 }
451
452 ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vqmmc);
453 if (ret) {
454 dev_err(host->dev,
455 "fail to disable boot enabled vmmc_aux reg\n");
456 return ret;
457 }
458
459 ret = omap_hsmmc_disable_boot_regulator(host->pbias);
460 if (ret) {
461 dev_err(host->dev,
462 "failed to disable boot enabled pbias reg\n");
463 return ret;
464 }
465
466 return 0;
467 }
468
469 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
470 {
471 int ocr_value = 0;
472 int ret;
473 struct mmc_host *mmc = host->mmc;
474
475 if (mmc_pdata(host)->set_power)
476 return 0;
477
478 mmc->supply.vmmc = devm_regulator_get_optional(host->dev, "vmmc");
479 if (IS_ERR(mmc->supply.vmmc)) {
480 ret = PTR_ERR(mmc->supply.vmmc);
481 if ((ret != -ENODEV) && host->dev->of_node)
482 return ret;
483 dev_dbg(host->dev, "unable to get vmmc regulator %ld\n",
484 PTR_ERR(mmc->supply.vmmc));
485 mmc->supply.vmmc = NULL;
486 } else {
487 ocr_value = mmc_regulator_get_ocrmask(mmc->supply.vmmc);
488 if (ocr_value > 0)
489 mmc_pdata(host)->ocr_mask = ocr_value;
490 }
491
492 /* Allow an aux regulator */
493 mmc->supply.vqmmc = devm_regulator_get_optional(host->dev, "vmmc_aux");
494 if (IS_ERR(mmc->supply.vqmmc)) {
495 ret = PTR_ERR(mmc->supply.vqmmc);
496 if ((ret != -ENODEV) && host->dev->of_node)
497 return ret;
498 dev_dbg(host->dev, "unable to get vmmc_aux regulator %ld\n",
499 PTR_ERR(mmc->supply.vqmmc));
500 mmc->supply.vqmmc = NULL;
501 }
502
503 host->pbias = devm_regulator_get_optional(host->dev, "pbias");
504 if (IS_ERR(host->pbias)) {
505 ret = PTR_ERR(host->pbias);
506 if ((ret != -ENODEV) && host->dev->of_node) {
507 dev_err(host->dev,
508 "SD card detect fail? enable CONFIG_REGULATOR_PBIAS\n");
509 return ret;
510 }
511 dev_dbg(host->dev, "unable to get pbias regulator %ld\n",
512 PTR_ERR(host->pbias));
513 host->pbias = NULL;
514 }
515
516 /* For eMMC do not power off when not in sleep state */
517 if (mmc_pdata(host)->no_regulator_off_init)
518 return 0;
519
520 ret = omap_hsmmc_disable_boot_regulators(host);
521 if (ret)
522 return ret;
523
524 return 0;
525 }
526
527 static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id);
528
529 static int omap_hsmmc_gpio_init(struct mmc_host *mmc,
530 struct omap_hsmmc_host *host,
531 struct omap_hsmmc_platform_data *pdata)
532 {
533 int ret;
534
535 if (gpio_is_valid(pdata->gpio_cod)) {
536 ret = mmc_gpio_request_cd(mmc, pdata->gpio_cod, 0);
537 if (ret)
538 return ret;
539
540 host->get_cover_state = omap_hsmmc_get_cover_state;
541 mmc_gpio_set_cd_isr(mmc, omap_hsmmc_cover_irq);
542 } else if (gpio_is_valid(pdata->gpio_cd)) {
543 ret = mmc_gpio_request_cd(mmc, pdata->gpio_cd, 0);
544 if (ret)
545 return ret;
546
547 host->card_detect = omap_hsmmc_card_detect;
548 }
549
550 if (gpio_is_valid(pdata->gpio_wp)) {
551 ret = mmc_gpio_request_ro(mmc, pdata->gpio_wp);
552 if (ret)
553 return ret;
554 }
555
556 return 0;
557 }
558
559 /*
560 * Start clock to the card
561 */
562 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
563 {
564 OMAP_HSMMC_WRITE(host->base, SYSCTL,
565 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
566 }
567
568 /*
569 * Stop clock to the card
570 */
571 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
572 {
573 OMAP_HSMMC_WRITE(host->base, SYSCTL,
574 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
575 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
576 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
577 }
578
579 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
580 struct mmc_command *cmd)
581 {
582 u32 irq_mask = INT_EN_MASK;
583 unsigned long flags;
584
585 if (host->use_dma)
586 irq_mask &= ~(BRR_EN | BWR_EN);
587
588 /* Disable timeout for erases */
589 if (cmd->opcode == MMC_ERASE)
590 irq_mask &= ~DTO_EN;
591
592 spin_lock_irqsave(&host->irq_lock, flags);
593 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
594 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
595
596 /* latch pending CIRQ, but don't signal MMC core */
597 if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
598 irq_mask |= CIRQ_EN;
599 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
600 spin_unlock_irqrestore(&host->irq_lock, flags);
601 }
602
603 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
604 {
605 u32 irq_mask = 0;
606 unsigned long flags;
607
608 spin_lock_irqsave(&host->irq_lock, flags);
609 /* no transfer running but need to keep cirq if enabled */
610 if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
611 irq_mask |= CIRQ_EN;
612 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
613 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
614 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
615 spin_unlock_irqrestore(&host->irq_lock, flags);
616 }
617
618 /* Calculate divisor for the given clock frequency */
619 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
620 {
621 u16 dsor = 0;
622
623 if (ios->clock) {
624 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
625 if (dsor > CLKD_MAX)
626 dsor = CLKD_MAX;
627 }
628
629 return dsor;
630 }
631
632 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
633 {
634 struct mmc_ios *ios = &host->mmc->ios;
635 unsigned long regval;
636 unsigned long timeout;
637 unsigned long clkdiv;
638
639 dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
640
641 omap_hsmmc_stop_clock(host);
642
643 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
644 regval = regval & ~(CLKD_MASK | DTO_MASK);
645 clkdiv = calc_divisor(host, ios);
646 regval = regval | (clkdiv << 6) | (DTO << 16);
647 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
648 OMAP_HSMMC_WRITE(host->base, SYSCTL,
649 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
650
651 /* Wait till the ICS bit is set */
652 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
653 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
654 && time_before(jiffies, timeout))
655 cpu_relax();
656
657 /*
658 * Enable High-Speed Support
659 * Pre-Requisites
660 * - Controller should support High-Speed-Enable Bit
661 * - Controller should not be using DDR Mode
662 * - Controller should advertise that it supports High Speed
663 * in capabilities register
664 * - MMC/SD clock coming out of controller > 25MHz
665 */
666 if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) &&
667 (ios->timing != MMC_TIMING_MMC_DDR52) &&
668 (ios->timing != MMC_TIMING_UHS_DDR50) &&
669 ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
670 regval = OMAP_HSMMC_READ(host->base, HCTL);
671 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
672 regval |= HSPE;
673 else
674 regval &= ~HSPE;
675
676 OMAP_HSMMC_WRITE(host->base, HCTL, regval);
677 }
678
679 omap_hsmmc_start_clock(host);
680 }
681
682 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
683 {
684 struct mmc_ios *ios = &host->mmc->ios;
685 u32 con;
686
687 con = OMAP_HSMMC_READ(host->base, CON);
688 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
689 ios->timing == MMC_TIMING_UHS_DDR50)
690 con |= DDR; /* configure in DDR mode */
691 else
692 con &= ~DDR;
693 switch (ios->bus_width) {
694 case MMC_BUS_WIDTH_8:
695 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
696 break;
697 case MMC_BUS_WIDTH_4:
698 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
699 OMAP_HSMMC_WRITE(host->base, HCTL,
700 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
701 break;
702 case MMC_BUS_WIDTH_1:
703 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
704 OMAP_HSMMC_WRITE(host->base, HCTL,
705 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
706 break;
707 }
708 }
709
710 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
711 {
712 struct mmc_ios *ios = &host->mmc->ios;
713 u32 con;
714
715 con = OMAP_HSMMC_READ(host->base, CON);
716 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
717 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
718 else
719 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
720 }
721
722 #ifdef CONFIG_PM
723
724 /*
725 * Restore the MMC host context, if it was lost as result of a
726 * power state change.
727 */
728 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
729 {
730 struct mmc_ios *ios = &host->mmc->ios;
731 u32 hctl, capa;
732 unsigned long timeout;
733
734 if (host->con == OMAP_HSMMC_READ(host->base, CON) &&
735 host->hctl == OMAP_HSMMC_READ(host->base, HCTL) &&
736 host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) &&
737 host->capa == OMAP_HSMMC_READ(host->base, CAPA))
738 return 0;
739
740 host->context_loss++;
741
742 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
743 if (host->power_mode != MMC_POWER_OFF &&
744 (1 << ios->vdd) <= MMC_VDD_23_24)
745 hctl = SDVS18;
746 else
747 hctl = SDVS30;
748 capa = VS30 | VS18;
749 } else {
750 hctl = SDVS18;
751 capa = VS18;
752 }
753
754 if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
755 hctl |= IWE;
756
757 OMAP_HSMMC_WRITE(host->base, HCTL,
758 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
759
760 OMAP_HSMMC_WRITE(host->base, CAPA,
761 OMAP_HSMMC_READ(host->base, CAPA) | capa);
762
763 OMAP_HSMMC_WRITE(host->base, HCTL,
764 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
765
766 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
767 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
768 && time_before(jiffies, timeout))
769 ;
770
771 OMAP_HSMMC_WRITE(host->base, ISE, 0);
772 OMAP_HSMMC_WRITE(host->base, IE, 0);
773 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
774
775 /* Do not initialize card-specific things if the power is off */
776 if (host->power_mode == MMC_POWER_OFF)
777 goto out;
778
779 omap_hsmmc_set_bus_width(host);
780
781 omap_hsmmc_set_clock(host);
782
783 omap_hsmmc_set_bus_mode(host);
784
785 out:
786 dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n",
787 host->context_loss);
788 return 0;
789 }
790
791 /*
792 * Save the MMC host context (store the number of power state changes so far).
793 */
794 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
795 {
796 host->con = OMAP_HSMMC_READ(host->base, CON);
797 host->hctl = OMAP_HSMMC_READ(host->base, HCTL);
798 host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL);
799 host->capa = OMAP_HSMMC_READ(host->base, CAPA);
800 }
801
802 #else
803
804 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
805 {
806 return 0;
807 }
808
809 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
810 {
811 }
812
813 #endif
814
815 /*
816 * Send init stream sequence to card
817 * before sending IDLE command
818 */
819 static void send_init_stream(struct omap_hsmmc_host *host)
820 {
821 int reg = 0;
822 unsigned long timeout;
823
824 if (host->protect_card)
825 return;
826
827 disable_irq(host->irq);
828
829 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
830 OMAP_HSMMC_WRITE(host->base, CON,
831 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
832 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
833
834 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
835 while ((reg != CC_EN) && time_before(jiffies, timeout))
836 reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
837
838 OMAP_HSMMC_WRITE(host->base, CON,
839 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
840
841 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
842 OMAP_HSMMC_READ(host->base, STAT);
843
844 enable_irq(host->irq);
845 }
846
847 static inline
848 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
849 {
850 int r = 1;
851
852 if (host->get_cover_state)
853 r = host->get_cover_state(host->dev);
854 return r;
855 }
856
857 static ssize_t
858 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
859 char *buf)
860 {
861 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
862 struct omap_hsmmc_host *host = mmc_priv(mmc);
863
864 return sprintf(buf, "%s\n",
865 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
866 }
867
868 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
869
870 static ssize_t
871 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
872 char *buf)
873 {
874 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
875 struct omap_hsmmc_host *host = mmc_priv(mmc);
876
877 return sprintf(buf, "%s\n", mmc_pdata(host)->name);
878 }
879
880 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
881
882 /*
883 * Configure the response type and send the cmd.
884 */
885 static void
886 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
887 struct mmc_data *data)
888 {
889 int cmdreg = 0, resptype = 0, cmdtype = 0;
890
891 dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
892 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
893 host->cmd = cmd;
894
895 omap_hsmmc_enable_irq(host, cmd);
896
897 host->response_busy = 0;
898 if (cmd->flags & MMC_RSP_PRESENT) {
899 if (cmd->flags & MMC_RSP_136)
900 resptype = 1;
901 else if (cmd->flags & MMC_RSP_BUSY) {
902 resptype = 3;
903 host->response_busy = 1;
904 } else
905 resptype = 2;
906 }
907
908 /*
909 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
910 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
911 * a val of 0x3, rest 0x0.
912 */
913 if (cmd == host->mrq->stop)
914 cmdtype = 0x3;
915
916 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
917
918 if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) &&
919 host->mrq->sbc) {
920 cmdreg |= ACEN_ACMD23;
921 OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg);
922 }
923 if (data) {
924 cmdreg |= DP_SELECT | MSBS | BCE;
925 if (data->flags & MMC_DATA_READ)
926 cmdreg |= DDIR;
927 else
928 cmdreg &= ~(DDIR);
929 }
930
931 if (host->use_dma)
932 cmdreg |= DMAE;
933
934 host->req_in_progress = 1;
935
936 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
937 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
938 }
939
940 static int
941 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
942 {
943 if (data->flags & MMC_DATA_WRITE)
944 return DMA_TO_DEVICE;
945 else
946 return DMA_FROM_DEVICE;
947 }
948
949 static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
950 struct mmc_data *data)
951 {
952 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
953 }
954
955 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
956 {
957 int dma_ch;
958 unsigned long flags;
959
960 spin_lock_irqsave(&host->irq_lock, flags);
961 host->req_in_progress = 0;
962 dma_ch = host->dma_ch;
963 spin_unlock_irqrestore(&host->irq_lock, flags);
964
965 omap_hsmmc_disable_irq(host);
966 /* Do not complete the request if DMA is still in progress */
967 if (mrq->data && host->use_dma && dma_ch != -1)
968 return;
969 host->mrq = NULL;
970 mmc_request_done(host->mmc, mrq);
971 pm_runtime_mark_last_busy(host->dev);
972 pm_runtime_put_autosuspend(host->dev);
973 }
974
975 /*
976 * Notify the transfer complete to MMC core
977 */
978 static void
979 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
980 {
981 if (!data) {
982 struct mmc_request *mrq = host->mrq;
983
984 /* TC before CC from CMD6 - don't know why, but it happens */
985 if (host->cmd && host->cmd->opcode == 6 &&
986 host->response_busy) {
987 host->response_busy = 0;
988 return;
989 }
990
991 omap_hsmmc_request_done(host, mrq);
992 return;
993 }
994
995 host->data = NULL;
996
997 if (!data->error)
998 data->bytes_xfered += data->blocks * (data->blksz);
999 else
1000 data->bytes_xfered = 0;
1001
1002 if (data->stop && (data->error || !host->mrq->sbc))
1003 omap_hsmmc_start_command(host, data->stop, NULL);
1004 else
1005 omap_hsmmc_request_done(host, data->mrq);
1006 }
1007
1008 /*
1009 * Notify the core about command completion
1010 */
1011 static void
1012 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
1013 {
1014 if (host->mrq->sbc && (host->cmd == host->mrq->sbc) &&
1015 !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) {
1016 host->cmd = NULL;
1017 omap_hsmmc_start_dma_transfer(host);
1018 omap_hsmmc_start_command(host, host->mrq->cmd,
1019 host->mrq->data);
1020 return;
1021 }
1022
1023 host->cmd = NULL;
1024
1025 if (cmd->flags & MMC_RSP_PRESENT) {
1026 if (cmd->flags & MMC_RSP_136) {
1027 /* response type 2 */
1028 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
1029 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
1030 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
1031 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
1032 } else {
1033 /* response types 1, 1b, 3, 4, 5, 6 */
1034 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
1035 }
1036 }
1037 if ((host->data == NULL && !host->response_busy) || cmd->error)
1038 omap_hsmmc_request_done(host, host->mrq);
1039 }
1040
1041 /*
1042 * DMA clean up for command errors
1043 */
1044 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
1045 {
1046 int dma_ch;
1047 unsigned long flags;
1048
1049 host->data->error = errno;
1050
1051 spin_lock_irqsave(&host->irq_lock, flags);
1052 dma_ch = host->dma_ch;
1053 host->dma_ch = -1;
1054 spin_unlock_irqrestore(&host->irq_lock, flags);
1055
1056 if (host->use_dma && dma_ch != -1) {
1057 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
1058
1059 dmaengine_terminate_all(chan);
1060 dma_unmap_sg(chan->device->dev,
1061 host->data->sg, host->data->sg_len,
1062 omap_hsmmc_get_dma_dir(host, host->data));
1063
1064 host->data->host_cookie = 0;
1065 }
1066 host->data = NULL;
1067 }
1068
1069 /*
1070 * Readable error output
1071 */
1072 #ifdef CONFIG_MMC_DEBUG
1073 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
1074 {
1075 /* --- means reserved bit without definition at documentation */
1076 static const char *omap_hsmmc_status_bits[] = {
1077 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
1078 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
1079 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
1080 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
1081 };
1082 char res[256];
1083 char *buf = res;
1084 int len, i;
1085
1086 len = sprintf(buf, "MMC IRQ 0x%x :", status);
1087 buf += len;
1088
1089 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
1090 if (status & (1 << i)) {
1091 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
1092 buf += len;
1093 }
1094
1095 dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
1096 }
1097 #else
1098 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
1099 u32 status)
1100 {
1101 }
1102 #endif /* CONFIG_MMC_DEBUG */
1103
1104 /*
1105 * MMC controller internal state machines reset
1106 *
1107 * Used to reset command or data internal state machines, using respectively
1108 * SRC or SRD bit of SYSCTL register
1109 * Can be called from interrupt context
1110 */
1111 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1112 unsigned long bit)
1113 {
1114 unsigned long i = 0;
1115 unsigned long limit = MMC_TIMEOUT_US;
1116
1117 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1118 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1119
1120 /*
1121 * OMAP4 ES2 and greater has an updated reset logic.
1122 * Monitor a 0->1 transition first
1123 */
1124 if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) {
1125 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
1126 && (i++ < limit))
1127 udelay(1);
1128 }
1129 i = 0;
1130
1131 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1132 (i++ < limit))
1133 udelay(1);
1134
1135 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1136 dev_err(mmc_dev(host->mmc),
1137 "Timeout waiting on controller reset in %s\n",
1138 __func__);
1139 }
1140
1141 static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
1142 int err, int end_cmd)
1143 {
1144 if (end_cmd) {
1145 omap_hsmmc_reset_controller_fsm(host, SRC);
1146 if (host->cmd)
1147 host->cmd->error = err;
1148 }
1149
1150 if (host->data) {
1151 omap_hsmmc_reset_controller_fsm(host, SRD);
1152 omap_hsmmc_dma_cleanup(host, err);
1153 } else if (host->mrq && host->mrq->cmd)
1154 host->mrq->cmd->error = err;
1155 }
1156
1157 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1158 {
1159 struct mmc_data *data;
1160 int end_cmd = 0, end_trans = 0;
1161 int error = 0;
1162
1163 data = host->data;
1164 dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1165
1166 if (status & ERR_EN) {
1167 omap_hsmmc_dbg_report_irq(host, status);
1168
1169 if (status & (CTO_EN | CCRC_EN))
1170 end_cmd = 1;
1171 if (host->data || host->response_busy) {
1172 end_trans = !end_cmd;
1173 host->response_busy = 0;
1174 }
1175 if (status & (CTO_EN | DTO_EN))
1176 hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
1177 else if (status & (CCRC_EN | DCRC_EN | DEB_EN | CEB_EN |
1178 BADA_EN))
1179 hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
1180
1181 if (status & ACE_EN) {
1182 u32 ac12;
1183 ac12 = OMAP_HSMMC_READ(host->base, AC12);
1184 if (!(ac12 & ACNE) && host->mrq->sbc) {
1185 end_cmd = 1;
1186 if (ac12 & ACTO)
1187 error = -ETIMEDOUT;
1188 else if (ac12 & (ACCE | ACEB | ACIE))
1189 error = -EILSEQ;
1190 host->mrq->sbc->error = error;
1191 hsmmc_command_incomplete(host, error, end_cmd);
1192 }
1193 dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12);
1194 }
1195 }
1196
1197 OMAP_HSMMC_WRITE(host->base, STAT, status);
1198 if (end_cmd || ((status & CC_EN) && host->cmd))
1199 omap_hsmmc_cmd_done(host, host->cmd);
1200 if ((end_trans || (status & TC_EN)) && host->mrq)
1201 omap_hsmmc_xfer_done(host, data);
1202 }
1203
1204 /*
1205 * MMC controller IRQ handler
1206 */
1207 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1208 {
1209 struct omap_hsmmc_host *host = dev_id;
1210 int status;
1211
1212 status = OMAP_HSMMC_READ(host->base, STAT);
1213 while (status & (INT_EN_MASK | CIRQ_EN)) {
1214 if (host->req_in_progress)
1215 omap_hsmmc_do_irq(host, status);
1216
1217 if (status & CIRQ_EN)
1218 mmc_signal_sdio_irq(host->mmc);
1219
1220 /* Flush posted write */
1221 status = OMAP_HSMMC_READ(host->base, STAT);
1222 }
1223
1224 return IRQ_HANDLED;
1225 }
1226
1227 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1228 {
1229 unsigned long i;
1230
1231 OMAP_HSMMC_WRITE(host->base, HCTL,
1232 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1233 for (i = 0; i < loops_per_jiffy; i++) {
1234 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1235 break;
1236 cpu_relax();
1237 }
1238 }
1239
1240 /*
1241 * Switch MMC interface voltage ... only relevant for MMC1.
1242 *
1243 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1244 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1245 * Some chips, like eMMC ones, use internal transceivers.
1246 */
1247 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1248 {
1249 u32 reg_val = 0;
1250 int ret;
1251
1252 /* Disable the clocks */
1253 pm_runtime_put_sync(host->dev);
1254 if (host->dbclk)
1255 clk_disable_unprepare(host->dbclk);
1256
1257 /* Turn the power off */
1258 ret = omap_hsmmc_set_power(host->dev, 0, 0);
1259
1260 /* Turn the power ON with given VDD 1.8 or 3.0v */
1261 if (!ret)
1262 ret = omap_hsmmc_set_power(host->dev, 1, vdd);
1263 pm_runtime_get_sync(host->dev);
1264 if (host->dbclk)
1265 clk_prepare_enable(host->dbclk);
1266
1267 if (ret != 0)
1268 goto err;
1269
1270 OMAP_HSMMC_WRITE(host->base, HCTL,
1271 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1272 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1273
1274 /*
1275 * If a MMC dual voltage card is detected, the set_ios fn calls
1276 * this fn with VDD bit set for 1.8V. Upon card removal from the
1277 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1278 *
1279 * Cope with a bit of slop in the range ... per data sheets:
1280 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1281 * but recommended values are 1.71V to 1.89V
1282 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1283 * but recommended values are 2.7V to 3.3V
1284 *
1285 * Board setup code shouldn't permit anything very out-of-range.
1286 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1287 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1288 */
1289 if ((1 << vdd) <= MMC_VDD_23_24)
1290 reg_val |= SDVS18;
1291 else
1292 reg_val |= SDVS30;
1293
1294 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1295 set_sd_bus_power(host);
1296
1297 return 0;
1298 err:
1299 dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1300 return ret;
1301 }
1302
1303 /* Protect the card while the cover is open */
1304 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1305 {
1306 if (!host->get_cover_state)
1307 return;
1308
1309 host->reqs_blocked = 0;
1310 if (host->get_cover_state(host->dev)) {
1311 if (host->protect_card) {
1312 dev_info(host->dev, "%s: cover is closed, "
1313 "card is now accessible\n",
1314 mmc_hostname(host->mmc));
1315 host->protect_card = 0;
1316 }
1317 } else {
1318 if (!host->protect_card) {
1319 dev_info(host->dev, "%s: cover is open, "
1320 "card is now inaccessible\n",
1321 mmc_hostname(host->mmc));
1322 host->protect_card = 1;
1323 }
1324 }
1325 }
1326
1327 /*
1328 * irq handler when (cell-phone) cover is mounted/removed
1329 */
1330 static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id)
1331 {
1332 struct omap_hsmmc_host *host = dev_id;
1333
1334 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1335
1336 omap_hsmmc_protect_card(host);
1337 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1338 return IRQ_HANDLED;
1339 }
1340
1341 static void omap_hsmmc_dma_callback(void *param)
1342 {
1343 struct omap_hsmmc_host *host = param;
1344 struct dma_chan *chan;
1345 struct mmc_data *data;
1346 int req_in_progress;
1347
1348 spin_lock_irq(&host->irq_lock);
1349 if (host->dma_ch < 0) {
1350 spin_unlock_irq(&host->irq_lock);
1351 return;
1352 }
1353
1354 data = host->mrq->data;
1355 chan = omap_hsmmc_get_dma_chan(host, data);
1356 if (!data->host_cookie)
1357 dma_unmap_sg(chan->device->dev,
1358 data->sg, data->sg_len,
1359 omap_hsmmc_get_dma_dir(host, data));
1360
1361 req_in_progress = host->req_in_progress;
1362 host->dma_ch = -1;
1363 spin_unlock_irq(&host->irq_lock);
1364
1365 /* If DMA has finished after TC, complete the request */
1366 if (!req_in_progress) {
1367 struct mmc_request *mrq = host->mrq;
1368
1369 host->mrq = NULL;
1370 mmc_request_done(host->mmc, mrq);
1371 pm_runtime_mark_last_busy(host->dev);
1372 pm_runtime_put_autosuspend(host->dev);
1373 }
1374 }
1375
1376 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1377 struct mmc_data *data,
1378 struct omap_hsmmc_next *next,
1379 struct dma_chan *chan)
1380 {
1381 int dma_len;
1382
1383 if (!next && data->host_cookie &&
1384 data->host_cookie != host->next_data.cookie) {
1385 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1386 " host->next_data.cookie %d\n",
1387 __func__, data->host_cookie, host->next_data.cookie);
1388 data->host_cookie = 0;
1389 }
1390
1391 /* Check if next job is already prepared */
1392 if (next || data->host_cookie != host->next_data.cookie) {
1393 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
1394 omap_hsmmc_get_dma_dir(host, data));
1395
1396 } else {
1397 dma_len = host->next_data.dma_len;
1398 host->next_data.dma_len = 0;
1399 }
1400
1401
1402 if (dma_len == 0)
1403 return -EINVAL;
1404
1405 if (next) {
1406 next->dma_len = dma_len;
1407 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1408 } else
1409 host->dma_len = dma_len;
1410
1411 return 0;
1412 }
1413
1414 /*
1415 * Routine to configure and start DMA for the MMC card
1416 */
1417 static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host,
1418 struct mmc_request *req)
1419 {
1420 struct dma_slave_config cfg;
1421 struct dma_async_tx_descriptor *tx;
1422 int ret = 0, i;
1423 struct mmc_data *data = req->data;
1424 struct dma_chan *chan;
1425
1426 /* Sanity check: all the SG entries must be aligned by block size. */
1427 for (i = 0; i < data->sg_len; i++) {
1428 struct scatterlist *sgl;
1429
1430 sgl = data->sg + i;
1431 if (sgl->length % data->blksz)
1432 return -EINVAL;
1433 }
1434 if ((data->blksz % 4) != 0)
1435 /* REVISIT: The MMC buffer increments only when MSB is written.
1436 * Return error for blksz which is non multiple of four.
1437 */
1438 return -EINVAL;
1439
1440 BUG_ON(host->dma_ch != -1);
1441
1442 chan = omap_hsmmc_get_dma_chan(host, data);
1443
1444 cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA;
1445 cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA;
1446 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1447 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1448 cfg.src_maxburst = data->blksz / 4;
1449 cfg.dst_maxburst = data->blksz / 4;
1450
1451 ret = dmaengine_slave_config(chan, &cfg);
1452 if (ret)
1453 return ret;
1454
1455 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
1456 if (ret)
1457 return ret;
1458
1459 tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1460 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1461 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1462 if (!tx) {
1463 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1464 /* FIXME: cleanup */
1465 return -1;
1466 }
1467
1468 tx->callback = omap_hsmmc_dma_callback;
1469 tx->callback_param = host;
1470
1471 /* Does not fail */
1472 dmaengine_submit(tx);
1473
1474 host->dma_ch = 1;
1475
1476 return 0;
1477 }
1478
1479 static void set_data_timeout(struct omap_hsmmc_host *host,
1480 unsigned int timeout_ns,
1481 unsigned int timeout_clks)
1482 {
1483 unsigned int timeout, cycle_ns;
1484 uint32_t reg, clkd, dto = 0;
1485
1486 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1487 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1488 if (clkd == 0)
1489 clkd = 1;
1490
1491 cycle_ns = 1000000000 / (host->clk_rate / clkd);
1492 timeout = timeout_ns / cycle_ns;
1493 timeout += timeout_clks;
1494 if (timeout) {
1495 while ((timeout & 0x80000000) == 0) {
1496 dto += 1;
1497 timeout <<= 1;
1498 }
1499 dto = 31 - dto;
1500 timeout <<= 1;
1501 if (timeout && dto)
1502 dto += 1;
1503 if (dto >= 13)
1504 dto -= 13;
1505 else
1506 dto = 0;
1507 if (dto > 14)
1508 dto = 14;
1509 }
1510
1511 reg &= ~DTO_MASK;
1512 reg |= dto << DTO_SHIFT;
1513 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1514 }
1515
1516 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host)
1517 {
1518 struct mmc_request *req = host->mrq;
1519 struct dma_chan *chan;
1520
1521 if (!req->data)
1522 return;
1523 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1524 | (req->data->blocks << 16));
1525 set_data_timeout(host, req->data->timeout_ns,
1526 req->data->timeout_clks);
1527 chan = omap_hsmmc_get_dma_chan(host, req->data);
1528 dma_async_issue_pending(chan);
1529 }
1530
1531 /*
1532 * Configure block length for MMC/SD cards and initiate the transfer.
1533 */
1534 static int
1535 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1536 {
1537 int ret;
1538 host->data = req->data;
1539
1540 if (req->data == NULL) {
1541 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1542 /*
1543 * Set an arbitrary 100ms data timeout for commands with
1544 * busy signal.
1545 */
1546 if (req->cmd->flags & MMC_RSP_BUSY)
1547 set_data_timeout(host, 100000000U, 0);
1548 return 0;
1549 }
1550
1551 if (host->use_dma) {
1552 ret = omap_hsmmc_setup_dma_transfer(host, req);
1553 if (ret != 0) {
1554 dev_err(mmc_dev(host->mmc), "MMC start dma failure\n");
1555 return ret;
1556 }
1557 }
1558 return 0;
1559 }
1560
1561 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1562 int err)
1563 {
1564 struct omap_hsmmc_host *host = mmc_priv(mmc);
1565 struct mmc_data *data = mrq->data;
1566
1567 if (host->use_dma && data->host_cookie) {
1568 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
1569
1570 dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
1571 omap_hsmmc_get_dma_dir(host, data));
1572 data->host_cookie = 0;
1573 }
1574 }
1575
1576 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1577 bool is_first_req)
1578 {
1579 struct omap_hsmmc_host *host = mmc_priv(mmc);
1580
1581 if (mrq->data->host_cookie) {
1582 mrq->data->host_cookie = 0;
1583 return ;
1584 }
1585
1586 if (host->use_dma) {
1587 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
1588
1589 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1590 &host->next_data, c))
1591 mrq->data->host_cookie = 0;
1592 }
1593 }
1594
1595 /*
1596 * Request function. for read/write operation
1597 */
1598 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1599 {
1600 struct omap_hsmmc_host *host = mmc_priv(mmc);
1601 int err;
1602
1603 BUG_ON(host->req_in_progress);
1604 BUG_ON(host->dma_ch != -1);
1605 pm_runtime_get_sync(host->dev);
1606 if (host->protect_card) {
1607 if (host->reqs_blocked < 3) {
1608 /*
1609 * Ensure the controller is left in a consistent
1610 * state by resetting the command and data state
1611 * machines.
1612 */
1613 omap_hsmmc_reset_controller_fsm(host, SRD);
1614 omap_hsmmc_reset_controller_fsm(host, SRC);
1615 host->reqs_blocked += 1;
1616 }
1617 req->cmd->error = -EBADF;
1618 if (req->data)
1619 req->data->error = -EBADF;
1620 req->cmd->retries = 0;
1621 mmc_request_done(mmc, req);
1622 pm_runtime_mark_last_busy(host->dev);
1623 pm_runtime_put_autosuspend(host->dev);
1624 return;
1625 } else if (host->reqs_blocked)
1626 host->reqs_blocked = 0;
1627 WARN_ON(host->mrq != NULL);
1628 host->mrq = req;
1629 host->clk_rate = clk_get_rate(host->fclk);
1630 err = omap_hsmmc_prepare_data(host, req);
1631 if (err) {
1632 req->cmd->error = err;
1633 if (req->data)
1634 req->data->error = err;
1635 host->mrq = NULL;
1636 mmc_request_done(mmc, req);
1637 pm_runtime_mark_last_busy(host->dev);
1638 pm_runtime_put_autosuspend(host->dev);
1639 return;
1640 }
1641 if (req->sbc && !(host->flags & AUTO_CMD23)) {
1642 omap_hsmmc_start_command(host, req->sbc, NULL);
1643 return;
1644 }
1645
1646 omap_hsmmc_start_dma_transfer(host);
1647 omap_hsmmc_start_command(host, req->cmd, req->data);
1648 }
1649
1650 /* Routine to configure clock values. Exposed API to core */
1651 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1652 {
1653 struct omap_hsmmc_host *host = mmc_priv(mmc);
1654 int do_send_init_stream = 0;
1655
1656 pm_runtime_get_sync(host->dev);
1657
1658 if (ios->power_mode != host->power_mode) {
1659 switch (ios->power_mode) {
1660 case MMC_POWER_OFF:
1661 omap_hsmmc_set_power(host->dev, 0, 0);
1662 break;
1663 case MMC_POWER_UP:
1664 omap_hsmmc_set_power(host->dev, 1, ios->vdd);
1665 break;
1666 case MMC_POWER_ON:
1667 do_send_init_stream = 1;
1668 break;
1669 }
1670 host->power_mode = ios->power_mode;
1671 }
1672
1673 /* FIXME: set registers based only on changes to ios */
1674
1675 omap_hsmmc_set_bus_width(host);
1676
1677 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1678 /* Only MMC1 can interface at 3V without some flavor
1679 * of external transceiver; but they all handle 1.8V.
1680 */
1681 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1682 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1683 /*
1684 * The mmc_select_voltage fn of the core does
1685 * not seem to set the power_mode to
1686 * MMC_POWER_UP upon recalculating the voltage.
1687 * vdd 1.8v.
1688 */
1689 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1690 dev_dbg(mmc_dev(host->mmc),
1691 "Switch operation failed\n");
1692 }
1693 }
1694
1695 omap_hsmmc_set_clock(host);
1696
1697 if (do_send_init_stream)
1698 send_init_stream(host);
1699
1700 omap_hsmmc_set_bus_mode(host);
1701
1702 pm_runtime_put_autosuspend(host->dev);
1703 }
1704
1705 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1706 {
1707 struct omap_hsmmc_host *host = mmc_priv(mmc);
1708
1709 if (!host->card_detect)
1710 return -ENOSYS;
1711 return host->card_detect(host->dev);
1712 }
1713
1714 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1715 {
1716 struct omap_hsmmc_host *host = mmc_priv(mmc);
1717
1718 if (mmc_pdata(host)->init_card)
1719 mmc_pdata(host)->init_card(card);
1720 }
1721
1722 static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
1723 {
1724 struct omap_hsmmc_host *host = mmc_priv(mmc);
1725 u32 irq_mask, con;
1726 unsigned long flags;
1727
1728 spin_lock_irqsave(&host->irq_lock, flags);
1729
1730 con = OMAP_HSMMC_READ(host->base, CON);
1731 irq_mask = OMAP_HSMMC_READ(host->base, ISE);
1732 if (enable) {
1733 host->flags |= HSMMC_SDIO_IRQ_ENABLED;
1734 irq_mask |= CIRQ_EN;
1735 con |= CTPL | CLKEXTFREE;
1736 } else {
1737 host->flags &= ~HSMMC_SDIO_IRQ_ENABLED;
1738 irq_mask &= ~CIRQ_EN;
1739 con &= ~(CTPL | CLKEXTFREE);
1740 }
1741 OMAP_HSMMC_WRITE(host->base, CON, con);
1742 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
1743
1744 /*
1745 * if enable, piggy back detection on current request
1746 * but always disable immediately
1747 */
1748 if (!host->req_in_progress || !enable)
1749 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
1750
1751 /* flush posted write */
1752 OMAP_HSMMC_READ(host->base, IE);
1753
1754 spin_unlock_irqrestore(&host->irq_lock, flags);
1755 }
1756
1757 static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host)
1758 {
1759 int ret;
1760
1761 /*
1762 * For omaps with wake-up path, wakeirq will be irq from pinctrl and
1763 * for other omaps, wakeirq will be from GPIO (dat line remuxed to
1764 * gpio). wakeirq is needed to detect sdio irq in runtime suspend state
1765 * with functional clock disabled.
1766 */
1767 if (!host->dev->of_node || !host->wake_irq)
1768 return -ENODEV;
1769
1770 ret = dev_pm_set_dedicated_wake_irq(host->dev, host->wake_irq);
1771 if (ret) {
1772 dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n");
1773 goto err;
1774 }
1775
1776 /*
1777 * Some omaps don't have wake-up path from deeper idle states
1778 * and need to remux SDIO DAT1 to GPIO for wake-up from idle.
1779 */
1780 if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) {
1781 struct pinctrl *p = devm_pinctrl_get(host->dev);
1782 if (!p) {
1783 ret = -ENODEV;
1784 goto err_free_irq;
1785 }
1786 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT))) {
1787 dev_info(host->dev, "missing default pinctrl state\n");
1788 devm_pinctrl_put(p);
1789 ret = -EINVAL;
1790 goto err_free_irq;
1791 }
1792
1793 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) {
1794 dev_info(host->dev, "missing idle pinctrl state\n");
1795 devm_pinctrl_put(p);
1796 ret = -EINVAL;
1797 goto err_free_irq;
1798 }
1799 devm_pinctrl_put(p);
1800 }
1801
1802 OMAP_HSMMC_WRITE(host->base, HCTL,
1803 OMAP_HSMMC_READ(host->base, HCTL) | IWE);
1804 return 0;
1805
1806 err_free_irq:
1807 dev_pm_clear_wake_irq(host->dev);
1808 err:
1809 dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n");
1810 host->wake_irq = 0;
1811 return ret;
1812 }
1813
1814 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1815 {
1816 u32 hctl, capa, value;
1817
1818 /* Only MMC1 supports 3.0V */
1819 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1820 hctl = SDVS30;
1821 capa = VS30 | VS18;
1822 } else {
1823 hctl = SDVS18;
1824 capa = VS18;
1825 }
1826
1827 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1828 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1829
1830 value = OMAP_HSMMC_READ(host->base, CAPA);
1831 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1832
1833 /* Set SD bus power bit */
1834 set_sd_bus_power(host);
1835 }
1836
1837 static int omap_hsmmc_multi_io_quirk(struct mmc_card *card,
1838 unsigned int direction, int blk_size)
1839 {
1840 /* This controller can't do multiblock reads due to hw bugs */
1841 if (direction == MMC_DATA_READ)
1842 return 1;
1843
1844 return blk_size;
1845 }
1846
1847 static struct mmc_host_ops omap_hsmmc_ops = {
1848 .post_req = omap_hsmmc_post_req,
1849 .pre_req = omap_hsmmc_pre_req,
1850 .request = omap_hsmmc_request,
1851 .set_ios = omap_hsmmc_set_ios,
1852 .get_cd = omap_hsmmc_get_cd,
1853 .get_ro = mmc_gpio_get_ro,
1854 .init_card = omap_hsmmc_init_card,
1855 .enable_sdio_irq = omap_hsmmc_enable_sdio_irq,
1856 };
1857
1858 #ifdef CONFIG_DEBUG_FS
1859
1860 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1861 {
1862 struct mmc_host *mmc = s->private;
1863 struct omap_hsmmc_host *host = mmc_priv(mmc);
1864
1865 seq_printf(s, "mmc%d:\n", mmc->index);
1866 seq_printf(s, "sdio irq mode\t%s\n",
1867 (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling");
1868
1869 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1870 seq_printf(s, "sdio irq \t%s\n",
1871 (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled"
1872 : "disabled");
1873 }
1874 seq_printf(s, "ctx_loss:\t%d\n", host->context_loss);
1875
1876 pm_runtime_get_sync(host->dev);
1877 seq_puts(s, "\nregs:\n");
1878 seq_printf(s, "CON:\t\t0x%08x\n",
1879 OMAP_HSMMC_READ(host->base, CON));
1880 seq_printf(s, "PSTATE:\t\t0x%08x\n",
1881 OMAP_HSMMC_READ(host->base, PSTATE));
1882 seq_printf(s, "HCTL:\t\t0x%08x\n",
1883 OMAP_HSMMC_READ(host->base, HCTL));
1884 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1885 OMAP_HSMMC_READ(host->base, SYSCTL));
1886 seq_printf(s, "IE:\t\t0x%08x\n",
1887 OMAP_HSMMC_READ(host->base, IE));
1888 seq_printf(s, "ISE:\t\t0x%08x\n",
1889 OMAP_HSMMC_READ(host->base, ISE));
1890 seq_printf(s, "CAPA:\t\t0x%08x\n",
1891 OMAP_HSMMC_READ(host->base, CAPA));
1892
1893 pm_runtime_mark_last_busy(host->dev);
1894 pm_runtime_put_autosuspend(host->dev);
1895
1896 return 0;
1897 }
1898
1899 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1900 {
1901 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1902 }
1903
1904 static const struct file_operations mmc_regs_fops = {
1905 .open = omap_hsmmc_regs_open,
1906 .read = seq_read,
1907 .llseek = seq_lseek,
1908 .release = single_release,
1909 };
1910
1911 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1912 {
1913 if (mmc->debugfs_root)
1914 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1915 mmc, &mmc_regs_fops);
1916 }
1917
1918 #else
1919
1920 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1921 {
1922 }
1923
1924 #endif
1925
1926 #ifdef CONFIG_OF
1927 static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = {
1928 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1929 .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1930 };
1931
1932 static const struct omap_mmc_of_data omap4_mmc_of_data = {
1933 .reg_offset = 0x100,
1934 };
1935 static const struct omap_mmc_of_data am33xx_mmc_of_data = {
1936 .reg_offset = 0x100,
1937 .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING,
1938 };
1939
1940 static const struct of_device_id omap_mmc_of_match[] = {
1941 {
1942 .compatible = "ti,omap2-hsmmc",
1943 },
1944 {
1945 .compatible = "ti,omap3-pre-es3-hsmmc",
1946 .data = &omap3_pre_es3_mmc_of_data,
1947 },
1948 {
1949 .compatible = "ti,omap3-hsmmc",
1950 },
1951 {
1952 .compatible = "ti,omap4-hsmmc",
1953 .data = &omap4_mmc_of_data,
1954 },
1955 {
1956 .compatible = "ti,am33xx-hsmmc",
1957 .data = &am33xx_mmc_of_data,
1958 },
1959 {},
1960 };
1961 MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1962
1963 static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1964 {
1965 struct omap_hsmmc_platform_data *pdata;
1966 struct device_node *np = dev->of_node;
1967
1968 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1969 if (!pdata)
1970 return ERR_PTR(-ENOMEM); /* out of memory */
1971
1972 if (of_find_property(np, "ti,dual-volt", NULL))
1973 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1974
1975 pdata->gpio_cd = -EINVAL;
1976 pdata->gpio_cod = -EINVAL;
1977 pdata->gpio_wp = -EINVAL;
1978
1979 if (of_find_property(np, "ti,non-removable", NULL)) {
1980 pdata->nonremovable = true;
1981 pdata->no_regulator_off_init = true;
1982 }
1983
1984 if (of_find_property(np, "ti,needs-special-reset", NULL))
1985 pdata->features |= HSMMC_HAS_UPDATED_RESET;
1986
1987 if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
1988 pdata->features |= HSMMC_HAS_HSPE_SUPPORT;
1989
1990 return pdata;
1991 }
1992 #else
1993 static inline struct omap_hsmmc_platform_data
1994 *of_get_hsmmc_pdata(struct device *dev)
1995 {
1996 return ERR_PTR(-EINVAL);
1997 }
1998 #endif
1999
2000 static int omap_hsmmc_probe(struct platform_device *pdev)
2001 {
2002 struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data;
2003 struct mmc_host *mmc;
2004 struct omap_hsmmc_host *host = NULL;
2005 struct resource *res;
2006 int ret, irq;
2007 const struct of_device_id *match;
2008 dma_cap_mask_t mask;
2009 unsigned tx_req, rx_req;
2010 const struct omap_mmc_of_data *data;
2011 void __iomem *base;
2012
2013 match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
2014 if (match) {
2015 pdata = of_get_hsmmc_pdata(&pdev->dev);
2016
2017 if (IS_ERR(pdata))
2018 return PTR_ERR(pdata);
2019
2020 if (match->data) {
2021 data = match->data;
2022 pdata->reg_offset = data->reg_offset;
2023 pdata->controller_flags |= data->controller_flags;
2024 }
2025 }
2026
2027 if (pdata == NULL) {
2028 dev_err(&pdev->dev, "Platform Data is missing\n");
2029 return -ENXIO;
2030 }
2031
2032 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2033 irq = platform_get_irq(pdev, 0);
2034 if (res == NULL || irq < 0)
2035 return -ENXIO;
2036
2037 base = devm_ioremap_resource(&pdev->dev, res);
2038 if (IS_ERR(base))
2039 return PTR_ERR(base);
2040
2041 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
2042 if (!mmc) {
2043 ret = -ENOMEM;
2044 goto err;
2045 }
2046
2047 ret = mmc_of_parse(mmc);
2048 if (ret)
2049 goto err1;
2050
2051 host = mmc_priv(mmc);
2052 host->mmc = mmc;
2053 host->pdata = pdata;
2054 host->dev = &pdev->dev;
2055 host->use_dma = 1;
2056 host->dma_ch = -1;
2057 host->irq = irq;
2058 host->mapbase = res->start + pdata->reg_offset;
2059 host->base = base + pdata->reg_offset;
2060 host->power_mode = MMC_POWER_OFF;
2061 host->next_data.cookie = 1;
2062 host->pbias_enabled = 0;
2063 host->vqmmc_enabled = 0;
2064
2065 ret = omap_hsmmc_gpio_init(mmc, host, pdata);
2066 if (ret)
2067 goto err_gpio;
2068
2069 platform_set_drvdata(pdev, host);
2070
2071 if (pdev->dev.of_node)
2072 host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1);
2073
2074 mmc->ops = &omap_hsmmc_ops;
2075
2076 mmc->f_min = OMAP_MMC_MIN_CLOCK;
2077
2078 if (pdata->max_freq > 0)
2079 mmc->f_max = pdata->max_freq;
2080 else if (mmc->f_max == 0)
2081 mmc->f_max = OMAP_MMC_MAX_CLOCK;
2082
2083 spin_lock_init(&host->irq_lock);
2084
2085 host->fclk = devm_clk_get(&pdev->dev, "fck");
2086 if (IS_ERR(host->fclk)) {
2087 ret = PTR_ERR(host->fclk);
2088 host->fclk = NULL;
2089 goto err1;
2090 }
2091
2092 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
2093 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
2094 omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk;
2095 }
2096
2097 device_init_wakeup(&pdev->dev, true);
2098 pm_runtime_enable(host->dev);
2099 pm_runtime_get_sync(host->dev);
2100 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
2101 pm_runtime_use_autosuspend(host->dev);
2102
2103 omap_hsmmc_context_save(host);
2104
2105 host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck");
2106 /*
2107 * MMC can still work without debounce clock.
2108 */
2109 if (IS_ERR(host->dbclk)) {
2110 host->dbclk = NULL;
2111 } else if (clk_prepare_enable(host->dbclk) != 0) {
2112 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
2113 host->dbclk = NULL;
2114 }
2115
2116 /* Since we do only SG emulation, we can have as many segs
2117 * as we want. */
2118 mmc->max_segs = 1024;
2119
2120 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
2121 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
2122 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2123 mmc->max_seg_size = mmc->max_req_size;
2124
2125 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
2126 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
2127
2128 mmc->caps |= mmc_pdata(host)->caps;
2129 if (mmc->caps & MMC_CAP_8_BIT_DATA)
2130 mmc->caps |= MMC_CAP_4_BIT_DATA;
2131
2132 if (mmc_pdata(host)->nonremovable)
2133 mmc->caps |= MMC_CAP_NONREMOVABLE;
2134
2135 mmc->pm_caps |= mmc_pdata(host)->pm_caps;
2136
2137 omap_hsmmc_conf_bus_power(host);
2138
2139 if (!pdev->dev.of_node) {
2140 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
2141 if (!res) {
2142 dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
2143 ret = -ENXIO;
2144 goto err_irq;
2145 }
2146 tx_req = res->start;
2147
2148 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
2149 if (!res) {
2150 dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
2151 ret = -ENXIO;
2152 goto err_irq;
2153 }
2154 rx_req = res->start;
2155 }
2156
2157 dma_cap_zero(mask);
2158 dma_cap_set(DMA_SLAVE, mask);
2159
2160 host->rx_chan =
2161 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
2162 &rx_req, &pdev->dev, "rx");
2163
2164 if (!host->rx_chan) {
2165 dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel\n");
2166 ret = -ENXIO;
2167 goto err_irq;
2168 }
2169
2170 host->tx_chan =
2171 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
2172 &tx_req, &pdev->dev, "tx");
2173
2174 if (!host->tx_chan) {
2175 dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel\n");
2176 ret = -ENXIO;
2177 goto err_irq;
2178 }
2179
2180 /* Request IRQ for MMC operations */
2181 ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0,
2182 mmc_hostname(mmc), host);
2183 if (ret) {
2184 dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2185 goto err_irq;
2186 }
2187
2188 ret = omap_hsmmc_reg_get(host);
2189 if (ret)
2190 goto err_irq;
2191
2192 mmc->ocr_avail = mmc_pdata(host)->ocr_mask;
2193
2194 omap_hsmmc_disable_irq(host);
2195
2196 /*
2197 * For now, only support SDIO interrupt if we have a separate
2198 * wake-up interrupt configured from device tree. This is because
2199 * the wake-up interrupt is needed for idle state and some
2200 * platforms need special quirks. And we don't want to add new
2201 * legacy mux platform init code callbacks any longer as we
2202 * are moving to DT based booting anyways.
2203 */
2204 ret = omap_hsmmc_configure_wake_irq(host);
2205 if (!ret)
2206 mmc->caps |= MMC_CAP_SDIO_IRQ;
2207
2208 omap_hsmmc_protect_card(host);
2209
2210 mmc_add_host(mmc);
2211
2212 if (mmc_pdata(host)->name != NULL) {
2213 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2214 if (ret < 0)
2215 goto err_slot_name;
2216 }
2217 if (host->get_cover_state) {
2218 ret = device_create_file(&mmc->class_dev,
2219 &dev_attr_cover_switch);
2220 if (ret < 0)
2221 goto err_slot_name;
2222 }
2223
2224 omap_hsmmc_debugfs(mmc);
2225 pm_runtime_mark_last_busy(host->dev);
2226 pm_runtime_put_autosuspend(host->dev);
2227
2228 return 0;
2229
2230 err_slot_name:
2231 mmc_remove_host(mmc);
2232 err_irq:
2233 device_init_wakeup(&pdev->dev, false);
2234 if (host->tx_chan)
2235 dma_release_channel(host->tx_chan);
2236 if (host->rx_chan)
2237 dma_release_channel(host->rx_chan);
2238 pm_runtime_dont_use_autosuspend(host->dev);
2239 pm_runtime_put_sync(host->dev);
2240 pm_runtime_disable(host->dev);
2241 if (host->dbclk)
2242 clk_disable_unprepare(host->dbclk);
2243 err1:
2244 err_gpio:
2245 mmc_free_host(mmc);
2246 err:
2247 return ret;
2248 }
2249
2250 static int omap_hsmmc_remove(struct platform_device *pdev)
2251 {
2252 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2253
2254 pm_runtime_get_sync(host->dev);
2255 mmc_remove_host(host->mmc);
2256
2257 dma_release_channel(host->tx_chan);
2258 dma_release_channel(host->rx_chan);
2259
2260 pm_runtime_dont_use_autosuspend(host->dev);
2261 pm_runtime_put_sync(host->dev);
2262 pm_runtime_disable(host->dev);
2263 device_init_wakeup(&pdev->dev, false);
2264 if (host->dbclk)
2265 clk_disable_unprepare(host->dbclk);
2266
2267 mmc_free_host(host->mmc);
2268
2269 return 0;
2270 }
2271
2272 #ifdef CONFIG_PM_SLEEP
2273 static int omap_hsmmc_suspend(struct device *dev)
2274 {
2275 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2276
2277 if (!host)
2278 return 0;
2279
2280 pm_runtime_get_sync(host->dev);
2281
2282 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2283 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2284 OMAP_HSMMC_WRITE(host->base, IE, 0);
2285 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2286 OMAP_HSMMC_WRITE(host->base, HCTL,
2287 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2288 }
2289
2290 if (host->dbclk)
2291 clk_disable_unprepare(host->dbclk);
2292
2293 pm_runtime_put_sync(host->dev);
2294 return 0;
2295 }
2296
2297 /* Routine to resume the MMC device */
2298 static int omap_hsmmc_resume(struct device *dev)
2299 {
2300 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2301
2302 if (!host)
2303 return 0;
2304
2305 pm_runtime_get_sync(host->dev);
2306
2307 if (host->dbclk)
2308 clk_prepare_enable(host->dbclk);
2309
2310 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2311 omap_hsmmc_conf_bus_power(host);
2312
2313 omap_hsmmc_protect_card(host);
2314 pm_runtime_mark_last_busy(host->dev);
2315 pm_runtime_put_autosuspend(host->dev);
2316 return 0;
2317 }
2318 #endif
2319
2320 static int omap_hsmmc_runtime_suspend(struct device *dev)
2321 {
2322 struct omap_hsmmc_host *host;
2323 unsigned long flags;
2324 int ret = 0;
2325
2326 host = platform_get_drvdata(to_platform_device(dev));
2327 omap_hsmmc_context_save(host);
2328 dev_dbg(dev, "disabled\n");
2329
2330 spin_lock_irqsave(&host->irq_lock, flags);
2331 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2332 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2333 /* disable sdio irq handling to prevent race */
2334 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2335 OMAP_HSMMC_WRITE(host->base, IE, 0);
2336
2337 if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) {
2338 /*
2339 * dat1 line low, pending sdio irq
2340 * race condition: possible irq handler running on
2341 * multi-core, abort
2342 */
2343 dev_dbg(dev, "pending sdio irq, abort suspend\n");
2344 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2345 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2346 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2347 pm_runtime_mark_last_busy(dev);
2348 ret = -EBUSY;
2349 goto abort;
2350 }
2351
2352 pinctrl_pm_select_idle_state(dev);
2353 } else {
2354 pinctrl_pm_select_idle_state(dev);
2355 }
2356
2357 abort:
2358 spin_unlock_irqrestore(&host->irq_lock, flags);
2359 return ret;
2360 }
2361
2362 static int omap_hsmmc_runtime_resume(struct device *dev)
2363 {
2364 struct omap_hsmmc_host *host;
2365 unsigned long flags;
2366
2367 host = platform_get_drvdata(to_platform_device(dev));
2368 omap_hsmmc_context_restore(host);
2369 dev_dbg(dev, "enabled\n");
2370
2371 spin_lock_irqsave(&host->irq_lock, flags);
2372 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2373 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2374
2375 pinctrl_pm_select_default_state(host->dev);
2376
2377 /* irq lost, if pinmux incorrect */
2378 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2379 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2380 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2381 } else {
2382 pinctrl_pm_select_default_state(host->dev);
2383 }
2384 spin_unlock_irqrestore(&host->irq_lock, flags);
2385 return 0;
2386 }
2387
2388 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2389 SET_SYSTEM_SLEEP_PM_OPS(omap_hsmmc_suspend, omap_hsmmc_resume)
2390 .runtime_suspend = omap_hsmmc_runtime_suspend,
2391 .runtime_resume = omap_hsmmc_runtime_resume,
2392 };
2393
2394 static struct platform_driver omap_hsmmc_driver = {
2395 .probe = omap_hsmmc_probe,
2396 .remove = omap_hsmmc_remove,
2397 .driver = {
2398 .name = DRIVER_NAME,
2399 .pm = &omap_hsmmc_dev_pm_ops,
2400 .of_match_table = of_match_ptr(omap_mmc_of_match),
2401 },
2402 };
2403
2404 module_platform_driver(omap_hsmmc_driver);
2405 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2406 MODULE_LICENSE("GPL");
2407 MODULE_ALIAS("platform:" DRIVER_NAME);
2408 MODULE_AUTHOR("Texas Instruments Inc");
CRIS linux kernel tree