2 * Atmel SDMMC controller driver.
4 * Copyright (C) 2015 Atmel,
5 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk.h>
18 #include <linux/err.h>
20 #include <linux/mmc/host.h>
21 #include <linux/mmc/slot-gpio.h>
22 #include <linux/module.h>
24 #include <linux/of_device.h>
26 #include <linux/pm_runtime.h>
28 #include "sdhci-pltfm.h"
30 #define SDMMC_CACR 0x230
31 #define SDMMC_CACR_CAPWREN BIT(0)
32 #define SDMMC_CACR_KEY (0x46 << 8)
34 struct sdhci_at91_priv
{
40 static const struct sdhci_ops sdhci_at91_sama5d2_ops
= {
41 .set_clock
= sdhci_set_clock
,
42 .set_bus_width
= sdhci_set_bus_width
,
44 .set_uhs_signaling
= sdhci_set_uhs_signaling
,
47 static const struct sdhci_pltfm_data soc_data_sama5d2
= {
48 .ops
= &sdhci_at91_sama5d2_ops
,
49 .quirks2
= SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST
,
52 static const struct of_device_id sdhci_at91_dt_match
[] = {
53 { .compatible
= "atmel,sama5d2-sdhci", .data
= &soc_data_sama5d2
},
58 static int sdhci_at91_runtime_suspend(struct device
*dev
)
60 struct sdhci_host
*host
= dev_get_drvdata(dev
);
61 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
62 struct sdhci_at91_priv
*priv
= sdhci_pltfm_priv(pltfm_host
);
65 ret
= sdhci_runtime_suspend_host(host
);
67 clk_disable_unprepare(priv
->gck
);
68 clk_disable_unprepare(priv
->hclock
);
69 clk_disable_unprepare(priv
->mainck
);
74 static int sdhci_at91_runtime_resume(struct device
*dev
)
76 struct sdhci_host
*host
= dev_get_drvdata(dev
);
77 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
78 struct sdhci_at91_priv
*priv
= sdhci_pltfm_priv(pltfm_host
);
81 ret
= clk_prepare_enable(priv
->mainck
);
83 dev_err(dev
, "can't enable mainck\n");
87 ret
= clk_prepare_enable(priv
->hclock
);
89 dev_err(dev
, "can't enable hclock\n");
93 ret
= clk_prepare_enable(priv
->gck
);
95 dev_err(dev
, "can't enable gck\n");
99 return sdhci_runtime_resume_host(host
);
101 #endif /* CONFIG_PM */
103 static const struct dev_pm_ops sdhci_at91_dev_pm_ops
= {
104 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend
,
105 pm_runtime_force_resume
)
106 SET_RUNTIME_PM_OPS(sdhci_at91_runtime_suspend
,
107 sdhci_at91_runtime_resume
,
111 static int sdhci_at91_probe(struct platform_device
*pdev
)
113 const struct of_device_id
*match
;
114 const struct sdhci_pltfm_data
*soc_data
;
115 struct sdhci_host
*host
;
116 struct sdhci_pltfm_host
*pltfm_host
;
117 struct sdhci_at91_priv
*priv
;
118 unsigned int caps0
, caps1
;
119 unsigned int clk_base
, clk_mul
;
120 unsigned int gck_rate
, real_gck_rate
;
123 match
= of_match_device(sdhci_at91_dt_match
, &pdev
->dev
);
126 soc_data
= match
->data
;
128 host
= sdhci_pltfm_init(pdev
, soc_data
, sizeof(*priv
));
130 return PTR_ERR(host
);
132 pltfm_host
= sdhci_priv(host
);
133 priv
= sdhci_pltfm_priv(pltfm_host
);
135 priv
->mainck
= devm_clk_get(&pdev
->dev
, "baseclk");
136 if (IS_ERR(priv
->mainck
)) {
137 dev_err(&pdev
->dev
, "failed to get baseclk\n");
138 return PTR_ERR(priv
->mainck
);
141 priv
->hclock
= devm_clk_get(&pdev
->dev
, "hclock");
142 if (IS_ERR(priv
->hclock
)) {
143 dev_err(&pdev
->dev
, "failed to get hclock\n");
144 return PTR_ERR(priv
->hclock
);
147 priv
->gck
= devm_clk_get(&pdev
->dev
, "multclk");
148 if (IS_ERR(priv
->gck
)) {
149 dev_err(&pdev
->dev
, "failed to get multclk\n");
150 return PTR_ERR(priv
->gck
);
154 * The mult clock is provided by as a generated clock by the PMC
155 * controller. In order to set the rate of gck, we have to get the
156 * base clock rate and the clock mult from capabilities.
158 clk_prepare_enable(priv
->hclock
);
159 caps0
= readl(host
->ioaddr
+ SDHCI_CAPABILITIES
);
160 caps1
= readl(host
->ioaddr
+ SDHCI_CAPABILITIES_1
);
161 clk_base
= (caps0
& SDHCI_CLOCK_V3_BASE_MASK
) >> SDHCI_CLOCK_BASE_SHIFT
;
162 clk_mul
= (caps1
& SDHCI_CLOCK_MUL_MASK
) >> SDHCI_CLOCK_MUL_SHIFT
;
163 gck_rate
= clk_base
* 1000000 * (clk_mul
+ 1);
164 ret
= clk_set_rate(priv
->gck
, gck_rate
);
166 dev_err(&pdev
->dev
, "failed to set gck");
167 goto hclock_disable_unprepare
;
170 * We need to check if we have the requested rate for gck because in
171 * some cases this rate could be not supported. If it happens, the rate
172 * is the closest one gck can provide. We have to update the value
175 real_gck_rate
= clk_get_rate(priv
->gck
);
176 if (real_gck_rate
!= gck_rate
) {
177 clk_mul
= real_gck_rate
/ (clk_base
* 1000000) - 1;
178 caps1
&= (~SDHCI_CLOCK_MUL_MASK
);
179 caps1
|= ((clk_mul
<< SDHCI_CLOCK_MUL_SHIFT
) & SDHCI_CLOCK_MUL_MASK
);
180 /* Set capabilities in r/w mode. */
181 writel(SDMMC_CACR_KEY
| SDMMC_CACR_CAPWREN
, host
->ioaddr
+ SDMMC_CACR
);
182 writel(caps1
, host
->ioaddr
+ SDHCI_CAPABILITIES_1
);
183 /* Set capabilities in ro mode. */
184 writel(0, host
->ioaddr
+ SDMMC_CACR
);
185 dev_info(&pdev
->dev
, "update clk mul to %u as gck rate is %u Hz\n",
186 clk_mul
, real_gck_rate
);
189 clk_prepare_enable(priv
->mainck
);
190 clk_prepare_enable(priv
->gck
);
192 ret
= mmc_of_parse(host
->mmc
);
194 goto clocks_disable_unprepare
;
196 sdhci_get_of_property(pdev
);
198 pm_runtime_get_noresume(&pdev
->dev
);
199 pm_runtime_set_active(&pdev
->dev
);
200 pm_runtime_enable(&pdev
->dev
);
201 pm_runtime_set_autosuspend_delay(&pdev
->dev
, 50);
202 pm_runtime_use_autosuspend(&pdev
->dev
);
204 ret
= sdhci_add_host(host
);
206 goto pm_runtime_disable
;
209 * When calling sdhci_runtime_suspend_host(), the sdhci layer makes
210 * the assumption that all the clocks of the controller are disabled.
211 * It means we can't get irq from it when it is runtime suspended.
212 * For that reason, it is not planned to wake-up on a card detect irq
213 * from the controller.
214 * If we want to use runtime PM and to be able to wake-up on card
215 * insertion, we have to use a GPIO for the card detection or we can
216 * use polling. Be aware that using polling will resume/suspend the
217 * controller between each attempt.
218 * Disable SDHCI_QUIRK_BROKEN_CARD_DETECTION to be sure nobody tries
219 * to enable polling via device tree with broken-cd property.
221 if (!(host
->mmc
->caps
& MMC_CAP_NONREMOVABLE
) &&
222 IS_ERR_VALUE(mmc_gpio_get_cd(host
->mmc
))) {
223 host
->mmc
->caps
|= MMC_CAP_NEEDS_POLL
;
224 host
->quirks
&= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION
;
227 pm_runtime_put_autosuspend(&pdev
->dev
);
232 pm_runtime_disable(&pdev
->dev
);
233 pm_runtime_set_suspended(&pdev
->dev
);
234 pm_runtime_put_noidle(&pdev
->dev
);
235 clocks_disable_unprepare
:
236 clk_disable_unprepare(priv
->gck
);
237 clk_disable_unprepare(priv
->mainck
);
238 hclock_disable_unprepare
:
239 clk_disable_unprepare(priv
->hclock
);
240 sdhci_pltfm_free(pdev
);
244 static int sdhci_at91_remove(struct platform_device
*pdev
)
246 struct sdhci_host
*host
= platform_get_drvdata(pdev
);
247 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
248 struct sdhci_at91_priv
*priv
= sdhci_pltfm_priv(pltfm_host
);
249 struct clk
*gck
= priv
->gck
;
250 struct clk
*hclock
= priv
->hclock
;
251 struct clk
*mainck
= priv
->mainck
;
253 pm_runtime_get_sync(&pdev
->dev
);
254 pm_runtime_disable(&pdev
->dev
);
255 pm_runtime_put_noidle(&pdev
->dev
);
257 sdhci_pltfm_unregister(pdev
);
259 clk_disable_unprepare(gck
);
260 clk_disable_unprepare(hclock
);
261 clk_disable_unprepare(mainck
);
266 static struct platform_driver sdhci_at91_driver
= {
268 .name
= "sdhci-at91",
269 .of_match_table
= sdhci_at91_dt_match
,
270 .pm
= &sdhci_at91_dev_pm_ops
,
272 .probe
= sdhci_at91_probe
,
273 .remove
= sdhci_at91_remove
,
276 module_platform_driver(sdhci_at91_driver
);
278 MODULE_DESCRIPTION("SDHCI driver for at91");
279 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
280 MODULE_LICENSE("GPL v2");