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Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[cris-mirror.git] / drivers / mmc / host / sdhci-pci-core.c
blob62aa5d0efceecc81c79f36806c91386a37502ff7
1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
2 *
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 *
10 * Thanks to the following companies for their support:
11 *
12 * - JMicron (hardware and technical support)
13 */
14
15 #include <linux/delay.h>
16 #include <linux/highmem.h>
17 #include <linux/module.h>
18 #include <linux/pci.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/slab.h>
21 #include <linux/device.h>
22 #include <linux/mmc/host.h>
23 #include <linux/mmc/mmc.h>
24 #include <linux/scatterlist.h>
25 #include <linux/io.h>
26 #include <linux/gpio.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/mmc/slot-gpio.h>
29 #include <linux/mmc/sdhci-pci-data.h>
30
31 #include "sdhci.h"
32 #include "sdhci-pci.h"
33 #include "sdhci-pci-o2micro.h"
34
35 /*****************************************************************************\
36 * *
37 * Hardware specific quirk handling *
38 * *
39 \*****************************************************************************/
40
41 static int ricoh_probe(struct sdhci_pci_chip *chip)
42 {
43 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
44 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
45 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
46 return 0;
47 }
48
49 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
50 {
51 slot->host->caps =
52 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
53 & SDHCI_TIMEOUT_CLK_MASK) |
54
55 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
56 & SDHCI_CLOCK_BASE_MASK) |
57
58 SDHCI_TIMEOUT_CLK_UNIT |
59 SDHCI_CAN_VDD_330 |
60 SDHCI_CAN_DO_HISPD |
61 SDHCI_CAN_DO_SDMA;
62 return 0;
63 }
64
65 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
66 {
67 /* Apply a delay to allow controller to settle */
68 /* Otherwise it becomes confused if card state changed
69 during suspend */
70 msleep(500);
71 return 0;
72 }
73
74 static const struct sdhci_pci_fixes sdhci_ricoh = {
75 .probe = ricoh_probe,
76 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
77 SDHCI_QUIRK_FORCE_DMA |
78 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
79 };
80
81 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
82 .probe_slot = ricoh_mmc_probe_slot,
83 .resume = ricoh_mmc_resume,
84 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
85 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
86 SDHCI_QUIRK_NO_CARD_NO_RESET |
87 SDHCI_QUIRK_MISSING_CAPS
88 };
89
90 static const struct sdhci_pci_fixes sdhci_ene_712 = {
91 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
92 SDHCI_QUIRK_BROKEN_DMA,
93 };
94
95 static const struct sdhci_pci_fixes sdhci_ene_714 = {
96 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
97 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
98 SDHCI_QUIRK_BROKEN_DMA,
99 };
100
101 static const struct sdhci_pci_fixes sdhci_cafe = {
102 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
103 SDHCI_QUIRK_NO_BUSY_IRQ |
104 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
105 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
106 };
107
108 static const struct sdhci_pci_fixes sdhci_intel_qrk = {
109 .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
110 };
111
112 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
113 {
114 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
115 return 0;
116 }
117
118 /*
119 * ADMA operation is disabled for Moorestown platform due to
120 * hardware bugs.
121 */
122 static int mrst_hc_probe(struct sdhci_pci_chip *chip)
123 {
124 /*
125 * slots number is fixed here for MRST as SDIO3/5 are never used and
126 * have hardware bugs.
127 */
128 chip->num_slots = 1;
129 return 0;
130 }
131
132 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
133 {
134 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
135 return 0;
136 }
137
138 #ifdef CONFIG_PM
139
140 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
141 {
142 struct sdhci_pci_slot *slot = dev_id;
143 struct sdhci_host *host = slot->host;
144
145 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
146 return IRQ_HANDLED;
147 }
148
149 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
150 {
151 int err, irq, gpio = slot->cd_gpio;
152
153 slot->cd_gpio = -EINVAL;
154 slot->cd_irq = -EINVAL;
155
156 if (!gpio_is_valid(gpio))
157 return;
158
159 err = gpio_request(gpio, "sd_cd");
160 if (err < 0)
161 goto out;
162
163 err = gpio_direction_input(gpio);
164 if (err < 0)
165 goto out_free;
166
167 irq = gpio_to_irq(gpio);
168 if (irq < 0)
169 goto out_free;
170
171 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
172 IRQF_TRIGGER_FALLING, "sd_cd", slot);
173 if (err)
174 goto out_free;
175
176 slot->cd_gpio = gpio;
177 slot->cd_irq = irq;
178
179 return;
180
181 out_free:
182 gpio_free(gpio);
183 out:
184 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
185 }
186
187 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
188 {
189 if (slot->cd_irq >= 0)
190 free_irq(slot->cd_irq, slot);
191 if (gpio_is_valid(slot->cd_gpio))
192 gpio_free(slot->cd_gpio);
193 }
194
195 #else
196
197 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
198 {
199 }
200
201 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
202 {
203 }
204
205 #endif
206
207 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
208 {
209 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
210 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC |
211 MMC_CAP2_HC_ERASE_SZ;
212 return 0;
213 }
214
215 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
216 {
217 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
218 return 0;
219 }
220
221 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
222 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
223 .probe_slot = mrst_hc_probe_slot,
224 };
225
226 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
227 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
228 .probe = mrst_hc_probe,
229 };
230
231 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
232 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
233 .allow_runtime_pm = true,
234 .own_cd_for_runtime_pm = true,
235 };
236
237 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
238 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
239 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
240 .allow_runtime_pm = true,
241 .probe_slot = mfd_sdio_probe_slot,
242 };
243
244 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
245 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
246 .allow_runtime_pm = true,
247 .probe_slot = mfd_emmc_probe_slot,
248 };
249
250 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
251 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
252 .probe_slot = pch_hc_probe_slot,
253 };
254
255 static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
256 {
257 u8 reg;
258
259 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
260 reg |= 0x10;
261 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
262 /* For eMMC, minimum is 1us but give it 9us for good measure */
263 udelay(9);
264 reg &= ~0x10;
265 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
266 /* For eMMC, minimum is 200us but give it 300us for good measure */
267 usleep_range(300, 1000);
268 }
269
270 static int spt_select_drive_strength(struct sdhci_host *host,
271 struct mmc_card *card,
272 unsigned int max_dtr,
273 int host_drv, int card_drv, int *drv_type)
274 {
275 int drive_strength;
276
277 if (sdhci_pci_spt_drive_strength > 0)
278 drive_strength = sdhci_pci_spt_drive_strength & 0xf;
279 else
280 drive_strength = 0; /* Default 50-ohm */
281
282 if ((mmc_driver_type_mask(drive_strength) & card_drv) == 0)
283 drive_strength = 0; /* Default 50-ohm */
284
285 return drive_strength;
286 }
287
288 /* Try to read the drive strength from the card */
289 static void spt_read_drive_strength(struct sdhci_host *host)
290 {
291 u32 val, i, t;
292 u16 m;
293
294 if (sdhci_pci_spt_drive_strength)
295 return;
296
297 sdhci_pci_spt_drive_strength = -1;
298
299 m = sdhci_readw(host, SDHCI_HOST_CONTROL2) & 0x7;
300 if (m != 3 && m != 5)
301 return;
302 val = sdhci_readl(host, SDHCI_PRESENT_STATE);
303 if (val & 0x3)
304 return;
305 sdhci_writel(host, 0x007f0023, SDHCI_INT_ENABLE);
306 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
307 sdhci_writew(host, 0x10, SDHCI_TRANSFER_MODE);
308 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
309 sdhci_writew(host, 512, SDHCI_BLOCK_SIZE);
310 sdhci_writew(host, 1, SDHCI_BLOCK_COUNT);
311 sdhci_writel(host, 0, SDHCI_ARGUMENT);
312 sdhci_writew(host, 0x83b, SDHCI_COMMAND);
313 for (i = 0; i < 1000; i++) {
314 val = sdhci_readl(host, SDHCI_INT_STATUS);
315 if (val & 0xffff8000)
316 return;
317 if (val & 0x20)
318 break;
319 udelay(1);
320 }
321 val = sdhci_readl(host, SDHCI_PRESENT_STATE);
322 if (!(val & 0x800))
323 return;
324 for (i = 0; i < 47; i++)
325 val = sdhci_readl(host, SDHCI_BUFFER);
326 t = val & 0xf00;
327 if (t != 0x200 && t != 0x300)
328 return;
329
330 sdhci_pci_spt_drive_strength = 0x10 | ((val >> 12) & 0xf);
331 }
332
333 static int bxt_get_cd(struct mmc_host *mmc)
334 {
335 int gpio_cd = mmc_gpio_get_cd(mmc);
336 struct sdhci_host *host = mmc_priv(mmc);
337 unsigned long flags;
338 int ret = 0;
339
340 if (!gpio_cd)
341 return 0;
342
343 pm_runtime_get_sync(mmc->parent);
344
345 spin_lock_irqsave(&host->lock, flags);
346
347 if (host->flags & SDHCI_DEVICE_DEAD)
348 goto out;
349
350 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
351 out:
352 spin_unlock_irqrestore(&host->lock, flags);
353
354 pm_runtime_mark_last_busy(mmc->parent);
355 pm_runtime_put_autosuspend(mmc->parent);
356
357 return ret;
358 }
359
360 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
361 {
362 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
363 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
364 MMC_CAP_BUS_WIDTH_TEST |
365 MMC_CAP_WAIT_WHILE_BUSY;
366 slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ;
367 slot->hw_reset = sdhci_pci_int_hw_reset;
368 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
369 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
370 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_SPT_EMMC) {
371 spt_read_drive_strength(slot->host);
372 slot->select_drive_strength = spt_select_drive_strength;
373 }
374 return 0;
375 }
376
377 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
378 {
379 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
380 MMC_CAP_BUS_WIDTH_TEST |
381 MMC_CAP_WAIT_WHILE_BUSY;
382 return 0;
383 }
384
385 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
386 {
387 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST |
388 MMC_CAP_WAIT_WHILE_BUSY;
389 slot->cd_con_id = NULL;
390 slot->cd_idx = 0;
391 slot->cd_override_level = true;
392 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD ||
393 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD)
394 slot->host->mmc_host_ops.get_cd = bxt_get_cd;
395
396 return 0;
397 }
398
399 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
400 .allow_runtime_pm = true,
401 .probe_slot = byt_emmc_probe_slot,
402 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
403 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
404 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
405 SDHCI_QUIRK2_STOP_WITH_TC,
406 };
407
408 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
409 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
410 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
411 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
412 .allow_runtime_pm = true,
413 .probe_slot = byt_sdio_probe_slot,
414 };
415
416 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
417 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
418 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
419 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
420 SDHCI_QUIRK2_STOP_WITH_TC,
421 .allow_runtime_pm = true,
422 .own_cd_for_runtime_pm = true,
423 .probe_slot = byt_sd_probe_slot,
424 };
425
426 /* Define Host controllers for Intel Merrifield platform */
427 #define INTEL_MRFL_EMMC_0 0
428 #define INTEL_MRFL_EMMC_1 1
429
430 static int intel_mrfl_mmc_probe_slot(struct sdhci_pci_slot *slot)
431 {
432 if ((PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_0) &&
433 (PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_1))
434 /* SD support is not ready yet */
435 return -ENODEV;
436
437 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
438 MMC_CAP_1_8V_DDR;
439
440 return 0;
441 }
442
443 static const struct sdhci_pci_fixes sdhci_intel_mrfl_mmc = {
444 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
445 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
446 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
447 .allow_runtime_pm = true,
448 .probe_slot = intel_mrfl_mmc_probe_slot,
449 };
450
451 /* O2Micro extra registers */
452 #define O2_SD_LOCK_WP 0xD3
453 #define O2_SD_MULTI_VCC3V 0xEE
454 #define O2_SD_CLKREQ 0xEC
455 #define O2_SD_CAPS 0xE0
456 #define O2_SD_ADMA1 0xE2
457 #define O2_SD_ADMA2 0xE7
458 #define O2_SD_INF_MOD 0xF1
459
460 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
461 {
462 u8 scratch;
463 int ret;
464
465 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
466 if (ret)
467 return ret;
468
469 /*
470 * Turn PMOS on [bit 0], set over current detection to 2.4 V
471 * [bit 1:2] and enable over current debouncing [bit 6].
472 */
473 if (on)
474 scratch |= 0x47;
475 else
476 scratch &= ~0x47;
477
478 return pci_write_config_byte(chip->pdev, 0xAE, scratch);
479 }
480
481 static int jmicron_probe(struct sdhci_pci_chip *chip)
482 {
483 int ret;
484 u16 mmcdev = 0;
485
486 if (chip->pdev->revision == 0) {
487 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
488 SDHCI_QUIRK_32BIT_DMA_SIZE |
489 SDHCI_QUIRK_32BIT_ADMA_SIZE |
490 SDHCI_QUIRK_RESET_AFTER_REQUEST |
491 SDHCI_QUIRK_BROKEN_SMALL_PIO;
492 }
493
494 /*
495 * JMicron chips can have two interfaces to the same hardware
496 * in order to work around limitations in Microsoft's driver.
497 * We need to make sure we only bind to one of them.
498 *
499 * This code assumes two things:
500 *
501 * 1. The PCI code adds subfunctions in order.
502 *
503 * 2. The MMC interface has a lower subfunction number
504 * than the SD interface.
505 */
506 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
507 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
508 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
509 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
510
511 if (mmcdev) {
512 struct pci_dev *sd_dev;
513
514 sd_dev = NULL;
515 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
516 mmcdev, sd_dev)) != NULL) {
517 if ((PCI_SLOT(chip->pdev->devfn) ==
518 PCI_SLOT(sd_dev->devfn)) &&
519 (chip->pdev->bus == sd_dev->bus))
520 break;
521 }
522
523 if (sd_dev) {
524 pci_dev_put(sd_dev);
525 dev_info(&chip->pdev->dev, "Refusing to bind to "
526 "secondary interface.\n");
527 return -ENODEV;
528 }
529 }
530
531 /*
532 * JMicron chips need a bit of a nudge to enable the power
533 * output pins.
534 */
535 ret = jmicron_pmos(chip, 1);
536 if (ret) {
537 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
538 return ret;
539 }
540
541 /* quirk for unsable RO-detection on JM388 chips */
542 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
543 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
544 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
545
546 return 0;
547 }
548
549 static void jmicron_enable_mmc(struct sdhci_host *host, int on)
550 {
551 u8 scratch;
552
553 scratch = readb(host->ioaddr + 0xC0);
554
555 if (on)
556 scratch |= 0x01;
557 else
558 scratch &= ~0x01;
559
560 writeb(scratch, host->ioaddr + 0xC0);
561 }
562
563 static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
564 {
565 if (slot->chip->pdev->revision == 0) {
566 u16 version;
567
568 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
569 version = (version & SDHCI_VENDOR_VER_MASK) >>
570 SDHCI_VENDOR_VER_SHIFT;
571
572 /*
573 * Older versions of the chip have lots of nasty glitches
574 * in the ADMA engine. It's best just to avoid it
575 * completely.
576 */
577 if (version < 0xAC)
578 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
579 }
580
581 /* JM388 MMC doesn't support 1.8V while SD supports it */
582 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
583 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
584 MMC_VDD_29_30 | MMC_VDD_30_31 |
585 MMC_VDD_165_195; /* allow 1.8V */
586 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
587 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
588 }
589
590 /*
591 * The secondary interface requires a bit set to get the
592 * interrupts.
593 */
594 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
595 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
596 jmicron_enable_mmc(slot->host, 1);
597
598 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
599
600 return 0;
601 }
602
603 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
604 {
605 if (dead)
606 return;
607
608 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
609 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
610 jmicron_enable_mmc(slot->host, 0);
611 }
612
613 static int jmicron_suspend(struct sdhci_pci_chip *chip)
614 {
615 int i;
616
617 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
618 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
619 for (i = 0; i < chip->num_slots; i++)
620 jmicron_enable_mmc(chip->slots[i]->host, 0);
621 }
622
623 return 0;
624 }
625
626 static int jmicron_resume(struct sdhci_pci_chip *chip)
627 {
628 int ret, i;
629
630 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
631 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
632 for (i = 0; i < chip->num_slots; i++)
633 jmicron_enable_mmc(chip->slots[i]->host, 1);
634 }
635
636 ret = jmicron_pmos(chip, 1);
637 if (ret) {
638 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
639 return ret;
640 }
641
642 return 0;
643 }
644
645 static const struct sdhci_pci_fixes sdhci_o2 = {
646 .probe = sdhci_pci_o2_probe,
647 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
648 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD,
649 .probe_slot = sdhci_pci_o2_probe_slot,
650 .resume = sdhci_pci_o2_resume,
651 };
652
653 static const struct sdhci_pci_fixes sdhci_jmicron = {
654 .probe = jmicron_probe,
655
656 .probe_slot = jmicron_probe_slot,
657 .remove_slot = jmicron_remove_slot,
658
659 .suspend = jmicron_suspend,
660 .resume = jmicron_resume,
661 };
662
663 /* SysKonnect CardBus2SDIO extra registers */
664 #define SYSKT_CTRL 0x200
665 #define SYSKT_RDFIFO_STAT 0x204
666 #define SYSKT_WRFIFO_STAT 0x208
667 #define SYSKT_POWER_DATA 0x20c
668 #define SYSKT_POWER_330 0xef
669 #define SYSKT_POWER_300 0xf8
670 #define SYSKT_POWER_184 0xcc
671 #define SYSKT_POWER_CMD 0x20d
672 #define SYSKT_POWER_START (1 << 7)
673 #define SYSKT_POWER_STATUS 0x20e
674 #define SYSKT_POWER_STATUS_OK (1 << 0)
675 #define SYSKT_BOARD_REV 0x210
676 #define SYSKT_CHIP_REV 0x211
677 #define SYSKT_CONF_DATA 0x212
678 #define SYSKT_CONF_DATA_1V8 (1 << 2)
679 #define SYSKT_CONF_DATA_2V5 (1 << 1)
680 #define SYSKT_CONF_DATA_3V3 (1 << 0)
681
682 static int syskt_probe(struct sdhci_pci_chip *chip)
683 {
684 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
685 chip->pdev->class &= ~0x0000FF;
686 chip->pdev->class |= PCI_SDHCI_IFDMA;
687 }
688 return 0;
689 }
690
691 static int syskt_probe_slot(struct sdhci_pci_slot *slot)
692 {
693 int tm, ps;
694
695 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
696 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
697 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
698 "board rev %d.%d, chip rev %d.%d\n",
699 board_rev >> 4, board_rev & 0xf,
700 chip_rev >> 4, chip_rev & 0xf);
701 if (chip_rev >= 0x20)
702 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
703
704 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
705 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
706 udelay(50);
707 tm = 10; /* Wait max 1 ms */
708 do {
709 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
710 if (ps & SYSKT_POWER_STATUS_OK)
711 break;
712 udelay(100);
713 } while (--tm);
714 if (!tm) {
715 dev_err(&slot->chip->pdev->dev,
716 "power regulator never stabilized");
717 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
718 return -ENODEV;
719 }
720
721 return 0;
722 }
723
724 static const struct sdhci_pci_fixes sdhci_syskt = {
725 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
726 .probe = syskt_probe,
727 .probe_slot = syskt_probe_slot,
728 };
729
730 static int via_probe(struct sdhci_pci_chip *chip)
731 {
732 if (chip->pdev->revision == 0x10)
733 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
734
735 return 0;
736 }
737
738 static const struct sdhci_pci_fixes sdhci_via = {
739 .probe = via_probe,
740 };
741
742 static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
743 {
744 slot->host->mmc->caps2 |= MMC_CAP2_HS200;
745 return 0;
746 }
747
748 static const struct sdhci_pci_fixes sdhci_rtsx = {
749 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
750 SDHCI_QUIRK2_BROKEN_64_BIT_DMA |
751 SDHCI_QUIRK2_BROKEN_DDR50,
752 .probe_slot = rtsx_probe_slot,
753 };
754
755 /*AMD chipset generation*/
756 enum amd_chipset_gen {
757 AMD_CHIPSET_BEFORE_ML,
758 AMD_CHIPSET_CZ,
759 AMD_CHIPSET_NL,
760 AMD_CHIPSET_UNKNOWN,
761 };
762
763 static int amd_probe(struct sdhci_pci_chip *chip)
764 {
765 struct pci_dev *smbus_dev;
766 enum amd_chipset_gen gen;
767
768 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
769 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
770 if (smbus_dev) {
771 gen = AMD_CHIPSET_BEFORE_ML;
772 } else {
773 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
774 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL);
775 if (smbus_dev) {
776 if (smbus_dev->revision < 0x51)
777 gen = AMD_CHIPSET_CZ;
778 else
779 gen = AMD_CHIPSET_NL;
780 } else {
781 gen = AMD_CHIPSET_UNKNOWN;
782 }
783 }
784
785 if ((gen == AMD_CHIPSET_BEFORE_ML) || (gen == AMD_CHIPSET_CZ)) {
786 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
787 chip->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
788 }
789
790 return 0;
791 }
792
793 static const struct sdhci_pci_fixes sdhci_amd = {
794 .probe = amd_probe,
795 };
796
797 static const struct pci_device_id pci_ids[] = {
798 {
799 .vendor = PCI_VENDOR_ID_RICOH,
800 .device = PCI_DEVICE_ID_RICOH_R5C822,
801 .subvendor = PCI_ANY_ID,
802 .subdevice = PCI_ANY_ID,
803 .driver_data = (kernel_ulong_t)&sdhci_ricoh,
804 },
805
806 {
807 .vendor = PCI_VENDOR_ID_RICOH,
808 .device = 0x843,
809 .subvendor = PCI_ANY_ID,
810 .subdevice = PCI_ANY_ID,
811 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
812 },
813
814 {
815 .vendor = PCI_VENDOR_ID_RICOH,
816 .device = 0xe822,
817 .subvendor = PCI_ANY_ID,
818 .subdevice = PCI_ANY_ID,
819 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
820 },
821
822 {
823 .vendor = PCI_VENDOR_ID_RICOH,
824 .device = 0xe823,
825 .subvendor = PCI_ANY_ID,
826 .subdevice = PCI_ANY_ID,
827 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
828 },
829
830 {
831 .vendor = PCI_VENDOR_ID_ENE,
832 .device = PCI_DEVICE_ID_ENE_CB712_SD,
833 .subvendor = PCI_ANY_ID,
834 .subdevice = PCI_ANY_ID,
835 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
836 },
837
838 {
839 .vendor = PCI_VENDOR_ID_ENE,
840 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
841 .subvendor = PCI_ANY_ID,
842 .subdevice = PCI_ANY_ID,
843 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
844 },
845
846 {
847 .vendor = PCI_VENDOR_ID_ENE,
848 .device = PCI_DEVICE_ID_ENE_CB714_SD,
849 .subvendor = PCI_ANY_ID,
850 .subdevice = PCI_ANY_ID,
851 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
852 },
853
854 {
855 .vendor = PCI_VENDOR_ID_ENE,
856 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
857 .subvendor = PCI_ANY_ID,
858 .subdevice = PCI_ANY_ID,
859 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
860 },
861
862 {
863 .vendor = PCI_VENDOR_ID_MARVELL,
864 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD,
865 .subvendor = PCI_ANY_ID,
866 .subdevice = PCI_ANY_ID,
867 .driver_data = (kernel_ulong_t)&sdhci_cafe,
868 },
869
870 {
871 .vendor = PCI_VENDOR_ID_JMICRON,
872 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
873 .subvendor = PCI_ANY_ID,
874 .subdevice = PCI_ANY_ID,
875 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
876 },
877
878 {
879 .vendor = PCI_VENDOR_ID_JMICRON,
880 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC,
881 .subvendor = PCI_ANY_ID,
882 .subdevice = PCI_ANY_ID,
883 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
884 },
885
886 {
887 .vendor = PCI_VENDOR_ID_JMICRON,
888 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD,
889 .subvendor = PCI_ANY_ID,
890 .subdevice = PCI_ANY_ID,
891 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
892 },
893
894 {
895 .vendor = PCI_VENDOR_ID_JMICRON,
896 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD,
897 .subvendor = PCI_ANY_ID,
898 .subdevice = PCI_ANY_ID,
899 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
900 },
901
902 {
903 .vendor = PCI_VENDOR_ID_SYSKONNECT,
904 .device = 0x8000,
905 .subvendor = PCI_ANY_ID,
906 .subdevice = PCI_ANY_ID,
907 .driver_data = (kernel_ulong_t)&sdhci_syskt,
908 },
909
910 {
911 .vendor = PCI_VENDOR_ID_VIA,
912 .device = 0x95d0,
913 .subvendor = PCI_ANY_ID,
914 .subdevice = PCI_ANY_ID,
915 .driver_data = (kernel_ulong_t)&sdhci_via,
916 },
917
918 {
919 .vendor = PCI_VENDOR_ID_REALTEK,
920 .device = 0x5250,
921 .subvendor = PCI_ANY_ID,
922 .subdevice = PCI_ANY_ID,
923 .driver_data = (kernel_ulong_t)&sdhci_rtsx,
924 },
925
926 {
927 .vendor = PCI_VENDOR_ID_INTEL,
928 .device = PCI_DEVICE_ID_INTEL_QRK_SD,
929 .subvendor = PCI_ANY_ID,
930 .subdevice = PCI_ANY_ID,
931 .driver_data = (kernel_ulong_t)&sdhci_intel_qrk,
932 },
933
934 {
935 .vendor = PCI_VENDOR_ID_INTEL,
936 .device = PCI_DEVICE_ID_INTEL_MRST_SD0,
937 .subvendor = PCI_ANY_ID,
938 .subdevice = PCI_ANY_ID,
939 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0,
940 },
941
942 {
943 .vendor = PCI_VENDOR_ID_INTEL,
944 .device = PCI_DEVICE_ID_INTEL_MRST_SD1,
945 .subvendor = PCI_ANY_ID,
946 .subdevice = PCI_ANY_ID,
947 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
948 },
949
950 {
951 .vendor = PCI_VENDOR_ID_INTEL,
952 .device = PCI_DEVICE_ID_INTEL_MRST_SD2,
953 .subvendor = PCI_ANY_ID,
954 .subdevice = PCI_ANY_ID,
955 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
956 },
957
958 {
959 .vendor = PCI_VENDOR_ID_INTEL,
960 .device = PCI_DEVICE_ID_INTEL_MFD_SD,
961 .subvendor = PCI_ANY_ID,
962 .subdevice = PCI_ANY_ID,
963 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
964 },
965
966 {
967 .vendor = PCI_VENDOR_ID_INTEL,
968 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1,
969 .subvendor = PCI_ANY_ID,
970 .subdevice = PCI_ANY_ID,
971 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
972 },
973
974 {
975 .vendor = PCI_VENDOR_ID_INTEL,
976 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2,
977 .subvendor = PCI_ANY_ID,
978 .subdevice = PCI_ANY_ID,
979 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
980 },
981
982 {
983 .vendor = PCI_VENDOR_ID_INTEL,
984 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0,
985 .subvendor = PCI_ANY_ID,
986 .subdevice = PCI_ANY_ID,
987 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
988 },
989
990 {
991 .vendor = PCI_VENDOR_ID_INTEL,
992 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1,
993 .subvendor = PCI_ANY_ID,
994 .subdevice = PCI_ANY_ID,
995 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
996 },
997
998 {
999 .vendor = PCI_VENDOR_ID_INTEL,
1000 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0,
1001 .subvendor = PCI_ANY_ID,
1002 .subdevice = PCI_ANY_ID,
1003 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
1004 },
1005
1006 {
1007 .vendor = PCI_VENDOR_ID_INTEL,
1008 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1,
1009 .subvendor = PCI_ANY_ID,
1010 .subdevice = PCI_ANY_ID,
1011 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
1012 },
1013
1014 {
1015 .vendor = PCI_VENDOR_ID_INTEL,
1016 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC,
1017 .subvendor = PCI_ANY_ID,
1018 .subdevice = PCI_ANY_ID,
1019 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1020 },
1021
1022 {
1023 .vendor = PCI_VENDOR_ID_INTEL,
1024 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO,
1025 .subvendor = PCI_ANY_ID,
1026 .subdevice = PCI_ANY_ID,
1027 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1028 },
1029
1030 {
1031 .vendor = PCI_VENDOR_ID_INTEL,
1032 .device = PCI_DEVICE_ID_INTEL_BYT_SD,
1033 .subvendor = PCI_ANY_ID,
1034 .subdevice = PCI_ANY_ID,
1035 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1036 },
1037
1038 {
1039 .vendor = PCI_VENDOR_ID_INTEL,
1040 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2,
1041 .subvendor = PCI_ANY_ID,
1042 .subdevice = PCI_ANY_ID,
1043 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1044 },
1045
1046 {
1047 .vendor = PCI_VENDOR_ID_INTEL,
1048 .device = PCI_DEVICE_ID_INTEL_BSW_EMMC,
1049 .subvendor = PCI_ANY_ID,
1050 .subdevice = PCI_ANY_ID,
1051 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1052 },
1053
1054 {
1055 .vendor = PCI_VENDOR_ID_INTEL,
1056 .device = PCI_DEVICE_ID_INTEL_BSW_SDIO,
1057 .subvendor = PCI_ANY_ID,
1058 .subdevice = PCI_ANY_ID,
1059 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1060 },
1061
1062 {
1063 .vendor = PCI_VENDOR_ID_INTEL,
1064 .device = PCI_DEVICE_ID_INTEL_BSW_SD,
1065 .subvendor = PCI_ANY_ID,
1066 .subdevice = PCI_ANY_ID,
1067 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1068 },
1069
1070 {
1071 .vendor = PCI_VENDOR_ID_INTEL,
1072 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO0,
1073 .subvendor = PCI_ANY_ID,
1074 .subdevice = PCI_ANY_ID,
1075 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
1076 },
1077
1078 {
1079 .vendor = PCI_VENDOR_ID_INTEL,
1080 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO1,
1081 .subvendor = PCI_ANY_ID,
1082 .subdevice = PCI_ANY_ID,
1083 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
1084 },
1085
1086 {
1087 .vendor = PCI_VENDOR_ID_INTEL,
1088 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO2,
1089 .subvendor = PCI_ANY_ID,
1090 .subdevice = PCI_ANY_ID,
1091 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
1092 },
1093
1094 {
1095 .vendor = PCI_VENDOR_ID_INTEL,
1096 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC0,
1097 .subvendor = PCI_ANY_ID,
1098 .subdevice = PCI_ANY_ID,
1099 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
1100 },
1101
1102 {
1103 .vendor = PCI_VENDOR_ID_INTEL,
1104 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC1,
1105 .subvendor = PCI_ANY_ID,
1106 .subdevice = PCI_ANY_ID,
1107 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
1108 },
1109
1110 {
1111 .vendor = PCI_VENDOR_ID_INTEL,
1112 .device = PCI_DEVICE_ID_INTEL_MRFL_MMC,
1113 .subvendor = PCI_ANY_ID,
1114 .subdevice = PCI_ANY_ID,
1115 .driver_data = (kernel_ulong_t)&sdhci_intel_mrfl_mmc,
1116 },
1117
1118 {
1119 .vendor = PCI_VENDOR_ID_INTEL,
1120 .device = PCI_DEVICE_ID_INTEL_SPT_EMMC,
1121 .subvendor = PCI_ANY_ID,
1122 .subdevice = PCI_ANY_ID,
1123 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1124 },
1125
1126 {
1127 .vendor = PCI_VENDOR_ID_INTEL,
1128 .device = PCI_DEVICE_ID_INTEL_SPT_SDIO,
1129 .subvendor = PCI_ANY_ID,
1130 .subdevice = PCI_ANY_ID,
1131 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1132 },
1133
1134 {
1135 .vendor = PCI_VENDOR_ID_INTEL,
1136 .device = PCI_DEVICE_ID_INTEL_SPT_SD,
1137 .subvendor = PCI_ANY_ID,
1138 .subdevice = PCI_ANY_ID,
1139 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1140 },
1141
1142 {
1143 .vendor = PCI_VENDOR_ID_INTEL,
1144 .device = PCI_DEVICE_ID_INTEL_DNV_EMMC,
1145 .subvendor = PCI_ANY_ID,
1146 .subdevice = PCI_ANY_ID,
1147 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1148 },
1149
1150 {
1151 .vendor = PCI_VENDOR_ID_INTEL,
1152 .device = PCI_DEVICE_ID_INTEL_BXT_EMMC,
1153 .subvendor = PCI_ANY_ID,
1154 .subdevice = PCI_ANY_ID,
1155 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1156 },
1157
1158 {
1159 .vendor = PCI_VENDOR_ID_INTEL,
1160 .device = PCI_DEVICE_ID_INTEL_BXT_SDIO,
1161 .subvendor = PCI_ANY_ID,
1162 .subdevice = PCI_ANY_ID,
1163 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1164 },
1165
1166 {
1167 .vendor = PCI_VENDOR_ID_INTEL,
1168 .device = PCI_DEVICE_ID_INTEL_BXT_SD,
1169 .subvendor = PCI_ANY_ID,
1170 .subdevice = PCI_ANY_ID,
1171 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1172 },
1173
1174 {
1175 .vendor = PCI_VENDOR_ID_INTEL,
1176 .device = PCI_DEVICE_ID_INTEL_APL_EMMC,
1177 .subvendor = PCI_ANY_ID,
1178 .subdevice = PCI_ANY_ID,
1179 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1180 },
1181
1182 {
1183 .vendor = PCI_VENDOR_ID_INTEL,
1184 .device = PCI_DEVICE_ID_INTEL_APL_SDIO,
1185 .subvendor = PCI_ANY_ID,
1186 .subdevice = PCI_ANY_ID,
1187 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1188 },
1189
1190 {
1191 .vendor = PCI_VENDOR_ID_INTEL,
1192 .device = PCI_DEVICE_ID_INTEL_APL_SD,
1193 .subvendor = PCI_ANY_ID,
1194 .subdevice = PCI_ANY_ID,
1195 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1196 },
1197
1198 {
1199 .vendor = PCI_VENDOR_ID_O2,
1200 .device = PCI_DEVICE_ID_O2_8120,
1201 .subvendor = PCI_ANY_ID,
1202 .subdevice = PCI_ANY_ID,
1203 .driver_data = (kernel_ulong_t)&sdhci_o2,
1204 },
1205
1206 {
1207 .vendor = PCI_VENDOR_ID_O2,
1208 .device = PCI_DEVICE_ID_O2_8220,
1209 .subvendor = PCI_ANY_ID,
1210 .subdevice = PCI_ANY_ID,
1211 .driver_data = (kernel_ulong_t)&sdhci_o2,
1212 },
1213
1214 {
1215 .vendor = PCI_VENDOR_ID_O2,
1216 .device = PCI_DEVICE_ID_O2_8221,
1217 .subvendor = PCI_ANY_ID,
1218 .subdevice = PCI_ANY_ID,
1219 .driver_data = (kernel_ulong_t)&sdhci_o2,
1220 },
1221
1222 {
1223 .vendor = PCI_VENDOR_ID_O2,
1224 .device = PCI_DEVICE_ID_O2_8320,
1225 .subvendor = PCI_ANY_ID,
1226 .subdevice = PCI_ANY_ID,
1227 .driver_data = (kernel_ulong_t)&sdhci_o2,
1228 },
1229
1230 {
1231 .vendor = PCI_VENDOR_ID_O2,
1232 .device = PCI_DEVICE_ID_O2_8321,
1233 .subvendor = PCI_ANY_ID,
1234 .subdevice = PCI_ANY_ID,
1235 .driver_data = (kernel_ulong_t)&sdhci_o2,
1236 },
1237
1238 {
1239 .vendor = PCI_VENDOR_ID_O2,
1240 .device = PCI_DEVICE_ID_O2_FUJIN2,
1241 .subvendor = PCI_ANY_ID,
1242 .subdevice = PCI_ANY_ID,
1243 .driver_data = (kernel_ulong_t)&sdhci_o2,
1244 },
1245
1246 {
1247 .vendor = PCI_VENDOR_ID_O2,
1248 .device = PCI_DEVICE_ID_O2_SDS0,
1249 .subvendor = PCI_ANY_ID,
1250 .subdevice = PCI_ANY_ID,
1251 .driver_data = (kernel_ulong_t)&sdhci_o2,
1252 },
1253
1254 {
1255 .vendor = PCI_VENDOR_ID_O2,
1256 .device = PCI_DEVICE_ID_O2_SDS1,
1257 .subvendor = PCI_ANY_ID,
1258 .subdevice = PCI_ANY_ID,
1259 .driver_data = (kernel_ulong_t)&sdhci_o2,
1260 },
1261
1262 {
1263 .vendor = PCI_VENDOR_ID_O2,
1264 .device = PCI_DEVICE_ID_O2_SEABIRD0,
1265 .subvendor = PCI_ANY_ID,
1266 .subdevice = PCI_ANY_ID,
1267 .driver_data = (kernel_ulong_t)&sdhci_o2,
1268 },
1269
1270 {
1271 .vendor = PCI_VENDOR_ID_O2,
1272 .device = PCI_DEVICE_ID_O2_SEABIRD1,
1273 .subvendor = PCI_ANY_ID,
1274 .subdevice = PCI_ANY_ID,
1275 .driver_data = (kernel_ulong_t)&sdhci_o2,
1276 },
1277 {
1278 .vendor = PCI_VENDOR_ID_AMD,
1279 .device = PCI_ANY_ID,
1280 .class = PCI_CLASS_SYSTEM_SDHCI << 8,
1281 .class_mask = 0xFFFF00,
1282 .subvendor = PCI_ANY_ID,
1283 .subdevice = PCI_ANY_ID,
1284 .driver_data = (kernel_ulong_t)&sdhci_amd,
1285 },
1286 { /* Generic SD host controller */
1287 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
1288 },
1289
1290 { /* end: all zeroes */ },
1291 };
1292
1293 MODULE_DEVICE_TABLE(pci, pci_ids);
1294
1295 /*****************************************************************************\
1296 * *
1297 * SDHCI core callbacks *
1298 * *
1299 \*****************************************************************************/
1300
1301 static int sdhci_pci_enable_dma(struct sdhci_host *host)
1302 {
1303 struct sdhci_pci_slot *slot;
1304 struct pci_dev *pdev;
1305
1306 slot = sdhci_priv(host);
1307 pdev = slot->chip->pdev;
1308
1309 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1310 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1311 (host->flags & SDHCI_USE_SDMA)) {
1312 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1313 "doesn't fully claim to support it.\n");
1314 }
1315
1316 pci_set_master(pdev);
1317
1318 return 0;
1319 }
1320
1321 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width)
1322 {
1323 u8 ctrl;
1324
1325 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1326
1327 switch (width) {
1328 case MMC_BUS_WIDTH_8:
1329 ctrl |= SDHCI_CTRL_8BITBUS;
1330 ctrl &= ~SDHCI_CTRL_4BITBUS;
1331 break;
1332 case MMC_BUS_WIDTH_4:
1333 ctrl |= SDHCI_CTRL_4BITBUS;
1334 ctrl &= ~SDHCI_CTRL_8BITBUS;
1335 break;
1336 default:
1337 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS);
1338 break;
1339 }
1340
1341 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1342 }
1343
1344 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
1345 {
1346 struct sdhci_pci_slot *slot = sdhci_priv(host);
1347 int rst_n_gpio = slot->rst_n_gpio;
1348
1349 if (!gpio_is_valid(rst_n_gpio))
1350 return;
1351 gpio_set_value_cansleep(rst_n_gpio, 0);
1352 /* For eMMC, minimum is 1us but give it 10us for good measure */
1353 udelay(10);
1354 gpio_set_value_cansleep(rst_n_gpio, 1);
1355 /* For eMMC, minimum is 200us but give it 300us for good measure */
1356 usleep_range(300, 1000);
1357 }
1358
1359 static void sdhci_pci_hw_reset(struct sdhci_host *host)
1360 {
1361 struct sdhci_pci_slot *slot = sdhci_priv(host);
1362
1363 if (slot->hw_reset)
1364 slot->hw_reset(host);
1365 }
1366
1367 static int sdhci_pci_select_drive_strength(struct sdhci_host *host,
1368 struct mmc_card *card,
1369 unsigned int max_dtr, int host_drv,
1370 int card_drv, int *drv_type)
1371 {
1372 struct sdhci_pci_slot *slot = sdhci_priv(host);
1373
1374 if (!slot->select_drive_strength)
1375 return 0;
1376
1377 return slot->select_drive_strength(host, card, max_dtr, host_drv,
1378 card_drv, drv_type);
1379 }
1380
1381 static const struct sdhci_ops sdhci_pci_ops = {
1382 .set_clock = sdhci_set_clock,
1383 .enable_dma = sdhci_pci_enable_dma,
1384 .set_bus_width = sdhci_pci_set_bus_width,
1385 .reset = sdhci_reset,
1386 .set_uhs_signaling = sdhci_set_uhs_signaling,
1387 .hw_reset = sdhci_pci_hw_reset,
1388 .select_drive_strength = sdhci_pci_select_drive_strength,
1389 };
1390
1391 /*****************************************************************************\
1392 * *
1393 * Suspend/resume *
1394 * *
1395 \*****************************************************************************/
1396
1397 #ifdef CONFIG_PM
1398
1399 static int sdhci_pci_suspend(struct device *dev)
1400 {
1401 struct pci_dev *pdev = to_pci_dev(dev);
1402 struct sdhci_pci_chip *chip;
1403 struct sdhci_pci_slot *slot;
1404 mmc_pm_flag_t slot_pm_flags;
1405 mmc_pm_flag_t pm_flags = 0;
1406 int i, ret;
1407
1408 chip = pci_get_drvdata(pdev);
1409 if (!chip)
1410 return 0;
1411
1412 for (i = 0; i < chip->num_slots; i++) {
1413 slot = chip->slots[i];
1414 if (!slot)
1415 continue;
1416
1417 ret = sdhci_suspend_host(slot->host);
1418
1419 if (ret)
1420 goto err_pci_suspend;
1421
1422 slot_pm_flags = slot->host->mmc->pm_flags;
1423 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1424 sdhci_enable_irq_wakeups(slot->host);
1425
1426 pm_flags |= slot_pm_flags;
1427 }
1428
1429 if (chip->fixes && chip->fixes->suspend) {
1430 ret = chip->fixes->suspend(chip);
1431 if (ret)
1432 goto err_pci_suspend;
1433 }
1434
1435 if (pm_flags & MMC_PM_KEEP_POWER) {
1436 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1437 device_init_wakeup(dev, true);
1438 else
1439 device_init_wakeup(dev, false);
1440 } else
1441 device_init_wakeup(dev, false);
1442
1443 return 0;
1444
1445 err_pci_suspend:
1446 while (--i >= 0)
1447 sdhci_resume_host(chip->slots[i]->host);
1448 return ret;
1449 }
1450
1451 static int sdhci_pci_resume(struct device *dev)
1452 {
1453 struct pci_dev *pdev = to_pci_dev(dev);
1454 struct sdhci_pci_chip *chip;
1455 struct sdhci_pci_slot *slot;
1456 int i, ret;
1457
1458 chip = pci_get_drvdata(pdev);
1459 if (!chip)
1460 return 0;
1461
1462 if (chip->fixes && chip->fixes->resume) {
1463 ret = chip->fixes->resume(chip);
1464 if (ret)
1465 return ret;
1466 }
1467
1468 for (i = 0; i < chip->num_slots; i++) {
1469 slot = chip->slots[i];
1470 if (!slot)
1471 continue;
1472
1473 ret = sdhci_resume_host(slot->host);
1474 if (ret)
1475 return ret;
1476 }
1477
1478 return 0;
1479 }
1480
1481 static int sdhci_pci_runtime_suspend(struct device *dev)
1482 {
1483 struct pci_dev *pdev = to_pci_dev(dev);
1484 struct sdhci_pci_chip *chip;
1485 struct sdhci_pci_slot *slot;
1486 int i, ret;
1487
1488 chip = pci_get_drvdata(pdev);
1489 if (!chip)
1490 return 0;
1491
1492 for (i = 0; i < chip->num_slots; i++) {
1493 slot = chip->slots[i];
1494 if (!slot)
1495 continue;
1496
1497 ret = sdhci_runtime_suspend_host(slot->host);
1498
1499 if (ret)
1500 goto err_pci_runtime_suspend;
1501 }
1502
1503 if (chip->fixes && chip->fixes->suspend) {
1504 ret = chip->fixes->suspend(chip);
1505 if (ret)
1506 goto err_pci_runtime_suspend;
1507 }
1508
1509 return 0;
1510
1511 err_pci_runtime_suspend:
1512 while (--i >= 0)
1513 sdhci_runtime_resume_host(chip->slots[i]->host);
1514 return ret;
1515 }
1516
1517 static int sdhci_pci_runtime_resume(struct device *dev)
1518 {
1519 struct pci_dev *pdev = to_pci_dev(dev);
1520 struct sdhci_pci_chip *chip;
1521 struct sdhci_pci_slot *slot;
1522 int i, ret;
1523
1524 chip = pci_get_drvdata(pdev);
1525 if (!chip)
1526 return 0;
1527
1528 if (chip->fixes && chip->fixes->resume) {
1529 ret = chip->fixes->resume(chip);
1530 if (ret)
1531 return ret;
1532 }
1533
1534 for (i = 0; i < chip->num_slots; i++) {
1535 slot = chip->slots[i];
1536 if (!slot)
1537 continue;
1538
1539 ret = sdhci_runtime_resume_host(slot->host);
1540 if (ret)
1541 return ret;
1542 }
1543
1544 return 0;
1545 }
1546
1547 #else /* CONFIG_PM */
1548
1549 #define sdhci_pci_suspend NULL
1550 #define sdhci_pci_resume NULL
1551
1552 #endif /* CONFIG_PM */
1553
1554 static const struct dev_pm_ops sdhci_pci_pm_ops = {
1555 .suspend = sdhci_pci_suspend,
1556 .resume = sdhci_pci_resume,
1557 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
1558 sdhci_pci_runtime_resume, NULL)
1559 };
1560
1561 /*****************************************************************************\
1562 * *
1563 * Device probing/removal *
1564 * *
1565 \*****************************************************************************/
1566
1567 static struct sdhci_pci_slot *sdhci_pci_probe_slot(
1568 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1569 int slotno)
1570 {
1571 struct sdhci_pci_slot *slot;
1572 struct sdhci_host *host;
1573 int ret, bar = first_bar + slotno;
1574
1575 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1576 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1577 return ERR_PTR(-ENODEV);
1578 }
1579
1580 if (pci_resource_len(pdev, bar) < 0x100) {
1581 dev_err(&pdev->dev, "Invalid iomem size. You may "
1582 "experience problems.\n");
1583 }
1584
1585 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1586 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1587 return ERR_PTR(-ENODEV);
1588 }
1589
1590 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1591 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1592 return ERR_PTR(-ENODEV);
1593 }
1594
1595 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot));
1596 if (IS_ERR(host)) {
1597 dev_err(&pdev->dev, "cannot allocate host\n");
1598 return ERR_CAST(host);
1599 }
1600
1601 slot = sdhci_priv(host);
1602
1603 slot->chip = chip;
1604 slot->host = host;
1605 slot->pci_bar = bar;
1606 slot->rst_n_gpio = -EINVAL;
1607 slot->cd_gpio = -EINVAL;
1608 slot->cd_idx = -1;
1609
1610 /* Retrieve platform data if there is any */
1611 if (*sdhci_pci_get_data)
1612 slot->data = sdhci_pci_get_data(pdev, slotno);
1613
1614 if (slot->data) {
1615 if (slot->data->setup) {
1616 ret = slot->data->setup(slot->data);
1617 if (ret) {
1618 dev_err(&pdev->dev, "platform setup failed\n");
1619 goto free;
1620 }
1621 }
1622 slot->rst_n_gpio = slot->data->rst_n_gpio;
1623 slot->cd_gpio = slot->data->cd_gpio;
1624 }
1625
1626 host->hw_name = "PCI";
1627 host->ops = &sdhci_pci_ops;
1628 host->quirks = chip->quirks;
1629 host->quirks2 = chip->quirks2;
1630
1631 host->irq = pdev->irq;
1632
1633 ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc));
1634 if (ret) {
1635 dev_err(&pdev->dev, "cannot request region\n");
1636 goto cleanup;
1637 }
1638
1639 host->ioaddr = pci_ioremap_bar(pdev, bar);
1640 if (!host->ioaddr) {
1641 dev_err(&pdev->dev, "failed to remap registers\n");
1642 ret = -ENOMEM;
1643 goto release;
1644 }
1645
1646 if (chip->fixes && chip->fixes->probe_slot) {
1647 ret = chip->fixes->probe_slot(slot);
1648 if (ret)
1649 goto unmap;
1650 }
1651
1652 if (gpio_is_valid(slot->rst_n_gpio)) {
1653 if (!gpio_request(slot->rst_n_gpio, "eMMC_reset")) {
1654 gpio_direction_output(slot->rst_n_gpio, 1);
1655 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
1656 slot->hw_reset = sdhci_pci_gpio_hw_reset;
1657 } else {
1658 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1659 slot->rst_n_gpio = -EINVAL;
1660 }
1661 }
1662
1663 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
1664 host->mmc->slotno = slotno;
1665 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
1666
1667 if (slot->cd_idx >= 0 &&
1668 mmc_gpiod_request_cd(host->mmc, slot->cd_con_id, slot->cd_idx,
1669 slot->cd_override_level, 0, NULL)) {
1670 dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
1671 slot->cd_idx = -1;
1672 }
1673
1674 ret = sdhci_add_host(host);
1675 if (ret)
1676 goto remove;
1677
1678 sdhci_pci_add_own_cd(slot);
1679
1680 /*
1681 * Check if the chip needs a separate GPIO for card detect to wake up
1682 * from runtime suspend. If it is not there, don't allow runtime PM.
1683 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
1684 */
1685 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
1686 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0)
1687 chip->allow_runtime_pm = false;
1688
1689 return slot;
1690
1691 remove:
1692 if (gpio_is_valid(slot->rst_n_gpio))
1693 gpio_free(slot->rst_n_gpio);
1694
1695 if (chip->fixes && chip->fixes->remove_slot)
1696 chip->fixes->remove_slot(slot, 0);
1697
1698 unmap:
1699 iounmap(host->ioaddr);
1700
1701 release:
1702 pci_release_region(pdev, bar);
1703
1704 cleanup:
1705 if (slot->data && slot->data->cleanup)
1706 slot->data->cleanup(slot->data);
1707
1708 free:
1709 sdhci_free_host(host);
1710
1711 return ERR_PTR(ret);
1712 }
1713
1714 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1715 {
1716 int dead;
1717 u32 scratch;
1718
1719 sdhci_pci_remove_own_cd(slot);
1720
1721 dead = 0;
1722 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1723 if (scratch == (u32)-1)
1724 dead = 1;
1725
1726 sdhci_remove_host(slot->host, dead);
1727
1728 if (gpio_is_valid(slot->rst_n_gpio))
1729 gpio_free(slot->rst_n_gpio);
1730
1731 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1732 slot->chip->fixes->remove_slot(slot, dead);
1733
1734 if (slot->data && slot->data->cleanup)
1735 slot->data->cleanup(slot->data);
1736
1737 pci_release_region(slot->chip->pdev, slot->pci_bar);
1738
1739 sdhci_free_host(slot->host);
1740 }
1741
1742 static void sdhci_pci_runtime_pm_allow(struct device *dev)
1743 {
1744 pm_runtime_put_noidle(dev);
1745 pm_runtime_allow(dev);
1746 pm_runtime_set_autosuspend_delay(dev, 50);
1747 pm_runtime_use_autosuspend(dev);
1748 pm_suspend_ignore_children(dev, 1);
1749 }
1750
1751 static void sdhci_pci_runtime_pm_forbid(struct device *dev)
1752 {
1753 pm_runtime_forbid(dev);
1754 pm_runtime_get_noresume(dev);
1755 }
1756
1757 static int sdhci_pci_probe(struct pci_dev *pdev,
1758 const struct pci_device_id *ent)
1759 {
1760 struct sdhci_pci_chip *chip;
1761 struct sdhci_pci_slot *slot;
1762
1763 u8 slots, first_bar;
1764 int ret, i;
1765
1766 BUG_ON(pdev == NULL);
1767 BUG_ON(ent == NULL);
1768
1769 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
1770 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
1771
1772 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1773 if (ret)
1774 return ret;
1775
1776 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1777 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1778 if (slots == 0)
1779 return -ENODEV;
1780
1781 BUG_ON(slots > MAX_SLOTS);
1782
1783 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1784 if (ret)
1785 return ret;
1786
1787 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1788
1789 if (first_bar > 5) {
1790 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1791 return -ENODEV;
1792 }
1793
1794 ret = pci_enable_device(pdev);
1795 if (ret)
1796 return ret;
1797
1798 chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL);
1799 if (!chip) {
1800 ret = -ENOMEM;
1801 goto err;
1802 }
1803
1804 chip->pdev = pdev;
1805 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
1806 if (chip->fixes) {
1807 chip->quirks = chip->fixes->quirks;
1808 chip->quirks2 = chip->fixes->quirks2;
1809 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
1810 }
1811 chip->num_slots = slots;
1812
1813 pci_set_drvdata(pdev, chip);
1814
1815 if (chip->fixes && chip->fixes->probe) {
1816 ret = chip->fixes->probe(chip);
1817 if (ret)
1818 goto free;
1819 }
1820
1821 slots = chip->num_slots; /* Quirk may have changed this */
1822
1823 for (i = 0; i < slots; i++) {
1824 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
1825 if (IS_ERR(slot)) {
1826 for (i--; i >= 0; i--)
1827 sdhci_pci_remove_slot(chip->slots[i]);
1828 ret = PTR_ERR(slot);
1829 goto free;
1830 }
1831
1832 chip->slots[i] = slot;
1833 }
1834
1835 if (chip->allow_runtime_pm)
1836 sdhci_pci_runtime_pm_allow(&pdev->dev);
1837
1838 return 0;
1839
1840 free:
1841 pci_set_drvdata(pdev, NULL);
1842 kfree(chip);
1843
1844 err:
1845 pci_disable_device(pdev);
1846 return ret;
1847 }
1848
1849 static void sdhci_pci_remove(struct pci_dev *pdev)
1850 {
1851 int i;
1852 struct sdhci_pci_chip *chip;
1853
1854 chip = pci_get_drvdata(pdev);
1855
1856 if (chip) {
1857 if (chip->allow_runtime_pm)
1858 sdhci_pci_runtime_pm_forbid(&pdev->dev);
1859
1860 for (i = 0; i < chip->num_slots; i++)
1861 sdhci_pci_remove_slot(chip->slots[i]);
1862
1863 pci_set_drvdata(pdev, NULL);
1864 kfree(chip);
1865 }
1866
1867 pci_disable_device(pdev);
1868 }
1869
1870 static struct pci_driver sdhci_driver = {
1871 .name = "sdhci-pci",
1872 .id_table = pci_ids,
1873 .probe = sdhci_pci_probe,
1874 .remove = sdhci_pci_remove,
1875 .driver = {
1876 .pm = &sdhci_pci_pm_ops
1877 },
1878 };
1879
1880 module_pci_driver(sdhci_driver);
1881
1882 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
1883 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1884 MODULE_LICENSE("GPL");
CRIS linux kernel tree