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locking/percpu-rwsem: Replace waitqueue with rcuwait
[cris-mirror.git] / include / uapi / drm / amdgpu_drm.h
blob396183628f3c5f9882126e6549af8a1ebc567c27
1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*-
2 *
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Copyright 2014 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
24 * OTHER DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32 #ifndef __AMDGPU_DRM_H__
33 #define __AMDGPU_DRM_H__
34
35 #include "drm.h"
36
37 #if defined(__cplusplus)
38 extern "C" {
39 #endif
40
41 #define DRM_AMDGPU_GEM_CREATE 0x00
42 #define DRM_AMDGPU_GEM_MMAP 0x01
43 #define DRM_AMDGPU_CTX 0x02
44 #define DRM_AMDGPU_BO_LIST 0x03
45 #define DRM_AMDGPU_CS 0x04
46 #define DRM_AMDGPU_INFO 0x05
47 #define DRM_AMDGPU_GEM_METADATA 0x06
48 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07
49 #define DRM_AMDGPU_GEM_VA 0x08
50 #define DRM_AMDGPU_WAIT_CS 0x09
51 #define DRM_AMDGPU_GEM_OP 0x10
52 #define DRM_AMDGPU_GEM_USERPTR 0x11
53 #define DRM_AMDGPU_WAIT_FENCES 0x12
54
55 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
56 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
57 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx)
58 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list)
59 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs)
60 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)
61 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)
62 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)
63 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va)
64 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
65 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
66 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
67 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
68
69 #define AMDGPU_GEM_DOMAIN_CPU 0x1
70 #define AMDGPU_GEM_DOMAIN_GTT 0x2
71 #define AMDGPU_GEM_DOMAIN_VRAM 0x4
72 #define AMDGPU_GEM_DOMAIN_GDS 0x8
73 #define AMDGPU_GEM_DOMAIN_GWS 0x10
74 #define AMDGPU_GEM_DOMAIN_OA 0x20
75
76 /* Flag that CPU access will be required for the case of VRAM domain */
77 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
78 /* Flag that CPU access will not work, this VRAM domain is invisible */
79 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1)
80 /* Flag that USWC attributes should be used for GTT */
81 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2)
82 /* Flag that the memory should be in VRAM and cleared */
83 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3)
84 /* Flag that create shadow bo(GTT) while allocating vram bo */
85 #define AMDGPU_GEM_CREATE_SHADOW (1 << 4)
86 /* Flag that allocating the BO should use linear VRAM */
87 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5)
88
89 struct drm_amdgpu_gem_create_in {
90 /** the requested memory size */
91 __u64 bo_size;
92 /** physical start_addr alignment in bytes for some HW requirements */
93 __u64 alignment;
94 /** the requested memory domains */
95 __u64 domains;
96 /** allocation flags */
97 __u64 domain_flags;
98 };
99
100 struct drm_amdgpu_gem_create_out {
101 /** returned GEM object handle */
102 __u32 handle;
103 __u32 _pad;
104 };
105
106 union drm_amdgpu_gem_create {
107 struct drm_amdgpu_gem_create_in in;
108 struct drm_amdgpu_gem_create_out out;
109 };
110
111 /** Opcode to create new residency list. */
112 #define AMDGPU_BO_LIST_OP_CREATE 0
113 /** Opcode to destroy previously created residency list */
114 #define AMDGPU_BO_LIST_OP_DESTROY 1
115 /** Opcode to update resource information in the list */
116 #define AMDGPU_BO_LIST_OP_UPDATE 2
117
118 struct drm_amdgpu_bo_list_in {
119 /** Type of operation */
120 __u32 operation;
121 /** Handle of list or 0 if we want to create one */
122 __u32 list_handle;
123 /** Number of BOs in list */
124 __u32 bo_number;
125 /** Size of each element describing BO */
126 __u32 bo_info_size;
127 /** Pointer to array describing BOs */
128 __u64 bo_info_ptr;
129 };
130
131 struct drm_amdgpu_bo_list_entry {
132 /** Handle of BO */
133 __u32 bo_handle;
134 /** New (if specified) BO priority to be used during migration */
135 __u32 bo_priority;
136 };
137
138 struct drm_amdgpu_bo_list_out {
139 /** Handle of resource list */
140 __u32 list_handle;
141 __u32 _pad;
142 };
143
144 union drm_amdgpu_bo_list {
145 struct drm_amdgpu_bo_list_in in;
146 struct drm_amdgpu_bo_list_out out;
147 };
148
149 /* context related */
150 #define AMDGPU_CTX_OP_ALLOC_CTX 1
151 #define AMDGPU_CTX_OP_FREE_CTX 2
152 #define AMDGPU_CTX_OP_QUERY_STATE 3
153
154 /* GPU reset status */
155 #define AMDGPU_CTX_NO_RESET 0
156 /* this the context caused it */
157 #define AMDGPU_CTX_GUILTY_RESET 1
158 /* some other context caused it */
159 #define AMDGPU_CTX_INNOCENT_RESET 2
160 /* unknown cause */
161 #define AMDGPU_CTX_UNKNOWN_RESET 3
162
163 struct drm_amdgpu_ctx_in {
164 /** AMDGPU_CTX_OP_* */
165 __u32 op;
166 /** For future use, no flags defined so far */
167 __u32 flags;
168 __u32 ctx_id;
169 __u32 _pad;
170 };
171
172 union drm_amdgpu_ctx_out {
173 struct {
174 __u32 ctx_id;
175 __u32 _pad;
176 } alloc;
177
178 struct {
179 /** For future use, no flags defined so far */
180 __u64 flags;
181 /** Number of resets caused by this context so far. */
182 __u32 hangs;
183 /** Reset status since the last call of the ioctl. */
184 __u32 reset_status;
185 } state;
186 };
187
188 union drm_amdgpu_ctx {
189 struct drm_amdgpu_ctx_in in;
190 union drm_amdgpu_ctx_out out;
191 };
192
193 /*
194 * This is not a reliable API and you should expect it to fail for any
195 * number of reasons and have fallback path that do not use userptr to
196 * perform any operation.
197 */
198 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0)
199 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1)
200 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2)
201 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3)
202
203 struct drm_amdgpu_gem_userptr {
204 __u64 addr;
205 __u64 size;
206 /* AMDGPU_GEM_USERPTR_* */
207 __u32 flags;
208 /* Resulting GEM handle */
209 __u32 handle;
210 };
211
212 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */
213 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0
214 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf
215 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4
216 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f
217 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9
218 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7
219 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12
220 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7
221 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15
222 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3
223 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17
224 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3
225 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19
226 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3
227 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21
228 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3
229
230 #define AMDGPU_TILING_SET(field, value) \
231 (((value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
232 #define AMDGPU_TILING_GET(value, field) \
233 (((value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
234
235 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1
236 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2
237
238 /** The same structure is shared for input/output */
239 struct drm_amdgpu_gem_metadata {
240 /** GEM Object handle */
241 __u32 handle;
242 /** Do we want get or set metadata */
243 __u32 op;
244 struct {
245 /** For future use, no flags defined so far */
246 __u64 flags;
247 /** family specific tiling info */
248 __u64 tiling_info;
249 __u32 data_size_bytes;
250 __u32 data[64];
251 } data;
252 };
253
254 struct drm_amdgpu_gem_mmap_in {
255 /** the GEM object handle */
256 __u32 handle;
257 __u32 _pad;
258 };
259
260 struct drm_amdgpu_gem_mmap_out {
261 /** mmap offset from the vma offset manager */
262 __u64 addr_ptr;
263 };
264
265 union drm_amdgpu_gem_mmap {
266 struct drm_amdgpu_gem_mmap_in in;
267 struct drm_amdgpu_gem_mmap_out out;
268 };
269
270 struct drm_amdgpu_gem_wait_idle_in {
271 /** GEM object handle */
272 __u32 handle;
273 /** For future use, no flags defined so far */
274 __u32 flags;
275 /** Absolute timeout to wait */
276 __u64 timeout;
277 };
278
279 struct drm_amdgpu_gem_wait_idle_out {
280 /** BO status: 0 - BO is idle, 1 - BO is busy */
281 __u32 status;
282 /** Returned current memory domain */
283 __u32 domain;
284 };
285
286 union drm_amdgpu_gem_wait_idle {
287 struct drm_amdgpu_gem_wait_idle_in in;
288 struct drm_amdgpu_gem_wait_idle_out out;
289 };
290
291 struct drm_amdgpu_wait_cs_in {
292 /** Command submission handle */
293 __u64 handle;
294 /** Absolute timeout to wait */
295 __u64 timeout;
296 __u32 ip_type;
297 __u32 ip_instance;
298 __u32 ring;
299 __u32 ctx_id;
300 };
301
302 struct drm_amdgpu_wait_cs_out {
303 /** CS status: 0 - CS completed, 1 - CS still busy */
304 __u64 status;
305 };
306
307 union drm_amdgpu_wait_cs {
308 struct drm_amdgpu_wait_cs_in in;
309 struct drm_amdgpu_wait_cs_out out;
310 };
311
312 struct drm_amdgpu_fence {
313 __u32 ctx_id;
314 __u32 ip_type;
315 __u32 ip_instance;
316 __u32 ring;
317 __u64 seq_no;
318 };
319
320 struct drm_amdgpu_wait_fences_in {
321 /** This points to uint64_t * which points to fences */
322 __u64 fences;
323 __u32 fence_count;
324 __u32 wait_all;
325 __u64 timeout_ns;
326 };
327
328 struct drm_amdgpu_wait_fences_out {
329 __u32 status;
330 __u32 first_signaled;
331 };
332
333 union drm_amdgpu_wait_fences {
334 struct drm_amdgpu_wait_fences_in in;
335 struct drm_amdgpu_wait_fences_out out;
336 };
337
338 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0
339 #define AMDGPU_GEM_OP_SET_PLACEMENT 1
340
341 /* Sets or returns a value associated with a buffer. */
342 struct drm_amdgpu_gem_op {
343 /** GEM object handle */
344 __u32 handle;
345 /** AMDGPU_GEM_OP_* */
346 __u32 op;
347 /** Input or return value */
348 __u64 value;
349 };
350
351 #define AMDGPU_VA_OP_MAP 1
352 #define AMDGPU_VA_OP_UNMAP 2
353
354 /* Delay the page table update till the next CS */
355 #define AMDGPU_VM_DELAY_UPDATE (1 << 0)
356
357 /* Mapping flags */
358 /* readable mapping */
359 #define AMDGPU_VM_PAGE_READABLE (1 << 1)
360 /* writable mapping */
361 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2)
362 /* executable mapping, new for VI */
363 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3)
364
365 struct drm_amdgpu_gem_va {
366 /** GEM object handle */
367 __u32 handle;
368 __u32 _pad;
369 /** AMDGPU_VA_OP_* */
370 __u32 operation;
371 /** AMDGPU_VM_PAGE_* */
372 __u32 flags;
373 /** va address to assign . Must be correctly aligned.*/
374 __u64 va_address;
375 /** Specify offset inside of BO to assign. Must be correctly aligned.*/
376 __u64 offset_in_bo;
377 /** Specify mapping size. Must be correctly aligned. */
378 __u64 map_size;
379 };
380
381 #define AMDGPU_HW_IP_GFX 0
382 #define AMDGPU_HW_IP_COMPUTE 1
383 #define AMDGPU_HW_IP_DMA 2
384 #define AMDGPU_HW_IP_UVD 3
385 #define AMDGPU_HW_IP_VCE 4
386 #define AMDGPU_HW_IP_NUM 5
387
388 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
389
390 #define AMDGPU_CHUNK_ID_IB 0x01
391 #define AMDGPU_CHUNK_ID_FENCE 0x02
392 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03
393
394 struct drm_amdgpu_cs_chunk {
395 __u32 chunk_id;
396 __u32 length_dw;
397 __u64 chunk_data;
398 };
399
400 struct drm_amdgpu_cs_in {
401 /** Rendering context id */
402 __u32 ctx_id;
403 /** Handle of resource list associated with CS */
404 __u32 bo_list_handle;
405 __u32 num_chunks;
406 __u32 _pad;
407 /** this points to __u64 * which point to cs chunks */
408 __u64 chunks;
409 };
410
411 struct drm_amdgpu_cs_out {
412 __u64 handle;
413 };
414
415 union drm_amdgpu_cs {
416 struct drm_amdgpu_cs_in in;
417 struct drm_amdgpu_cs_out out;
418 };
419
420 /* Specify flags to be used for IB */
421
422 /* This IB should be submitted to CE */
423 #define AMDGPU_IB_FLAG_CE (1<<0)
424
425 /* CE Preamble */
426 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1)
427
428 struct drm_amdgpu_cs_chunk_ib {
429 __u32 _pad;
430 /** AMDGPU_IB_FLAG_* */
431 __u32 flags;
432 /** Virtual address to begin IB execution */
433 __u64 va_start;
434 /** Size of submission */
435 __u32 ib_bytes;
436 /** HW IP to submit to */
437 __u32 ip_type;
438 /** HW IP index of the same type to submit to */
439 __u32 ip_instance;
440 /** Ring index to submit to */
441 __u32 ring;
442 };
443
444 struct drm_amdgpu_cs_chunk_dep {
445 __u32 ip_type;
446 __u32 ip_instance;
447 __u32 ring;
448 __u32 ctx_id;
449 __u64 handle;
450 };
451
452 struct drm_amdgpu_cs_chunk_fence {
453 __u32 handle;
454 __u32 offset;
455 };
456
457 struct drm_amdgpu_cs_chunk_data {
458 union {
459 struct drm_amdgpu_cs_chunk_ib ib_data;
460 struct drm_amdgpu_cs_chunk_fence fence_data;
461 };
462 };
463
464 /**
465 * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU
466 *
467 */
468 #define AMDGPU_IDS_FLAGS_FUSION 0x1
469 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2
470
471 /* indicate if acceleration can be working */
472 #define AMDGPU_INFO_ACCEL_WORKING 0x00
473 /* get the crtc_id from the mode object id? */
474 #define AMDGPU_INFO_CRTC_FROM_ID 0x01
475 /* query hw IP info */
476 #define AMDGPU_INFO_HW_IP_INFO 0x02
477 /* query hw IP instance count for the specified type */
478 #define AMDGPU_INFO_HW_IP_COUNT 0x03
479 /* timestamp for GL_ARB_timer_query */
480 #define AMDGPU_INFO_TIMESTAMP 0x05
481 /* Query the firmware version */
482 #define AMDGPU_INFO_FW_VERSION 0x0e
483 /* Subquery id: Query VCE firmware version */
484 #define AMDGPU_INFO_FW_VCE 0x1
485 /* Subquery id: Query UVD firmware version */
486 #define AMDGPU_INFO_FW_UVD 0x2
487 /* Subquery id: Query GMC firmware version */
488 #define AMDGPU_INFO_FW_GMC 0x03
489 /* Subquery id: Query GFX ME firmware version */
490 #define AMDGPU_INFO_FW_GFX_ME 0x04
491 /* Subquery id: Query GFX PFP firmware version */
492 #define AMDGPU_INFO_FW_GFX_PFP 0x05
493 /* Subquery id: Query GFX CE firmware version */
494 #define AMDGPU_INFO_FW_GFX_CE 0x06
495 /* Subquery id: Query GFX RLC firmware version */
496 #define AMDGPU_INFO_FW_GFX_RLC 0x07
497 /* Subquery id: Query GFX MEC firmware version */
498 #define AMDGPU_INFO_FW_GFX_MEC 0x08
499 /* Subquery id: Query SMC firmware version */
500 #define AMDGPU_INFO_FW_SMC 0x0a
501 /* Subquery id: Query SDMA firmware version */
502 #define AMDGPU_INFO_FW_SDMA 0x0b
503 /* number of bytes moved for TTM migration */
504 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
505 /* the used VRAM size */
506 #define AMDGPU_INFO_VRAM_USAGE 0x10
507 /* the used GTT size */
508 #define AMDGPU_INFO_GTT_USAGE 0x11
509 /* Information about GDS, etc. resource configuration */
510 #define AMDGPU_INFO_GDS_CONFIG 0x13
511 /* Query information about VRAM and GTT domains */
512 #define AMDGPU_INFO_VRAM_GTT 0x14
513 /* Query information about register in MMR address space*/
514 #define AMDGPU_INFO_READ_MMR_REG 0x15
515 /* Query information about device: rev id, family, etc. */
516 #define AMDGPU_INFO_DEV_INFO 0x16
517 /* visible vram usage */
518 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17
519 /* number of TTM buffer evictions */
520 #define AMDGPU_INFO_NUM_EVICTIONS 0x18
521 /* Query memory about VRAM and GTT domains */
522 #define AMDGPU_INFO_MEMORY 0x19
523 /* Query vce clock table */
524 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A
525 /* Query vbios related information */
526 #define AMDGPU_INFO_VBIOS 0x1B
527 /* Subquery id: Query vbios size */
528 #define AMDGPU_INFO_VBIOS_SIZE 0x1
529 /* Subquery id: Query vbios image */
530 #define AMDGPU_INFO_VBIOS_IMAGE 0x2
531
532 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
533 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
534 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8
535 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff
536
537 struct drm_amdgpu_query_fw {
538 /** AMDGPU_INFO_FW_* */
539 __u32 fw_type;
540 /**
541 * Index of the IP if there are more IPs of
542 * the same type.
543 */
544 __u32 ip_instance;
545 /**
546 * Index of the engine. Whether this is used depends
547 * on the firmware type. (e.g. MEC, SDMA)
548 */
549 __u32 index;
550 __u32 _pad;
551 };
552
553 /* Input structure for the INFO ioctl */
554 struct drm_amdgpu_info {
555 /* Where the return value will be stored */
556 __u64 return_pointer;
557 /* The size of the return value. Just like "size" in "snprintf",
558 * it limits how many bytes the kernel can write. */
559 __u32 return_size;
560 /* The query request id. */
561 __u32 query;
562
563 union {
564 struct {
565 __u32 id;
566 __u32 _pad;
567 } mode_crtc;
568
569 struct {
570 /** AMDGPU_HW_IP_* */
571 __u32 type;
572 /**
573 * Index of the IP if there are more IPs of the same
574 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT.
575 */
576 __u32 ip_instance;
577 } query_hw_ip;
578
579 struct {
580 __u32 dword_offset;
581 /** number of registers to read */
582 __u32 count;
583 __u32 instance;
584 /** For future use, no flags defined so far */
585 __u32 flags;
586 } read_mmr_reg;
587
588 struct drm_amdgpu_query_fw query_fw;
589
590 struct {
591 __u32 type;
592 __u32 offset;
593 } vbios_info;
594 };
595 };
596
597 struct drm_amdgpu_info_gds {
598 /** GDS GFX partition size */
599 __u32 gds_gfx_partition_size;
600 /** GDS compute partition size */
601 __u32 compute_partition_size;
602 /** total GDS memory size */
603 __u32 gds_total_size;
604 /** GWS size per GFX partition */
605 __u32 gws_per_gfx_partition;
606 /** GSW size per compute partition */
607 __u32 gws_per_compute_partition;
608 /** OA size per GFX partition */
609 __u32 oa_per_gfx_partition;
610 /** OA size per compute partition */
611 __u32 oa_per_compute_partition;
612 __u32 _pad;
613 };
614
615 struct drm_amdgpu_info_vram_gtt {
616 __u64 vram_size;
617 __u64 vram_cpu_accessible_size;
618 __u64 gtt_size;
619 };
620
621 struct drm_amdgpu_heap_info {
622 /** max. physical memory */
623 __u64 total_heap_size;
624
625 /** Theoretical max. available memory in the given heap */
626 __u64 usable_heap_size;
627
628 /**
629 * Number of bytes allocated in the heap. This includes all processes
630 * and private allocations in the kernel. It changes when new buffers
631 * are allocated, freed, and moved. It cannot be larger than
632 * heap_size.
633 */
634 __u64 heap_usage;
635
636 /**
637 * Theoretical possible max. size of buffer which
638 * could be allocated in the given heap
639 */
640 __u64 max_allocation;
641 };
642
643 struct drm_amdgpu_memory_info {
644 struct drm_amdgpu_heap_info vram;
645 struct drm_amdgpu_heap_info cpu_accessible_vram;
646 struct drm_amdgpu_heap_info gtt;
647 };
648
649 struct drm_amdgpu_info_firmware {
650 __u32 ver;
651 __u32 feature;
652 };
653
654 #define AMDGPU_VRAM_TYPE_UNKNOWN 0
655 #define AMDGPU_VRAM_TYPE_GDDR1 1
656 #define AMDGPU_VRAM_TYPE_DDR2 2
657 #define AMDGPU_VRAM_TYPE_GDDR3 3
658 #define AMDGPU_VRAM_TYPE_GDDR4 4
659 #define AMDGPU_VRAM_TYPE_GDDR5 5
660 #define AMDGPU_VRAM_TYPE_HBM 6
661 #define AMDGPU_VRAM_TYPE_DDR3 7
662
663 struct drm_amdgpu_info_device {
664 /** PCI Device ID */
665 __u32 device_id;
666 /** Internal chip revision: A0, A1, etc.) */
667 __u32 chip_rev;
668 __u32 external_rev;
669 /** Revision id in PCI Config space */
670 __u32 pci_rev;
671 __u32 family;
672 __u32 num_shader_engines;
673 __u32 num_shader_arrays_per_engine;
674 /* in KHz */
675 __u32 gpu_counter_freq;
676 __u64 max_engine_clock;
677 __u64 max_memory_clock;
678 /* cu information */
679 __u32 cu_active_number;
680 __u32 cu_ao_mask;
681 __u32 cu_bitmap[4][4];
682 /** Render backend pipe mask. One render backend is CB+DB. */
683 __u32 enabled_rb_pipes_mask;
684 __u32 num_rb_pipes;
685 __u32 num_hw_gfx_contexts;
686 __u32 _pad;
687 __u64 ids_flags;
688 /** Starting virtual address for UMDs. */
689 __u64 virtual_address_offset;
690 /** The maximum virtual address */
691 __u64 virtual_address_max;
692 /** Required alignment of virtual addresses. */
693 __u32 virtual_address_alignment;
694 /** Page table entry - fragment size */
695 __u32 pte_fragment_size;
696 __u32 gart_page_size;
697 /** constant engine ram size*/
698 __u32 ce_ram_size;
699 /** video memory type info*/
700 __u32 vram_type;
701 /** video memory bit width*/
702 __u32 vram_bit_width;
703 /* vce harvesting instance */
704 __u32 vce_harvest_config;
705 };
706
707 struct drm_amdgpu_info_hw_ip {
708 /** Version of h/w IP */
709 __u32 hw_ip_version_major;
710 __u32 hw_ip_version_minor;
711 /** Capabilities */
712 __u64 capabilities_flags;
713 /** command buffer address start alignment*/
714 __u32 ib_start_alignment;
715 /** command buffer size alignment*/
716 __u32 ib_size_alignment;
717 /** Bitmask of available rings. Bit 0 means ring 0, etc. */
718 __u32 available_rings;
719 __u32 _pad;
720 };
721
722 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6
723
724 struct drm_amdgpu_info_vce_clock_table_entry {
725 /** System clock */
726 __u32 sclk;
727 /** Memory clock */
728 __u32 mclk;
729 /** VCE clock */
730 __u32 eclk;
731 __u32 pad;
732 };
733
734 struct drm_amdgpu_info_vce_clock_table {
735 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES];
736 __u32 num_valid_entries;
737 __u32 pad;
738 };
739
740 /*
741 * Supported GPU families
742 */
743 #define AMDGPU_FAMILY_UNKNOWN 0
744 #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */
745 #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */
746 #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */
747 #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */
748 #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */
749
750 #if defined(__cplusplus)
751 }
752 #endif
753
754 #endif
CRIS linux kernel tree