arch/arm/mach-mxs/mach-mxs.c

   1 /*
   2  * Copyright 2012 Freescale Semiconductor, Inc.
   3  * Copyright 2012 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <linux/clk.h>
  14 #include <linux/clk/mxs.h>
  15 #include <linux/clkdev.h>
  16 #include <linux/clocksource.h>
  17 #include <linux/delay.h>
  18 #include <linux/err.h>
  19 #include <linux/gpio.h>
  20 #include <linux/init.h>
  21 #include <linux/irqchip/mxs.h>
  22 #include <linux/reboot.h>
  23 #include <linux/micrel_phy.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/phy.h>
  27 #include <linux/pinctrl/consumer.h>
  28 #include <linux/sys_soc.h>
  29 #include <asm/mach/arch.h>
  30 #include <asm/mach/map.h>
  31 #include <asm/mach/time.h>
  32 #include <asm/system_misc.h>
  33
  34 #include "pm.h"
  35
  36 /* MXS DIGCTL SAIF CLKMUX */
  37 #define MXS_DIGCTL_SAIF_CLKMUX_DIRECT           0x0
  38 #define MXS_DIGCTL_SAIF_CLKMUX_CROSSINPUT       0x1
  39 #define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0         0x2
  40 #define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR1         0x3
  41
  42 #define HW_DIGCTL_CHIPID        0x310
  43 #define HW_DIGCTL_CHIPID_MASK   (0xffff << 16)
  44 #define HW_DIGCTL_REV_MASK      0xff
  45 #define HW_DIGCTL_CHIPID_MX23   (0x3780 << 16)
  46 #define HW_DIGCTL_CHIPID_MX28   (0x2800 << 16)
  47
  48 #define MXS_CHIP_REVISION_1_0   0x10
  49 #define MXS_CHIP_REVISION_1_1   0x11
  50 #define MXS_CHIP_REVISION_1_2   0x12
  51 #define MXS_CHIP_REVISION_1_3   0x13
  52 #define MXS_CHIP_REVISION_1_4   0x14
  53 #define MXS_CHIP_REV_UNKNOWN    0xff
  54
  55 #define MXS_GPIO_NR(bank, nr)   ((bank) * 32 + (nr))
  56
  57 #define MXS_SET_ADDR            0x4
  58 #define MXS_CLR_ADDR            0x8
  59 #define MXS_TOG_ADDR            0xc
  60
  61 static u32 chipid;
  62 static u32 socid;
  63
  64 static inline void __mxs_setl(u32 mask, void __iomem *reg)
  65 {
  66         __raw_writel(mask, reg + MXS_SET_ADDR);
  67 }
  68
  69 static inline void __mxs_clrl(u32 mask, void __iomem *reg)
  70 {
  71         __raw_writel(mask, reg + MXS_CLR_ADDR);
  72 }
  73
  74 static inline void __mxs_togl(u32 mask, void __iomem *reg)
  75 {
  76         __raw_writel(mask, reg + MXS_TOG_ADDR);
  77 }
  78
  79 #define OCOTP_WORD_OFFSET               0x20
  80 #define OCOTP_WORD_COUNT                0x20
  81
  82 #define BM_OCOTP_CTRL_BUSY              (1 << 8)
  83 #define BM_OCOTP_CTRL_ERROR             (1 << 9)
  84 #define BM_OCOTP_CTRL_RD_BANK_OPEN      (1 << 12)
  85
  86 static DEFINE_MUTEX(ocotp_mutex);
  87 static u32 ocotp_words[OCOTP_WORD_COUNT];
  88
  89 static const u32 *mxs_get_ocotp(void)
  90 {
  91         struct device_node *np;
  92         void __iomem *ocotp_base;
  93         int timeout = 0x400;
  94         size_t i;
  95         static int once;
  96
  97         if (once)
  98                 return ocotp_words;
  99
 100         np = of_find_compatible_node(NULL, NULL, "fsl,ocotp");
 101         ocotp_base = of_iomap(np, 0);
 102         WARN_ON(!ocotp_base);
 103
 104         mutex_lock(&ocotp_mutex);
 105
 106         /*
 107          * clk_enable(hbus_clk) for ocotp can be skipped
 108          * as it must be on when system is running.
 109          */
 110
 111         /* try to clear ERROR bit */
 112         __mxs_clrl(BM_OCOTP_CTRL_ERROR, ocotp_base);
 113
 114         /* check both BUSY and ERROR cleared */
 115         while ((__raw_readl(ocotp_base) &
 116                 (BM_OCOTP_CTRL_BUSY | BM_OCOTP_CTRL_ERROR)) && --timeout)
 117                 cpu_relax();
 118
 119         if (unlikely(!timeout))
 120                 goto error_unlock;
 121
 122         /* open OCOTP banks for read */
 123         __mxs_setl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base);
 124
 125         /* approximately wait 32 hclk cycles */
 126         udelay(1);
 127
 128         /* poll BUSY bit becoming cleared */
 129         timeout = 0x400;
 130         while ((__raw_readl(ocotp_base) & BM_OCOTP_CTRL_BUSY) && --timeout)
 131                 cpu_relax();
 132
 133         if (unlikely(!timeout))
 134                 goto error_unlock;
 135
 136         for (i = 0; i < OCOTP_WORD_COUNT; i++)
 137                 ocotp_words[i] = __raw_readl(ocotp_base + OCOTP_WORD_OFFSET +
 138                                                 i * 0x10);
 139
 140         /* close banks for power saving */
 141         __mxs_clrl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base);
 142
 143         once = 1;
 144
 145         mutex_unlock(&ocotp_mutex);
 146
 147         return ocotp_words;
 148
 149 error_unlock:
 150         mutex_unlock(&ocotp_mutex);
 151         pr_err("%s: timeout in reading OCOTP\n", __func__);
 152         return NULL;
 153 }
 154
 155 enum mac_oui {
 156         OUI_FSL,
 157         OUI_DENX,
 158         OUI_CRYSTALFONTZ,
 159 };
 160
 161 static void __init update_fec_mac_prop(enum mac_oui oui)
 162 {
 163         struct device_node *np, *from = NULL;
 164         struct property *newmac;
 165         const u32 *ocotp = mxs_get_ocotp();
 166         u8 *macaddr;
 167         u32 val;
 168         int i;
 169
 170         for (i = 0; i < 2; i++) {
 171                 np = of_find_compatible_node(from, NULL, "fsl,imx28-fec");
 172                 if (!np)
 173                         return;
 174
 175                 from = np;
 176
 177                 if (of_get_property(np, "local-mac-address", NULL))
 178                         continue;
 179
 180                 newmac = kzalloc(sizeof(*newmac) + 6, GFP_KERNEL);
 181                 if (!newmac)
 182                         return;
 183                 newmac->value = newmac + 1;
 184                 newmac->length = 6;
 185
 186                 newmac->name = kstrdup("local-mac-address", GFP_KERNEL);
 187                 if (!newmac->name) {
 188                         kfree(newmac);
 189                         return;
 190                 }
 191
 192                 /*
 193                  * OCOTP only stores the last 4 octets for each mac address,
 194                  * so hard-code OUI here.
 195                  */
 196                 macaddr = newmac->value;
 197                 switch (oui) {
 198                 case OUI_FSL:
 199                         macaddr[0] = 0x00;
 200                         macaddr[1] = 0x04;
 201                         macaddr[2] = 0x9f;
 202                         break;
 203                 case OUI_DENX:
 204                         macaddr[0] = 0xc0;
 205                         macaddr[1] = 0xe5;
 206                         macaddr[2] = 0x4e;
 207                         break;
 208                 case OUI_CRYSTALFONTZ:
 209                         macaddr[0] = 0x58;
 210                         macaddr[1] = 0xb9;
 211                         macaddr[2] = 0xe1;
 212                         break;
 213                 }
 214                 val = ocotp[i];
 215                 macaddr[3] = (val >> 16) & 0xff;
 216                 macaddr[4] = (val >> 8) & 0xff;
 217                 macaddr[5] = (val >> 0) & 0xff;
 218
 219                 of_update_property(np, newmac);
 220         }
 221 }
 222
 223 static inline void enable_clk_enet_out(void)
 224 {
 225         struct clk *clk = clk_get_sys("enet_out", NULL);
 226
 227         if (!IS_ERR(clk))
 228                 clk_prepare_enable(clk);
 229 }
 230
 231 static void __init imx28_evk_init(void)
 232 {
 233         update_fec_mac_prop(OUI_FSL);
 234
 235         mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0);
 236 }
 237
 238 static int apx4devkit_phy_fixup(struct phy_device *phy)
 239 {
 240         phy->dev_flags |= MICREL_PHY_50MHZ_CLK;
 241         return 0;
 242 }
 243
 244 static void __init apx4devkit_init(void)
 245 {
 246         enable_clk_enet_out();
 247
 248         if (IS_BUILTIN(CONFIG_PHYLIB))
 249                 phy_register_fixup_for_uid(PHY_ID_KSZ8051, MICREL_PHY_ID_MASK,
 250                                            apx4devkit_phy_fixup);
 251 }
 252
 253 #define ENET0_MDC__GPIO_4_0     MXS_GPIO_NR(4, 0)
 254 #define ENET0_MDIO__GPIO_4_1    MXS_GPIO_NR(4, 1)
 255 #define ENET0_RX_EN__GPIO_4_2   MXS_GPIO_NR(4, 2)
 256 #define ENET0_RXD0__GPIO_4_3    MXS_GPIO_NR(4, 3)
 257 #define ENET0_RXD1__GPIO_4_4    MXS_GPIO_NR(4, 4)
 258 #define ENET0_TX_EN__GPIO_4_6   MXS_GPIO_NR(4, 6)
 259 #define ENET0_TXD0__GPIO_4_7    MXS_GPIO_NR(4, 7)
 260 #define ENET0_TXD1__GPIO_4_8    MXS_GPIO_NR(4, 8)
 261 #define ENET_CLK__GPIO_4_16     MXS_GPIO_NR(4, 16)
 262
 263 #define TX28_FEC_PHY_POWER      MXS_GPIO_NR(3, 29)
 264 #define TX28_FEC_PHY_RESET      MXS_GPIO_NR(4, 13)
 265 #define TX28_FEC_nINT           MXS_GPIO_NR(4, 5)
 266
 267 static const struct gpio tx28_gpios[] __initconst = {
 268         { ENET0_MDC__GPIO_4_0, GPIOF_OUT_INIT_LOW, "GPIO_4_0" },
 269         { ENET0_MDIO__GPIO_4_1, GPIOF_OUT_INIT_LOW, "GPIO_4_1" },
 270         { ENET0_RX_EN__GPIO_4_2, GPIOF_OUT_INIT_LOW, "GPIO_4_2" },
 271         { ENET0_RXD0__GPIO_4_3, GPIOF_OUT_INIT_LOW, "GPIO_4_3" },
 272         { ENET0_RXD1__GPIO_4_4, GPIOF_OUT_INIT_LOW, "GPIO_4_4" },
 273         { ENET0_TX_EN__GPIO_4_6, GPIOF_OUT_INIT_LOW, "GPIO_4_6" },
 274         { ENET0_TXD0__GPIO_4_7, GPIOF_OUT_INIT_LOW, "GPIO_4_7" },
 275         { ENET0_TXD1__GPIO_4_8, GPIOF_OUT_INIT_LOW, "GPIO_4_8" },
 276         { ENET_CLK__GPIO_4_16, GPIOF_OUT_INIT_LOW, "GPIO_4_16" },
 277         { TX28_FEC_PHY_POWER, GPIOF_OUT_INIT_LOW, "fec-phy-power" },
 278         { TX28_FEC_PHY_RESET, GPIOF_OUT_INIT_LOW, "fec-phy-reset" },
 279         { TX28_FEC_nINT, GPIOF_DIR_IN, "fec-int" },
 280 };
 281
 282 static void __init tx28_post_init(void)
 283 {
 284         struct device_node *np;
 285         struct platform_device *pdev;
 286         struct pinctrl *pctl;
 287         int ret;
 288
 289         enable_clk_enet_out();
 290
 291         np = of_find_compatible_node(NULL, NULL, "fsl,imx28-fec");
 292         pdev = of_find_device_by_node(np);
 293         if (!pdev) {
 294                 pr_err("%s: failed to find fec device\n", __func__);
 295                 return;
 296         }
 297
 298         pctl = pinctrl_get_select(&pdev->dev, "gpio_mode");
 299         if (IS_ERR(pctl)) {
 300                 pr_err("%s: failed to get pinctrl state\n", __func__);
 301                 return;
 302         }
 303
 304         ret = gpio_request_array(tx28_gpios, ARRAY_SIZE(tx28_gpios));
 305         if (ret) {
 306                 pr_err("%s: failed to request gpios: %d\n", __func__, ret);
 307                 return;
 308         }
 309
 310         /* Power up fec phy */
 311         gpio_set_value(TX28_FEC_PHY_POWER, 1);
 312         msleep(26); /* 25ms according to data sheet */
 313
 314         /* Mode strap pins */
 315         gpio_set_value(ENET0_RX_EN__GPIO_4_2, 1);
 316         gpio_set_value(ENET0_RXD0__GPIO_4_3, 1);
 317         gpio_set_value(ENET0_RXD1__GPIO_4_4, 1);
 318
 319         udelay(100); /* minimum assertion time for nRST */
 320
 321         /* Deasserting FEC PHY RESET */
 322         gpio_set_value(TX28_FEC_PHY_RESET, 1);
 323
 324         pinctrl_put(pctl);
 325 }
 326
 327 static void __init crystalfontz_init(void)
 328 {
 329         update_fec_mac_prop(OUI_CRYSTALFONTZ);
 330 }
 331
 332 static const char __init *mxs_get_soc_id(void)
 333 {
 334         struct device_node *np;
 335         void __iomem *digctl_base;
 336
 337         np = of_find_compatible_node(NULL, NULL, "fsl,imx23-digctl");
 338         digctl_base = of_iomap(np, 0);
 339         WARN_ON(!digctl_base);
 340
 341         chipid = readl(digctl_base + HW_DIGCTL_CHIPID);
 342         socid = chipid & HW_DIGCTL_CHIPID_MASK;
 343
 344         iounmap(digctl_base);
 345         of_node_put(np);
 346
 347         switch (socid) {
 348         case HW_DIGCTL_CHIPID_MX23:
 349                 return "i.MX23";
 350         case HW_DIGCTL_CHIPID_MX28:
 351                 return "i.MX28";
 352         default:
 353                 return "Unknown";
 354         }
 355 }
 356
 357 static u32 __init mxs_get_cpu_rev(void)
 358 {
 359         u32 rev = chipid & HW_DIGCTL_REV_MASK;
 360
 361         switch (socid) {
 362         case HW_DIGCTL_CHIPID_MX23:
 363                 switch (rev) {
 364                 case 0x0:
 365                         return MXS_CHIP_REVISION_1_0;
 366                 case 0x1:
 367                         return MXS_CHIP_REVISION_1_1;
 368                 case 0x2:
 369                         return MXS_CHIP_REVISION_1_2;
 370                 case 0x3:
 371                         return MXS_CHIP_REVISION_1_3;
 372                 case 0x4:
 373                         return MXS_CHIP_REVISION_1_4;
 374                 default:
 375                         return MXS_CHIP_REV_UNKNOWN;
 376                 }
 377         case HW_DIGCTL_CHIPID_MX28:
 378                 switch (rev) {
 379                 case 0x0:
 380                         return MXS_CHIP_REVISION_1_1;
 381                 case 0x1:
 382                         return MXS_CHIP_REVISION_1_2;
 383                 default:
 384                         return MXS_CHIP_REV_UNKNOWN;
 385                 }
 386         default:
 387                 return MXS_CHIP_REV_UNKNOWN;
 388         }
 389 }
 390
 391 static const char __init *mxs_get_revision(void)
 392 {
 393         u32 rev = mxs_get_cpu_rev();
 394
 395         if (rev != MXS_CHIP_REV_UNKNOWN)
 396                 return kasprintf(GFP_KERNEL, "TO%d.%d", (rev >> 4) & 0xf,
 397                                 rev & 0xf);
 398         else
 399                 return kasprintf(GFP_KERNEL, "%s", "Unknown");
 400 }
 401
 402 static void __init mxs_machine_init(void)
 403 {
 404         struct device_node *root;
 405         struct device *parent;
 406         struct soc_device *soc_dev;
 407         struct soc_device_attribute *soc_dev_attr;
 408         int ret;
 409
 410         soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
 411         if (!soc_dev_attr)
 412                 return;
 413
 414         root = of_find_node_by_path("/");
 415         ret = of_property_read_string(root, "model", &soc_dev_attr->machine);
 416         if (ret)
 417                 return;
 418
 419         soc_dev_attr->family = "Freescale MXS Family";
 420         soc_dev_attr->soc_id = mxs_get_soc_id();
 421         soc_dev_attr->revision = mxs_get_revision();
 422
 423         soc_dev = soc_device_register(soc_dev_attr);
 424         if (IS_ERR(soc_dev)) {
 425                 kfree(soc_dev_attr->revision);
 426                 kfree(soc_dev_attr);
 427                 return;
 428         }
 429
 430         parent = soc_device_to_device(soc_dev);
 431
 432         if (of_machine_is_compatible("fsl,imx28-evk"))
 433                 imx28_evk_init();
 434         else if (of_machine_is_compatible("bluegiga,apx4devkit"))
 435                 apx4devkit_init();
 436         else if (of_machine_is_compatible("crystalfontz,cfa10037") ||
 437                  of_machine_is_compatible("crystalfontz,cfa10049") ||
 438                  of_machine_is_compatible("crystalfontz,cfa10055") ||
 439                  of_machine_is_compatible("crystalfontz,cfa10057"))
 440                 crystalfontz_init();
 441
 442         of_platform_populate(NULL, of_default_bus_match_table,
 443                              NULL, parent);
 444
 445         if (of_machine_is_compatible("karo,tx28"))
 446                 tx28_post_init();
 447 }
 448
 449 #define MX23_CLKCTRL_RESET_OFFSET       0x120
 450 #define MX28_CLKCTRL_RESET_OFFSET       0x1e0
 451 #define MXS_CLKCTRL_RESET_CHIP          (1 << 1)
 452
 453 /*
 454  * Reset the system. It is called by machine_restart().
 455  */
 456 static void mxs_restart(enum reboot_mode mode, const char *cmd)
 457 {
 458         struct device_node *np;
 459         void __iomem *reset_addr;
 460
 461         np = of_find_compatible_node(NULL, NULL, "fsl,clkctrl");
 462         reset_addr = of_iomap(np, 0);
 463         if (!reset_addr)
 464                 goto soft;
 465
 466         if (of_device_is_compatible(np, "fsl,imx23-clkctrl"))
 467                 reset_addr += MX23_CLKCTRL_RESET_OFFSET;
 468         else
 469                 reset_addr += MX28_CLKCTRL_RESET_OFFSET;
 470
 471         /* reset the chip */
 472         __mxs_setl(MXS_CLKCTRL_RESET_CHIP, reset_addr);
 473
 474         pr_err("Failed to assert the chip reset\n");
 475
 476         /* Delay to allow the serial port to show the message */
 477         mdelay(50);
 478
 479 soft:
 480         /* We'll take a jump through zero as a poor second */
 481         soft_restart(0);
 482 }
 483
 484 static void __init mxs_timer_init(void)
 485 {
 486         if (of_machine_is_compatible("fsl,imx23"))
 487                 mx23_clocks_init();
 488         else
 489                 mx28_clocks_init();
 490         clocksource_of_init();
 491 }
 492
 493 static const char *mxs_dt_compat[] __initdata = {
 494         "fsl,imx28",
 495         "fsl,imx23",
 496         NULL,
 497 };
 498
 499 DT_MACHINE_START(MXS, "Freescale MXS (Device Tree)")
 500         .handle_irq     = icoll_handle_irq,
 501         .init_time      = mxs_timer_init,
 502         .init_machine   = mxs_machine_init,
 503         .init_late      = mxs_pm_init,
 504         .dt_compat      = mxs_dt_compat,
 505         .restart        = mxs_restart,
 506 MACHINE_END