2 * OMAP4 specific common source file.
4 * Copyright (C) 2010 Texas Instruments, Inc.
6 * Santosh Shilimkar <santosh.shilimkar@ti.com>
9 * This program is free software,you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/init.h>
17 #include <linux/irq.h>
18 #include <linux/irqchip.h>
19 #include <linux/platform_device.h>
20 #include <linux/memblock.h>
21 #include <linux/of_irq.h>
22 #include <linux/of_platform.h>
23 #include <linux/export.h>
24 #include <linux/irqchip/arm-gic.h>
25 #include <linux/of_address.h>
26 #include <linux/reboot.h>
28 #include <asm/hardware/cache-l2x0.h>
29 #include <asm/mach/map.h>
30 #include <asm/memblock.h>
31 #include <asm/smp_twd.h>
33 #include "omap-wakeupgen.h"
39 #include "prminst44xx.h"
40 #include "prcm_mpu44xx.h"
41 #include "omap4-sar-layout.h"
42 #include "omap-secure.h"
45 #ifdef CONFIG_CACHE_L2X0
46 static void __iomem
*l2cache_base
;
49 static void __iomem
*sar_ram_base
;
50 static void __iomem
*gic_dist_base_addr
;
51 static void __iomem
*twd_base
;
53 #define IRQ_LOCALTIMER 29
55 #ifdef CONFIG_OMAP4_ERRATA_I688
56 /* Used to implement memory barrier on DRAM path */
57 #define OMAP4_DRAM_BARRIER_VA 0xfe600000
59 void __iomem
*dram_sync
, *sram_sync
;
61 static phys_addr_t paddr
;
64 void omap_bus_sync(void)
66 if (dram_sync
&& sram_sync
) {
67 writel_relaxed(readl_relaxed(dram_sync
), dram_sync
);
68 writel_relaxed(readl_relaxed(sram_sync
), sram_sync
);
72 EXPORT_SYMBOL(omap_bus_sync
);
74 /* Steal one page physical memory for barrier implementation */
75 int __init
omap_barrier_reserve_memblock(void)
78 size
= ALIGN(PAGE_SIZE
, SZ_1M
);
79 paddr
= arm_memblock_steal(size
, SZ_1M
);
84 void __init
omap_barriers_init(void)
86 struct map_desc dram_io_desc
[1];
88 dram_io_desc
[0].virtual = OMAP4_DRAM_BARRIER_VA
;
89 dram_io_desc
[0].pfn
= __phys_to_pfn(paddr
);
90 dram_io_desc
[0].length
= size
;
91 dram_io_desc
[0].type
= MT_MEMORY_SO
;
92 iotable_init(dram_io_desc
, ARRAY_SIZE(dram_io_desc
));
93 dram_sync
= (void __iomem
*) dram_io_desc
[0].virtual;
94 sram_sync
= (void __iomem
*) OMAP4_SRAM_VA
;
96 pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
97 (long long) paddr
, dram_io_desc
[0].virtual);
101 void __init
omap_barriers_init(void)
105 void __init
gic_init_irq(void)
107 void __iomem
*omap_irq_base
;
109 /* Static mapping, never released */
110 gic_dist_base_addr
= ioremap(OMAP44XX_GIC_DIST_BASE
, SZ_4K
);
111 BUG_ON(!gic_dist_base_addr
);
113 twd_base
= ioremap(OMAP44XX_LOCAL_TWD_BASE
, SZ_4K
);
116 /* Static mapping, never released */
117 omap_irq_base
= ioremap(OMAP44XX_GIC_CPU_BASE
, SZ_512
);
118 BUG_ON(!omap_irq_base
);
120 omap_wakeupgen_init();
122 gic_init(0, 29, gic_dist_base_addr
, omap_irq_base
);
125 void gic_dist_disable(void)
127 if (gic_dist_base_addr
)
128 __raw_writel(0x0, gic_dist_base_addr
+ GIC_DIST_CTRL
);
131 bool gic_dist_disabled(void)
133 return !(__raw_readl(gic_dist_base_addr
+ GIC_DIST_CTRL
) & 0x1);
136 void gic_timer_retrigger(void)
138 u32 twd_int
= __raw_readl(twd_base
+ TWD_TIMER_INTSTAT
);
139 u32 gic_int
= __raw_readl(gic_dist_base_addr
+ GIC_DIST_PENDING_SET
);
140 u32 twd_ctrl
= __raw_readl(twd_base
+ TWD_TIMER_CONTROL
);
142 if (twd_int
&& !(gic_int
& BIT(IRQ_LOCALTIMER
))) {
144 * The local timer interrupt got lost while the distributor was
145 * disabled. Ack the pending interrupt, and retrigger it.
147 pr_warn("%s: lost localtimer interrupt\n", __func__
);
148 __raw_writel(1, twd_base
+ TWD_TIMER_INTSTAT
);
149 if (!(twd_ctrl
& TWD_TIMER_CONTROL_PERIODIC
)) {
150 __raw_writel(1, twd_base
+ TWD_TIMER_COUNTER
);
151 twd_ctrl
|= TWD_TIMER_CONTROL_ENABLE
;
152 __raw_writel(twd_ctrl
, twd_base
+ TWD_TIMER_CONTROL
);
157 #ifdef CONFIG_CACHE_L2X0
159 void __iomem
*omap4_get_l2cache_base(void)
164 static void omap4_l2x0_disable(void)
166 /* Disable PL310 L2 Cache controller */
167 omap_smc1(0x102, 0x0);
170 static void omap4_l2x0_set_debug(unsigned long val
)
172 /* Program PL310 L2 Cache controller debug register */
173 omap_smc1(0x100, val
);
176 static int __init
omap_l2_cache_init(void)
181 * To avoid code running on other OMAPs in
184 if (!cpu_is_omap44xx())
187 /* Static mapping, never released */
188 l2cache_base
= ioremap(OMAP44XX_L2CACHE_BASE
, SZ_4K
);
189 if (WARN_ON(!l2cache_base
))
193 * 16-way associativity, parity disabled
194 * Way size - 32KB (es1.0)
195 * Way size - 64KB (es2.0 +)
197 aux_ctrl
= ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT
) |
199 (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT
) |
200 (0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT
));
202 if (omap_rev() == OMAP4430_REV_ES1_0
) {
203 aux_ctrl
|= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT
;
205 aux_ctrl
|= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT
) |
206 (1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT
) |
207 (1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT
) |
208 (1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT
) |
209 (1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT
));
211 if (omap_rev() != OMAP4430_REV_ES1_0
)
212 omap_smc1(0x109, aux_ctrl
);
214 /* Enable PL310 L2 Cache controller */
215 omap_smc1(0x102, 0x1);
217 if (of_have_populated_dt())
218 l2x0_of_init(aux_ctrl
, L2X0_AUX_CTRL_MASK
);
220 l2x0_init(l2cache_base
, aux_ctrl
, L2X0_AUX_CTRL_MASK
);
223 * Override default outer_cache.disable with a OMAP4
226 outer_cache
.disable
= omap4_l2x0_disable
;
227 outer_cache
.set_debug
= omap4_l2x0_set_debug
;
231 omap_early_initcall(omap_l2_cache_init
);
234 void __iomem
*omap4_get_sar_ram_base(void)
240 * SAR RAM used to save and restore the HW
241 * context in low power modes
243 static int __init
omap4_sar_ram_init(void)
245 unsigned long sar_base
;
248 * To avoid code running on other OMAPs in
251 if (cpu_is_omap44xx())
252 sar_base
= OMAP44XX_SAR_RAM_BASE
;
253 else if (soc_is_omap54xx())
254 sar_base
= OMAP54XX_SAR_RAM_BASE
;
258 /* Static mapping, never released */
259 sar_ram_base
= ioremap(sar_base
, SZ_16K
);
260 if (WARN_ON(!sar_ram_base
))
265 omap_early_initcall(omap4_sar_ram_init
);
267 void __init
omap_gic_of_init(void)
269 struct device_node
*np
;
271 /* Extract GIC distributor and TWD bases for OMAP4460 ROM Errata WA */
272 if (!cpu_is_omap446x())
273 goto skip_errata_init
;
275 np
= of_find_compatible_node(NULL
, NULL
, "arm,cortex-a9-gic");
276 gic_dist_base_addr
= of_iomap(np
, 0);
277 WARN_ON(!gic_dist_base_addr
);
279 np
= of_find_compatible_node(NULL
, NULL
, "arm,cortex-a9-twd-timer");
280 twd_base
= of_iomap(np
, 0);
284 omap_wakeupgen_init();
288 #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
289 static int omap4_twl6030_hsmmc_late_init(struct device
*dev
)
292 struct platform_device
*pdev
= container_of(dev
,
293 struct platform_device
, dev
);
294 struct omap_mmc_platform_data
*pdata
= dev
->platform_data
;
296 /* Setting MMC1 Card detect Irq */
298 irq
= twl6030_mmc_card_detect_config();
300 dev_err(dev
, "%s: Error card detect config(%d)\n",
304 pdata
->slots
[0].card_detect_irq
= irq
;
305 pdata
->slots
[0].card_detect
= twl6030_mmc_card_detect
;
310 static __init
void omap4_twl6030_hsmmc_set_late_init(struct device
*dev
)
312 struct omap_mmc_platform_data
*pdata
;
314 /* dev can be null if CONFIG_MMC_OMAP_HS is not set */
316 pr_err("Failed %s\n", __func__
);
319 pdata
= dev
->platform_data
;
320 pdata
->init
= omap4_twl6030_hsmmc_late_init
;
323 int __init
omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info
*controllers
)
325 struct omap2_hsmmc_info
*c
;
327 omap_hsmmc_init(controllers
);
328 for (c
= controllers
; c
->mmc
; c
++) {
329 /* pdev can be null if CONFIG_MMC_OMAP_HS is not set */
332 omap4_twl6030_hsmmc_set_late_init(&c
->pdev
->dev
);
338 int __init
omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info
*controllers
)