Linux 3.11-rc3
[cris-mirror.git] / arch / arm / plat-omap / counter_32k.c
blobd9bc98eb2a6b6b80559faa096f47cda066060e00
1 /*
2 * OMAP 32ksynctimer/counter_32k-related code
4 * Copyright (C) 2009 Texas Instruments
5 * Copyright (C) 2010 Nokia Corporation
6 * Tony Lindgren <tony@atomide.com>
7 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * NOTE: This timer is not the same timer as the old OMAP1 MPU timer.
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/clk.h>
18 #include <linux/err.h>
19 #include <linux/io.h>
20 #include <linux/clocksource.h>
21 #include <linux/sched_clock.h>
23 #include <asm/mach/time.h>
25 #include <plat/counter-32k.h>
27 /* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */
28 #define OMAP2_32KSYNCNT_REV_OFF 0x0
29 #define OMAP2_32KSYNCNT_REV_SCHEME (0x3 << 30)
30 #define OMAP2_32KSYNCNT_CR_OFF_LOW 0x10
31 #define OMAP2_32KSYNCNT_CR_OFF_HIGH 0x30
34 * 32KHz clocksource ... always available, on pretty most chips except
35 * OMAP 730 and 1510. Other timers could be used as clocksources, with
36 * higher resolution in free-running counter modes (e.g. 12 MHz xtal),
37 * but systems won't necessarily want to spend resources that way.
39 static void __iomem *sync32k_cnt_reg;
41 static u32 notrace omap_32k_read_sched_clock(void)
43 return sync32k_cnt_reg ? __raw_readl(sync32k_cnt_reg) : 0;
46 /**
47 * omap_read_persistent_clock - Return time from a persistent clock.
49 * Reads the time from a source which isn't disabled during PM, the
50 * 32k sync timer. Convert the cycles elapsed since last read into
51 * nsecs and adds to a monotonically increasing timespec.
53 static struct timespec persistent_ts;
54 static cycles_t cycles;
55 static unsigned int persistent_mult, persistent_shift;
56 static DEFINE_SPINLOCK(read_persistent_clock_lock);
58 static void omap_read_persistent_clock(struct timespec *ts)
60 unsigned long long nsecs;
61 cycles_t last_cycles;
62 unsigned long flags;
64 spin_lock_irqsave(&read_persistent_clock_lock, flags);
66 last_cycles = cycles;
67 cycles = sync32k_cnt_reg ? __raw_readl(sync32k_cnt_reg) : 0;
69 nsecs = clocksource_cyc2ns(cycles - last_cycles,
70 persistent_mult, persistent_shift);
72 timespec_add_ns(&persistent_ts, nsecs);
74 *ts = persistent_ts;
76 spin_unlock_irqrestore(&read_persistent_clock_lock, flags);
79 /**
80 * omap_init_clocksource_32k - setup and register counter 32k as a
81 * kernel clocksource
82 * @pbase: base addr of counter_32k module
83 * @size: size of counter_32k to map
85 * Returns 0 upon success or negative error code upon failure.
88 int __init omap_init_clocksource_32k(void __iomem *vbase)
90 int ret;
93 * 32k sync Counter IP register offsets vary between the
94 * highlander version and the legacy ones.
95 * The 'SCHEME' bits(30-31) of the revision register is used
96 * to identify the version.
98 if (__raw_readl(vbase + OMAP2_32KSYNCNT_REV_OFF) &
99 OMAP2_32KSYNCNT_REV_SCHEME)
100 sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_HIGH;
101 else
102 sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_LOW;
105 * 120000 rough estimate from the calculations in
106 * __clocksource_updatefreq_scale.
108 clocks_calc_mult_shift(&persistent_mult, &persistent_shift,
109 32768, NSEC_PER_SEC, 120000);
111 ret = clocksource_mmio_init(sync32k_cnt_reg, "32k_counter", 32768,
112 250, 32, clocksource_mmio_readl_up);
113 if (ret) {
114 pr_err("32k_counter: can't register clocksource\n");
115 return ret;
118 setup_sched_clock(omap_32k_read_sched_clock, 32, 32768);
119 register_persistent_clock(NULL, omap_read_persistent_clock);
120 pr_info("OMAP clocksource: 32k_counter at 32768 Hz\n");
122 return 0;