arch/mn10300/include/asm/timer-regs.h

   1 /* AM33v2 on-board timer module registers
   2  *
   3  * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
   4  * Written by David Howells (dhowells@redhat.com)
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public Licence
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the Licence, or (at your option) any later version.
  10  */
  11
  12 #ifndef _ASM_TIMER_REGS_H
  13 #define _ASM_TIMER_REGS_H
  14
  15 #include <asm/cpu-regs.h>
  16 #include <asm/intctl-regs.h>
  17
  18 #ifdef __KERNEL__
  19
  20 /*
  21  * Timer prescalar control
  22  */
  23 #define TMPSCNT                 __SYSREG(0xd4003071, u8) /* timer prescaler control */
  24 #define TMPSCNT_ENABLE          0x80    /* timer prescaler enable */
  25 #define TMPSCNT_DISABLE         0x00    /* timer prescaler disable */
  26
  27 /*
  28  * 8-bit timers
  29  */
  30 #define TM0MD                   __SYSREG(0xd4003000, u8) /* timer 0 mode register */
  31 #define TM0MD_SRC               0x07    /* timer source */
  32 #define TM0MD_SRC_IOCLK         0x00    /* - IOCLK */
  33 #define TM0MD_SRC_IOCLK_8       0x01    /* - 1/8 IOCLK */
  34 #define TM0MD_SRC_IOCLK_32      0x02    /* - 1/32 IOCLK */
  35 #define TM0MD_SRC_TM1UFLOW      0x05    /* - timer 1 underflow */
  36 #define TM0MD_SRC_TM2UFLOW      0x06    /* - timer 2 underflow */
  37 #if     defined(CONFIG_AM33_2)
  38 #define TM0MD_SRC_TM2IO         0x03    /* - TM2IO pin input */
  39 #define TM0MD_SRC_TM0IO         0x07    /* - TM0IO pin input */
  40 #endif /* CONFIG_AM33_2 */
  41 #define TM0MD_INIT_COUNTER      0x40    /* initialize TMnBC = TMnBR */
  42 #define TM0MD_COUNT_ENABLE      0x80    /* timer count enable */
  43
  44 #define TM1MD                   __SYSREG(0xd4003001, u8) /* timer 1 mode register */
  45 #define TM1MD_SRC               0x07    /* timer source */
  46 #define TM1MD_SRC_IOCLK         0x00    /* - IOCLK */
  47 #define TM1MD_SRC_IOCLK_8       0x01    /* - 1/8 IOCLK */
  48 #define TM1MD_SRC_IOCLK_32      0x02    /* - 1/32 IOCLK */
  49 #define TM1MD_SRC_TM0CASCADE    0x03    /* - cascade with timer 0 */
  50 #define TM1MD_SRC_TM0UFLOW      0x04    /* - timer 0 underflow */
  51 #define TM1MD_SRC_TM2UFLOW      0x06    /* - timer 2 underflow */
  52 #if defined(CONFIG_AM33_2)
  53 #define TM1MD_SRC_TM1IO         0x07    /* - TM1IO pin input */
  54 #endif  /* CONFIG_AM33_2 */
  55 #define TM1MD_INIT_COUNTER      0x40    /* initialize TMnBC = TMnBR */
  56 #define TM1MD_COUNT_ENABLE      0x80    /* timer count enable */
  57
  58 #define TM2MD                   __SYSREG(0xd4003002, u8) /* timer 2 mode register */
  59 #define TM2MD_SRC               0x07    /* timer source */
  60 #define TM2MD_SRC_IOCLK         0x00    /* - IOCLK */
  61 #define TM2MD_SRC_IOCLK_8       0x01    /* - 1/8 IOCLK */
  62 #define TM2MD_SRC_IOCLK_32      0x02    /* - 1/32 IOCLK */
  63 #define TM2MD_SRC_TM1CASCADE    0x03    /* - cascade with timer 1 */
  64 #define TM2MD_SRC_TM0UFLOW      0x04    /* - timer 0 underflow */
  65 #define TM2MD_SRC_TM1UFLOW      0x05    /* - timer 1 underflow */
  66 #if defined(CONFIG_AM33_2)
  67 #define TM2MD_SRC_TM2IO         0x07    /* - TM2IO pin input */
  68 #endif  /* CONFIG_AM33_2 */
  69 #define TM2MD_INIT_COUNTER      0x40    /* initialize TMnBC = TMnBR */
  70 #define TM2MD_COUNT_ENABLE      0x80    /* timer count enable */
  71
  72 #define TM3MD                   __SYSREG(0xd4003003, u8) /* timer 3 mode register */
  73 #define TM3MD_SRC               0x07    /* timer source */
  74 #define TM3MD_SRC_IOCLK         0x00    /* - IOCLK */
  75 #define TM3MD_SRC_IOCLK_8       0x01    /* - 1/8 IOCLK */
  76 #define TM3MD_SRC_IOCLK_32      0x02    /* - 1/32 IOCLK */
  77 #define TM3MD_SRC_TM2CASCADE    0x03    /* - cascade with timer 2 */
  78 #define TM3MD_SRC_TM0UFLOW      0x04    /* - timer 0 underflow */
  79 #define TM3MD_SRC_TM1UFLOW      0x05    /* - timer 1 underflow */
  80 #define TM3MD_SRC_TM2UFLOW      0x06    /* - timer 2 underflow */
  81 #if defined(CONFIG_AM33_2)
  82 #define TM3MD_SRC_TM3IO         0x07    /* - TM3IO pin input */
  83 #endif  /* CONFIG_AM33_2 */
  84 #define TM3MD_INIT_COUNTER      0x40    /* initialize TMnBC = TMnBR */
  85 #define TM3MD_COUNT_ENABLE      0x80    /* timer count enable */
  86
  87 #define TM01MD                  __SYSREG(0xd4003000, u16)  /* timer 0:1 mode register */
  88
  89 #define TM0BR                   __SYSREG(0xd4003010, u8)   /* timer 0 base register */
  90 #define TM1BR                   __SYSREG(0xd4003011, u8)   /* timer 1 base register */
  91 #define TM2BR                   __SYSREG(0xd4003012, u8)   /* timer 2 base register */
  92 #define TM3BR                   __SYSREG(0xd4003013, u8)   /* timer 3 base register */
  93 #define TM01BR                  __SYSREG(0xd4003010, u16)  /* timer 0:1 base register */
  94
  95 #define TM0BC                   __SYSREGC(0xd4003020, u8)  /* timer 0 binary counter */
  96 #define TM1BC                   __SYSREGC(0xd4003021, u8)  /* timer 1 binary counter */
  97 #define TM2BC                   __SYSREGC(0xd4003022, u8)  /* timer 2 binary counter */
  98 #define TM3BC                   __SYSREGC(0xd4003023, u8)  /* timer 3 binary counter */
  99 #define TM01BC                  __SYSREGC(0xd4003020, u16) /* timer 0:1 binary counter */
 100
 101 #define TM0IRQ                  2       /* timer 0 IRQ */
 102 #define TM1IRQ                  3       /* timer 1 IRQ */
 103 #define TM2IRQ                  4       /* timer 2 IRQ */
 104 #define TM3IRQ                  5       /* timer 3 IRQ */
 105
 106 #define TM0ICR                  GxICR(TM0IRQ)   /* timer 0 uflow intr ctrl reg */
 107 #define TM1ICR                  GxICR(TM1IRQ)   /* timer 1 uflow intr ctrl reg */
 108 #define TM2ICR                  GxICR(TM2IRQ)   /* timer 2 uflow intr ctrl reg */
 109 #define TM3ICR                  GxICR(TM3IRQ)   /* timer 3 uflow intr ctrl reg */
 110
 111 /*
 112  * 16-bit timers 4,5 & 7-15
 113  */
 114 #define TM4MD                   __SYSREG(0xd4003080, u8)   /* timer 4 mode register */
 115 #define TM4MD_SRC               0x07    /* timer source */
 116 #define TM4MD_SRC_IOCLK         0x00    /* - IOCLK */
 117 #define TM4MD_SRC_IOCLK_8       0x01    /* - 1/8 IOCLK */
 118 #define TM4MD_SRC_IOCLK_32      0x02    /* - 1/32 IOCLK */
 119 #define TM4MD_SRC_TM0UFLOW      0x04    /* - timer 0 underflow */
 120 #define TM4MD_SRC_TM1UFLOW      0x05    /* - timer 1 underflow */
 121 #define TM4MD_SRC_TM2UFLOW      0x06    /* - timer 2 underflow */
 122 #if defined(CONFIG_AM33_2)
 123 #define TM4MD_SRC_TM4IO         0x07    /* - TM4IO pin input */
 124 #endif  /* CONFIG_AM33_2 */
 125 #define TM4MD_INIT_COUNTER      0x40    /* initialize TMnBC = TMnBR */
 126 #define TM4MD_COUNT_ENABLE      0x80    /* timer count enable */
 127
 128 #define TM5MD                   __SYSREG(0xd4003082, u8)   /* timer 5 mode register */
 129 #define TM5MD_SRC               0x07    /* timer source */
 130 #define TM5MD_SRC_IOCLK         0x00    /* - IOCLK */
 131 #define TM5MD_SRC_IOCLK_8       0x01    /* - 1/8 IOCLK */
 132 #define TM5MD_SRC_IOCLK_32      0x02    /* - 1/32 IOCLK */
 133 #define TM5MD_SRC_TM4CASCADE    0x03    /* - cascade with timer 4 */
 134 #define TM5MD_SRC_TM0UFLOW      0x04    /* - timer 0 underflow */
 135 #define TM5MD_SRC_TM1UFLOW      0x05    /* - timer 1 underflow */
 136 #define TM5MD_SRC_TM2UFLOW      0x06    /* - timer 2 underflow */
 137 #if defined(CONFIG_AM33_2)
 138 #define TM5MD_SRC_TM5IO         0x07    /* - TM5IO pin input */
 139 #else   /* !CONFIG_AM33_2 */
 140 #define TM5MD_SRC_TM7UFLOW      0x07    /* - timer 7 underflow */
 141 #endif  /* CONFIG_AM33_2 */
 142 #define TM5MD_INIT_COUNTER      0x40    /* initialize TMnBC = TMnBR */
 143 #define TM5MD_COUNT_ENABLE      0x80    /* timer count enable */
 144
 145 #define TM7MD                   __SYSREG(0xd4003086, u8)   /* timer 7 mode register */
 146 #define TM7MD_SRC               0x07    /* timer source */
 147 #define TM7MD_SRC_IOCLK         0x00    /* - IOCLK */
 148 #define TM7MD_SRC_IOCLK_8       0x01    /* - 1/8 IOCLK */
 149 #define TM7MD_SRC_IOCLK_32      0x02    /* - 1/32 IOCLK */
 150 #define TM7MD_SRC_TM0UFLOW      0x04    /* - timer 0 underflow */
 151 #define TM7MD_SRC_TM1UFLOW      0x05    /* - timer 1 underflow */
 152 #define TM7MD_SRC_TM2UFLOW      0x06    /* - timer 2 underflow */
 153 #if defined(CONFIG_AM33_2)
 154 #define TM7MD_SRC_TM7IO         0x07    /* - TM7IO pin input */
 155 #endif  /* CONFIG_AM33_2 */
 156 #define TM7MD_INIT_COUNTER      0x40    /* initialize TMnBC = TMnBR */
 157 #define TM7MD_COUNT_ENABLE      0x80    /* timer count enable */
 158
 159 #define TM8MD                   __SYSREG(0xd4003088, u8)   /* timer 8 mode register */
 160 #define TM8MD_SRC               0x07    /* timer source */
 161 #define TM8MD_SRC_IOCLK         0x00    /* - IOCLK */
 162 #define TM8MD_SRC_IOCLK_8       0x01    /* - 1/8 IOCLK */
 163 #define TM8MD_SRC_IOCLK_32      0x02    /* - 1/32 IOCLK */
 164 #define TM8MD_SRC_TM7CASCADE    0x03    /* - cascade with timer 7 */
 165 #define TM8MD_SRC_TM0UFLOW      0x04    /* - timer 0 underflow */
 166 #define TM8MD_SRC_TM1UFLOW      0x05    /* - timer 1 underflow */
 167 #define TM8MD_SRC_TM2UFLOW      0x06    /* - timer 2 underflow */
 168 #if defined(CONFIG_AM33_2)
 169 #define TM8MD_SRC_TM8IO         0x07    /* - TM8IO pin input */
 170 #else   /* !CONFIG_AM33_2 */
 171 #define TM8MD_SRC_TM7UFLOW      0x07    /* - timer 7 underflow */
 172 #endif  /* CONFIG_AM33_2 */
 173 #define TM8MD_INIT_COUNTER      0x40    /* initialize TMnBC = TMnBR */
 174 #define TM8MD_COUNT_ENABLE      0x80    /* timer count enable */
 175
 176 #define TM9MD                   __SYSREG(0xd400308a, u8)   /* timer 9 mode register */
 177 #define TM9MD_SRC               0x07    /* timer source */
 178 #define TM9MD_SRC_IOCLK         0x00    /* - IOCLK */
 179 #define TM9MD_SRC_IOCLK_8       0x01    /* - 1/8 IOCLK */
 180 #define TM9MD_SRC_IOCLK_32      0x02    /* - 1/32 IOCLK */
 181 #define TM9MD_SRC_TM8CASCADE    0x03    /* - cascade with timer 8 */
 182 #define TM9MD_SRC_TM0UFLOW      0x04    /* - timer 0 underflow */
 183 #define TM9MD_SRC_TM1UFLOW      0x05    /* - timer 1 underflow */
 184 #define TM9MD_SRC_TM2UFLOW      0x06    /* - timer 2 underflow */
 185 #if defined(CONFIG_AM33_2)
 186 #define TM9MD_SRC_TM9IO         0x07    /* - TM9IO pin input */
 187 #else   /* !CONFIG_AM33_2 */
 188 #define TM9MD_SRC_TM7UFLOW      0x07    /* - timer 7 underflow */
 189 #endif  /* CONFIG_AM33_2 */
 190 #define TM9MD_INIT_COUNTER      0x40    /* initialize TMnBC = TMnBR */
 191 #define TM9MD_COUNT_ENABLE      0x80    /* timer count enable */
 192
 193 #define TM10MD                  __SYSREG(0xd400308c, u8)   /* timer 10 mode register */
 194 #define TM10MD_SRC              0x07    /* timer source */
 195 #define TM10MD_SRC_IOCLK        0x00    /* - IOCLK */
 196 #define TM10MD_SRC_IOCLK_8      0x01    /* - 1/8 IOCLK */
 197 #define TM10MD_SRC_IOCLK_32     0x02    /* - 1/32 IOCLK */
 198 #define TM10MD_SRC_TM9CASCADE   0x03    /* - cascade with timer 9 */
 199 #define TM10MD_SRC_TM0UFLOW     0x04    /* - timer 0 underflow */
 200 #define TM10MD_SRC_TM1UFLOW     0x05    /* - timer 1 underflow */
 201 #define TM10MD_SRC_TM2UFLOW     0x06    /* - timer 2 underflow */
 202 #if defined(CONFIG_AM33_2)
 203 #define TM10MD_SRC_TM10IO       0x07    /* - TM10IO pin input */
 204 #else   /* !CONFIG_AM33_2 */
 205 #define TM10MD_SRC_TM7UFLOW     0x07    /* - timer 7 underflow */
 206 #endif  /* CONFIG_AM33_2 */
 207 #define TM10MD_INIT_COUNTER     0x40    /* initialize TMnBC = TMnBR */
 208 #define TM10MD_COUNT_ENABLE     0x80    /* timer count enable */
 209
 210 #define TM11MD                  __SYSREG(0xd400308e, u8)   /* timer 11 mode register */
 211 #define TM11MD_SRC              0x07    /* timer source */
 212 #define TM11MD_SRC_IOCLK        0x00    /* - IOCLK */
 213 #define TM11MD_SRC_IOCLK_8      0x01    /* - 1/8 IOCLK */
 214 #define TM11MD_SRC_IOCLK_32     0x02    /* - 1/32 IOCLK */
 215 #define TM11MD_SRC_TM0UFLOW     0x04    /* - timer 0 underflow */
 216 #define TM11MD_SRC_TM1UFLOW     0x05    /* - timer 1 underflow */
 217 #define TM11MD_SRC_TM2UFLOW     0x06    /* - timer 2 underflow */
 218 #if defined(CONFIG_AM33_2)
 219 #define TM11MD_SRC_TM11IO       0x07    /* - TM11IO pin input */
 220 #else   /* !CONFIG_AM33_2 */
 221 #define TM11MD_SRC_TM7UFLOW     0x07    /* - timer 7 underflow */
 222 #endif  /* CONFIG_AM33_2 */
 223 #define TM11MD_INIT_COUNTER     0x40    /* initialize TMnBC = TMnBR */
 224 #define TM11MD_COUNT_ENABLE     0x80    /* timer count enable */
 225
 226 #if defined(CONFIG_AM34_2)
 227 #define TM12MD                  __SYSREG(0xd4003180, u8)   /* timer 11 mode register */
 228 #define TM12MD_SRC              0x07    /* timer source */
 229 #define TM12MD_SRC_IOCLK        0x00    /* - IOCLK */
 230 #define TM12MD_SRC_IOCLK_8      0x01    /* - 1/8 IOCLK */
 231 #define TM12MD_SRC_IOCLK_32     0x02    /* - 1/32 IOCLK */
 232 #define TM12MD_SRC_TM0UFLOW     0x04    /* - timer 0 underflow */
 233 #define TM12MD_SRC_TM1UFLOW     0x05    /* - timer 1 underflow */
 234 #define TM12MD_SRC_TM2UFLOW     0x06    /* - timer 2 underflow */
 235 #define TM12MD_SRC_TM7UFLOW     0x07    /* - timer 7 underflow */
 236 #define TM12MD_INIT_COUNTER     0x40    /* initialize TMnBC = TMnBR */
 237 #define TM12MD_COUNT_ENABLE     0x80    /* timer count enable */
 238
 239 #define TM13MD                  __SYSREG(0xd4003182, u8)   /* timer 11 mode register */
 240 #define TM13MD_SRC              0x07    /* timer source */
 241 #define TM13MD_SRC_IOCLK        0x00    /* - IOCLK */
 242 #define TM13MD_SRC_IOCLK_8      0x01    /* - 1/8 IOCLK */
 243 #define TM13MD_SRC_IOCLK_32     0x02    /* - 1/32 IOCLK */
 244 #define TM13MD_SRC_TM12CASCADE  0x03    /* - cascade with timer 12 */
 245 #define TM13MD_SRC_TM0UFLOW     0x04    /* - timer 0 underflow */
 246 #define TM13MD_SRC_TM1UFLOW     0x05    /* - timer 1 underflow */
 247 #define TM13MD_SRC_TM2UFLOW     0x06    /* - timer 2 underflow */
 248 #define TM13MD_SRC_TM7UFLOW     0x07    /* - timer 7 underflow */
 249 #define TM13MD_INIT_COUNTER     0x40    /* initialize TMnBC = TMnBR */
 250 #define TM13MD_COUNT_ENABLE     0x80    /* timer count enable */
 251
 252 #define TM14MD                  __SYSREG(0xd4003184, u8)   /* timer 11 mode register */
 253 #define TM14MD_SRC              0x07    /* timer source */
 254 #define TM14MD_SRC_IOCLK        0x00    /* - IOCLK */
 255 #define TM14MD_SRC_IOCLK_8      0x01    /* - 1/8 IOCLK */
 256 #define TM14MD_SRC_IOCLK_32     0x02    /* - 1/32 IOCLK */
 257 #define TM14MD_SRC_TM13CASCADE  0x03    /* - cascade with timer 13 */
 258 #define TM14MD_SRC_TM0UFLOW     0x04    /* - timer 0 underflow */
 259 #define TM14MD_SRC_TM1UFLOW     0x05    /* - timer 1 underflow */
 260 #define TM14MD_SRC_TM2UFLOW     0x06    /* - timer 2 underflow */
 261 #define TM14MD_SRC_TM7UFLOW     0x07    /* - timer 7 underflow */
 262 #define TM14MD_INIT_COUNTER     0x40    /* initialize TMnBC = TMnBR */
 263 #define TM14MD_COUNT_ENABLE     0x80    /* timer count enable */
 264
 265 #define TM15MD                  __SYSREG(0xd4003186, u8)   /* timer 11 mode register */
 266 #define TM15MD_SRC              0x07    /* timer source */
 267 #define TM15MD_SRC_IOCLK        0x00    /* - IOCLK */
 268 #define TM15MD_SRC_IOCLK_8      0x01    /* - 1/8 IOCLK */
 269 #define TM15MD_SRC_IOCLK_32     0x02    /* - 1/32 IOCLK */
 270 #define TM15MD_SRC_TM0UFLOW     0x04    /* - timer 0 underflow */
 271 #define TM15MD_SRC_TM1UFLOW     0x05    /* - timer 1 underflow */
 272 #define TM15MD_SRC_TM2UFLOW     0x06    /* - timer 2 underflow */
 273 #define TM15MD_SRC_TM7UFLOW     0x07    /* - timer 7 underflow */
 274 #define TM15MD_INIT_COUNTER     0x40    /* initialize TMnBC = TMnBR */
 275 #define TM15MD_COUNT_ENABLE     0x80    /* timer count enable */
 276 #endif  /* CONFIG_AM34_2 */
 277
 278
 279 #define TM4BR                   __SYSREG(0xd4003090, u16)  /* timer 4 base register */
 280 #define TM5BR                   __SYSREG(0xd4003092, u16)  /* timer 5 base register */
 281 #define TM45BR                  __SYSREG(0xd4003090, u32)  /* timer 4:5 base register */
 282 #define TM7BR                   __SYSREG(0xd4003096, u16)  /* timer 7 base register */
 283 #define TM8BR                   __SYSREG(0xd4003098, u16)  /* timer 8 base register */
 284 #define TM9BR                   __SYSREG(0xd400309a, u16)  /* timer 9 base register */
 285 #define TM89BR                  __SYSREG(0xd4003098, u32)  /* timer 8:9 base register */
 286 #define TM10BR                  __SYSREG(0xd400309c, u16)  /* timer 10 base register */
 287 #define TM11BR                  __SYSREG(0xd400309e, u16)  /* timer 11 base register */
 288 #if defined(CONFIG_AM34_2)
 289 #define TM12BR                  __SYSREG(0xd4003190, u16)  /* timer 12 base register */
 290 #define TM13BR                  __SYSREG(0xd4003192, u16)  /* timer 13 base register */
 291 #define TM14BR                  __SYSREG(0xd4003194, u16)  /* timer 14 base register */
 292 #define TM15BR                  __SYSREG(0xd4003196, u16)  /* timer 15 base register */
 293 #endif  /* CONFIG_AM34_2 */
 294
 295 #define TM4BC                   __SYSREG(0xd40030a0, u16)  /* timer 4 binary counter */
 296 #define TM5BC                   __SYSREG(0xd40030a2, u16)  /* timer 5 binary counter */
 297 #define TM45BC                  __SYSREG(0xd40030a0, u32)  /* timer 4:5 binary counter */
 298 #define TM7BC                   __SYSREG(0xd40030a6, u16)  /* timer 7 binary counter */
 299 #define TM8BC                   __SYSREG(0xd40030a8, u16)  /* timer 8 binary counter */
 300 #define TM9BC                   __SYSREG(0xd40030aa, u16)  /* timer 9 binary counter */
 301 #define TM89BC                  __SYSREG(0xd40030a8, u32)  /* timer 8:9 binary counter */
 302 #define TM10BC                  __SYSREG(0xd40030ac, u16)  /* timer 10 binary counter */
 303 #define TM11BC                  __SYSREG(0xd40030ae, u16)  /* timer 11 binary counter */
 304 #if defined(CONFIG_AM34_2)
 305 #define TM12BC                  __SYSREG(0xd40031a0, u16)  /* timer 12 binary counter */
 306 #define TM13BC                  __SYSREG(0xd40031a2, u16)  /* timer 13 binary counter */
 307 #define TM14BC                  __SYSREG(0xd40031a4, u16)  /* timer 14 binary counter */
 308 #define TM15BC                  __SYSREG(0xd40031a6, u16)  /* timer 15 binary counter */
 309 #endif  /* CONFIG_AM34_2 */
 310
 311 #define TM4IRQ                  6       /* timer 4 IRQ */
 312 #define TM5IRQ                  7       /* timer 5 IRQ */
 313 #define TM7IRQ                  11      /* timer 7 IRQ */
 314 #define TM8IRQ                  12      /* timer 8 IRQ */
 315 #define TM9IRQ                  13      /* timer 9 IRQ */
 316 #define TM10IRQ                 14      /* timer 10 IRQ */
 317 #define TM11IRQ                 15      /* timer 11 IRQ */
 318 #if defined(CONFIG_AM34_2)
 319 #define TM12IRQ                 64      /* timer 12 IRQ */
 320 #define TM13IRQ                 65      /* timer 13 IRQ */
 321 #define TM14IRQ                 66      /* timer 14 IRQ */
 322 #define TM15IRQ                 67      /* timer 15 IRQ */
 323 #endif  /* CONFIG_AM34_2 */
 324
 325 #define TM4ICR                  GxICR(TM4IRQ)   /* timer 4 uflow intr ctrl reg */
 326 #define TM5ICR                  GxICR(TM5IRQ)   /* timer 5 uflow intr ctrl reg */
 327 #define TM7ICR                  GxICR(TM7IRQ)   /* timer 7 uflow intr ctrl reg */
 328 #define TM8ICR                  GxICR(TM8IRQ)   /* timer 8 uflow intr ctrl reg */
 329 #define TM9ICR                  GxICR(TM9IRQ)   /* timer 9 uflow intr ctrl reg */
 330 #define TM10ICR                 GxICR(TM10IRQ)  /* timer 10 uflow intr ctrl reg */
 331 #define TM11ICR                 GxICR(TM11IRQ)  /* timer 11 uflow intr ctrl reg */
 332 #if defined(CONFIG_AM34_2)
 333 #define TM12ICR                 GxICR(TM12IRQ)  /* timer 12 uflow intr ctrl reg */
 334 #define TM13ICR                 GxICR(TM13IRQ)  /* timer 13 uflow intr ctrl reg */
 335 #define TM14ICR                 GxICR(TM14IRQ)  /* timer 14 uflow intr ctrl reg */
 336 #define TM15ICR                 GxICR(TM15IRQ)  /* timer 15 uflow intr ctrl reg */
 337 #endif  /* CONFIG_AM34_2 */
 338
 339 /*
 340  * 16-bit timer 6
 341  */
 342 #define TM6MD                   __SYSREG(0xd4003084, u16)  /* timer6 mode register */
 343 #define TM6MD_SRC               0x0007  /* timer source */
 344 #define TM6MD_SRC_IOCLK         0x0000  /* - IOCLK */
 345 #define TM6MD_SRC_IOCLK_8       0x0001  /* - 1/8 IOCLK */
 346 #define TM6MD_SRC_IOCLK_32      0x0002  /* - 1/32 IOCLK */
 347 #define TM6MD_SRC_TM0UFLOW      0x0004  /* - timer 0 underflow */
 348 #define TM6MD_SRC_TM1UFLOW      0x0005  /* - timer 1 underflow */
 349 #define TM6MD_SRC_TM2UFLOW      0x0006  /* - timer 2 underflow */
 350 #if defined(CONFIG_AM33_2)
 351 /* #define      TM6MD_SRC_TM6IOB_BOTH   0x0006 */       /* - TM6IOB pin input (both edges) */
 352 #define TM6MD_SRC_TM6IOB_SINGLE 0x0007  /* - TM6IOB pin input (single edge) */
 353 #endif  /* CONFIG_AM33_2 */
 354 #define TM6MD_ONESHOT_ENABLE    0x0040  /* oneshot count */
 355 #define TM6MD_CLR_ENABLE        0x0010  /* clear count enable */
 356 #if     defined(CONFIG_AM33_2)
 357 #define TM6MD_TRIG_ENABLE       0x0080  /* TM6IOB pin trigger enable */
 358 #define TM6MD_PWM               0x3800  /* PWM output mode */
 359 #define TM6MD_PWM_DIS           0x0000  /* - disabled */
 360 #define TM6MD_PWM_10BIT         0x1000  /* - 10 bits mode */
 361 #define TM6MD_PWM_11BIT         0x1800  /* - 11 bits mode */
 362 #define TM6MD_PWM_12BIT         0x3000  /* - 12 bits mode */
 363 #define TM6MD_PWM_14BIT         0x3800  /* - 14 bits mode */
 364 #endif  /* CONFIG_AM33_2 */
 365
 366 #define TM6MD_INIT_COUNTER      0x4000  /* initialize TMnBC to zero */
 367 #define TM6MD_COUNT_ENABLE      0x8000  /* timer count enable */
 368
 369 #define TM6MDA                  __SYSREG(0xd40030b4, u8)   /* timer6 cmp/cap A mode reg */
 370 #define TM6MDA_MODE_CMP_SINGLE  0x00    /* - compare, single buffer mode */
 371 #define TM6MDA_MODE_CMP_DOUBLE  0x40    /* - compare, double buffer mode */
 372 #if     defined(CONFIG_AM33_2)
 373 #define TM6MDA_OUT              0x07    /* output select */
 374 #define TM6MDA_OUT_SETA_RESETB  0x00    /* - set at match A, reset at match B */
 375 #define TM6MDA_OUT_SETA_RESETOV 0x01    /* - set at match A, reset at overflow */
 376 #define TM6MDA_OUT_SETA         0x02    /* - set at match A */
 377 #define TM6MDA_OUT_RESETA       0x03    /* - reset at match A */
 378 #define TM6MDA_OUT_TOGGLE       0x04    /* - toggle on match A */
 379 #define TM6MDA_MODE             0xc0    /* compare A register mode */
 380 #define TM6MDA_MODE_CAP_S_EDGE  0x80    /* - capture, single edge mode */
 381 #define TM6MDA_MODE_CAP_D_EDGE  0xc0    /* - capture, double edge mode */
 382 #define TM6MDA_EDGE             0x20    /* compare A edge select */
 383 #define TM6MDA_EDGE_FALLING     0x00    /* capture on falling edge */
 384 #define TM6MDA_EDGE_RISING      0x20    /* capture on rising edge */
 385 #define TM6MDA_CAPTURE_ENABLE   0x10    /* capture enable */
 386 #else   /* !CONFIG_AM33_2 */
 387 #define TM6MDA_MODE             0x40    /* compare A register mode */
 388 #endif  /* CONFIG_AM33_2 */
 389
 390 #define TM6MDB                  __SYSREG(0xd40030b5, u8)   /* timer6 cmp/cap B mode reg */
 391 #define TM6MDB_MODE_CMP_SINGLE  0x00    /* - compare, single buffer mode */
 392 #define TM6MDB_MODE_CMP_DOUBLE  0x40    /* - compare, double buffer mode */
 393 #if defined(CONFIG_AM33_2)
 394 #define TM6MDB_OUT              0x07    /* output select */
 395 #define TM6MDB_OUT_SETB_RESETA  0x00    /* - set at match B, reset at match A */
 396 #define TM6MDB_OUT_SETB_RESETOV 0x01    /* - set at match B */
 397 #define TM6MDB_OUT_RESETB       0x03    /* - reset at match B */
 398 #define TM6MDB_OUT_TOGGLE       0x04    /* - toggle on match B */
 399 #define TM6MDB_MODE             0xc0    /* compare B register mode */
 400 #define TM6MDB_MODE_CAP_S_EDGE  0x80    /* - capture, single edge mode */
 401 #define TM6MDB_MODE_CAP_D_EDGE  0xc0    /* - capture, double edge mode */
 402 #define TM6MDB_EDGE             0x20    /* compare B edge select */
 403 #define TM6MDB_EDGE_FALLING     0x00    /* capture on falling edge */
 404 #define TM6MDB_EDGE_RISING      0x20    /* capture on rising edge */
 405 #define TM6MDB_CAPTURE_ENABLE   0x10    /* capture enable */
 406 #else   /* !CONFIG_AM33_2 */
 407 #define TM6MDB_MODE             0x40    /* compare B register mode */
 408 #endif  /* CONFIG_AM33_2 */
 409
 410 #define TM6CA                   __SYSREG(0xd40030c4, u16)   /* timer6 cmp/capture reg A */
 411 #define TM6CB                   __SYSREG(0xd40030d4, u16)   /* timer6 cmp/capture reg B */
 412 #define TM6BC                   __SYSREG(0xd40030a4, u16)   /* timer6 binary counter */
 413
 414 #define TM6IRQ                  6       /* timer 6 IRQ */
 415 #define TM6AIRQ                 9       /* timer 6A IRQ */
 416 #define TM6BIRQ                 10      /* timer 6B IRQ */
 417
 418 #define TM6ICR                  GxICR(TM6IRQ)   /* timer 6 uflow intr ctrl reg */
 419 #define TM6AICR                 GxICR(TM6AIRQ)  /* timer 6A intr control reg */
 420 #define TM6BICR                 GxICR(TM6BIRQ)  /* timer 6B intr control reg */
 421
 422 #if defined(CONFIG_AM34_2)
 423 /*
 424  * MTM: OS Tick-Timer
 425  */
 426 #define TMTMD                   __SYSREG(0xd4004100, u8)        /* Tick Timer mode register */
 427 #define TMTMD_TMTLDE            0x40    /* initialize TMTBC = TMTBR */
 428 #define TMTMD_TMTCNE            0x80    /* timer count enable       */
 429
 430 #define TMTBR                   __SYSREG(0xd4004110, u32)       /* Tick Timer mode reg */
 431 #define TMTBC                   __SYSREG(0xd4004120, u32)       /* Tick Timer mode reg */
 432
 433 /*
 434  * MTM: OS Timestamp-Timer
 435  */
 436 #define TMSMD                   __SYSREG(0xd4004140, u8)        /* Tick Timer mode register */
 437 #define TMSMD_TMSLDE            0x40            /* initialize TMSBC = TMSBR */
 438 #define TMSMD_TMSCNE            0x80            /* timer count enable       */
 439
 440 #define TMSBR                   __SYSREG(0xd4004150, u32)       /* Tick Timer mode register */
 441 #define TMSBC                   __SYSREG(0xd4004160, u32)       /* Tick Timer mode register */
 442
 443 #define TMTIRQ                  119             /* OS Tick timer   IRQ */
 444 #define TMSIRQ                  120             /* Timestamp timer IRQ */
 445
 446 #define TMTICR                  GxICR(TMTIRQ)   /* OS Tick timer   uflow intr ctrl reg */
 447 #define TMSICR                  GxICR(TMSIRQ)   /* Timestamp timer uflow intr ctrl reg */
 448 #endif  /* CONFIG_AM34_2 */
 449
 450 #endif /* __KERNEL__ */
 451
 452 #endif /* _ASM_TIMER_REGS_H */