arch/tile/include/asm/irqflags.h

   1 /*
   2  * Copyright 2010 Tilera Corporation. All Rights Reserved.
   3  *
   4  *   This program is free software; you can redistribute it and/or
   5  *   modify it under the terms of the GNU General Public License
   6  *   as published by the Free Software Foundation, version 2.
   7  *
   8  *   This program is distributed in the hope that it will be useful, but
   9  *   WITHOUT ANY WARRANTY; without even the implied warranty of
  10  *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  11  *   NON INFRINGEMENT.  See the GNU General Public License for
  12  *   more details.
  13  */
  14
  15 #ifndef _ASM_TILE_IRQFLAGS_H
  16 #define _ASM_TILE_IRQFLAGS_H
  17
  18 #include <arch/interrupts.h>
  19 #include <arch/chip.h>
  20
  21 /*
  22  * The set of interrupts we want to allow when interrupts are nominally
  23  * disabled.  The remainder are effectively "NMI" interrupts from
  24  * the point of view of the generic Linux code.  Note that synchronous
  25  * interrupts (aka "non-queued") are not blocked by the mask in any case.
  26  */
  27 #define LINUX_MASKABLE_INTERRUPTS \
  28         (~((_AC(1,ULL) << INT_PERF_COUNT) | (_AC(1,ULL) << INT_AUX_PERF_COUNT)))
  29
  30 #if CHIP_HAS_SPLIT_INTR_MASK()
  31 /* The same macro, but for the two 32-bit SPRs separately. */
  32 #define LINUX_MASKABLE_INTERRUPTS_LO (-1)
  33 #define LINUX_MASKABLE_INTERRUPTS_HI \
  34         (~((1 << (INT_PERF_COUNT - 32)) | (1 << (INT_AUX_PERF_COUNT - 32))))
  35 #endif
  36
  37 #ifndef __ASSEMBLY__
  38
  39 /* NOTE: we can't include <linux/percpu.h> due to #include dependencies. */
  40 #include <asm/percpu.h>
  41 #include <arch/spr_def.h>
  42
  43 /*
  44  * Set and clear kernel interrupt masks.
  45  *
  46  * NOTE: __insn_mtspr() is a compiler builtin marked as a memory
  47  * clobber.  We rely on it being equivalent to a compiler barrier in
  48  * this code since arch_local_irq_save() and friends must act as
  49  * compiler barriers.  This compiler semantic is baked into enough
  50  * places that the compiler will maintain it going forward.
  51  */
  52 #if CHIP_HAS_SPLIT_INTR_MASK()
  53 #if INT_PERF_COUNT < 32 || INT_AUX_PERF_COUNT < 32 || INT_MEM_ERROR >= 32
  54 # error Fix assumptions about which word various interrupts are in
  55 #endif
  56 #define interrupt_mask_set(n) do { \
  57         int __n = (n); \
  58         int __mask = 1 << (__n & 0x1f); \
  59         if (__n < 32) \
  60                 __insn_mtspr(SPR_INTERRUPT_MASK_SET_K_0, __mask); \
  61         else \
  62                 __insn_mtspr(SPR_INTERRUPT_MASK_SET_K_1, __mask); \
  63 } while (0)
  64 #define interrupt_mask_reset(n) do { \
  65         int __n = (n); \
  66         int __mask = 1 << (__n & 0x1f); \
  67         if (__n < 32) \
  68                 __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K_0, __mask); \
  69         else \
  70                 __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K_1, __mask); \
  71 } while (0)
  72 #define interrupt_mask_check(n) ({ \
  73         int __n = (n); \
  74         (((__n < 32) ? \
  75          __insn_mfspr(SPR_INTERRUPT_MASK_K_0) : \
  76          __insn_mfspr(SPR_INTERRUPT_MASK_K_1)) \
  77           >> (__n & 0x1f)) & 1; \
  78 })
  79 #define interrupt_mask_set_mask(mask) do { \
  80         unsigned long long __m = (mask); \
  81         __insn_mtspr(SPR_INTERRUPT_MASK_SET_K_0, (unsigned long)(__m)); \
  82         __insn_mtspr(SPR_INTERRUPT_MASK_SET_K_1, (unsigned long)(__m>>32)); \
  83 } while (0)
  84 #define interrupt_mask_reset_mask(mask) do { \
  85         unsigned long long __m = (mask); \
  86         __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K_0, (unsigned long)(__m)); \
  87         __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K_1, (unsigned long)(__m>>32)); \
  88 } while (0)
  89 #define interrupt_mask_save_mask() \
  90         (__insn_mfspr(SPR_INTERRUPT_MASK_SET_K_0) | \
  91          (((unsigned long long)__insn_mfspr(SPR_INTERRUPT_MASK_SET_K_1))<<32))
  92 #define interrupt_mask_restore_mask(mask) do { \
  93         unsigned long long __m = (mask); \
  94         __insn_mtspr(SPR_INTERRUPT_MASK_K_0, (unsigned long)(__m)); \
  95         __insn_mtspr(SPR_INTERRUPT_MASK_K_1, (unsigned long)(__m>>32)); \
  96 } while (0)
  97 #else
  98 #define interrupt_mask_set(n) \
  99         __insn_mtspr(SPR_INTERRUPT_MASK_SET_K, (1UL << (n)))
 100 #define interrupt_mask_reset(n) \
 101         __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K, (1UL << (n)))
 102 #define interrupt_mask_check(n) \
 103         ((__insn_mfspr(SPR_INTERRUPT_MASK_K) >> (n)) & 1)
 104 #define interrupt_mask_set_mask(mask) \
 105         __insn_mtspr(SPR_INTERRUPT_MASK_SET_K, (mask))
 106 #define interrupt_mask_reset_mask(mask) \
 107         __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K, (mask))
 108 #define interrupt_mask_save_mask() \
 109         __insn_mfspr(SPR_INTERRUPT_MASK_K)
 110 #define interrupt_mask_restore_mask(mask) \
 111         __insn_mtspr(SPR_INTERRUPT_MASK_K, (mask))
 112 #endif
 113
 114 /*
 115  * The set of interrupts we want active if irqs are enabled.
 116  * Note that in particular, the tile timer interrupt comes and goes
 117  * from this set, since we have no other way to turn off the timer.
 118  * Likewise, INTCTRL_K is removed and re-added during device
 119  * interrupts, as is the the hardwall UDN_FIREWALL interrupt.
 120  * We use a low bit (MEM_ERROR) as our sentinel value and make sure it
 121  * is always claimed as an "active interrupt" so we can query that bit
 122  * to know our current state.
 123  */
 124 DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask);
 125 #define INITIAL_INTERRUPTS_ENABLED (1ULL << INT_MEM_ERROR)
 126
 127 /* Disable interrupts. */
 128 #define arch_local_irq_disable() \
 129         interrupt_mask_set_mask(LINUX_MASKABLE_INTERRUPTS)
 130
 131 /* Disable all interrupts, including NMIs. */
 132 #define arch_local_irq_disable_all() \
 133         interrupt_mask_set_mask(-1ULL)
 134
 135 /* Re-enable all maskable interrupts. */
 136 #define arch_local_irq_enable() \
 137         interrupt_mask_reset_mask(__get_cpu_var(interrupts_enabled_mask))
 138
 139 /* Disable or enable interrupts based on flag argument. */
 140 #define arch_local_irq_restore(disabled) do { \
 141         if (disabled) \
 142                 arch_local_irq_disable(); \
 143         else \
 144                 arch_local_irq_enable(); \
 145 } while (0)
 146
 147 /* Return true if "flags" argument means interrupts are disabled. */
 148 #define arch_irqs_disabled_flags(flags) ((flags) != 0)
 149
 150 /* Return true if interrupts are currently disabled. */
 151 #define arch_irqs_disabled() interrupt_mask_check(INT_MEM_ERROR)
 152
 153 /* Save whether interrupts are currently disabled. */
 154 #define arch_local_save_flags() arch_irqs_disabled()
 155
 156 /* Save whether interrupts are currently disabled, then disable them. */
 157 #define arch_local_irq_save() ({ \
 158         unsigned long __flags = arch_local_save_flags(); \
 159         arch_local_irq_disable(); \
 160         __flags; })
 161
 162 /* Prevent the given interrupt from being enabled next time we enable irqs. */
 163 #define arch_local_irq_mask(interrupt) \
 164         (__get_cpu_var(interrupts_enabled_mask) &= ~(1ULL << (interrupt)))
 165
 166 /* Prevent the given interrupt from being enabled immediately. */
 167 #define arch_local_irq_mask_now(interrupt) do { \
 168         arch_local_irq_mask(interrupt); \
 169         interrupt_mask_set(interrupt); \
 170 } while (0)
 171
 172 /* Allow the given interrupt to be enabled next time we enable irqs. */
 173 #define arch_local_irq_unmask(interrupt) \
 174         (__get_cpu_var(interrupts_enabled_mask) |= (1ULL << (interrupt)))
 175
 176 /* Allow the given interrupt to be enabled immediately, if !irqs_disabled. */
 177 #define arch_local_irq_unmask_now(interrupt) do { \
 178         arch_local_irq_unmask(interrupt); \
 179         if (!irqs_disabled()) \
 180                 interrupt_mask_reset(interrupt); \
 181 } while (0)
 182
 183 #else /* __ASSEMBLY__ */
 184
 185 /* We provide a somewhat more restricted set for assembly. */
 186
 187 #ifdef __tilegx__
 188
 189 #if INT_MEM_ERROR != 0
 190 # error Fix IRQS_DISABLED() macro
 191 #endif
 192
 193 /* Return 0 or 1 to indicate whether interrupts are currently disabled. */
 194 #define IRQS_DISABLED(tmp)                                      \
 195         mfspr   tmp, SPR_INTERRUPT_MASK_K;                      \
 196         andi    tmp, tmp, 1
 197
 198 /* Load up a pointer to &interrupts_enabled_mask. */
 199 #define GET_INTERRUPTS_ENABLED_MASK_PTR(reg)                    \
 200         moveli reg, hw2_last(interrupts_enabled_mask);          \
 201         shl16insli reg, reg, hw1(interrupts_enabled_mask);      \
 202         shl16insli reg, reg, hw0(interrupts_enabled_mask);      \
 203         add     reg, reg, tp
 204
 205 /* Disable interrupts. */
 206 #define IRQ_DISABLE(tmp0, tmp1)                                 \
 207         moveli  tmp0, hw2_last(LINUX_MASKABLE_INTERRUPTS);      \
 208         shl16insli tmp0, tmp0, hw1(LINUX_MASKABLE_INTERRUPTS);  \
 209         shl16insli tmp0, tmp0, hw0(LINUX_MASKABLE_INTERRUPTS);  \
 210         mtspr   SPR_INTERRUPT_MASK_SET_K, tmp0
 211
 212 /* Disable ALL synchronous interrupts (used by NMI entry). */
 213 #define IRQ_DISABLE_ALL(tmp)                                    \
 214         movei   tmp, -1;                                        \
 215         mtspr   SPR_INTERRUPT_MASK_SET_K, tmp
 216
 217 /* Enable interrupts. */
 218 #define IRQ_ENABLE_LOAD(tmp0, tmp1)                             \
 219         GET_INTERRUPTS_ENABLED_MASK_PTR(tmp0);                  \
 220         ld      tmp0, tmp0
 221 #define IRQ_ENABLE_APPLY(tmp0, tmp1)                            \
 222         mtspr   SPR_INTERRUPT_MASK_RESET_K, tmp0
 223
 224 #else /* !__tilegx__ */
 225
 226 /*
 227  * Return 0 or 1 to indicate whether interrupts are currently disabled.
 228  * Note that it's important that we use a bit from the "low" mask word,
 229  * since when we are enabling, that is the word we write first, so if we
 230  * are interrupted after only writing half of the mask, the interrupt
 231  * handler will correctly observe that we have interrupts enabled, and
 232  * will enable interrupts itself on return from the interrupt handler
 233  * (making the original code's write of the "high" mask word idempotent).
 234  */
 235 #define IRQS_DISABLED(tmp)                                      \
 236         mfspr   tmp, SPR_INTERRUPT_MASK_K_0;                    \
 237         shri    tmp, tmp, INT_MEM_ERROR;                        \
 238         andi    tmp, tmp, 1
 239
 240 /* Load up a pointer to &interrupts_enabled_mask. */
 241 #define GET_INTERRUPTS_ENABLED_MASK_PTR(reg)                    \
 242         moveli  reg, lo16(interrupts_enabled_mask);             \
 243         auli    reg, reg, ha16(interrupts_enabled_mask);        \
 244         add     reg, reg, tp
 245
 246 /* Disable interrupts. */
 247 #define IRQ_DISABLE(tmp0, tmp1)                                 \
 248         {                                                       \
 249          movei  tmp0, LINUX_MASKABLE_INTERRUPTS_LO;             \
 250          moveli tmp1, lo16(LINUX_MASKABLE_INTERRUPTS_HI)        \
 251         };                                                      \
 252         {                                                       \
 253          mtspr  SPR_INTERRUPT_MASK_SET_K_0, tmp0;               \
 254          auli   tmp1, tmp1, ha16(LINUX_MASKABLE_INTERRUPTS_HI)  \
 255         };                                                      \
 256         mtspr   SPR_INTERRUPT_MASK_SET_K_1, tmp1
 257
 258 /* Disable ALL synchronous interrupts (used by NMI entry). */
 259 #define IRQ_DISABLE_ALL(tmp)                                    \
 260         movei   tmp, -1;                                        \
 261         mtspr   SPR_INTERRUPT_MASK_SET_K_0, tmp;                \
 262         mtspr   SPR_INTERRUPT_MASK_SET_K_1, tmp
 263
 264 /* Enable interrupts. */
 265 #define IRQ_ENABLE_LOAD(tmp0, tmp1)                             \
 266         GET_INTERRUPTS_ENABLED_MASK_PTR(tmp0);                  \
 267         {                                                       \
 268          lw     tmp0, tmp0;                                     \
 269          addi   tmp1, tmp0, 4                                   \
 270         };                                                      \
 271         lw      tmp1, tmp1
 272 #define IRQ_ENABLE_APPLY(tmp0, tmp1)                            \
 273         mtspr   SPR_INTERRUPT_MASK_RESET_K_0, tmp0;             \
 274         mtspr   SPR_INTERRUPT_MASK_RESET_K_1, tmp1
 275 #endif
 276
 277 #define IRQ_ENABLE(tmp0, tmp1)                                  \
 278         IRQ_ENABLE_LOAD(tmp0, tmp1);                            \
 279         IRQ_ENABLE_APPLY(tmp0, tmp1)
 280
 281 /*
 282  * Do the CPU's IRQ-state tracing from assembly code. We call a
 283  * C function, but almost everywhere we do, we don't mind clobbering
 284  * all the caller-saved registers.
 285  */
 286 #ifdef CONFIG_TRACE_IRQFLAGS
 287 # define TRACE_IRQS_ON  jal trace_hardirqs_on
 288 # define TRACE_IRQS_OFF jal trace_hardirqs_off
 289 #else
 290 # define TRACE_IRQS_ON
 291 # define TRACE_IRQS_OFF
 292 #endif
 293
 294 #endif /* __ASSEMBLY__ */
 295
 296 #endif /* _ASM_TILE_IRQFLAGS_H */