arch/x86/include/asm/rio.h

   1 /*
   2  * Derived from include/asm-x86/mach-summit/mach_mpparse.h
   3  *          and include/asm-x86/mach-default/bios_ebda.h
   4  *
   5  * Author: Laurent Vivier <Laurent.Vivier@bull.net>
   6  */
   7
   8 #ifndef _ASM_X86_RIO_H
   9 #define _ASM_X86_RIO_H
  10
  11 #define RIO_TABLE_VERSION       3
  12
  13 struct rio_table_hdr {
  14         u8 version;             /* Version number of this data structure  */
  15         u8 num_scal_dev;        /* # of Scalability devices               */
  16         u8 num_rio_dev;         /* # of RIO I/O devices                   */
  17 } __attribute__((packed));
  18
  19 struct scal_detail {
  20         u8 node_id;             /* Scalability Node ID                    */
  21         u32 CBAR;               /* Address of 1MB register space          */
  22         u8 port0node;           /* Node ID port connected to: 0xFF=None   */
  23         u8 port0port;           /* Port num port connected to: 0,1,2, or  */
  24                                 /* 0xFF=None                              */
  25         u8 port1node;           /* Node ID port connected to: 0xFF = None */
  26         u8 port1port;           /* Port num port connected to: 0,1,2, or  */
  27                                 /* 0xFF=None                              */
  28         u8 port2node;           /* Node ID port connected to: 0xFF = None */
  29         u8 port2port;           /* Port num port connected to: 0,1,2, or  */
  30                                 /* 0xFF=None                              */
  31         u8 chassis_num;         /* 1 based Chassis number (1 = boot node) */
  32 } __attribute__((packed));
  33
  34 struct rio_detail {
  35         u8 node_id;             /* RIO Node ID                            */
  36         u32 BBAR;               /* Address of 1MB register space          */
  37         u8 type;                /* Type of device                         */
  38         u8 owner_id;            /* Node ID of Hurricane that owns this    */
  39                                 /* node                                   */
  40         u8 port0node;           /* Node ID port connected to: 0xFF=None   */
  41         u8 port0port;           /* Port num port connected to: 0,1,2, or  */
  42                                 /* 0xFF=None                              */
  43         u8 port1node;           /* Node ID port connected to: 0xFF=None   */
  44         u8 port1port;           /* Port num port connected to: 0,1,2, or  */
  45                                 /* 0xFF=None                              */
  46         u8 first_slot;          /* Lowest slot number below this Calgary  */
  47         u8 status;              /* Bit 0 = 1 : the XAPIC is used          */
  48                                 /*       = 0 : the XAPIC is not used, ie: */
  49                                 /*            ints fwded to another XAPIC */
  50                                 /*           Bits1:7 Reserved             */
  51         u8 WP_index;            /* instance index - lower ones have       */
  52                                 /*     lower slot numbers/PCI bus numbers */
  53         u8 chassis_num;         /* 1 based Chassis number                 */
  54 } __attribute__((packed));
  55
  56 enum {
  57         HURR_SCALABILTY = 0,    /* Hurricane Scalability info */
  58         HURR_RIOIB      = 2,    /* Hurricane RIOIB info       */
  59         COMPAT_CALGARY  = 4,    /* Compatibility Calgary      */
  60         ALT_CALGARY     = 5,    /* Second Planar Calgary      */
  61 };
  62
  63 #endif /* _ASM_X86_RIO_H */