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Linux 3.11-rc3
[cris-mirror.git] / drivers / gpio / gpio-ep93xx.c
blob56b98eebe1fc0b7f04ce4a7b5a0fbfa31ccda65f
1 /*
2 * Generic EP93xx GPIO handling
3 *
4 * Copyright (c) 2008 Ryan Mallon
5 * Copyright (c) 2011 H Hartley Sweeten <hsweeten@visionengravers.com>
6 *
7 * Based on code originally from:
8 * linux/arch/arm/mach-ep93xx/core.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/io.h>
19 #include <linux/gpio.h>
20 #include <linux/irq.h>
21 #include <linux/slab.h>
22 #include <linux/basic_mmio_gpio.h>
23
24 #include <mach/hardware.h>
25 #include <mach/gpio-ep93xx.h>
26
27 #define irq_to_gpio(irq) ((irq) - gpio_to_irq(0))
28
29 struct ep93xx_gpio {
30 void __iomem *mmio_base;
31 struct bgpio_chip bgc[8];
32 };
33
34 /*************************************************************************
35 * Interrupt handling for EP93xx on-chip GPIOs
36 *************************************************************************/
37 static unsigned char gpio_int_unmasked[3];
38 static unsigned char gpio_int_enabled[3];
39 static unsigned char gpio_int_type1[3];
40 static unsigned char gpio_int_type2[3];
41 static unsigned char gpio_int_debounce[3];
42
43 /* Port ordering is: A B F */
44 static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c };
45 static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 };
46 static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 };
47 static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 };
48 static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
49
50 static void ep93xx_gpio_update_int_params(unsigned port)
51 {
52 BUG_ON(port > 2);
53
54 __raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
55
56 __raw_writeb(gpio_int_type2[port],
57 EP93XX_GPIO_REG(int_type2_register_offset[port]));
58
59 __raw_writeb(gpio_int_type1[port],
60 EP93XX_GPIO_REG(int_type1_register_offset[port]));
61
62 __raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
63 EP93XX_GPIO_REG(int_en_register_offset[port]));
64 }
65
66 static void ep93xx_gpio_int_debounce(unsigned int irq, bool enable)
67 {
68 int line = irq_to_gpio(irq);
69 int port = line >> 3;
70 int port_mask = 1 << (line & 7);
71
72 if (enable)
73 gpio_int_debounce[port] |= port_mask;
74 else
75 gpio_int_debounce[port] &= ~port_mask;
76
77 __raw_writeb(gpio_int_debounce[port],
78 EP93XX_GPIO_REG(int_debounce_register_offset[port]));
79 }
80
81 static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
82 {
83 unsigned char status;
84 int i;
85
86 status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
87 for (i = 0; i < 8; i++) {
88 if (status & (1 << i)) {
89 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
90 generic_handle_irq(gpio_irq);
91 }
92 }
93
94 status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
95 for (i = 0; i < 8; i++) {
96 if (status & (1 << i)) {
97 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
98 generic_handle_irq(gpio_irq);
99 }
100 }
101 }
102
103 static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
104 {
105 /*
106 * map discontiguous hw irq range to continuous sw irq range:
107 *
108 * IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
109 */
110 int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
111 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
112
113 generic_handle_irq(gpio_irq);
114 }
115
116 static void ep93xx_gpio_irq_ack(struct irq_data *d)
117 {
118 int line = irq_to_gpio(d->irq);
119 int port = line >> 3;
120 int port_mask = 1 << (line & 7);
121
122 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
123 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
124 ep93xx_gpio_update_int_params(port);
125 }
126
127 __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
128 }
129
130 static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
131 {
132 int line = irq_to_gpio(d->irq);
133 int port = line >> 3;
134 int port_mask = 1 << (line & 7);
135
136 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
137 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
138
139 gpio_int_unmasked[port] &= ~port_mask;
140 ep93xx_gpio_update_int_params(port);
141
142 __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
143 }
144
145 static void ep93xx_gpio_irq_mask(struct irq_data *d)
146 {
147 int line = irq_to_gpio(d->irq);
148 int port = line >> 3;
149
150 gpio_int_unmasked[port] &= ~(1 << (line & 7));
151 ep93xx_gpio_update_int_params(port);
152 }
153
154 static void ep93xx_gpio_irq_unmask(struct irq_data *d)
155 {
156 int line = irq_to_gpio(d->irq);
157 int port = line >> 3;
158
159 gpio_int_unmasked[port] |= 1 << (line & 7);
160 ep93xx_gpio_update_int_params(port);
161 }
162
163 /*
164 * gpio_int_type1 controls whether the interrupt is level (0) or
165 * edge (1) triggered, while gpio_int_type2 controls whether it
166 * triggers on low/falling (0) or high/rising (1).
167 */
168 static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
169 {
170 const int gpio = irq_to_gpio(d->irq);
171 const int port = gpio >> 3;
172 const int port_mask = 1 << (gpio & 7);
173 irq_flow_handler_t handler;
174
175 gpio_direction_input(gpio);
176
177 switch (type) {
178 case IRQ_TYPE_EDGE_RISING:
179 gpio_int_type1[port] |= port_mask;
180 gpio_int_type2[port] |= port_mask;
181 handler = handle_edge_irq;
182 break;
183 case IRQ_TYPE_EDGE_FALLING:
184 gpio_int_type1[port] |= port_mask;
185 gpio_int_type2[port] &= ~port_mask;
186 handler = handle_edge_irq;
187 break;
188 case IRQ_TYPE_LEVEL_HIGH:
189 gpio_int_type1[port] &= ~port_mask;
190 gpio_int_type2[port] |= port_mask;
191 handler = handle_level_irq;
192 break;
193 case IRQ_TYPE_LEVEL_LOW:
194 gpio_int_type1[port] &= ~port_mask;
195 gpio_int_type2[port] &= ~port_mask;
196 handler = handle_level_irq;
197 break;
198 case IRQ_TYPE_EDGE_BOTH:
199 gpio_int_type1[port] |= port_mask;
200 /* set initial polarity based on current input level */
201 if (gpio_get_value(gpio))
202 gpio_int_type2[port] &= ~port_mask; /* falling */
203 else
204 gpio_int_type2[port] |= port_mask; /* rising */
205 handler = handle_edge_irq;
206 break;
207 default:
208 return -EINVAL;
209 }
210
211 __irq_set_handler_locked(d->irq, handler);
212
213 gpio_int_enabled[port] |= port_mask;
214
215 ep93xx_gpio_update_int_params(port);
216
217 return 0;
218 }
219
220 static struct irq_chip ep93xx_gpio_irq_chip = {
221 .name = "GPIO",
222 .irq_ack = ep93xx_gpio_irq_ack,
223 .irq_mask_ack = ep93xx_gpio_irq_mask_ack,
224 .irq_mask = ep93xx_gpio_irq_mask,
225 .irq_unmask = ep93xx_gpio_irq_unmask,
226 .irq_set_type = ep93xx_gpio_irq_type,
227 };
228
229 static void ep93xx_gpio_init_irq(void)
230 {
231 int gpio_irq;
232
233 for (gpio_irq = gpio_to_irq(0);
234 gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
235 irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip,
236 handle_level_irq);
237 set_irq_flags(gpio_irq, IRQF_VALID);
238 }
239
240 irq_set_chained_handler(IRQ_EP93XX_GPIO_AB,
241 ep93xx_gpio_ab_irq_handler);
242 irq_set_chained_handler(IRQ_EP93XX_GPIO0MUX,
243 ep93xx_gpio_f_irq_handler);
244 irq_set_chained_handler(IRQ_EP93XX_GPIO1MUX,
245 ep93xx_gpio_f_irq_handler);
246 irq_set_chained_handler(IRQ_EP93XX_GPIO2MUX,
247 ep93xx_gpio_f_irq_handler);
248 irq_set_chained_handler(IRQ_EP93XX_GPIO3MUX,
249 ep93xx_gpio_f_irq_handler);
250 irq_set_chained_handler(IRQ_EP93XX_GPIO4MUX,
251 ep93xx_gpio_f_irq_handler);
252 irq_set_chained_handler(IRQ_EP93XX_GPIO5MUX,
253 ep93xx_gpio_f_irq_handler);
254 irq_set_chained_handler(IRQ_EP93XX_GPIO6MUX,
255 ep93xx_gpio_f_irq_handler);
256 irq_set_chained_handler(IRQ_EP93XX_GPIO7MUX,
257 ep93xx_gpio_f_irq_handler);
258 }
259
260
261 /*************************************************************************
262 * gpiolib interface for EP93xx on-chip GPIOs
263 *************************************************************************/
264 struct ep93xx_gpio_bank {
265 const char *label;
266 int data;
267 int dir;
268 int base;
269 bool has_debounce;
270 };
271
272 #define EP93XX_GPIO_BANK(_label, _data, _dir, _base, _debounce) \
273 { \
274 .label = _label, \
275 .data = _data, \
276 .dir = _dir, \
277 .base = _base, \
278 .has_debounce = _debounce, \
279 }
280
281 static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = {
282 EP93XX_GPIO_BANK("A", 0x00, 0x10, 0, true),
283 EP93XX_GPIO_BANK("B", 0x04, 0x14, 8, true),
284 EP93XX_GPIO_BANK("C", 0x08, 0x18, 40, false),
285 EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24, false),
286 EP93XX_GPIO_BANK("E", 0x20, 0x24, 32, false),
287 EP93XX_GPIO_BANK("F", 0x30, 0x34, 16, true),
288 EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48, false),
289 EP93XX_GPIO_BANK("H", 0x40, 0x44, 56, false),
290 };
291
292 static int ep93xx_gpio_set_debounce(struct gpio_chip *chip,
293 unsigned offset, unsigned debounce)
294 {
295 int gpio = chip->base + offset;
296 int irq = gpio_to_irq(gpio);
297
298 if (irq < 0)
299 return -EINVAL;
300
301 ep93xx_gpio_int_debounce(irq, debounce ? true : false);
302
303 return 0;
304 }
305
306 /*
307 * Map GPIO A0..A7 (0..7) to irq 64..71,
308 * B0..B7 (7..15) to irq 72..79, and
309 * F0..F7 (16..24) to irq 80..87.
310 */
311 static int ep93xx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
312 {
313 int gpio = chip->base + offset;
314
315 if (gpio > EP93XX_GPIO_LINE_MAX_IRQ)
316 return -EINVAL;
317
318 return 64 + gpio;
319 }
320
321 static int ep93xx_gpio_add_bank(struct bgpio_chip *bgc, struct device *dev,
322 void __iomem *mmio_base, struct ep93xx_gpio_bank *bank)
323 {
324 void __iomem *data = mmio_base + bank->data;
325 void __iomem *dir = mmio_base + bank->dir;
326 int err;
327
328 err = bgpio_init(bgc, dev, 1, data, NULL, NULL, dir, NULL, 0);
329 if (err)
330 return err;
331
332 bgc->gc.label = bank->label;
333 bgc->gc.base = bank->base;
334
335 if (bank->has_debounce) {
336 bgc->gc.set_debounce = ep93xx_gpio_set_debounce;
337 bgc->gc.to_irq = ep93xx_gpio_to_irq;
338 }
339
340 return gpiochip_add(&bgc->gc);
341 }
342
343 static int ep93xx_gpio_probe(struct platform_device *pdev)
344 {
345 struct ep93xx_gpio *ep93xx_gpio;
346 struct resource *res;
347 void __iomem *mmio;
348 int i;
349 int ret;
350
351 ep93xx_gpio = kzalloc(sizeof(*ep93xx_gpio), GFP_KERNEL);
352 if (!ep93xx_gpio)
353 return -ENOMEM;
354
355 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
356 if (!res) {
357 ret = -ENXIO;
358 goto exit_free;
359 }
360
361 if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
362 ret = -EBUSY;
363 goto exit_free;
364 }
365
366 mmio = ioremap(res->start, resource_size(res));
367 if (!mmio) {
368 ret = -ENXIO;
369 goto exit_release;
370 }
371 ep93xx_gpio->mmio_base = mmio;
372
373 for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
374 struct bgpio_chip *bgc = &ep93xx_gpio->bgc[i];
375 struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i];
376
377 if (ep93xx_gpio_add_bank(bgc, &pdev->dev, mmio, bank))
378 dev_warn(&pdev->dev, "Unable to add gpio bank %s\n",
379 bank->label);
380 }
381
382 ep93xx_gpio_init_irq();
383
384 return 0;
385
386 exit_release:
387 release_mem_region(res->start, resource_size(res));
388 exit_free:
389 kfree(ep93xx_gpio);
390 dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, ret);
391 return ret;
392 }
393
394 static struct platform_driver ep93xx_gpio_driver = {
395 .driver = {
396 .name = "gpio-ep93xx",
397 .owner = THIS_MODULE,
398 },
399 .probe = ep93xx_gpio_probe,
400 };
401
402 static int __init ep93xx_gpio_init(void)
403 {
404 return platform_driver_register(&ep93xx_gpio_driver);
405 }
406 postcore_initcall(ep93xx_gpio_init);
407
408 MODULE_AUTHOR("Ryan Mallon <ryan@bluewatersys.com> "
409 "H Hartley Sweeten <hsweeten@visionengravers.com>");
410 MODULE_DESCRIPTION("EP93XX GPIO driver");
411 MODULE_LICENSE("GPL");
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