drivers/infiniband/hw/mlx5/mlx5_ib.h

   1 /*
   2  * Copyright (c) 2013, Mellanox Technologies inc.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef MLX5_IB_H
  34 #define MLX5_IB_H
  35
  36 #include <linux/kernel.h>
  37 #include <linux/sched.h>
  38 #include <rdma/ib_verbs.h>
  39 #include <rdma/ib_smi.h>
  40 #include <linux/mlx5/driver.h>
  41 #include <linux/mlx5/cq.h>
  42 #include <linux/mlx5/qp.h>
  43 #include <linux/mlx5/srq.h>
  44 #include <linux/types.h>
  45
  46 #define mlx5_ib_dbg(dev, format, arg...)                                \
  47 pr_debug("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__,    \
  48          __LINE__, current->pid, ##arg)
  49
  50 #define mlx5_ib_err(dev, format, arg...)                                \
  51 pr_err("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__,      \
  52         __LINE__, current->pid, ##arg)
  53
  54 #define mlx5_ib_warn(dev, format, arg...)                               \
  55 pr_warn("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__,     \
  56         __LINE__, current->pid, ##arg)
  57
  58 enum {
  59         MLX5_IB_MMAP_CMD_SHIFT  = 8,
  60         MLX5_IB_MMAP_CMD_MASK   = 0xff,
  61 };
  62
  63 enum mlx5_ib_mmap_cmd {
  64         MLX5_IB_MMAP_REGULAR_PAGE               = 0,
  65         MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES       = 1, /* always last */
  66 };
  67
  68 enum {
  69         MLX5_RES_SCAT_DATA32_CQE        = 0x1,
  70         MLX5_RES_SCAT_DATA64_CQE        = 0x2,
  71         MLX5_REQ_SCAT_DATA32_CQE        = 0x11,
  72         MLX5_REQ_SCAT_DATA64_CQE        = 0x22,
  73 };
  74
  75 enum mlx5_ib_latency_class {
  76         MLX5_IB_LATENCY_CLASS_LOW,
  77         MLX5_IB_LATENCY_CLASS_MEDIUM,
  78         MLX5_IB_LATENCY_CLASS_HIGH,
  79         MLX5_IB_LATENCY_CLASS_FAST_PATH
  80 };
  81
  82 enum mlx5_ib_mad_ifc_flags {
  83         MLX5_MAD_IFC_IGNORE_MKEY        = 1,
  84         MLX5_MAD_IFC_IGNORE_BKEY        = 2,
  85         MLX5_MAD_IFC_NET_VIEW           = 4,
  86 };
  87
  88 struct mlx5_ib_ucontext {
  89         struct ib_ucontext      ibucontext;
  90         struct list_head        db_page_list;
  91
  92         /* protect doorbell record alloc/free
  93          */
  94         struct mutex            db_page_mutex;
  95         struct mlx5_uuar_info   uuari;
  96 };
  97
  98 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext)
  99 {
 100         return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext);
 101 }
 102
 103 struct mlx5_ib_pd {
 104         struct ib_pd            ibpd;
 105         u32                     pdn;
 106         u32                     pa_lkey;
 107 };
 108
 109 /* Use macros here so that don't have to duplicate
 110  * enum ib_send_flags and enum ib_qp_type for low-level driver
 111  */
 112
 113 #define MLX5_IB_SEND_UMR_UNREG  IB_SEND_RESERVED_START
 114 #define MLX5_IB_QPT_REG_UMR     IB_QPT_RESERVED1
 115 #define MLX5_IB_WR_UMR          IB_WR_RESERVED1
 116
 117 struct wr_list {
 118         u16     opcode;
 119         u16     next;
 120 };
 121
 122 struct mlx5_ib_wq {
 123         u64                    *wrid;
 124         u32                    *wr_data;
 125         struct wr_list         *w_list;
 126         unsigned               *wqe_head;
 127         u16                     unsig_count;
 128
 129         /* serialize post to the work queue
 130          */
 131         spinlock_t              lock;
 132         int                     wqe_cnt;
 133         int                     max_post;
 134         int                     max_gs;
 135         int                     offset;
 136         int                     wqe_shift;
 137         unsigned                head;
 138         unsigned                tail;
 139         u16                     cur_post;
 140         u16                     last_poll;
 141         void                   *qend;
 142 };
 143
 144 enum {
 145         MLX5_QP_USER,
 146         MLX5_QP_KERNEL,
 147         MLX5_QP_EMPTY
 148 };
 149
 150 struct mlx5_ib_qp {
 151         struct ib_qp            ibqp;
 152         struct mlx5_core_qp     mqp;
 153         struct mlx5_buf         buf;
 154
 155         struct mlx5_db          db;
 156         struct mlx5_ib_wq       rq;
 157
 158         u32                     doorbell_qpn;
 159         u8                      sq_signal_bits;
 160         u8                      fm_cache;
 161         int                     sq_max_wqes_per_wr;
 162         int                     sq_spare_wqes;
 163         struct mlx5_ib_wq       sq;
 164
 165         struct ib_umem         *umem;
 166         int                     buf_size;
 167
 168         /* serialize qp state modifications
 169          */
 170         struct mutex            mutex;
 171         u16                     xrcdn;
 172         u32                     flags;
 173         u8                      port;
 174         u8                      alt_port;
 175         u8                      atomic_rd_en;
 176         u8                      resp_depth;
 177         u8                      state;
 178         int                     mlx_type;
 179         int                     wq_sig;
 180         int                     scat_cqe;
 181         int                     max_inline_data;
 182         struct mlx5_bf         *bf;
 183         int                     has_rq;
 184
 185         /* only for user space QPs. For kernel
 186          * we have it from the bf object
 187          */
 188         int                     uuarn;
 189
 190         int                     create_type;
 191         u32                     pa_lkey;
 192 };
 193
 194 struct mlx5_ib_cq_buf {
 195         struct mlx5_buf         buf;
 196         struct ib_umem          *umem;
 197         int                     cqe_size;
 198 };
 199
 200 enum mlx5_ib_qp_flags {
 201         MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK     = 1 << 0,
 202         MLX5_IB_QP_SIGNATURE_HANDLING           = 1 << 1,
 203 };
 204
 205 struct mlx5_shared_mr_info {
 206         int mr_id;
 207         struct ib_umem          *umem;
 208 };
 209
 210 struct mlx5_ib_cq {
 211         struct ib_cq            ibcq;
 212         struct mlx5_core_cq     mcq;
 213         struct mlx5_ib_cq_buf   buf;
 214         struct mlx5_db          db;
 215
 216         /* serialize access to the CQ
 217          */
 218         spinlock_t              lock;
 219
 220         /* protect resize cq
 221          */
 222         struct mutex            resize_mutex;
 223         struct mlx5_ib_cq_resize *resize_buf;
 224         struct ib_umem         *resize_umem;
 225         int                     cqe_size;
 226 };
 227
 228 struct mlx5_ib_srq {
 229         struct ib_srq           ibsrq;
 230         struct mlx5_core_srq    msrq;
 231         struct mlx5_buf         buf;
 232         struct mlx5_db          db;
 233         u64                    *wrid;
 234         /* protect SRQ hanlding
 235          */
 236         spinlock_t              lock;
 237         int                     head;
 238         int                     tail;
 239         u16                     wqe_ctr;
 240         struct ib_umem         *umem;
 241         /* serialize arming a SRQ
 242          */
 243         struct mutex            mutex;
 244         int                     wq_sig;
 245 };
 246
 247 struct mlx5_ib_xrcd {
 248         struct ib_xrcd          ibxrcd;
 249         u32                     xrcdn;
 250 };
 251
 252 struct mlx5_ib_mr {
 253         struct ib_mr            ibmr;
 254         struct mlx5_core_mr     mmr;
 255         struct ib_umem         *umem;
 256         struct mlx5_shared_mr_info      *smr_info;
 257         struct list_head        list;
 258         int                     order;
 259         int                     umred;
 260         __be64                  *pas;
 261         dma_addr_t              dma;
 262         int                     npages;
 263         struct completion       done;
 264         enum ib_wc_status       status;
 265 };
 266
 267 struct mlx5_ib_fast_reg_page_list {
 268         struct ib_fast_reg_page_list    ibfrpl;
 269         __be64                         *mapped_page_list;
 270         dma_addr_t                      map;
 271 };
 272
 273 struct umr_common {
 274         struct ib_pd    *pd;
 275         struct ib_cq    *cq;
 276         struct ib_qp    *qp;
 277         struct ib_mr    *mr;
 278         /* control access to UMR QP
 279          */
 280         struct semaphore        sem;
 281 };
 282
 283 enum {
 284         MLX5_FMR_INVALID,
 285         MLX5_FMR_VALID,
 286         MLX5_FMR_BUSY,
 287 };
 288
 289 struct mlx5_ib_fmr {
 290         struct ib_fmr                   ibfmr;
 291         struct mlx5_core_mr             mr;
 292         int                             access_flags;
 293         int                             state;
 294         /* protect fmr state
 295          */
 296         spinlock_t                      lock;
 297         u64                             wrid;
 298         struct ib_send_wr               wr[2];
 299         u8                              page_shift;
 300         struct ib_fast_reg_page_list    page_list;
 301 };
 302
 303 struct mlx5_cache_ent {
 304         struct list_head        head;
 305         /* sync access to the cahce entry
 306          */
 307         spinlock_t              lock;
 308
 309
 310         struct dentry          *dir;
 311         char                    name[4];
 312         u32                     order;
 313         u32                     size;
 314         u32                     cur;
 315         u32                     miss;
 316         u32                     limit;
 317
 318         struct dentry          *fsize;
 319         struct dentry          *fcur;
 320         struct dentry          *fmiss;
 321         struct dentry          *flimit;
 322
 323         struct mlx5_ib_dev     *dev;
 324         struct work_struct      work;
 325         struct delayed_work     dwork;
 326 };
 327
 328 struct mlx5_mr_cache {
 329         struct workqueue_struct *wq;
 330         struct mlx5_cache_ent   ent[MAX_MR_CACHE_ENTRIES];
 331         int                     stopped;
 332         struct dentry           *root;
 333         unsigned long           last_add;
 334 };
 335
 336 struct mlx5_ib_resources {
 337         struct ib_cq    *c0;
 338         struct ib_xrcd  *x0;
 339         struct ib_xrcd  *x1;
 340         struct ib_pd    *p0;
 341         struct ib_srq   *s0;
 342 };
 343
 344 struct mlx5_ib_dev {
 345         struct ib_device                ib_dev;
 346         struct mlx5_core_dev            mdev;
 347         MLX5_DECLARE_DOORBELL_LOCK(uar_lock);
 348         struct list_head                eqs_list;
 349         int                             num_ports;
 350         int                             num_comp_vectors;
 351         /* serialize update of capability mask
 352          */
 353         struct mutex                    cap_mask_mutex;
 354         bool                            ib_active;
 355         struct umr_common               umrc;
 356         /* sync used page count stats
 357          */
 358         spinlock_t                      mr_lock;
 359         struct mlx5_ib_resources        devr;
 360         struct mlx5_mr_cache            cache;
 361 };
 362
 363 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq)
 364 {
 365         return container_of(mcq, struct mlx5_ib_cq, mcq);
 366 }
 367
 368 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd)
 369 {
 370         return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd);
 371 }
 372
 373 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev)
 374 {
 375         return container_of(ibdev, struct mlx5_ib_dev, ib_dev);
 376 }
 377
 378 static inline struct mlx5_ib_fmr *to_mfmr(struct ib_fmr *ibfmr)
 379 {
 380         return container_of(ibfmr, struct mlx5_ib_fmr, ibfmr);
 381 }
 382
 383 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq)
 384 {
 385         return container_of(ibcq, struct mlx5_ib_cq, ibcq);
 386 }
 387
 388 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp)
 389 {
 390         return container_of(mqp, struct mlx5_ib_qp, mqp);
 391 }
 392
 393 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd)
 394 {
 395         return container_of(ibpd, struct mlx5_ib_pd, ibpd);
 396 }
 397
 398 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq)
 399 {
 400         return container_of(ibsrq, struct mlx5_ib_srq, ibsrq);
 401 }
 402
 403 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp)
 404 {
 405         return container_of(ibqp, struct mlx5_ib_qp, ibqp);
 406 }
 407
 408 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq)
 409 {
 410         return container_of(msrq, struct mlx5_ib_srq, msrq);
 411 }
 412
 413 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr)
 414 {
 415         return container_of(ibmr, struct mlx5_ib_mr, ibmr);
 416 }
 417
 418 static inline struct mlx5_ib_fast_reg_page_list *to_mfrpl(struct ib_fast_reg_page_list *ibfrpl)
 419 {
 420         return container_of(ibfrpl, struct mlx5_ib_fast_reg_page_list, ibfrpl);
 421 }
 422
 423 struct mlx5_ib_ah {
 424         struct ib_ah            ibah;
 425         struct mlx5_av          av;
 426 };
 427
 428 static inline struct mlx5_ib_ah *to_mah(struct ib_ah *ibah)
 429 {
 430         return container_of(ibah, struct mlx5_ib_ah, ibah);
 431 }
 432
 433 static inline struct mlx5_ib_dev *mlx5_core2ibdev(struct mlx5_core_dev *dev)
 434 {
 435         return container_of(dev, struct mlx5_ib_dev, mdev);
 436 }
 437
 438 static inline struct mlx5_ib_dev *mlx5_pci2ibdev(struct pci_dev *pdev)
 439 {
 440         return mlx5_core2ibdev(pci2mlx5_core_dev(pdev));
 441 }
 442
 443 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt,
 444                         struct mlx5_db *db);
 445 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db);
 446 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
 447 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
 448 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index);
 449 int mlx5_MAD_IFC(struct mlx5_ib_dev *dev, int ignore_mkey, int ignore_bkey,
 450                  int port, struct ib_wc *in_wc, struct ib_grh *in_grh,
 451                  void *in_mad, void *response_mad);
 452 struct ib_ah *create_ib_ah(struct ib_ah_attr *ah_attr,
 453                            struct mlx5_ib_ah *ah);
 454 struct ib_ah *mlx5_ib_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr);
 455 int mlx5_ib_query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr);
 456 int mlx5_ib_destroy_ah(struct ib_ah *ah);
 457 struct ib_srq *mlx5_ib_create_srq(struct ib_pd *pd,
 458                                   struct ib_srq_init_attr *init_attr,
 459                                   struct ib_udata *udata);
 460 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
 461                        enum ib_srq_attr_mask attr_mask, struct ib_udata *udata);
 462 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr);
 463 int mlx5_ib_destroy_srq(struct ib_srq *srq);
 464 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr,
 465                           struct ib_recv_wr **bad_wr);
 466 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
 467                                 struct ib_qp_init_attr *init_attr,
 468                                 struct ib_udata *udata);
 469 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
 470                       int attr_mask, struct ib_udata *udata);
 471 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
 472                      struct ib_qp_init_attr *qp_init_attr);
 473 int mlx5_ib_destroy_qp(struct ib_qp *qp);
 474 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
 475                       struct ib_send_wr **bad_wr);
 476 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
 477                       struct ib_recv_wr **bad_wr);
 478 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n);
 479 struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev, int entries,
 480                                 int vector, struct ib_ucontext *context,
 481                                 struct ib_udata *udata);
 482 int mlx5_ib_destroy_cq(struct ib_cq *cq);
 483 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
 484 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
 485 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period);
 486 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata);
 487 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc);
 488 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
 489                                   u64 virt_addr, int access_flags,
 490                                   struct ib_udata *udata);
 491 int mlx5_ib_dereg_mr(struct ib_mr *ibmr);
 492 struct ib_mr *mlx5_ib_alloc_fast_reg_mr(struct ib_pd *pd,
 493                                         int max_page_list_len);
 494 struct ib_fast_reg_page_list *mlx5_ib_alloc_fast_reg_page_list(struct ib_device *ibdev,
 495                                                                int page_list_len);
 496 void mlx5_ib_free_fast_reg_page_list(struct ib_fast_reg_page_list *page_list);
 497 struct ib_fmr *mlx5_ib_fmr_alloc(struct ib_pd *pd, int acc,
 498                                  struct ib_fmr_attr *fmr_attr);
 499 int mlx5_ib_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list,
 500                       int npages, u64 iova);
 501 int mlx5_ib_unmap_fmr(struct list_head *fmr_list);
 502 int mlx5_ib_fmr_dealloc(struct ib_fmr *ibfmr);
 503 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num,
 504                         struct ib_wc *in_wc, struct ib_grh *in_grh,
 505                         struct ib_mad *in_mad, struct ib_mad *out_mad);
 506 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
 507                                           struct ib_ucontext *context,
 508                                           struct ib_udata *udata);
 509 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd);
 510 int mlx5_vector2eqn(struct mlx5_ib_dev *dev, int vector, int *eqn, int *irqn);
 511 int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset);
 512 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port);
 513 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
 514                        struct ib_port_attr *props);
 515 int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev);
 516 void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev);
 517 void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr, int *count, int *shift,
 518                         int *ncont, int *order);
 519 void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
 520                           int page_shift, __be64 *pas, int umr);
 521 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num);
 522 int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq);
 523 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev);
 524 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev);
 525 int mlx5_mr_ib_cont_pages(struct ib_umem *umem, u64 addr, int *count, int *shift);
 526 void mlx5_umr_cq_handler(struct ib_cq *cq, void *cq_context);
 527
 528 static inline void init_query_mad(struct ib_smp *mad)
 529 {
 530         mad->base_version  = 1;
 531         mad->mgmt_class    = IB_MGMT_CLASS_SUBN_LID_ROUTED;
 532         mad->class_version = 1;
 533         mad->method        = IB_MGMT_METHOD_GET;
 534 }
 535
 536 static inline u8 convert_access(int acc)
 537 {
 538         return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC       : 0) |
 539                (acc & IB_ACCESS_REMOTE_WRITE  ? MLX5_PERM_REMOTE_WRITE : 0) |
 540                (acc & IB_ACCESS_REMOTE_READ   ? MLX5_PERM_REMOTE_READ  : 0) |
 541                (acc & IB_ACCESS_LOCAL_WRITE   ? MLX5_PERM_LOCAL_WRITE  : 0) |
 542                MLX5_PERM_LOCAL_READ;
 543 }
 544
 545 #endif /* MLX5_IB_H */