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Linux 3.11-rc3
[cris-mirror.git] / drivers / infiniband / hw / ocrdma / ocrdma_hw.c
blob0965278dd2ed7e805f7c1a8e1d9eae03b9c3765b
1 /*******************************************************************
2 * This file is part of the Emulex RoCE Device Driver for *
3 * RoCE (RDMA over Converged Ethernet) CNA Adapters. *
4 * Copyright (C) 2008-2012 Emulex. All rights reserved. *
5 * EMULEX and SLI are trademarks of Emulex. *
6 * www.emulex.com *
7 * *
8 * This program is free software; you can redistribute it and/or *
9 * modify it under the terms of version 2 of the GNU General *
10 * Public License as published by the Free Software Foundation. *
11 * This program is distributed in the hope that it will be useful. *
12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16 * TO BE LEGALLY INVALID. See the GNU General Public License for *
17 * more details, a copy of which can be found in the file COPYING *
18 * included with this package. *
19 *
20 * Contact Information:
21 * linux-drivers@emulex.com
22 *
23 * Emulex
24 * 3333 Susan Street
25 * Costa Mesa, CA 92626
26 *******************************************************************/
27
28 #include <linux/sched.h>
29 #include <linux/interrupt.h>
30 #include <linux/log2.h>
31 #include <linux/dma-mapping.h>
32
33 #include <rdma/ib_verbs.h>
34 #include <rdma/ib_user_verbs.h>
35 #include <rdma/ib_addr.h>
36
37 #include "ocrdma.h"
38 #include "ocrdma_hw.h"
39 #include "ocrdma_verbs.h"
40 #include "ocrdma_ah.h"
41
42 enum mbx_status {
43 OCRDMA_MBX_STATUS_FAILED = 1,
44 OCRDMA_MBX_STATUS_ILLEGAL_FIELD = 3,
45 OCRDMA_MBX_STATUS_OOR = 100,
46 OCRDMA_MBX_STATUS_INVALID_PD = 101,
47 OCRDMA_MBX_STATUS_PD_INUSE = 102,
48 OCRDMA_MBX_STATUS_INVALID_CQ = 103,
49 OCRDMA_MBX_STATUS_INVALID_QP = 104,
50 OCRDMA_MBX_STATUS_INVALID_LKEY = 105,
51 OCRDMA_MBX_STATUS_ORD_EXCEEDS = 106,
52 OCRDMA_MBX_STATUS_IRD_EXCEEDS = 107,
53 OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS = 108,
54 OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS = 109,
55 OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS = 110,
56 OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS = 111,
57 OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS = 112,
58 OCRDMA_MBX_STATUS_INVALID_STATE_CHANGE = 113,
59 OCRDMA_MBX_STATUS_MW_BOUND = 114,
60 OCRDMA_MBX_STATUS_INVALID_VA = 115,
61 OCRDMA_MBX_STATUS_INVALID_LENGTH = 116,
62 OCRDMA_MBX_STATUS_INVALID_FBO = 117,
63 OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS = 118,
64 OCRDMA_MBX_STATUS_INVALID_PBE_SIZE = 119,
65 OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY = 120,
66 OCRDMA_MBX_STATUS_INVALID_PBL_SHIFT = 121,
67 OCRDMA_MBX_STATUS_INVALID_SRQ_ID = 129,
68 OCRDMA_MBX_STATUS_SRQ_ERROR = 133,
69 OCRDMA_MBX_STATUS_RQE_EXCEEDS = 134,
70 OCRDMA_MBX_STATUS_MTU_EXCEEDS = 135,
71 OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS = 136,
72 OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS = 137,
73 OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS = 138,
74 OCRDMA_MBX_STATUS_QP_BOUND = 130,
75 OCRDMA_MBX_STATUS_INVALID_CHANGE = 139,
76 OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP = 140,
77 OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER = 141,
78 OCRDMA_MBX_STATUS_MW_STILL_BOUND = 142,
79 OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID = 143,
80 OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS = 144
81 };
82
83 enum additional_status {
84 OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES = 22
85 };
86
87 enum cqe_status {
88 OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES = 1,
89 OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER = 2,
90 OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES = 3,
91 OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING = 4,
92 OCRDMA_MBX_CQE_STATUS_DMA_FAILED = 5
93 };
94
95 static inline void *ocrdma_get_eqe(struct ocrdma_eq *eq)
96 {
97 return (u8 *)eq->q.va + (eq->q.tail * sizeof(struct ocrdma_eqe));
98 }
99
100 static inline void ocrdma_eq_inc_tail(struct ocrdma_eq *eq)
101 {
102 eq->q.tail = (eq->q.tail + 1) & (OCRDMA_EQ_LEN - 1);
103 }
104
105 static inline void *ocrdma_get_mcqe(struct ocrdma_dev *dev)
106 {
107 struct ocrdma_mcqe *cqe = (struct ocrdma_mcqe *)
108 ((u8 *) dev->mq.cq.va +
109 (dev->mq.cq.tail * sizeof(struct ocrdma_mcqe)));
110
111 if (!(le32_to_cpu(cqe->valid_ae_cmpl_cons) & OCRDMA_MCQE_VALID_MASK))
112 return NULL;
113 return cqe;
114 }
115
116 static inline void ocrdma_mcq_inc_tail(struct ocrdma_dev *dev)
117 {
118 dev->mq.cq.tail = (dev->mq.cq.tail + 1) & (OCRDMA_MQ_CQ_LEN - 1);
119 }
120
121 static inline struct ocrdma_mqe *ocrdma_get_mqe(struct ocrdma_dev *dev)
122 {
123 return (struct ocrdma_mqe *)((u8 *) dev->mq.sq.va +
124 (dev->mq.sq.head *
125 sizeof(struct ocrdma_mqe)));
126 }
127
128 static inline void ocrdma_mq_inc_head(struct ocrdma_dev *dev)
129 {
130 dev->mq.sq.head = (dev->mq.sq.head + 1) & (OCRDMA_MQ_LEN - 1);
131 }
132
133 static inline void *ocrdma_get_mqe_rsp(struct ocrdma_dev *dev)
134 {
135 return (void *)((u8 *) dev->mq.sq.va +
136 (dev->mqe_ctx.tag * sizeof(struct ocrdma_mqe)));
137 }
138
139 enum ib_qp_state get_ibqp_state(enum ocrdma_qp_state qps)
140 {
141 switch (qps) {
142 case OCRDMA_QPS_RST:
143 return IB_QPS_RESET;
144 case OCRDMA_QPS_INIT:
145 return IB_QPS_INIT;
146 case OCRDMA_QPS_RTR:
147 return IB_QPS_RTR;
148 case OCRDMA_QPS_RTS:
149 return IB_QPS_RTS;
150 case OCRDMA_QPS_SQD:
151 case OCRDMA_QPS_SQ_DRAINING:
152 return IB_QPS_SQD;
153 case OCRDMA_QPS_SQE:
154 return IB_QPS_SQE;
155 case OCRDMA_QPS_ERR:
156 return IB_QPS_ERR;
157 };
158 return IB_QPS_ERR;
159 }
160
161 static enum ocrdma_qp_state get_ocrdma_qp_state(enum ib_qp_state qps)
162 {
163 switch (qps) {
164 case IB_QPS_RESET:
165 return OCRDMA_QPS_RST;
166 case IB_QPS_INIT:
167 return OCRDMA_QPS_INIT;
168 case IB_QPS_RTR:
169 return OCRDMA_QPS_RTR;
170 case IB_QPS_RTS:
171 return OCRDMA_QPS_RTS;
172 case IB_QPS_SQD:
173 return OCRDMA_QPS_SQD;
174 case IB_QPS_SQE:
175 return OCRDMA_QPS_SQE;
176 case IB_QPS_ERR:
177 return OCRDMA_QPS_ERR;
178 };
179 return OCRDMA_QPS_ERR;
180 }
181
182 static int ocrdma_get_mbx_errno(u32 status)
183 {
184 int err_num = -EFAULT;
185 u8 mbox_status = (status & OCRDMA_MBX_RSP_STATUS_MASK) >>
186 OCRDMA_MBX_RSP_STATUS_SHIFT;
187 u8 add_status = (status & OCRDMA_MBX_RSP_ASTATUS_MASK) >>
188 OCRDMA_MBX_RSP_ASTATUS_SHIFT;
189
190 switch (mbox_status) {
191 case OCRDMA_MBX_STATUS_OOR:
192 case OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS:
193 err_num = -EAGAIN;
194 break;
195
196 case OCRDMA_MBX_STATUS_INVALID_PD:
197 case OCRDMA_MBX_STATUS_INVALID_CQ:
198 case OCRDMA_MBX_STATUS_INVALID_SRQ_ID:
199 case OCRDMA_MBX_STATUS_INVALID_QP:
200 case OCRDMA_MBX_STATUS_INVALID_CHANGE:
201 case OCRDMA_MBX_STATUS_MTU_EXCEEDS:
202 case OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER:
203 case OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID:
204 case OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS:
205 case OCRDMA_MBX_STATUS_ILLEGAL_FIELD:
206 case OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY:
207 case OCRDMA_MBX_STATUS_INVALID_LKEY:
208 case OCRDMA_MBX_STATUS_INVALID_VA:
209 case OCRDMA_MBX_STATUS_INVALID_LENGTH:
210 case OCRDMA_MBX_STATUS_INVALID_FBO:
211 case OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS:
212 case OCRDMA_MBX_STATUS_INVALID_PBE_SIZE:
213 case OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP:
214 case OCRDMA_MBX_STATUS_SRQ_ERROR:
215 case OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS:
216 err_num = -EINVAL;
217 break;
218
219 case OCRDMA_MBX_STATUS_PD_INUSE:
220 case OCRDMA_MBX_STATUS_QP_BOUND:
221 case OCRDMA_MBX_STATUS_MW_STILL_BOUND:
222 case OCRDMA_MBX_STATUS_MW_BOUND:
223 err_num = -EBUSY;
224 break;
225
226 case OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS:
227 case OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS:
228 case OCRDMA_MBX_STATUS_RQE_EXCEEDS:
229 case OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS:
230 case OCRDMA_MBX_STATUS_ORD_EXCEEDS:
231 case OCRDMA_MBX_STATUS_IRD_EXCEEDS:
232 case OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS:
233 case OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS:
234 case OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS:
235 err_num = -ENOBUFS;
236 break;
237
238 case OCRDMA_MBX_STATUS_FAILED:
239 switch (add_status) {
240 case OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES:
241 err_num = -EAGAIN;
242 break;
243 }
244 default:
245 err_num = -EFAULT;
246 }
247 return err_num;
248 }
249
250 static int ocrdma_get_mbx_cqe_errno(u16 cqe_status)
251 {
252 int err_num = -EINVAL;
253
254 switch (cqe_status) {
255 case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES:
256 err_num = -EPERM;
257 break;
258 case OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER:
259 err_num = -EINVAL;
260 break;
261 case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES:
262 case OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING:
263 err_num = -EAGAIN;
264 break;
265 case OCRDMA_MBX_CQE_STATUS_DMA_FAILED:
266 err_num = -EIO;
267 break;
268 }
269 return err_num;
270 }
271
272 void ocrdma_ring_cq_db(struct ocrdma_dev *dev, u16 cq_id, bool armed,
273 bool solicited, u16 cqe_popped)
274 {
275 u32 val = cq_id & OCRDMA_DB_CQ_RING_ID_MASK;
276
277 val |= ((cq_id & OCRDMA_DB_CQ_RING_ID_EXT_MASK) <<
278 OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT);
279
280 if (armed)
281 val |= (1 << OCRDMA_DB_CQ_REARM_SHIFT);
282 if (solicited)
283 val |= (1 << OCRDMA_DB_CQ_SOLICIT_SHIFT);
284 val |= (cqe_popped << OCRDMA_DB_CQ_NUM_POPPED_SHIFT);
285 iowrite32(val, dev->nic_info.db + OCRDMA_DB_CQ_OFFSET);
286 }
287
288 static void ocrdma_ring_mq_db(struct ocrdma_dev *dev)
289 {
290 u32 val = 0;
291
292 val |= dev->mq.sq.id & OCRDMA_MQ_ID_MASK;
293 val |= 1 << OCRDMA_MQ_NUM_MQE_SHIFT;
294 iowrite32(val, dev->nic_info.db + OCRDMA_DB_MQ_OFFSET);
295 }
296
297 static void ocrdma_ring_eq_db(struct ocrdma_dev *dev, u16 eq_id,
298 bool arm, bool clear_int, u16 num_eqe)
299 {
300 u32 val = 0;
301
302 val |= eq_id & OCRDMA_EQ_ID_MASK;
303 val |= ((eq_id & OCRDMA_EQ_ID_EXT_MASK) << OCRDMA_EQ_ID_EXT_MASK_SHIFT);
304 if (arm)
305 val |= (1 << OCRDMA_REARM_SHIFT);
306 if (clear_int)
307 val |= (1 << OCRDMA_EQ_CLR_SHIFT);
308 val |= (1 << OCRDMA_EQ_TYPE_SHIFT);
309 val |= (num_eqe << OCRDMA_NUM_EQE_SHIFT);
310 iowrite32(val, dev->nic_info.db + OCRDMA_DB_EQ_OFFSET);
311 }
312
313 static void ocrdma_init_mch(struct ocrdma_mbx_hdr *cmd_hdr,
314 u8 opcode, u8 subsys, u32 cmd_len)
315 {
316 cmd_hdr->subsys_op = (opcode | (subsys << OCRDMA_MCH_SUBSYS_SHIFT));
317 cmd_hdr->timeout = 20; /* seconds */
318 cmd_hdr->cmd_len = cmd_len - sizeof(struct ocrdma_mbx_hdr);
319 }
320
321 static void *ocrdma_init_emb_mqe(u8 opcode, u32 cmd_len)
322 {
323 struct ocrdma_mqe *mqe;
324
325 mqe = kzalloc(sizeof(struct ocrdma_mqe), GFP_KERNEL);
326 if (!mqe)
327 return NULL;
328 mqe->hdr.spcl_sge_cnt_emb |=
329 (OCRDMA_MQE_EMBEDDED << OCRDMA_MQE_HDR_EMB_SHIFT) &
330 OCRDMA_MQE_HDR_EMB_MASK;
331 mqe->hdr.pyld_len = cmd_len - sizeof(struct ocrdma_mqe_hdr);
332
333 ocrdma_init_mch(&mqe->u.emb_req.mch, opcode, OCRDMA_SUBSYS_ROCE,
334 mqe->hdr.pyld_len);
335 return mqe;
336 }
337
338 static void ocrdma_free_q(struct ocrdma_dev *dev, struct ocrdma_queue_info *q)
339 {
340 dma_free_coherent(&dev->nic_info.pdev->dev, q->size, q->va, q->dma);
341 }
342
343 static int ocrdma_alloc_q(struct ocrdma_dev *dev,
344 struct ocrdma_queue_info *q, u16 len, u16 entry_size)
345 {
346 memset(q, 0, sizeof(*q));
347 q->len = len;
348 q->entry_size = entry_size;
349 q->size = len * entry_size;
350 q->va = dma_alloc_coherent(&dev->nic_info.pdev->dev, q->size,
351 &q->dma, GFP_KERNEL);
352 if (!q->va)
353 return -ENOMEM;
354 memset(q->va, 0, q->size);
355 return 0;
356 }
357
358 static void ocrdma_build_q_pages(struct ocrdma_pa *q_pa, int cnt,
359 dma_addr_t host_pa, int hw_page_size)
360 {
361 int i;
362
363 for (i = 0; i < cnt; i++) {
364 q_pa[i].lo = (u32) (host_pa & 0xffffffff);
365 q_pa[i].hi = (u32) upper_32_bits(host_pa);
366 host_pa += hw_page_size;
367 }
368 }
369
370 static void ocrdma_assign_eq_vect_gen2(struct ocrdma_dev *dev,
371 struct ocrdma_eq *eq)
372 {
373 /* assign vector and update vector id for next EQ */
374 eq->vector = dev->nic_info.msix.start_vector;
375 dev->nic_info.msix.start_vector += 1;
376 }
377
378 static void ocrdma_free_eq_vect_gen2(struct ocrdma_dev *dev)
379 {
380 /* this assumes that EQs are freed in exactly reverse order
381 * as its allocation.
382 */
383 dev->nic_info.msix.start_vector -= 1;
384 }
385
386 static int ocrdma_mbx_delete_q(struct ocrdma_dev *dev, struct ocrdma_queue_info *q,
387 int queue_type)
388 {
389 u8 opcode = 0;
390 int status;
391 struct ocrdma_delete_q_req *cmd = dev->mbx_cmd;
392
393 switch (queue_type) {
394 case QTYPE_MCCQ:
395 opcode = OCRDMA_CMD_DELETE_MQ;
396 break;
397 case QTYPE_CQ:
398 opcode = OCRDMA_CMD_DELETE_CQ;
399 break;
400 case QTYPE_EQ:
401 opcode = OCRDMA_CMD_DELETE_EQ;
402 break;
403 default:
404 BUG();
405 }
406 memset(cmd, 0, sizeof(*cmd));
407 ocrdma_init_mch(&cmd->req, opcode, OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
408 cmd->id = q->id;
409
410 status = be_roce_mcc_cmd(dev->nic_info.netdev,
411 cmd, sizeof(*cmd), NULL, NULL);
412 if (!status)
413 q->created = false;
414 return status;
415 }
416
417 static int ocrdma_mbx_create_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
418 {
419 int status;
420 struct ocrdma_create_eq_req *cmd = dev->mbx_cmd;
421 struct ocrdma_create_eq_rsp *rsp = dev->mbx_cmd;
422
423 memset(cmd, 0, sizeof(*cmd));
424 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_EQ, OCRDMA_SUBSYS_COMMON,
425 sizeof(*cmd));
426 if (dev->nic_info.dev_family == OCRDMA_GEN2_FAMILY)
427 cmd->req.rsvd_version = 0;
428 else
429 cmd->req.rsvd_version = 2;
430
431 cmd->num_pages = 4;
432 cmd->valid = OCRDMA_CREATE_EQ_VALID;
433 cmd->cnt = 4 << OCRDMA_CREATE_EQ_CNT_SHIFT;
434
435 ocrdma_build_q_pages(&cmd->pa[0], cmd->num_pages, eq->q.dma,
436 PAGE_SIZE_4K);
437 status = be_roce_mcc_cmd(dev->nic_info.netdev, cmd, sizeof(*cmd), NULL,
438 NULL);
439 if (!status) {
440 eq->q.id = rsp->vector_eqid & 0xffff;
441 if (dev->nic_info.dev_family == OCRDMA_GEN2_FAMILY)
442 ocrdma_assign_eq_vect_gen2(dev, eq);
443 else {
444 eq->vector = (rsp->vector_eqid >> 16) & 0xffff;
445 dev->nic_info.msix.start_vector += 1;
446 }
447 eq->q.created = true;
448 }
449 return status;
450 }
451
452 static int ocrdma_create_eq(struct ocrdma_dev *dev,
453 struct ocrdma_eq *eq, u16 q_len)
454 {
455 int status;
456
457 status = ocrdma_alloc_q(dev, &eq->q, OCRDMA_EQ_LEN,
458 sizeof(struct ocrdma_eqe));
459 if (status)
460 return status;
461
462 status = ocrdma_mbx_create_eq(dev, eq);
463 if (status)
464 goto mbx_err;
465 eq->dev = dev;
466 ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
467
468 return 0;
469 mbx_err:
470 ocrdma_free_q(dev, &eq->q);
471 return status;
472 }
473
474 static int ocrdma_get_irq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
475 {
476 int irq;
477
478 if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX)
479 irq = dev->nic_info.pdev->irq;
480 else
481 irq = dev->nic_info.msix.vector_list[eq->vector];
482 return irq;
483 }
484
485 static void _ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
486 {
487 if (eq->q.created) {
488 ocrdma_mbx_delete_q(dev, &eq->q, QTYPE_EQ);
489 if (dev->nic_info.dev_family == OCRDMA_GEN2_FAMILY)
490 ocrdma_free_eq_vect_gen2(dev);
491 ocrdma_free_q(dev, &eq->q);
492 }
493 }
494
495 static void ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
496 {
497 int irq;
498
499 /* disarm EQ so that interrupts are not generated
500 * during freeing and EQ delete is in progress.
501 */
502 ocrdma_ring_eq_db(dev, eq->q.id, false, false, 0);
503
504 irq = ocrdma_get_irq(dev, eq);
505 free_irq(irq, eq);
506 _ocrdma_destroy_eq(dev, eq);
507 }
508
509 static void ocrdma_destroy_qp_eqs(struct ocrdma_dev *dev)
510 {
511 int i;
512
513 /* deallocate the data path eqs */
514 for (i = 0; i < dev->eq_cnt; i++)
515 ocrdma_destroy_eq(dev, &dev->qp_eq_tbl[i]);
516 }
517
518 static int ocrdma_mbx_mq_cq_create(struct ocrdma_dev *dev,
519 struct ocrdma_queue_info *cq,
520 struct ocrdma_queue_info *eq)
521 {
522 struct ocrdma_create_cq_cmd *cmd = dev->mbx_cmd;
523 struct ocrdma_create_cq_cmd_rsp *rsp = dev->mbx_cmd;
524 int status;
525
526 memset(cmd, 0, sizeof(*cmd));
527 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_CQ,
528 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
529
530 cmd->pgsz_pgcnt = PAGES_4K_SPANNED(cq->va, cq->size);
531 cmd->ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
532 cmd->eqn = (eq->id << OCRDMA_CREATE_CQ_EQID_SHIFT);
533
534 ocrdma_build_q_pages(&cmd->pa[0], cmd->pgsz_pgcnt,
535 cq->dma, PAGE_SIZE_4K);
536 status = be_roce_mcc_cmd(dev->nic_info.netdev,
537 cmd, sizeof(*cmd), NULL, NULL);
538 if (!status) {
539 cq->id = (rsp->cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
540 cq->created = true;
541 }
542 return status;
543 }
544
545 static u32 ocrdma_encoded_q_len(int q_len)
546 {
547 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
548
549 if (len_encoded == 16)
550 len_encoded = 0;
551 return len_encoded;
552 }
553
554 static int ocrdma_mbx_create_mq(struct ocrdma_dev *dev,
555 struct ocrdma_queue_info *mq,
556 struct ocrdma_queue_info *cq)
557 {
558 int num_pages, status;
559 struct ocrdma_create_mq_req *cmd = dev->mbx_cmd;
560 struct ocrdma_create_mq_rsp *rsp = dev->mbx_cmd;
561 struct ocrdma_pa *pa;
562
563 memset(cmd, 0, sizeof(*cmd));
564 num_pages = PAGES_4K_SPANNED(mq->va, mq->size);
565
566 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_MQ_EXT,
567 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
568 cmd->req.rsvd_version = 1;
569 cmd->cqid_pages = num_pages;
570 cmd->cqid_pages |= (cq->id << OCRDMA_CREATE_MQ_CQ_ID_SHIFT);
571 cmd->async_cqid_valid = OCRDMA_CREATE_MQ_ASYNC_CQ_VALID;
572 cmd->async_event_bitmap = Bit(20);
573 cmd->async_cqid_ringsize = cq->id;
574 cmd->async_cqid_ringsize |= (ocrdma_encoded_q_len(mq->len) <<
575 OCRDMA_CREATE_MQ_RING_SIZE_SHIFT);
576 cmd->valid = OCRDMA_CREATE_MQ_VALID;
577 pa = &cmd->pa[0];
578
579 ocrdma_build_q_pages(pa, num_pages, mq->dma, PAGE_SIZE_4K);
580 status = be_roce_mcc_cmd(dev->nic_info.netdev,
581 cmd, sizeof(*cmd), NULL, NULL);
582 if (!status) {
583 mq->id = rsp->id;
584 mq->created = true;
585 }
586 return status;
587 }
588
589 static int ocrdma_create_mq(struct ocrdma_dev *dev)
590 {
591 int status;
592
593 /* Alloc completion queue for Mailbox queue */
594 status = ocrdma_alloc_q(dev, &dev->mq.cq, OCRDMA_MQ_CQ_LEN,
595 sizeof(struct ocrdma_mcqe));
596 if (status)
597 goto alloc_err;
598
599 status = ocrdma_mbx_mq_cq_create(dev, &dev->mq.cq, &dev->meq.q);
600 if (status)
601 goto mbx_cq_free;
602
603 memset(&dev->mqe_ctx, 0, sizeof(dev->mqe_ctx));
604 init_waitqueue_head(&dev->mqe_ctx.cmd_wait);
605 mutex_init(&dev->mqe_ctx.lock);
606
607 /* Alloc Mailbox queue */
608 status = ocrdma_alloc_q(dev, &dev->mq.sq, OCRDMA_MQ_LEN,
609 sizeof(struct ocrdma_mqe));
610 if (status)
611 goto mbx_cq_destroy;
612 status = ocrdma_mbx_create_mq(dev, &dev->mq.sq, &dev->mq.cq);
613 if (status)
614 goto mbx_q_free;
615 ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, 0);
616 return 0;
617
618 mbx_q_free:
619 ocrdma_free_q(dev, &dev->mq.sq);
620 mbx_cq_destroy:
621 ocrdma_mbx_delete_q(dev, &dev->mq.cq, QTYPE_CQ);
622 mbx_cq_free:
623 ocrdma_free_q(dev, &dev->mq.cq);
624 alloc_err:
625 return status;
626 }
627
628 static void ocrdma_destroy_mq(struct ocrdma_dev *dev)
629 {
630 struct ocrdma_queue_info *mbxq, *cq;
631
632 /* mqe_ctx lock synchronizes with any other pending cmds. */
633 mutex_lock(&dev->mqe_ctx.lock);
634 mbxq = &dev->mq.sq;
635 if (mbxq->created) {
636 ocrdma_mbx_delete_q(dev, mbxq, QTYPE_MCCQ);
637 ocrdma_free_q(dev, mbxq);
638 }
639 mutex_unlock(&dev->mqe_ctx.lock);
640
641 cq = &dev->mq.cq;
642 if (cq->created) {
643 ocrdma_mbx_delete_q(dev, cq, QTYPE_CQ);
644 ocrdma_free_q(dev, cq);
645 }
646 }
647
648 static void ocrdma_process_qpcat_error(struct ocrdma_dev *dev,
649 struct ocrdma_qp *qp)
650 {
651 enum ib_qp_state new_ib_qps = IB_QPS_ERR;
652 enum ib_qp_state old_ib_qps;
653
654 if (qp == NULL)
655 BUG();
656 ocrdma_qp_state_machine(qp, new_ib_qps, &old_ib_qps);
657 }
658
659 static void ocrdma_dispatch_ibevent(struct ocrdma_dev *dev,
660 struct ocrdma_ae_mcqe *cqe)
661 {
662 struct ocrdma_qp *qp = NULL;
663 struct ocrdma_cq *cq = NULL;
664 struct ib_event ib_evt;
665 int cq_event = 0;
666 int qp_event = 1;
667 int srq_event = 0;
668 int dev_event = 0;
669 int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >>
670 OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT;
671
672 if (cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPVALID)
673 qp = dev->qp_tbl[cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPID_MASK];
674 if (cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQVALID)
675 cq = dev->cq_tbl[cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQID_MASK];
676
677 ib_evt.device = &dev->ibdev;
678
679 switch (type) {
680 case OCRDMA_CQ_ERROR:
681 ib_evt.element.cq = &cq->ibcq;
682 ib_evt.event = IB_EVENT_CQ_ERR;
683 cq_event = 1;
684 qp_event = 0;
685 break;
686 case OCRDMA_CQ_OVERRUN_ERROR:
687 ib_evt.element.cq = &cq->ibcq;
688 ib_evt.event = IB_EVENT_CQ_ERR;
689 break;
690 case OCRDMA_CQ_QPCAT_ERROR:
691 ib_evt.element.qp = &qp->ibqp;
692 ib_evt.event = IB_EVENT_QP_FATAL;
693 ocrdma_process_qpcat_error(dev, qp);
694 break;
695 case OCRDMA_QP_ACCESS_ERROR:
696 ib_evt.element.qp = &qp->ibqp;
697 ib_evt.event = IB_EVENT_QP_ACCESS_ERR;
698 break;
699 case OCRDMA_QP_COMM_EST_EVENT:
700 ib_evt.element.qp = &qp->ibqp;
701 ib_evt.event = IB_EVENT_COMM_EST;
702 break;
703 case OCRDMA_SQ_DRAINED_EVENT:
704 ib_evt.element.qp = &qp->ibqp;
705 ib_evt.event = IB_EVENT_SQ_DRAINED;
706 break;
707 case OCRDMA_DEVICE_FATAL_EVENT:
708 ib_evt.element.port_num = 1;
709 ib_evt.event = IB_EVENT_DEVICE_FATAL;
710 qp_event = 0;
711 dev_event = 1;
712 break;
713 case OCRDMA_SRQCAT_ERROR:
714 ib_evt.element.srq = &qp->srq->ibsrq;
715 ib_evt.event = IB_EVENT_SRQ_ERR;
716 srq_event = 1;
717 qp_event = 0;
718 break;
719 case OCRDMA_SRQ_LIMIT_EVENT:
720 ib_evt.element.srq = &qp->srq->ibsrq;
721 ib_evt.event = IB_EVENT_SRQ_LIMIT_REACHED;
722 srq_event = 1;
723 qp_event = 0;
724 break;
725 case OCRDMA_QP_LAST_WQE_EVENT:
726 ib_evt.element.qp = &qp->ibqp;
727 ib_evt.event = IB_EVENT_QP_LAST_WQE_REACHED;
728 break;
729 default:
730 cq_event = 0;
731 qp_event = 0;
732 srq_event = 0;
733 dev_event = 0;
734 pr_err("%s() unknown type=0x%x\n", __func__, type);
735 break;
736 }
737
738 if (qp_event) {
739 if (qp->ibqp.event_handler)
740 qp->ibqp.event_handler(&ib_evt, qp->ibqp.qp_context);
741 } else if (cq_event) {
742 if (cq->ibcq.event_handler)
743 cq->ibcq.event_handler(&ib_evt, cq->ibcq.cq_context);
744 } else if (srq_event) {
745 if (qp->srq->ibsrq.event_handler)
746 qp->srq->ibsrq.event_handler(&ib_evt,
747 qp->srq->ibsrq.
748 srq_context);
749 } else if (dev_event)
750 ib_dispatch_event(&ib_evt);
751
752 }
753
754 static void ocrdma_process_acqe(struct ocrdma_dev *dev, void *ae_cqe)
755 {
756 /* async CQE processing */
757 struct ocrdma_ae_mcqe *cqe = ae_cqe;
758 u32 evt_code = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_CODE_MASK) >>
759 OCRDMA_AE_MCQE_EVENT_CODE_SHIFT;
760
761 if (evt_code == OCRDMA_ASYNC_EVE_CODE)
762 ocrdma_dispatch_ibevent(dev, cqe);
763 else
764 pr_err("%s(%d) invalid evt code=0x%x\n", __func__,
765 dev->id, evt_code);
766 }
767
768 static void ocrdma_process_mcqe(struct ocrdma_dev *dev, struct ocrdma_mcqe *cqe)
769 {
770 if (dev->mqe_ctx.tag == cqe->tag_lo && dev->mqe_ctx.cmd_done == false) {
771 dev->mqe_ctx.cqe_status = (cqe->status &
772 OCRDMA_MCQE_STATUS_MASK) >> OCRDMA_MCQE_STATUS_SHIFT;
773 dev->mqe_ctx.ext_status =
774 (cqe->status & OCRDMA_MCQE_ESTATUS_MASK)
775 >> OCRDMA_MCQE_ESTATUS_SHIFT;
776 dev->mqe_ctx.cmd_done = true;
777 wake_up(&dev->mqe_ctx.cmd_wait);
778 } else
779 pr_err("%s() cqe for invalid tag0x%x.expected=0x%x\n",
780 __func__, cqe->tag_lo, dev->mqe_ctx.tag);
781 }
782
783 static int ocrdma_mq_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
784 {
785 u16 cqe_popped = 0;
786 struct ocrdma_mcqe *cqe;
787
788 while (1) {
789 cqe = ocrdma_get_mcqe(dev);
790 if (cqe == NULL)
791 break;
792 ocrdma_le32_to_cpu(cqe, sizeof(*cqe));
793 cqe_popped += 1;
794 if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_AE_MASK)
795 ocrdma_process_acqe(dev, cqe);
796 else if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_CMPL_MASK)
797 ocrdma_process_mcqe(dev, cqe);
798 else
799 pr_err("%s() cqe->compl is not set.\n", __func__);
800 memset(cqe, 0, sizeof(struct ocrdma_mcqe));
801 ocrdma_mcq_inc_tail(dev);
802 }
803 ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, cqe_popped);
804 return 0;
805 }
806
807 static void ocrdma_qp_buddy_cq_handler(struct ocrdma_dev *dev,
808 struct ocrdma_cq *cq)
809 {
810 unsigned long flags;
811 struct ocrdma_qp *qp;
812 bool buddy_cq_found = false;
813 /* Go through list of QPs in error state which are using this CQ
814 * and invoke its callback handler to trigger CQE processing for
815 * error/flushed CQE. It is rare to find more than few entries in
816 * this list as most consumers stops after getting error CQE.
817 * List is traversed only once when a matching buddy cq found for a QP.
818 */
819 spin_lock_irqsave(&dev->flush_q_lock, flags);
820 list_for_each_entry(qp, &cq->sq_head, sq_entry) {
821 if (qp->srq)
822 continue;
823 /* if wq and rq share the same cq, than comp_handler
824 * is already invoked.
825 */
826 if (qp->sq_cq == qp->rq_cq)
827 continue;
828 /* if completion came on sq, rq's cq is buddy cq.
829 * if completion came on rq, sq's cq is buddy cq.
830 */
831 if (qp->sq_cq == cq)
832 cq = qp->rq_cq;
833 else
834 cq = qp->sq_cq;
835 buddy_cq_found = true;
836 break;
837 }
838 spin_unlock_irqrestore(&dev->flush_q_lock, flags);
839 if (buddy_cq_found == false)
840 return;
841 if (cq->ibcq.comp_handler) {
842 spin_lock_irqsave(&cq->comp_handler_lock, flags);
843 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
844 spin_unlock_irqrestore(&cq->comp_handler_lock, flags);
845 }
846 }
847
848 static void ocrdma_qp_cq_handler(struct ocrdma_dev *dev, u16 cq_idx)
849 {
850 unsigned long flags;
851 struct ocrdma_cq *cq;
852
853 if (cq_idx >= OCRDMA_MAX_CQ)
854 BUG();
855
856 cq = dev->cq_tbl[cq_idx];
857 if (cq == NULL) {
858 pr_err("%s%d invalid id=0x%x\n", __func__, dev->id, cq_idx);
859 return;
860 }
861 spin_lock_irqsave(&cq->cq_lock, flags);
862 cq->armed = false;
863 cq->solicited = false;
864 spin_unlock_irqrestore(&cq->cq_lock, flags);
865
866 ocrdma_ring_cq_db(dev, cq->id, false, false, 0);
867
868 if (cq->ibcq.comp_handler) {
869 spin_lock_irqsave(&cq->comp_handler_lock, flags);
870 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
871 spin_unlock_irqrestore(&cq->comp_handler_lock, flags);
872 }
873 ocrdma_qp_buddy_cq_handler(dev, cq);
874 }
875
876 static void ocrdma_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
877 {
878 /* process the MQ-CQE. */
879 if (cq_id == dev->mq.cq.id)
880 ocrdma_mq_cq_handler(dev, cq_id);
881 else
882 ocrdma_qp_cq_handler(dev, cq_id);
883 }
884
885 static irqreturn_t ocrdma_irq_handler(int irq, void *handle)
886 {
887 struct ocrdma_eq *eq = handle;
888 struct ocrdma_dev *dev = eq->dev;
889 struct ocrdma_eqe eqe;
890 struct ocrdma_eqe *ptr;
891 u16 eqe_popped = 0;
892 u16 cq_id;
893 while (1) {
894 ptr = ocrdma_get_eqe(eq);
895 eqe = *ptr;
896 ocrdma_le32_to_cpu(&eqe, sizeof(eqe));
897 if ((eqe.id_valid & OCRDMA_EQE_VALID_MASK) == 0)
898 break;
899 eqe_popped += 1;
900 ptr->id_valid = 0;
901 /* check whether its CQE or not. */
902 if ((eqe.id_valid & OCRDMA_EQE_FOR_CQE_MASK) == 0) {
903 cq_id = eqe.id_valid >> OCRDMA_EQE_RESOURCE_ID_SHIFT;
904 ocrdma_cq_handler(dev, cq_id);
905 }
906 ocrdma_eq_inc_tail(eq);
907 }
908 ocrdma_ring_eq_db(dev, eq->q.id, true, true, eqe_popped);
909 /* Ring EQ doorbell with num_popped to 0 to enable interrupts again. */
910 if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX)
911 ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
912 return IRQ_HANDLED;
913 }
914
915 static void ocrdma_post_mqe(struct ocrdma_dev *dev, struct ocrdma_mqe *cmd)
916 {
917 struct ocrdma_mqe *mqe;
918
919 dev->mqe_ctx.tag = dev->mq.sq.head;
920 dev->mqe_ctx.cmd_done = false;
921 mqe = ocrdma_get_mqe(dev);
922 cmd->hdr.tag_lo = dev->mq.sq.head;
923 ocrdma_copy_cpu_to_le32(mqe, cmd, sizeof(*mqe));
924 /* make sure descriptor is written before ringing doorbell */
925 wmb();
926 ocrdma_mq_inc_head(dev);
927 ocrdma_ring_mq_db(dev);
928 }
929
930 static int ocrdma_wait_mqe_cmpl(struct ocrdma_dev *dev)
931 {
932 long status;
933 /* 30 sec timeout */
934 status = wait_event_timeout(dev->mqe_ctx.cmd_wait,
935 (dev->mqe_ctx.cmd_done != false),
936 msecs_to_jiffies(30000));
937 if (status)
938 return 0;
939 else
940 return -1;
941 }
942
943 /* issue a mailbox command on the MQ */
944 static int ocrdma_mbx_cmd(struct ocrdma_dev *dev, struct ocrdma_mqe *mqe)
945 {
946 int status = 0;
947 u16 cqe_status, ext_status;
948 struct ocrdma_mqe *rsp;
949
950 mutex_lock(&dev->mqe_ctx.lock);
951 ocrdma_post_mqe(dev, mqe);
952 status = ocrdma_wait_mqe_cmpl(dev);
953 if (status)
954 goto mbx_err;
955 cqe_status = dev->mqe_ctx.cqe_status;
956 ext_status = dev->mqe_ctx.ext_status;
957 rsp = ocrdma_get_mqe_rsp(dev);
958 ocrdma_copy_le32_to_cpu(mqe, rsp, (sizeof(*mqe)));
959 if (cqe_status || ext_status) {
960 pr_err
961 ("%s() opcode=0x%x, cqe_status=0x%x, ext_status=0x%x\n",
962 __func__,
963 (rsp->u.rsp.subsys_op & OCRDMA_MBX_RSP_OPCODE_MASK) >>
964 OCRDMA_MBX_RSP_OPCODE_SHIFT, cqe_status, ext_status);
965 status = ocrdma_get_mbx_cqe_errno(cqe_status);
966 goto mbx_err;
967 }
968 if (mqe->u.rsp.status & OCRDMA_MBX_RSP_STATUS_MASK)
969 status = ocrdma_get_mbx_errno(mqe->u.rsp.status);
970 mbx_err:
971 mutex_unlock(&dev->mqe_ctx.lock);
972 return status;
973 }
974
975 static void ocrdma_get_attr(struct ocrdma_dev *dev,
976 struct ocrdma_dev_attr *attr,
977 struct ocrdma_mbx_query_config *rsp)
978 {
979 attr->max_pd =
980 (rsp->max_pd_ca_ack_delay & OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK) >>
981 OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT;
982 attr->max_qp =
983 (rsp->qp_srq_cq_ird_ord & OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK) >>
984 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT;
985 attr->max_send_sge = ((rsp->max_write_send_sge &
986 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
987 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT);
988 attr->max_recv_sge = (rsp->max_write_send_sge &
989 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
990 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT;
991 attr->max_srq_sge = (rsp->max_srq_rqe_sge &
992 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK) >>
993 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET;
994 attr->max_ord_per_qp = (rsp->max_ird_ord_per_qp &
995 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK) >>
996 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT;
997 attr->max_ird_per_qp = (rsp->max_ird_ord_per_qp &
998 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK) >>
999 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT;
1000 attr->cq_overflow_detect = (rsp->qp_srq_cq_ird_ord &
1001 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK) >>
1002 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT;
1003 attr->srq_supported = (rsp->qp_srq_cq_ird_ord &
1004 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK) >>
1005 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT;
1006 attr->local_ca_ack_delay = (rsp->max_pd_ca_ack_delay &
1007 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK) >>
1008 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT;
1009 attr->max_mr = rsp->max_mr;
1010 attr->max_mr_size = ~0ull;
1011 attr->max_fmr = 0;
1012 attr->max_pages_per_frmr = rsp->max_pages_per_frmr;
1013 attr->max_num_mr_pbl = rsp->max_num_mr_pbl;
1014 attr->max_cqe = rsp->max_cq_cqes_per_cq &
1015 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK;
1016 attr->wqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1017 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK) >>
1018 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET) *
1019 OCRDMA_WQE_STRIDE;
1020 attr->rqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1021 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK) >>
1022 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET) *
1023 OCRDMA_WQE_STRIDE;
1024 attr->max_inline_data =
1025 attr->wqe_size - (sizeof(struct ocrdma_hdr_wqe) +
1026 sizeof(struct ocrdma_sge));
1027 if (dev->nic_info.dev_family == OCRDMA_GEN2_FAMILY) {
1028 attr->ird = 1;
1029 attr->ird_page_size = OCRDMA_MIN_Q_PAGE_SIZE;
1030 attr->num_ird_pages = MAX_OCRDMA_IRD_PAGES;
1031 }
1032 dev->attr.max_wqe = rsp->max_wqes_rqes_per_q >>
1033 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET;
1034 dev->attr.max_rqe = rsp->max_wqes_rqes_per_q &
1035 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK;
1036 }
1037
1038 static int ocrdma_check_fw_config(struct ocrdma_dev *dev,
1039 struct ocrdma_fw_conf_rsp *conf)
1040 {
1041 u32 fn_mode;
1042
1043 fn_mode = conf->fn_mode & OCRDMA_FN_MODE_RDMA;
1044 if (fn_mode != OCRDMA_FN_MODE_RDMA)
1045 return -EINVAL;
1046 dev->base_eqid = conf->base_eqid;
1047 dev->max_eq = conf->max_eq;
1048 dev->attr.max_cq = OCRDMA_MAX_CQ - 1;
1049 return 0;
1050 }
1051
1052 /* can be issued only during init time. */
1053 static int ocrdma_mbx_query_fw_ver(struct ocrdma_dev *dev)
1054 {
1055 int status = -ENOMEM;
1056 struct ocrdma_mqe *cmd;
1057 struct ocrdma_fw_ver_rsp *rsp;
1058
1059 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_VER, sizeof(*cmd));
1060 if (!cmd)
1061 return -ENOMEM;
1062 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1063 OCRDMA_CMD_GET_FW_VER,
1064 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1065
1066 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1067 if (status)
1068 goto mbx_err;
1069 rsp = (struct ocrdma_fw_ver_rsp *)cmd;
1070 memset(&dev->attr.fw_ver[0], 0, sizeof(dev->attr.fw_ver));
1071 memcpy(&dev->attr.fw_ver[0], &rsp->running_ver[0],
1072 sizeof(rsp->running_ver));
1073 ocrdma_le32_to_cpu(dev->attr.fw_ver, sizeof(rsp->running_ver));
1074 mbx_err:
1075 kfree(cmd);
1076 return status;
1077 }
1078
1079 /* can be issued only during init time. */
1080 static int ocrdma_mbx_query_fw_config(struct ocrdma_dev *dev)
1081 {
1082 int status = -ENOMEM;
1083 struct ocrdma_mqe *cmd;
1084 struct ocrdma_fw_conf_rsp *rsp;
1085
1086 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_CONFIG, sizeof(*cmd));
1087 if (!cmd)
1088 return -ENOMEM;
1089 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1090 OCRDMA_CMD_GET_FW_CONFIG,
1091 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1092 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1093 if (status)
1094 goto mbx_err;
1095 rsp = (struct ocrdma_fw_conf_rsp *)cmd;
1096 status = ocrdma_check_fw_config(dev, rsp);
1097 mbx_err:
1098 kfree(cmd);
1099 return status;
1100 }
1101
1102 static int ocrdma_mbx_query_dev(struct ocrdma_dev *dev)
1103 {
1104 int status = -ENOMEM;
1105 struct ocrdma_mbx_query_config *rsp;
1106 struct ocrdma_mqe *cmd;
1107
1108 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_CONFIG, sizeof(*cmd));
1109 if (!cmd)
1110 return status;
1111 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1112 if (status)
1113 goto mbx_err;
1114 rsp = (struct ocrdma_mbx_query_config *)cmd;
1115 ocrdma_get_attr(dev, &dev->attr, rsp);
1116 mbx_err:
1117 kfree(cmd);
1118 return status;
1119 }
1120
1121 int ocrdma_mbx_alloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1122 {
1123 int status = -ENOMEM;
1124 struct ocrdma_alloc_pd *cmd;
1125 struct ocrdma_alloc_pd_rsp *rsp;
1126
1127 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD, sizeof(*cmd));
1128 if (!cmd)
1129 return status;
1130 if (pd->dpp_enabled)
1131 cmd->enable_dpp_rsvd |= OCRDMA_ALLOC_PD_ENABLE_DPP;
1132 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1133 if (status)
1134 goto mbx_err;
1135 rsp = (struct ocrdma_alloc_pd_rsp *)cmd;
1136 pd->id = rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_PDID_MASK;
1137 if (rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_DPP) {
1138 pd->dpp_enabled = true;
1139 pd->dpp_page = rsp->dpp_page_pdid >>
1140 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT;
1141 } else {
1142 pd->dpp_enabled = false;
1143 pd->num_dpp_qp = 0;
1144 }
1145 mbx_err:
1146 kfree(cmd);
1147 return status;
1148 }
1149
1150 int ocrdma_mbx_dealloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1151 {
1152 int status = -ENOMEM;
1153 struct ocrdma_dealloc_pd *cmd;
1154
1155 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD, sizeof(*cmd));
1156 if (!cmd)
1157 return status;
1158 cmd->id = pd->id;
1159 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1160 kfree(cmd);
1161 return status;
1162 }
1163
1164 static int ocrdma_build_q_conf(u32 *num_entries, int entry_size,
1165 int *num_pages, int *page_size)
1166 {
1167 int i;
1168 int mem_size;
1169
1170 *num_entries = roundup_pow_of_two(*num_entries);
1171 mem_size = *num_entries * entry_size;
1172 /* find the possible lowest possible multiplier */
1173 for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1174 if (mem_size <= (OCRDMA_Q_PAGE_BASE_SIZE << i))
1175 break;
1176 }
1177 if (i >= OCRDMA_MAX_Q_PAGE_SIZE_CNT)
1178 return -EINVAL;
1179 mem_size = roundup(mem_size,
1180 ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES));
1181 *num_pages =
1182 mem_size / ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1183 *page_size = ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1184 *num_entries = mem_size / entry_size;
1185 return 0;
1186 }
1187
1188 static int ocrdma_mbx_create_ah_tbl(struct ocrdma_dev *dev)
1189 {
1190 int i ;
1191 int status = 0;
1192 int max_ah;
1193 struct ocrdma_create_ah_tbl *cmd;
1194 struct ocrdma_create_ah_tbl_rsp *rsp;
1195 struct pci_dev *pdev = dev->nic_info.pdev;
1196 dma_addr_t pa;
1197 struct ocrdma_pbe *pbes;
1198
1199 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_AH_TBL, sizeof(*cmd));
1200 if (!cmd)
1201 return status;
1202
1203 max_ah = OCRDMA_MAX_AH;
1204 dev->av_tbl.size = sizeof(struct ocrdma_av) * max_ah;
1205
1206 /* number of PBEs in PBL */
1207 cmd->ah_conf = (OCRDMA_AH_TBL_PAGES <<
1208 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT) &
1209 OCRDMA_CREATE_AH_NUM_PAGES_MASK;
1210
1211 /* page size */
1212 for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1213 if (PAGE_SIZE == (OCRDMA_MIN_Q_PAGE_SIZE << i))
1214 break;
1215 }
1216 cmd->ah_conf |= (i << OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT) &
1217 OCRDMA_CREATE_AH_PAGE_SIZE_MASK;
1218
1219 /* ah_entry size */
1220 cmd->ah_conf |= (sizeof(struct ocrdma_av) <<
1221 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT) &
1222 OCRDMA_CREATE_AH_ENTRY_SIZE_MASK;
1223
1224 dev->av_tbl.pbl.va = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
1225 &dev->av_tbl.pbl.pa,
1226 GFP_KERNEL);
1227 if (dev->av_tbl.pbl.va == NULL)
1228 goto mem_err;
1229
1230 dev->av_tbl.va = dma_alloc_coherent(&pdev->dev, dev->av_tbl.size,
1231 &pa, GFP_KERNEL);
1232 if (dev->av_tbl.va == NULL)
1233 goto mem_err_ah;
1234 dev->av_tbl.pa = pa;
1235 dev->av_tbl.num_ah = max_ah;
1236 memset(dev->av_tbl.va, 0, dev->av_tbl.size);
1237
1238 pbes = (struct ocrdma_pbe *)dev->av_tbl.pbl.va;
1239 for (i = 0; i < dev->av_tbl.size / OCRDMA_MIN_Q_PAGE_SIZE; i++) {
1240 pbes[i].pa_lo = (u32) (pa & 0xffffffff);
1241 pbes[i].pa_hi = (u32) upper_32_bits(pa);
1242 pa += PAGE_SIZE;
1243 }
1244 cmd->tbl_addr[0].lo = (u32)(dev->av_tbl.pbl.pa & 0xFFFFFFFF);
1245 cmd->tbl_addr[0].hi = (u32)upper_32_bits(dev->av_tbl.pbl.pa);
1246 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1247 if (status)
1248 goto mbx_err;
1249 rsp = (struct ocrdma_create_ah_tbl_rsp *)cmd;
1250 dev->av_tbl.ahid = rsp->ahid & 0xFFFF;
1251 kfree(cmd);
1252 return 0;
1253
1254 mbx_err:
1255 dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1256 dev->av_tbl.pa);
1257 dev->av_tbl.va = NULL;
1258 mem_err_ah:
1259 dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1260 dev->av_tbl.pbl.pa);
1261 dev->av_tbl.pbl.va = NULL;
1262 dev->av_tbl.size = 0;
1263 mem_err:
1264 kfree(cmd);
1265 return status;
1266 }
1267
1268 static void ocrdma_mbx_delete_ah_tbl(struct ocrdma_dev *dev)
1269 {
1270 struct ocrdma_delete_ah_tbl *cmd;
1271 struct pci_dev *pdev = dev->nic_info.pdev;
1272
1273 if (dev->av_tbl.va == NULL)
1274 return;
1275
1276 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_AH_TBL, sizeof(*cmd));
1277 if (!cmd)
1278 return;
1279 cmd->ahid = dev->av_tbl.ahid;
1280
1281 ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1282 dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1283 dev->av_tbl.pa);
1284 dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1285 dev->av_tbl.pbl.pa);
1286 kfree(cmd);
1287 }
1288
1289 /* Multiple CQs uses the EQ. This routine returns least used
1290 * EQ to associate with CQ. This will distributes the interrupt
1291 * processing and CPU load to associated EQ, vector and so to that CPU.
1292 */
1293 static u16 ocrdma_bind_eq(struct ocrdma_dev *dev)
1294 {
1295 int i, selected_eq = 0, cq_cnt = 0;
1296 u16 eq_id;
1297
1298 mutex_lock(&dev->dev_lock);
1299 cq_cnt = dev->qp_eq_tbl[0].cq_cnt;
1300 eq_id = dev->qp_eq_tbl[0].q.id;
1301 /* find the EQ which is has the least number of
1302 * CQs associated with it.
1303 */
1304 for (i = 0; i < dev->eq_cnt; i++) {
1305 if (dev->qp_eq_tbl[i].cq_cnt < cq_cnt) {
1306 cq_cnt = dev->qp_eq_tbl[i].cq_cnt;
1307 eq_id = dev->qp_eq_tbl[i].q.id;
1308 selected_eq = i;
1309 }
1310 }
1311 dev->qp_eq_tbl[selected_eq].cq_cnt += 1;
1312 mutex_unlock(&dev->dev_lock);
1313 return eq_id;
1314 }
1315
1316 static void ocrdma_unbind_eq(struct ocrdma_dev *dev, u16 eq_id)
1317 {
1318 int i;
1319
1320 mutex_lock(&dev->dev_lock);
1321 for (i = 0; i < dev->eq_cnt; i++) {
1322 if (dev->qp_eq_tbl[i].q.id != eq_id)
1323 continue;
1324 dev->qp_eq_tbl[i].cq_cnt -= 1;
1325 break;
1326 }
1327 mutex_unlock(&dev->dev_lock);
1328 }
1329
1330 int ocrdma_mbx_create_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq,
1331 int entries, int dpp_cq)
1332 {
1333 int status = -ENOMEM; int max_hw_cqe;
1334 struct pci_dev *pdev = dev->nic_info.pdev;
1335 struct ocrdma_create_cq *cmd;
1336 struct ocrdma_create_cq_rsp *rsp;
1337 u32 hw_pages, cqe_size, page_size, cqe_count;
1338
1339 if (dpp_cq)
1340 return -EINVAL;
1341 if (entries > dev->attr.max_cqe) {
1342 pr_err("%s(%d) max_cqe=0x%x, requester_cqe=0x%x\n",
1343 __func__, dev->id, dev->attr.max_cqe, entries);
1344 return -EINVAL;
1345 }
1346 if (dpp_cq && (dev->nic_info.dev_family != OCRDMA_GEN2_FAMILY))
1347 return -EINVAL;
1348
1349 if (dpp_cq) {
1350 cq->max_hw_cqe = 1;
1351 max_hw_cqe = 1;
1352 cqe_size = OCRDMA_DPP_CQE_SIZE;
1353 hw_pages = 1;
1354 } else {
1355 cq->max_hw_cqe = dev->attr.max_cqe;
1356 max_hw_cqe = dev->attr.max_cqe;
1357 cqe_size = sizeof(struct ocrdma_cqe);
1358 hw_pages = OCRDMA_CREATE_CQ_MAX_PAGES;
1359 }
1360
1361 cq->len = roundup(max_hw_cqe * cqe_size, OCRDMA_MIN_Q_PAGE_SIZE);
1362
1363 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_CQ, sizeof(*cmd));
1364 if (!cmd)
1365 return -ENOMEM;
1366 ocrdma_init_mch(&cmd->cmd.req, OCRDMA_CMD_CREATE_CQ,
1367 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1368 cq->va = dma_alloc_coherent(&pdev->dev, cq->len, &cq->pa, GFP_KERNEL);
1369 if (!cq->va) {
1370 status = -ENOMEM;
1371 goto mem_err;
1372 }
1373 memset(cq->va, 0, cq->len);
1374 page_size = cq->len / hw_pages;
1375 cmd->cmd.pgsz_pgcnt = (page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
1376 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
1377 cmd->cmd.pgsz_pgcnt |= hw_pages;
1378 cmd->cmd.ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
1379
1380 if (dev->eq_cnt < 0)
1381 goto eq_err;
1382 cq->eqn = ocrdma_bind_eq(dev);
1383 cmd->cmd.req.rsvd_version = OCRDMA_CREATE_CQ_VER2;
1384 cqe_count = cq->len / cqe_size;
1385 if (cqe_count > 1024)
1386 /* Set cnt to 3 to indicate more than 1024 cq entries */
1387 cmd->cmd.ev_cnt_flags |= (0x3 << OCRDMA_CREATE_CQ_CNT_SHIFT);
1388 else {
1389 u8 count = 0;
1390 switch (cqe_count) {
1391 case 256:
1392 count = 0;
1393 break;
1394 case 512:
1395 count = 1;
1396 break;
1397 case 1024:
1398 count = 2;
1399 break;
1400 default:
1401 goto mbx_err;
1402 }
1403 cmd->cmd.ev_cnt_flags |= (count << OCRDMA_CREATE_CQ_CNT_SHIFT);
1404 }
1405 /* shared eq between all the consumer cqs. */
1406 cmd->cmd.eqn = cq->eqn;
1407 if (dev->nic_info.dev_family == OCRDMA_GEN2_FAMILY) {
1408 if (dpp_cq)
1409 cmd->cmd.pgsz_pgcnt |= OCRDMA_CREATE_CQ_DPP <<
1410 OCRDMA_CREATE_CQ_TYPE_SHIFT;
1411 cq->phase_change = false;
1412 cmd->cmd.cqe_count = (cq->len / cqe_size);
1413 } else {
1414 cmd->cmd.cqe_count = (cq->len / cqe_size) - 1;
1415 cmd->cmd.ev_cnt_flags |= OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID;
1416 cq->phase_change = true;
1417 }
1418
1419 ocrdma_build_q_pages(&cmd->cmd.pa[0], hw_pages, cq->pa, page_size);
1420 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1421 if (status)
1422 goto mbx_err;
1423
1424 rsp = (struct ocrdma_create_cq_rsp *)cmd;
1425 cq->id = (u16) (rsp->rsp.cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
1426 kfree(cmd);
1427 return 0;
1428 mbx_err:
1429 ocrdma_unbind_eq(dev, cq->eqn);
1430 eq_err:
1431 dma_free_coherent(&pdev->dev, cq->len, cq->va, cq->pa);
1432 mem_err:
1433 kfree(cmd);
1434 return status;
1435 }
1436
1437 int ocrdma_mbx_destroy_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq)
1438 {
1439 int status = -ENOMEM;
1440 struct ocrdma_destroy_cq *cmd;
1441
1442 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_CQ, sizeof(*cmd));
1443 if (!cmd)
1444 return status;
1445 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_DELETE_CQ,
1446 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1447
1448 cmd->bypass_flush_qid |=
1449 (cq->id << OCRDMA_DESTROY_CQ_QID_SHIFT) &
1450 OCRDMA_DESTROY_CQ_QID_MASK;
1451
1452 ocrdma_unbind_eq(dev, cq->eqn);
1453 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1454 if (status)
1455 goto mbx_err;
1456 dma_free_coherent(&dev->nic_info.pdev->dev, cq->len, cq->va, cq->pa);
1457 mbx_err:
1458 kfree(cmd);
1459 return status;
1460 }
1461
1462 int ocrdma_mbx_alloc_lkey(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1463 u32 pdid, int addr_check)
1464 {
1465 int status = -ENOMEM;
1466 struct ocrdma_alloc_lkey *cmd;
1467 struct ocrdma_alloc_lkey_rsp *rsp;
1468
1469 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_LKEY, sizeof(*cmd));
1470 if (!cmd)
1471 return status;
1472 cmd->pdid = pdid;
1473 cmd->pbl_sz_flags |= addr_check;
1474 cmd->pbl_sz_flags |= (hwmr->fr_mr << OCRDMA_ALLOC_LKEY_FMR_SHIFT);
1475 cmd->pbl_sz_flags |=
1476 (hwmr->remote_wr << OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT);
1477 cmd->pbl_sz_flags |=
1478 (hwmr->remote_rd << OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT);
1479 cmd->pbl_sz_flags |=
1480 (hwmr->local_wr << OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT);
1481 cmd->pbl_sz_flags |=
1482 (hwmr->remote_atomic << OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT);
1483 cmd->pbl_sz_flags |=
1484 (hwmr->num_pbls << OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT);
1485
1486 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1487 if (status)
1488 goto mbx_err;
1489 rsp = (struct ocrdma_alloc_lkey_rsp *)cmd;
1490 hwmr->lkey = rsp->lrkey;
1491 mbx_err:
1492 kfree(cmd);
1493 return status;
1494 }
1495
1496 int ocrdma_mbx_dealloc_lkey(struct ocrdma_dev *dev, int fr_mr, u32 lkey)
1497 {
1498 int status = -ENOMEM;
1499 struct ocrdma_dealloc_lkey *cmd;
1500
1501 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_LKEY, sizeof(*cmd));
1502 if (!cmd)
1503 return -ENOMEM;
1504 cmd->lkey = lkey;
1505 cmd->rsvd_frmr = fr_mr ? 1 : 0;
1506 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1507 if (status)
1508 goto mbx_err;
1509 mbx_err:
1510 kfree(cmd);
1511 return status;
1512 }
1513
1514 static int ocrdma_mbx_reg_mr(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1515 u32 pdid, u32 pbl_cnt, u32 pbe_size, u32 last)
1516 {
1517 int status = -ENOMEM;
1518 int i;
1519 struct ocrdma_reg_nsmr *cmd;
1520 struct ocrdma_reg_nsmr_rsp *rsp;
1521
1522 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR, sizeof(*cmd));
1523 if (!cmd)
1524 return -ENOMEM;
1525 cmd->num_pbl_pdid =
1526 pdid | (hwmr->num_pbls << OCRDMA_REG_NSMR_NUM_PBL_SHIFT);
1527
1528 cmd->flags_hpage_pbe_sz |= (hwmr->remote_wr <<
1529 OCRDMA_REG_NSMR_REMOTE_WR_SHIFT);
1530 cmd->flags_hpage_pbe_sz |= (hwmr->remote_rd <<
1531 OCRDMA_REG_NSMR_REMOTE_RD_SHIFT);
1532 cmd->flags_hpage_pbe_sz |= (hwmr->local_wr <<
1533 OCRDMA_REG_NSMR_LOCAL_WR_SHIFT);
1534 cmd->flags_hpage_pbe_sz |= (hwmr->remote_atomic <<
1535 OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT);
1536 cmd->flags_hpage_pbe_sz |= (hwmr->mw_bind <<
1537 OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT);
1538 cmd->flags_hpage_pbe_sz |= (last << OCRDMA_REG_NSMR_LAST_SHIFT);
1539
1540 cmd->flags_hpage_pbe_sz |= (hwmr->pbe_size / OCRDMA_MIN_HPAGE_SIZE);
1541 cmd->flags_hpage_pbe_sz |= (hwmr->pbl_size / OCRDMA_MIN_HPAGE_SIZE) <<
1542 OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT;
1543 cmd->totlen_low = hwmr->len;
1544 cmd->totlen_high = upper_32_bits(hwmr->len);
1545 cmd->fbo_low = (u32) (hwmr->fbo & 0xffffffff);
1546 cmd->fbo_high = (u32) upper_32_bits(hwmr->fbo);
1547 cmd->va_loaddr = (u32) hwmr->va;
1548 cmd->va_hiaddr = (u32) upper_32_bits(hwmr->va);
1549
1550 for (i = 0; i < pbl_cnt; i++) {
1551 cmd->pbl[i].lo = (u32) (hwmr->pbl_table[i].pa & 0xffffffff);
1552 cmd->pbl[i].hi = upper_32_bits(hwmr->pbl_table[i].pa);
1553 }
1554 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1555 if (status)
1556 goto mbx_err;
1557 rsp = (struct ocrdma_reg_nsmr_rsp *)cmd;
1558 hwmr->lkey = rsp->lrkey;
1559 mbx_err:
1560 kfree(cmd);
1561 return status;
1562 }
1563
1564 static int ocrdma_mbx_reg_mr_cont(struct ocrdma_dev *dev,
1565 struct ocrdma_hw_mr *hwmr, u32 pbl_cnt,
1566 u32 pbl_offset, u32 last)
1567 {
1568 int status = -ENOMEM;
1569 int i;
1570 struct ocrdma_reg_nsmr_cont *cmd;
1571
1572 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR_CONT, sizeof(*cmd));
1573 if (!cmd)
1574 return -ENOMEM;
1575 cmd->lrkey = hwmr->lkey;
1576 cmd->num_pbl_offset = (pbl_cnt << OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT) |
1577 (pbl_offset & OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK);
1578 cmd->last = last << OCRDMA_REG_NSMR_CONT_LAST_SHIFT;
1579
1580 for (i = 0; i < pbl_cnt; i++) {
1581 cmd->pbl[i].lo =
1582 (u32) (hwmr->pbl_table[i + pbl_offset].pa & 0xffffffff);
1583 cmd->pbl[i].hi =
1584 upper_32_bits(hwmr->pbl_table[i + pbl_offset].pa);
1585 }
1586 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1587 if (status)
1588 goto mbx_err;
1589 mbx_err:
1590 kfree(cmd);
1591 return status;
1592 }
1593
1594 int ocrdma_reg_mr(struct ocrdma_dev *dev,
1595 struct ocrdma_hw_mr *hwmr, u32 pdid, int acc)
1596 {
1597 int status;
1598 u32 last = 0;
1599 u32 cur_pbl_cnt, pbl_offset;
1600 u32 pending_pbl_cnt = hwmr->num_pbls;
1601
1602 pbl_offset = 0;
1603 cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
1604 if (cur_pbl_cnt == pending_pbl_cnt)
1605 last = 1;
1606
1607 status = ocrdma_mbx_reg_mr(dev, hwmr, pdid,
1608 cur_pbl_cnt, hwmr->pbe_size, last);
1609 if (status) {
1610 pr_err("%s() status=%d\n", __func__, status);
1611 return status;
1612 }
1613 /* if there is no more pbls to register then exit. */
1614 if (last)
1615 return 0;
1616
1617 while (!last) {
1618 pbl_offset += cur_pbl_cnt;
1619 pending_pbl_cnt -= cur_pbl_cnt;
1620 cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
1621 /* if we reach the end of the pbls, then need to set the last
1622 * bit, indicating no more pbls to register for this memory key.
1623 */
1624 if (cur_pbl_cnt == pending_pbl_cnt)
1625 last = 1;
1626
1627 status = ocrdma_mbx_reg_mr_cont(dev, hwmr, cur_pbl_cnt,
1628 pbl_offset, last);
1629 if (status)
1630 break;
1631 }
1632 if (status)
1633 pr_err("%s() err. status=%d\n", __func__, status);
1634
1635 return status;
1636 }
1637
1638 bool ocrdma_is_qp_in_sq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
1639 {
1640 struct ocrdma_qp *tmp;
1641 bool found = false;
1642 list_for_each_entry(tmp, &cq->sq_head, sq_entry) {
1643 if (qp == tmp) {
1644 found = true;
1645 break;
1646 }
1647 }
1648 return found;
1649 }
1650
1651 bool ocrdma_is_qp_in_rq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
1652 {
1653 struct ocrdma_qp *tmp;
1654 bool found = false;
1655 list_for_each_entry(tmp, &cq->rq_head, rq_entry) {
1656 if (qp == tmp) {
1657 found = true;
1658 break;
1659 }
1660 }
1661 return found;
1662 }
1663
1664 void ocrdma_flush_qp(struct ocrdma_qp *qp)
1665 {
1666 bool found;
1667 unsigned long flags;
1668
1669 spin_lock_irqsave(&qp->dev->flush_q_lock, flags);
1670 found = ocrdma_is_qp_in_sq_flushlist(qp->sq_cq, qp);
1671 if (!found)
1672 list_add_tail(&qp->sq_entry, &qp->sq_cq->sq_head);
1673 if (!qp->srq) {
1674 found = ocrdma_is_qp_in_rq_flushlist(qp->rq_cq, qp);
1675 if (!found)
1676 list_add_tail(&qp->rq_entry, &qp->rq_cq->rq_head);
1677 }
1678 spin_unlock_irqrestore(&qp->dev->flush_q_lock, flags);
1679 }
1680
1681 int ocrdma_qp_state_machine(struct ocrdma_qp *qp, enum ib_qp_state new_ib_state,
1682 enum ib_qp_state *old_ib_state)
1683 {
1684 unsigned long flags;
1685 int status = 0;
1686 enum ocrdma_qp_state new_state;
1687 new_state = get_ocrdma_qp_state(new_ib_state);
1688
1689 /* sync with wqe and rqe posting */
1690 spin_lock_irqsave(&qp->q_lock, flags);
1691
1692 if (old_ib_state)
1693 *old_ib_state = get_ibqp_state(qp->state);
1694 if (new_state == qp->state) {
1695 spin_unlock_irqrestore(&qp->q_lock, flags);
1696 return 1;
1697 }
1698
1699 switch (qp->state) {
1700 case OCRDMA_QPS_RST:
1701 switch (new_state) {
1702 case OCRDMA_QPS_RST:
1703 case OCRDMA_QPS_INIT:
1704 break;
1705 default:
1706 status = -EINVAL;
1707 break;
1708 };
1709 break;
1710 case OCRDMA_QPS_INIT:
1711 /* qps: INIT->XXX */
1712 switch (new_state) {
1713 case OCRDMA_QPS_INIT:
1714 case OCRDMA_QPS_RTR:
1715 break;
1716 case OCRDMA_QPS_ERR:
1717 ocrdma_flush_qp(qp);
1718 break;
1719 default:
1720 status = -EINVAL;
1721 break;
1722 };
1723 break;
1724 case OCRDMA_QPS_RTR:
1725 /* qps: RTS->XXX */
1726 switch (new_state) {
1727 case OCRDMA_QPS_RTS:
1728 break;
1729 case OCRDMA_QPS_ERR:
1730 ocrdma_flush_qp(qp);
1731 break;
1732 default:
1733 status = -EINVAL;
1734 break;
1735 };
1736 break;
1737 case OCRDMA_QPS_RTS:
1738 /* qps: RTS->XXX */
1739 switch (new_state) {
1740 case OCRDMA_QPS_SQD:
1741 case OCRDMA_QPS_SQE:
1742 break;
1743 case OCRDMA_QPS_ERR:
1744 ocrdma_flush_qp(qp);
1745 break;
1746 default:
1747 status = -EINVAL;
1748 break;
1749 };
1750 break;
1751 case OCRDMA_QPS_SQD:
1752 /* qps: SQD->XXX */
1753 switch (new_state) {
1754 case OCRDMA_QPS_RTS:
1755 case OCRDMA_QPS_SQE:
1756 case OCRDMA_QPS_ERR:
1757 break;
1758 default:
1759 status = -EINVAL;
1760 break;
1761 };
1762 break;
1763 case OCRDMA_QPS_SQE:
1764 switch (new_state) {
1765 case OCRDMA_QPS_RTS:
1766 case OCRDMA_QPS_ERR:
1767 break;
1768 default:
1769 status = -EINVAL;
1770 break;
1771 };
1772 break;
1773 case OCRDMA_QPS_ERR:
1774 /* qps: ERR->XXX */
1775 switch (new_state) {
1776 case OCRDMA_QPS_RST:
1777 break;
1778 default:
1779 status = -EINVAL;
1780 break;
1781 };
1782 break;
1783 default:
1784 status = -EINVAL;
1785 break;
1786 };
1787 if (!status)
1788 qp->state = new_state;
1789
1790 spin_unlock_irqrestore(&qp->q_lock, flags);
1791 return status;
1792 }
1793
1794 static u32 ocrdma_set_create_qp_mbx_access_flags(struct ocrdma_qp *qp)
1795 {
1796 u32 flags = 0;
1797 if (qp->cap_flags & OCRDMA_QP_INB_RD)
1798 flags |= OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK;
1799 if (qp->cap_flags & OCRDMA_QP_INB_WR)
1800 flags |= OCRDMA_CREATE_QP_REQ_INB_WREN_MASK;
1801 if (qp->cap_flags & OCRDMA_QP_MW_BIND)
1802 flags |= OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK;
1803 if (qp->cap_flags & OCRDMA_QP_LKEY0)
1804 flags |= OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK;
1805 if (qp->cap_flags & OCRDMA_QP_FAST_REG)
1806 flags |= OCRDMA_CREATE_QP_REQ_FMR_EN_MASK;
1807 return flags;
1808 }
1809
1810 static int ocrdma_set_create_qp_sq_cmd(struct ocrdma_create_qp_req *cmd,
1811 struct ib_qp_init_attr *attrs,
1812 struct ocrdma_qp *qp)
1813 {
1814 int status;
1815 u32 len, hw_pages, hw_page_size;
1816 dma_addr_t pa;
1817 struct ocrdma_dev *dev = qp->dev;
1818 struct pci_dev *pdev = dev->nic_info.pdev;
1819 u32 max_wqe_allocated;
1820 u32 max_sges = attrs->cap.max_send_sge;
1821
1822 max_wqe_allocated = attrs->cap.max_send_wr;
1823 /* need to allocate one extra to for GEN1 family */
1824 if (dev->nic_info.dev_family != OCRDMA_GEN2_FAMILY)
1825 max_wqe_allocated += 1;
1826
1827 status = ocrdma_build_q_conf(&max_wqe_allocated,
1828 dev->attr.wqe_size, &hw_pages, &hw_page_size);
1829 if (status) {
1830 pr_err("%s() req. max_send_wr=0x%x\n", __func__,
1831 max_wqe_allocated);
1832 return -EINVAL;
1833 }
1834 qp->sq.max_cnt = max_wqe_allocated;
1835 len = (hw_pages * hw_page_size);
1836
1837 qp->sq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
1838 if (!qp->sq.va)
1839 return -EINVAL;
1840 memset(qp->sq.va, 0, len);
1841 qp->sq.len = len;
1842 qp->sq.pa = pa;
1843 qp->sq.entry_size = dev->attr.wqe_size;
1844 ocrdma_build_q_pages(&cmd->wq_addr[0], hw_pages, pa, hw_page_size);
1845
1846 cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
1847 << OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT);
1848 cmd->num_wq_rq_pages |= (hw_pages <<
1849 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT) &
1850 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK;
1851 cmd->max_sge_send_write |= (max_sges <<
1852 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT) &
1853 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK;
1854 cmd->max_sge_send_write |= (max_sges <<
1855 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT) &
1856 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK;
1857 cmd->max_wqe_rqe |= (ilog2(qp->sq.max_cnt) <<
1858 OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT) &
1859 OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK;
1860 cmd->wqe_rqe_size |= (dev->attr.wqe_size <<
1861 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT) &
1862 OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK;
1863 return 0;
1864 }
1865
1866 static int ocrdma_set_create_qp_rq_cmd(struct ocrdma_create_qp_req *cmd,
1867 struct ib_qp_init_attr *attrs,
1868 struct ocrdma_qp *qp)
1869 {
1870 int status;
1871 u32 len, hw_pages, hw_page_size;
1872 dma_addr_t pa = 0;
1873 struct ocrdma_dev *dev = qp->dev;
1874 struct pci_dev *pdev = dev->nic_info.pdev;
1875 u32 max_rqe_allocated = attrs->cap.max_recv_wr + 1;
1876
1877 status = ocrdma_build_q_conf(&max_rqe_allocated, dev->attr.rqe_size,
1878 &hw_pages, &hw_page_size);
1879 if (status) {
1880 pr_err("%s() req. max_recv_wr=0x%x\n", __func__,
1881 attrs->cap.max_recv_wr + 1);
1882 return status;
1883 }
1884 qp->rq.max_cnt = max_rqe_allocated;
1885 len = (hw_pages * hw_page_size);
1886
1887 qp->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
1888 if (!qp->rq.va)
1889 return -ENOMEM;
1890 memset(qp->rq.va, 0, len);
1891 qp->rq.pa = pa;
1892 qp->rq.len = len;
1893 qp->rq.entry_size = dev->attr.rqe_size;
1894
1895 ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
1896 cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
1897 OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT);
1898 cmd->num_wq_rq_pages |=
1899 (hw_pages << OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT) &
1900 OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK;
1901 cmd->max_sge_recv_flags |= (attrs->cap.max_recv_sge <<
1902 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT) &
1903 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK;
1904 cmd->max_wqe_rqe |= (ilog2(qp->rq.max_cnt) <<
1905 OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT) &
1906 OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK;
1907 cmd->wqe_rqe_size |= (dev->attr.rqe_size <<
1908 OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT) &
1909 OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK;
1910 return 0;
1911 }
1912
1913 static void ocrdma_set_create_qp_dpp_cmd(struct ocrdma_create_qp_req *cmd,
1914 struct ocrdma_pd *pd,
1915 struct ocrdma_qp *qp,
1916 u8 enable_dpp_cq, u16 dpp_cq_id)
1917 {
1918 pd->num_dpp_qp--;
1919 qp->dpp_enabled = true;
1920 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
1921 if (!enable_dpp_cq)
1922 return;
1923 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
1924 cmd->dpp_credits_cqid = dpp_cq_id;
1925 cmd->dpp_credits_cqid |= OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT <<
1926 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT;
1927 }
1928
1929 static int ocrdma_set_create_qp_ird_cmd(struct ocrdma_create_qp_req *cmd,
1930 struct ocrdma_qp *qp)
1931 {
1932 struct ocrdma_dev *dev = qp->dev;
1933 struct pci_dev *pdev = dev->nic_info.pdev;
1934 dma_addr_t pa = 0;
1935 int ird_page_size = dev->attr.ird_page_size;
1936 int ird_q_len = dev->attr.num_ird_pages * ird_page_size;
1937
1938 if (dev->attr.ird == 0)
1939 return 0;
1940
1941 qp->ird_q_va = dma_alloc_coherent(&pdev->dev, ird_q_len,
1942 &pa, GFP_KERNEL);
1943 if (!qp->ird_q_va)
1944 return -ENOMEM;
1945 memset(qp->ird_q_va, 0, ird_q_len);
1946 ocrdma_build_q_pages(&cmd->ird_addr[0], dev->attr.num_ird_pages,
1947 pa, ird_page_size);
1948 return 0;
1949 }
1950
1951 static void ocrdma_get_create_qp_rsp(struct ocrdma_create_qp_rsp *rsp,
1952 struct ocrdma_qp *qp,
1953 struct ib_qp_init_attr *attrs,
1954 u16 *dpp_offset, u16 *dpp_credit_lmt)
1955 {
1956 u32 max_wqe_allocated, max_rqe_allocated;
1957 qp->id = rsp->qp_id & OCRDMA_CREATE_QP_RSP_QP_ID_MASK;
1958 qp->rq.dbid = rsp->sq_rq_id & OCRDMA_CREATE_QP_RSP_RQ_ID_MASK;
1959 qp->sq.dbid = rsp->sq_rq_id >> OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT;
1960 qp->max_ird = rsp->max_ord_ird & OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK;
1961 qp->max_ord = (rsp->max_ord_ird >> OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT);
1962 qp->dpp_enabled = false;
1963 if (rsp->dpp_response & OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK) {
1964 qp->dpp_enabled = true;
1965 *dpp_credit_lmt = (rsp->dpp_response &
1966 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK) >>
1967 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT;
1968 *dpp_offset = (rsp->dpp_response &
1969 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK) >>
1970 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT;
1971 }
1972 max_wqe_allocated =
1973 rsp->max_wqe_rqe >> OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT;
1974 max_wqe_allocated = 1 << max_wqe_allocated;
1975 max_rqe_allocated = 1 << ((u16)rsp->max_wqe_rqe);
1976
1977 qp->sq.max_cnt = max_wqe_allocated;
1978 qp->sq.max_wqe_idx = max_wqe_allocated - 1;
1979
1980 if (!attrs->srq) {
1981 qp->rq.max_cnt = max_rqe_allocated;
1982 qp->rq.max_wqe_idx = max_rqe_allocated - 1;
1983 }
1984 }
1985
1986 int ocrdma_mbx_create_qp(struct ocrdma_qp *qp, struct ib_qp_init_attr *attrs,
1987 u8 enable_dpp_cq, u16 dpp_cq_id, u16 *dpp_offset,
1988 u16 *dpp_credit_lmt)
1989 {
1990 int status = -ENOMEM;
1991 u32 flags = 0;
1992 struct ocrdma_dev *dev = qp->dev;
1993 struct ocrdma_pd *pd = qp->pd;
1994 struct pci_dev *pdev = dev->nic_info.pdev;
1995 struct ocrdma_cq *cq;
1996 struct ocrdma_create_qp_req *cmd;
1997 struct ocrdma_create_qp_rsp *rsp;
1998 int qptype;
1999
2000 switch (attrs->qp_type) {
2001 case IB_QPT_GSI:
2002 qptype = OCRDMA_QPT_GSI;
2003 break;
2004 case IB_QPT_RC:
2005 qptype = OCRDMA_QPT_RC;
2006 break;
2007 case IB_QPT_UD:
2008 qptype = OCRDMA_QPT_UD;
2009 break;
2010 default:
2011 return -EINVAL;
2012 };
2013
2014 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_QP, sizeof(*cmd));
2015 if (!cmd)
2016 return status;
2017 cmd->type_pgsz_pdn |= (qptype << OCRDMA_CREATE_QP_REQ_QPT_SHIFT) &
2018 OCRDMA_CREATE_QP_REQ_QPT_MASK;
2019 status = ocrdma_set_create_qp_sq_cmd(cmd, attrs, qp);
2020 if (status)
2021 goto sq_err;
2022
2023 if (attrs->srq) {
2024 struct ocrdma_srq *srq = get_ocrdma_srq(attrs->srq);
2025 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK;
2026 cmd->rq_addr[0].lo = srq->id;
2027 qp->srq = srq;
2028 } else {
2029 status = ocrdma_set_create_qp_rq_cmd(cmd, attrs, qp);
2030 if (status)
2031 goto rq_err;
2032 }
2033
2034 status = ocrdma_set_create_qp_ird_cmd(cmd, qp);
2035 if (status)
2036 goto mbx_err;
2037
2038 cmd->type_pgsz_pdn |= (pd->id << OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT) &
2039 OCRDMA_CREATE_QP_REQ_PD_ID_MASK;
2040
2041 flags = ocrdma_set_create_qp_mbx_access_flags(qp);
2042
2043 cmd->max_sge_recv_flags |= flags;
2044 cmd->max_ord_ird |= (dev->attr.max_ord_per_qp <<
2045 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT) &
2046 OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK;
2047 cmd->max_ord_ird |= (dev->attr.max_ird_per_qp <<
2048 OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT) &
2049 OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK;
2050 cq = get_ocrdma_cq(attrs->send_cq);
2051 cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT) &
2052 OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK;
2053 qp->sq_cq = cq;
2054 cq = get_ocrdma_cq(attrs->recv_cq);
2055 cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT) &
2056 OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK;
2057 qp->rq_cq = cq;
2058
2059 if (pd->dpp_enabled && attrs->cap.max_inline_data && pd->num_dpp_qp &&
2060 (attrs->cap.max_inline_data <= dev->attr.max_inline_data))
2061 ocrdma_set_create_qp_dpp_cmd(cmd, pd, qp, enable_dpp_cq,
2062 dpp_cq_id);
2063
2064 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2065 if (status)
2066 goto mbx_err;
2067 rsp = (struct ocrdma_create_qp_rsp *)cmd;
2068 ocrdma_get_create_qp_rsp(rsp, qp, attrs, dpp_offset, dpp_credit_lmt);
2069 qp->state = OCRDMA_QPS_RST;
2070 kfree(cmd);
2071 return 0;
2072 mbx_err:
2073 if (qp->rq.va)
2074 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2075 rq_err:
2076 pr_err("%s(%d) rq_err\n", __func__, dev->id);
2077 dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2078 sq_err:
2079 pr_err("%s(%d) sq_err\n", __func__, dev->id);
2080 kfree(cmd);
2081 return status;
2082 }
2083
2084 int ocrdma_mbx_query_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
2085 struct ocrdma_qp_params *param)
2086 {
2087 int status = -ENOMEM;
2088 struct ocrdma_query_qp *cmd;
2089 struct ocrdma_query_qp_rsp *rsp;
2090
2091 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_QP, sizeof(*cmd));
2092 if (!cmd)
2093 return status;
2094 cmd->qp_id = qp->id;
2095 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2096 if (status)
2097 goto mbx_err;
2098 rsp = (struct ocrdma_query_qp_rsp *)cmd;
2099 memcpy(param, &rsp->params, sizeof(struct ocrdma_qp_params));
2100 mbx_err:
2101 kfree(cmd);
2102 return status;
2103 }
2104
2105 int ocrdma_resolve_dgid(struct ocrdma_dev *dev, union ib_gid *dgid,
2106 u8 *mac_addr)
2107 {
2108 struct in6_addr in6;
2109
2110 memcpy(&in6, dgid, sizeof in6);
2111 if (rdma_is_multicast_addr(&in6))
2112 rdma_get_mcast_mac(&in6, mac_addr);
2113 else if (rdma_link_local_addr(&in6))
2114 rdma_get_ll_mac(&in6, mac_addr);
2115 else {
2116 pr_err("%s() fail to resolve mac_addr.\n", __func__);
2117 return -EINVAL;
2118 }
2119 return 0;
2120 }
2121
2122 static void ocrdma_set_av_params(struct ocrdma_qp *qp,
2123 struct ocrdma_modify_qp *cmd,
2124 struct ib_qp_attr *attrs)
2125 {
2126 struct ib_ah_attr *ah_attr = &attrs->ah_attr;
2127 union ib_gid sgid;
2128 u32 vlan_id;
2129 u8 mac_addr[6];
2130 if ((ah_attr->ah_flags & IB_AH_GRH) == 0)
2131 return;
2132 cmd->params.tclass_sq_psn |=
2133 (ah_attr->grh.traffic_class << OCRDMA_QP_PARAMS_TCLASS_SHIFT);
2134 cmd->params.rnt_rc_sl_fl |=
2135 (ah_attr->grh.flow_label & OCRDMA_QP_PARAMS_FLOW_LABEL_MASK);
2136 cmd->params.hop_lmt_rq_psn |=
2137 (ah_attr->grh.hop_limit << OCRDMA_QP_PARAMS_HOP_LMT_SHIFT);
2138 cmd->flags |= OCRDMA_QP_PARA_FLOW_LBL_VALID;
2139 memcpy(&cmd->params.dgid[0], &ah_attr->grh.dgid.raw[0],
2140 sizeof(cmd->params.dgid));
2141 ocrdma_query_gid(&qp->dev->ibdev, 1,
2142 ah_attr->grh.sgid_index, &sgid);
2143 qp->sgid_idx = ah_attr->grh.sgid_index;
2144 memcpy(&cmd->params.sgid[0], &sgid.raw[0], sizeof(cmd->params.sgid));
2145 ocrdma_resolve_dgid(qp->dev, &ah_attr->grh.dgid, &mac_addr[0]);
2146 cmd->params.dmac_b0_to_b3 = mac_addr[0] | (mac_addr[1] << 8) |
2147 (mac_addr[2] << 16) | (mac_addr[3] << 24);
2148 /* convert them to LE format. */
2149 ocrdma_cpu_to_le32(&cmd->params.dgid[0], sizeof(cmd->params.dgid));
2150 ocrdma_cpu_to_le32(&cmd->params.sgid[0], sizeof(cmd->params.sgid));
2151 cmd->params.vlan_dmac_b4_to_b5 = mac_addr[4] | (mac_addr[5] << 8);
2152 vlan_id = rdma_get_vlan_id(&sgid);
2153 if (vlan_id && (vlan_id < 0x1000)) {
2154 cmd->params.vlan_dmac_b4_to_b5 |=
2155 vlan_id << OCRDMA_QP_PARAMS_VLAN_SHIFT;
2156 cmd->flags |= OCRDMA_QP_PARA_VLAN_EN_VALID;
2157 }
2158 }
2159
2160 static int ocrdma_set_qp_params(struct ocrdma_qp *qp,
2161 struct ocrdma_modify_qp *cmd,
2162 struct ib_qp_attr *attrs, int attr_mask,
2163 enum ib_qp_state old_qps)
2164 {
2165 int status = 0;
2166 struct net_device *netdev = qp->dev->nic_info.netdev;
2167 int eth_mtu = iboe_get_mtu(netdev->mtu);
2168
2169 if (attr_mask & IB_QP_PKEY_INDEX) {
2170 cmd->params.path_mtu_pkey_indx |= (attrs->pkey_index &
2171 OCRDMA_QP_PARAMS_PKEY_INDEX_MASK);
2172 cmd->flags |= OCRDMA_QP_PARA_PKEY_VALID;
2173 }
2174 if (attr_mask & IB_QP_QKEY) {
2175 qp->qkey = attrs->qkey;
2176 cmd->params.qkey = attrs->qkey;
2177 cmd->flags |= OCRDMA_QP_PARA_QKEY_VALID;
2178 }
2179 if (attr_mask & IB_QP_AV)
2180 ocrdma_set_av_params(qp, cmd, attrs);
2181 else if (qp->qp_type == IB_QPT_GSI || qp->qp_type == IB_QPT_UD) {
2182 /* set the default mac address for UD, GSI QPs */
2183 cmd->params.dmac_b0_to_b3 = qp->dev->nic_info.mac_addr[0] |
2184 (qp->dev->nic_info.mac_addr[1] << 8) |
2185 (qp->dev->nic_info.mac_addr[2] << 16) |
2186 (qp->dev->nic_info.mac_addr[3] << 24);
2187 cmd->params.vlan_dmac_b4_to_b5 = qp->dev->nic_info.mac_addr[4] |
2188 (qp->dev->nic_info.mac_addr[5] << 8);
2189 }
2190 if ((attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) &&
2191 attrs->en_sqd_async_notify) {
2192 cmd->params.max_sge_recv_flags |=
2193 OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC;
2194 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2195 }
2196 if (attr_mask & IB_QP_DEST_QPN) {
2197 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->dest_qp_num &
2198 OCRDMA_QP_PARAMS_DEST_QPN_MASK);
2199 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2200 }
2201 if (attr_mask & IB_QP_PATH_MTU) {
2202 if (ib_mtu_enum_to_int(eth_mtu) <
2203 ib_mtu_enum_to_int(attrs->path_mtu)) {
2204 status = -EINVAL;
2205 goto pmtu_err;
2206 }
2207 cmd->params.path_mtu_pkey_indx |=
2208 (ib_mtu_enum_to_int(attrs->path_mtu) <<
2209 OCRDMA_QP_PARAMS_PATH_MTU_SHIFT) &
2210 OCRDMA_QP_PARAMS_PATH_MTU_MASK;
2211 cmd->flags |= OCRDMA_QP_PARA_PMTU_VALID;
2212 }
2213 if (attr_mask & IB_QP_TIMEOUT) {
2214 cmd->params.ack_to_rnr_rtc_dest_qpn |= attrs->timeout <<
2215 OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT;
2216 cmd->flags |= OCRDMA_QP_PARA_ACK_TO_VALID;
2217 }
2218 if (attr_mask & IB_QP_RETRY_CNT) {
2219 cmd->params.rnt_rc_sl_fl |= (attrs->retry_cnt <<
2220 OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT) &
2221 OCRDMA_QP_PARAMS_RETRY_CNT_MASK;
2222 cmd->flags |= OCRDMA_QP_PARA_RETRY_CNT_VALID;
2223 }
2224 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
2225 cmd->params.rnt_rc_sl_fl |= (attrs->min_rnr_timer <<
2226 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT) &
2227 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK;
2228 cmd->flags |= OCRDMA_QP_PARA_RNT_VALID;
2229 }
2230 if (attr_mask & IB_QP_RNR_RETRY) {
2231 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->rnr_retry <<
2232 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT)
2233 & OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK;
2234 cmd->flags |= OCRDMA_QP_PARA_RRC_VALID;
2235 }
2236 if (attr_mask & IB_QP_SQ_PSN) {
2237 cmd->params.tclass_sq_psn |= (attrs->sq_psn & 0x00ffffff);
2238 cmd->flags |= OCRDMA_QP_PARA_SQPSN_VALID;
2239 }
2240 if (attr_mask & IB_QP_RQ_PSN) {
2241 cmd->params.hop_lmt_rq_psn |= (attrs->rq_psn & 0x00ffffff);
2242 cmd->flags |= OCRDMA_QP_PARA_RQPSN_VALID;
2243 }
2244 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2245 if (attrs->max_rd_atomic > qp->dev->attr.max_ord_per_qp) {
2246 status = -EINVAL;
2247 goto pmtu_err;
2248 }
2249 qp->max_ord = attrs->max_rd_atomic;
2250 cmd->flags |= OCRDMA_QP_PARA_MAX_ORD_VALID;
2251 }
2252 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2253 if (attrs->max_dest_rd_atomic > qp->dev->attr.max_ird_per_qp) {
2254 status = -EINVAL;
2255 goto pmtu_err;
2256 }
2257 qp->max_ird = attrs->max_dest_rd_atomic;
2258 cmd->flags |= OCRDMA_QP_PARA_MAX_IRD_VALID;
2259 }
2260 cmd->params.max_ord_ird = (qp->max_ord <<
2261 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT) |
2262 (qp->max_ird & OCRDMA_QP_PARAMS_MAX_IRD_MASK);
2263 pmtu_err:
2264 return status;
2265 }
2266
2267 int ocrdma_mbx_modify_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
2268 struct ib_qp_attr *attrs, int attr_mask,
2269 enum ib_qp_state old_qps)
2270 {
2271 int status = -ENOMEM;
2272 struct ocrdma_modify_qp *cmd;
2273
2274 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_QP, sizeof(*cmd));
2275 if (!cmd)
2276 return status;
2277
2278 cmd->params.id = qp->id;
2279 cmd->flags = 0;
2280 if (attr_mask & IB_QP_STATE) {
2281 cmd->params.max_sge_recv_flags |=
2282 (get_ocrdma_qp_state(attrs->qp_state) <<
2283 OCRDMA_QP_PARAMS_STATE_SHIFT) &
2284 OCRDMA_QP_PARAMS_STATE_MASK;
2285 cmd->flags |= OCRDMA_QP_PARA_QPS_VALID;
2286 } else
2287 cmd->params.max_sge_recv_flags |=
2288 (qp->state << OCRDMA_QP_PARAMS_STATE_SHIFT) &
2289 OCRDMA_QP_PARAMS_STATE_MASK;
2290 status = ocrdma_set_qp_params(qp, cmd, attrs, attr_mask, old_qps);
2291 if (status)
2292 goto mbx_err;
2293 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2294 if (status)
2295 goto mbx_err;
2296
2297 mbx_err:
2298 kfree(cmd);
2299 return status;
2300 }
2301
2302 int ocrdma_mbx_destroy_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp)
2303 {
2304 int status = -ENOMEM;
2305 struct ocrdma_destroy_qp *cmd;
2306 struct pci_dev *pdev = dev->nic_info.pdev;
2307
2308 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_QP, sizeof(*cmd));
2309 if (!cmd)
2310 return status;
2311 cmd->qp_id = qp->id;
2312 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2313 if (status)
2314 goto mbx_err;
2315
2316 mbx_err:
2317 kfree(cmd);
2318 if (qp->sq.va)
2319 dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2320 if (!qp->srq && qp->rq.va)
2321 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2322 if (qp->dpp_enabled)
2323 qp->pd->num_dpp_qp++;
2324 return status;
2325 }
2326
2327 int ocrdma_mbx_create_srq(struct ocrdma_srq *srq,
2328 struct ib_srq_init_attr *srq_attr,
2329 struct ocrdma_pd *pd)
2330 {
2331 int status = -ENOMEM;
2332 int hw_pages, hw_page_size;
2333 int len;
2334 struct ocrdma_create_srq_rsp *rsp;
2335 struct ocrdma_create_srq *cmd;
2336 dma_addr_t pa;
2337 struct ocrdma_dev *dev = srq->dev;
2338 struct pci_dev *pdev = dev->nic_info.pdev;
2339 u32 max_rqe_allocated;
2340
2341 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_SRQ, sizeof(*cmd));
2342 if (!cmd)
2343 return status;
2344
2345 cmd->pgsz_pdid = pd->id & OCRDMA_CREATE_SRQ_PD_ID_MASK;
2346 max_rqe_allocated = srq_attr->attr.max_wr + 1;
2347 status = ocrdma_build_q_conf(&max_rqe_allocated,
2348 dev->attr.rqe_size,
2349 &hw_pages, &hw_page_size);
2350 if (status) {
2351 pr_err("%s() req. max_wr=0x%x\n", __func__,
2352 srq_attr->attr.max_wr);
2353 status = -EINVAL;
2354 goto ret;
2355 }
2356 len = hw_pages * hw_page_size;
2357 srq->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2358 if (!srq->rq.va) {
2359 status = -ENOMEM;
2360 goto ret;
2361 }
2362 ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
2363
2364 srq->rq.entry_size = dev->attr.rqe_size;
2365 srq->rq.pa = pa;
2366 srq->rq.len = len;
2367 srq->rq.max_cnt = max_rqe_allocated;
2368
2369 cmd->max_sge_rqe = ilog2(max_rqe_allocated);
2370 cmd->max_sge_rqe |= srq_attr->attr.max_sge <<
2371 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT;
2372
2373 cmd->pgsz_pdid |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
2374 << OCRDMA_CREATE_SRQ_PG_SZ_SHIFT);
2375 cmd->pages_rqe_sz |= (dev->attr.rqe_size
2376 << OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT)
2377 & OCRDMA_CREATE_SRQ_RQE_SIZE_MASK;
2378 cmd->pages_rqe_sz |= hw_pages << OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT;
2379
2380 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2381 if (status)
2382 goto mbx_err;
2383 rsp = (struct ocrdma_create_srq_rsp *)cmd;
2384 srq->id = rsp->id;
2385 srq->rq.dbid = rsp->id;
2386 max_rqe_allocated = ((rsp->max_sge_rqe_allocated &
2387 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK) >>
2388 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT);
2389 max_rqe_allocated = (1 << max_rqe_allocated);
2390 srq->rq.max_cnt = max_rqe_allocated;
2391 srq->rq.max_wqe_idx = max_rqe_allocated - 1;
2392 srq->rq.max_sges = (rsp->max_sge_rqe_allocated &
2393 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK) >>
2394 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT;
2395 goto ret;
2396 mbx_err:
2397 dma_free_coherent(&pdev->dev, srq->rq.len, srq->rq.va, pa);
2398 ret:
2399 kfree(cmd);
2400 return status;
2401 }
2402
2403 int ocrdma_mbx_modify_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2404 {
2405 int status = -ENOMEM;
2406 struct ocrdma_modify_srq *cmd;
2407 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_SRQ, sizeof(*cmd));
2408 if (!cmd)
2409 return status;
2410 cmd->id = srq->id;
2411 cmd->limit_max_rqe |= srq_attr->srq_limit <<
2412 OCRDMA_MODIFY_SRQ_LIMIT_SHIFT;
2413 status = ocrdma_mbx_cmd(srq->dev, (struct ocrdma_mqe *)cmd);
2414 kfree(cmd);
2415 return status;
2416 }
2417
2418 int ocrdma_mbx_query_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2419 {
2420 int status = -ENOMEM;
2421 struct ocrdma_query_srq *cmd;
2422 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_SRQ, sizeof(*cmd));
2423 if (!cmd)
2424 return status;
2425 cmd->id = srq->rq.dbid;
2426 status = ocrdma_mbx_cmd(srq->dev, (struct ocrdma_mqe *)cmd);
2427 if (status == 0) {
2428 struct ocrdma_query_srq_rsp *rsp =
2429 (struct ocrdma_query_srq_rsp *)cmd;
2430 srq_attr->max_sge =
2431 rsp->srq_lmt_max_sge &
2432 OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK;
2433 srq_attr->max_wr =
2434 rsp->max_rqe_pdid >> OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT;
2435 srq_attr->srq_limit = rsp->srq_lmt_max_sge >>
2436 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT;
2437 }
2438 kfree(cmd);
2439 return status;
2440 }
2441
2442 int ocrdma_mbx_destroy_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq)
2443 {
2444 int status = -ENOMEM;
2445 struct ocrdma_destroy_srq *cmd;
2446 struct pci_dev *pdev = dev->nic_info.pdev;
2447 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_SRQ, sizeof(*cmd));
2448 if (!cmd)
2449 return status;
2450 cmd->id = srq->id;
2451 status = ocrdma_mbx_cmd(srq->dev, (struct ocrdma_mqe *)cmd);
2452 if (srq->rq.va)
2453 dma_free_coherent(&pdev->dev, srq->rq.len,
2454 srq->rq.va, srq->rq.pa);
2455 kfree(cmd);
2456 return status;
2457 }
2458
2459 int ocrdma_alloc_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
2460 {
2461 int i;
2462 int status = -EINVAL;
2463 struct ocrdma_av *av;
2464 unsigned long flags;
2465
2466 av = dev->av_tbl.va;
2467 spin_lock_irqsave(&dev->av_tbl.lock, flags);
2468 for (i = 0; i < dev->av_tbl.num_ah; i++) {
2469 if (av->valid == 0) {
2470 av->valid = OCRDMA_AV_VALID;
2471 ah->av = av;
2472 ah->id = i;
2473 status = 0;
2474 break;
2475 }
2476 av++;
2477 }
2478 if (i == dev->av_tbl.num_ah)
2479 status = -EAGAIN;
2480 spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
2481 return status;
2482 }
2483
2484 int ocrdma_free_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
2485 {
2486 unsigned long flags;
2487 spin_lock_irqsave(&dev->av_tbl.lock, flags);
2488 ah->av->valid = 0;
2489 spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
2490 return 0;
2491 }
2492
2493 static int ocrdma_create_mq_eq(struct ocrdma_dev *dev)
2494 {
2495 int status;
2496 int irq;
2497 unsigned long flags = 0;
2498 int num_eq = 0;
2499
2500 if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX)
2501 flags = IRQF_SHARED;
2502 else {
2503 num_eq = dev->nic_info.msix.num_vectors -
2504 dev->nic_info.msix.start_vector;
2505 /* minimum two vectors/eq are required for rdma to work.
2506 * one for control path and one for data path.
2507 */
2508 if (num_eq < 2)
2509 return -EBUSY;
2510 }
2511
2512 status = ocrdma_create_eq(dev, &dev->meq, OCRDMA_EQ_LEN);
2513 if (status)
2514 return status;
2515 sprintf(dev->meq.irq_name, "ocrdma_mq%d", dev->id);
2516 irq = ocrdma_get_irq(dev, &dev->meq);
2517 status = request_irq(irq, ocrdma_irq_handler, flags, dev->meq.irq_name,
2518 &dev->meq);
2519 if (status)
2520 _ocrdma_destroy_eq(dev, &dev->meq);
2521 return status;
2522 }
2523
2524 static int ocrdma_create_qp_eqs(struct ocrdma_dev *dev)
2525 {
2526 int num_eq, i, status = 0;
2527 int irq;
2528 unsigned long flags = 0;
2529
2530 num_eq = dev->nic_info.msix.num_vectors -
2531 dev->nic_info.msix.start_vector;
2532 if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX) {
2533 num_eq = 1;
2534 flags = IRQF_SHARED;
2535 } else
2536 num_eq = min_t(u32, num_eq, num_online_cpus());
2537 dev->qp_eq_tbl = kzalloc(sizeof(struct ocrdma_eq) * num_eq, GFP_KERNEL);
2538 if (!dev->qp_eq_tbl)
2539 return -ENOMEM;
2540
2541 for (i = 0; i < num_eq; i++) {
2542 status = ocrdma_create_eq(dev, &dev->qp_eq_tbl[i],
2543 OCRDMA_EQ_LEN);
2544 if (status) {
2545 status = -EINVAL;
2546 break;
2547 }
2548 sprintf(dev->qp_eq_tbl[i].irq_name, "ocrdma_qp%d-%d",
2549 dev->id, i);
2550 irq = ocrdma_get_irq(dev, &dev->qp_eq_tbl[i]);
2551 status = request_irq(irq, ocrdma_irq_handler, flags,
2552 dev->qp_eq_tbl[i].irq_name,
2553 &dev->qp_eq_tbl[i]);
2554 if (status) {
2555 _ocrdma_destroy_eq(dev, &dev->qp_eq_tbl[i]);
2556 status = -EINVAL;
2557 break;
2558 }
2559 dev->eq_cnt += 1;
2560 }
2561 /* one eq is sufficient for data path to work */
2562 if (dev->eq_cnt >= 1)
2563 return 0;
2564 if (status)
2565 ocrdma_destroy_qp_eqs(dev);
2566 return status;
2567 }
2568
2569 int ocrdma_init_hw(struct ocrdma_dev *dev)
2570 {
2571 int status;
2572 /* set up control path eq */
2573 status = ocrdma_create_mq_eq(dev);
2574 if (status)
2575 return status;
2576 /* set up data path eq */
2577 status = ocrdma_create_qp_eqs(dev);
2578 if (status)
2579 goto qpeq_err;
2580 status = ocrdma_create_mq(dev);
2581 if (status)
2582 goto mq_err;
2583 status = ocrdma_mbx_query_fw_config(dev);
2584 if (status)
2585 goto conf_err;
2586 status = ocrdma_mbx_query_dev(dev);
2587 if (status)
2588 goto conf_err;
2589 status = ocrdma_mbx_query_fw_ver(dev);
2590 if (status)
2591 goto conf_err;
2592 status = ocrdma_mbx_create_ah_tbl(dev);
2593 if (status)
2594 goto conf_err;
2595 return 0;
2596
2597 conf_err:
2598 ocrdma_destroy_mq(dev);
2599 mq_err:
2600 ocrdma_destroy_qp_eqs(dev);
2601 qpeq_err:
2602 ocrdma_destroy_eq(dev, &dev->meq);
2603 pr_err("%s() status=%d\n", __func__, status);
2604 return status;
2605 }
2606
2607 void ocrdma_cleanup_hw(struct ocrdma_dev *dev)
2608 {
2609 ocrdma_mbx_delete_ah_tbl(dev);
2610
2611 /* cleanup the data path eqs */
2612 ocrdma_destroy_qp_eqs(dev);
2613
2614 /* cleanup the control path */
2615 ocrdma_destroy_mq(dev);
2616 ocrdma_destroy_eq(dev, &dev->meq);
2617 }
CRIS linux kernel tree