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Linux 3.11-rc3
[cris-mirror.git] / drivers / media / pci / cx23885 / cx23885-dvb.c
blob9c5ed10b2c5eb8e5d1c03897d2bf5813f68a41fa
1 /*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22 #include <linux/module.h>
23 #include <linux/init.h>
24 #include <linux/device.h>
25 #include <linux/fs.h>
26 #include <linux/kthread.h>
27 #include <linux/file.h>
28 #include <linux/suspend.h>
29
30 #include "cx23885.h"
31 #include <media/v4l2-common.h>
32
33 #include "dvb_ca_en50221.h"
34 #include "s5h1409.h"
35 #include "s5h1411.h"
36 #include "mt2131.h"
37 #include "tda8290.h"
38 #include "tda18271.h"
39 #include "lgdt330x.h"
40 #include "xc4000.h"
41 #include "xc5000.h"
42 #include "max2165.h"
43 #include "tda10048.h"
44 #include "tuner-xc2028.h"
45 #include "tuner-simple.h"
46 #include "dib7000p.h"
47 #include "dibx000_common.h"
48 #include "zl10353.h"
49 #include "stv0900.h"
50 #include "stv0900_reg.h"
51 #include "stv6110.h"
52 #include "lnbh24.h"
53 #include "cx24116.h"
54 #include "cimax2.h"
55 #include "lgs8gxx.h"
56 #include "netup-eeprom.h"
57 #include "netup-init.h"
58 #include "lgdt3305.h"
59 #include "atbm8830.h"
60 #include "ts2020.h"
61 #include "ds3000.h"
62 #include "cx23885-f300.h"
63 #include "altera-ci.h"
64 #include "stv0367.h"
65 #include "drxk.h"
66 #include "mt2063.h"
67 #include "stv090x.h"
68 #include "stb6100.h"
69 #include "stb6100_cfg.h"
70 #include "tda10071.h"
71 #include "a8293.h"
72
73 static unsigned int debug;
74
75 #define dprintk(level, fmt, arg...)\
76 do { if (debug >= level)\
77 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
78 } while (0)
79
80 /* ------------------------------------------------------------------ */
81
82 static unsigned int alt_tuner;
83 module_param(alt_tuner, int, 0644);
84 MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
85
86 DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
87
88 /* ------------------------------------------------------------------ */
89
90 static int dvb_buf_setup(struct videobuf_queue *q,
91 unsigned int *count, unsigned int *size)
92 {
93 struct cx23885_tsport *port = q->priv_data;
94
95 port->ts_packet_size = 188 * 4;
96 port->ts_packet_count = 32;
97
98 *size = port->ts_packet_size * port->ts_packet_count;
99 *count = 32;
100 return 0;
101 }
102
103 static int dvb_buf_prepare(struct videobuf_queue *q,
104 struct videobuf_buffer *vb, enum v4l2_field field)
105 {
106 struct cx23885_tsport *port = q->priv_data;
107 return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field);
108 }
109
110 static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
111 {
112 struct cx23885_tsport *port = q->priv_data;
113 cx23885_buf_queue(port, (struct cx23885_buffer *)vb);
114 }
115
116 static void dvb_buf_release(struct videobuf_queue *q,
117 struct videobuf_buffer *vb)
118 {
119 cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
120 }
121
122 static int cx23885_dvb_set_frontend(struct dvb_frontend *fe);
123
124 static void cx23885_dvb_gate_ctrl(struct cx23885_tsport *port, int open)
125 {
126 struct videobuf_dvb_frontends *f;
127 struct videobuf_dvb_frontend *fe;
128
129 f = &port->frontends;
130
131 if (f->gate <= 1) /* undefined or fe0 */
132 fe = videobuf_dvb_get_frontend(f, 1);
133 else
134 fe = videobuf_dvb_get_frontend(f, f->gate);
135
136 if (fe && fe->dvb.frontend && fe->dvb.frontend->ops.i2c_gate_ctrl)
137 fe->dvb.frontend->ops.i2c_gate_ctrl(fe->dvb.frontend, open);
138
139 /*
140 * FIXME: Improve this path to avoid calling the
141 * cx23885_dvb_set_frontend() every time it passes here.
142 */
143 cx23885_dvb_set_frontend(fe->dvb.frontend);
144 }
145
146 static struct videobuf_queue_ops dvb_qops = {
147 .buf_setup = dvb_buf_setup,
148 .buf_prepare = dvb_buf_prepare,
149 .buf_queue = dvb_buf_queue,
150 .buf_release = dvb_buf_release,
151 };
152
153 static struct s5h1409_config hauppauge_generic_config = {
154 .demod_address = 0x32 >> 1,
155 .output_mode = S5H1409_SERIAL_OUTPUT,
156 .gpio = S5H1409_GPIO_ON,
157 .qam_if = 44000,
158 .inversion = S5H1409_INVERSION_OFF,
159 .status_mode = S5H1409_DEMODLOCKING,
160 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
161 };
162
163 static struct tda10048_config hauppauge_hvr1200_config = {
164 .demod_address = 0x10 >> 1,
165 .output_mode = TDA10048_SERIAL_OUTPUT,
166 .fwbulkwritelen = TDA10048_BULKWRITE_200,
167 .inversion = TDA10048_INVERSION_ON,
168 .dtv6_if_freq_khz = TDA10048_IF_3300,
169 .dtv7_if_freq_khz = TDA10048_IF_3800,
170 .dtv8_if_freq_khz = TDA10048_IF_4300,
171 .clk_freq_khz = TDA10048_CLK_16000,
172 };
173
174 static struct tda10048_config hauppauge_hvr1210_config = {
175 .demod_address = 0x10 >> 1,
176 .output_mode = TDA10048_SERIAL_OUTPUT,
177 .fwbulkwritelen = TDA10048_BULKWRITE_200,
178 .inversion = TDA10048_INVERSION_ON,
179 .dtv6_if_freq_khz = TDA10048_IF_3300,
180 .dtv7_if_freq_khz = TDA10048_IF_3500,
181 .dtv8_if_freq_khz = TDA10048_IF_4000,
182 .clk_freq_khz = TDA10048_CLK_16000,
183 };
184
185 static struct s5h1409_config hauppauge_ezqam_config = {
186 .demod_address = 0x32 >> 1,
187 .output_mode = S5H1409_SERIAL_OUTPUT,
188 .gpio = S5H1409_GPIO_OFF,
189 .qam_if = 4000,
190 .inversion = S5H1409_INVERSION_ON,
191 .status_mode = S5H1409_DEMODLOCKING,
192 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
193 };
194
195 static struct s5h1409_config hauppauge_hvr1800lp_config = {
196 .demod_address = 0x32 >> 1,
197 .output_mode = S5H1409_SERIAL_OUTPUT,
198 .gpio = S5H1409_GPIO_OFF,
199 .qam_if = 44000,
200 .inversion = S5H1409_INVERSION_OFF,
201 .status_mode = S5H1409_DEMODLOCKING,
202 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
203 };
204
205 static struct s5h1409_config hauppauge_hvr1500_config = {
206 .demod_address = 0x32 >> 1,
207 .output_mode = S5H1409_SERIAL_OUTPUT,
208 .gpio = S5H1409_GPIO_OFF,
209 .inversion = S5H1409_INVERSION_OFF,
210 .status_mode = S5H1409_DEMODLOCKING,
211 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
212 };
213
214 static struct mt2131_config hauppauge_generic_tunerconfig = {
215 0x61
216 };
217
218 static struct lgdt330x_config fusionhdtv_5_express = {
219 .demod_address = 0x0e,
220 .demod_chip = LGDT3303,
221 .serial_mpeg = 0x40,
222 };
223
224 static struct s5h1409_config hauppauge_hvr1500q_config = {
225 .demod_address = 0x32 >> 1,
226 .output_mode = S5H1409_SERIAL_OUTPUT,
227 .gpio = S5H1409_GPIO_ON,
228 .qam_if = 44000,
229 .inversion = S5H1409_INVERSION_OFF,
230 .status_mode = S5H1409_DEMODLOCKING,
231 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
232 };
233
234 static struct s5h1409_config dvico_s5h1409_config = {
235 .demod_address = 0x32 >> 1,
236 .output_mode = S5H1409_SERIAL_OUTPUT,
237 .gpio = S5H1409_GPIO_ON,
238 .qam_if = 44000,
239 .inversion = S5H1409_INVERSION_OFF,
240 .status_mode = S5H1409_DEMODLOCKING,
241 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
242 };
243
244 static struct s5h1411_config dvico_s5h1411_config = {
245 .output_mode = S5H1411_SERIAL_OUTPUT,
246 .gpio = S5H1411_GPIO_ON,
247 .qam_if = S5H1411_IF_44000,
248 .vsb_if = S5H1411_IF_44000,
249 .inversion = S5H1411_INVERSION_OFF,
250 .status_mode = S5H1411_DEMODLOCKING,
251 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
252 };
253
254 static struct s5h1411_config hcw_s5h1411_config = {
255 .output_mode = S5H1411_SERIAL_OUTPUT,
256 .gpio = S5H1411_GPIO_OFF,
257 .vsb_if = S5H1411_IF_44000,
258 .qam_if = S5H1411_IF_4000,
259 .inversion = S5H1411_INVERSION_ON,
260 .status_mode = S5H1411_DEMODLOCKING,
261 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
262 };
263
264 static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
265 .i2c_address = 0x61,
266 .if_khz = 5380,
267 };
268
269 static struct xc5000_config dvico_xc5000_tunerconfig = {
270 .i2c_address = 0x64,
271 .if_khz = 5380,
272 };
273
274 static struct tda829x_config tda829x_no_probe = {
275 .probe_tuner = TDA829X_DONT_PROBE,
276 };
277
278 static struct tda18271_std_map hauppauge_tda18271_std_map = {
279 .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
280 .if_lvl = 6, .rfagc_top = 0x37 },
281 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
282 .if_lvl = 6, .rfagc_top = 0x37 },
283 };
284
285 static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = {
286 .dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4,
287 .if_lvl = 1, .rfagc_top = 0x37, },
288 .dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5,
289 .if_lvl = 1, .rfagc_top = 0x37, },
290 .dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6,
291 .if_lvl = 1, .rfagc_top = 0x37, },
292 };
293
294 static struct tda18271_config hauppauge_tda18271_config = {
295 .std_map = &hauppauge_tda18271_std_map,
296 .gate = TDA18271_GATE_ANALOG,
297 .output_opt = TDA18271_OUTPUT_LT_OFF,
298 };
299
300 static struct tda18271_config hauppauge_hvr1200_tuner_config = {
301 .std_map = &hauppauge_hvr1200_tda18271_std_map,
302 .gate = TDA18271_GATE_ANALOG,
303 .output_opt = TDA18271_OUTPUT_LT_OFF,
304 };
305
306 static struct tda18271_config hauppauge_hvr1210_tuner_config = {
307 .gate = TDA18271_GATE_DIGITAL,
308 .output_opt = TDA18271_OUTPUT_LT_OFF,
309 };
310
311 static struct tda18271_std_map hauppauge_hvr127x_std_map = {
312 .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4,
313 .if_lvl = 1, .rfagc_top = 0x58 },
314 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
315 .if_lvl = 1, .rfagc_top = 0x58 },
316 };
317
318 static struct tda18271_config hauppauge_hvr127x_config = {
319 .std_map = &hauppauge_hvr127x_std_map,
320 .output_opt = TDA18271_OUTPUT_LT_OFF,
321 };
322
323 static struct lgdt3305_config hauppauge_lgdt3305_config = {
324 .i2c_addr = 0x0e,
325 .mpeg_mode = LGDT3305_MPEG_SERIAL,
326 .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
327 .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
328 .deny_i2c_rptr = 1,
329 .spectral_inversion = 1,
330 .qam_if_khz = 4000,
331 .vsb_if_khz = 3250,
332 };
333
334 static struct dibx000_agc_config xc3028_agc_config = {
335 BAND_VHF | BAND_UHF, /* band_caps */
336
337 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
338 * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
339 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
340 * P_agc_nb_est=2, P_agc_write=0
341 */
342 (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
343 (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
344
345 712, /* inv_gain */
346 21, /* time_stabiliz */
347
348 0, /* alpha_level */
349 118, /* thlock */
350
351 0, /* wbd_inv */
352 2867, /* wbd_ref */
353 0, /* wbd_sel */
354 2, /* wbd_alpha */
355
356 0, /* agc1_max */
357 0, /* agc1_min */
358 39718, /* agc2_max */
359 9930, /* agc2_min */
360 0, /* agc1_pt1 */
361 0, /* agc1_pt2 */
362 0, /* agc1_pt3 */
363 0, /* agc1_slope1 */
364 0, /* agc1_slope2 */
365 0, /* agc2_pt1 */
366 128, /* agc2_pt2 */
367 29, /* agc2_slope1 */
368 29, /* agc2_slope2 */
369
370 17, /* alpha_mant */
371 27, /* alpha_exp */
372 23, /* beta_mant */
373 51, /* beta_exp */
374
375 1, /* perform_agc_softsplit */
376 };
377
378 /* PLL Configuration for COFDM BW_MHz = 8.000000
379 * With external clock = 30.000000 */
380 static struct dibx000_bandwidth_config xc3028_bw_config = {
381 60000, /* internal */
382 30000, /* sampling */
383 1, /* pll_cfg: prediv */
384 8, /* pll_cfg: ratio */
385 3, /* pll_cfg: range */
386 1, /* pll_cfg: reset */
387 0, /* pll_cfg: bypass */
388 0, /* misc: refdiv */
389 0, /* misc: bypclk_div */
390 1, /* misc: IO_CLK_en_core */
391 1, /* misc: ADClkSrc */
392 0, /* misc: modulo */
393 (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
394 (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
395 20452225, /* timf */
396 30000000 /* xtal_hz */
397 };
398
399 static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
400 .output_mpeg2_in_188_bytes = 1,
401 .hostbus_diversity = 1,
402 .tuner_is_baseband = 0,
403 .update_lna = NULL,
404
405 .agc_config_count = 1,
406 .agc = &xc3028_agc_config,
407 .bw = &xc3028_bw_config,
408
409 .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
410 .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
411 .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
412
413 .pwm_freq_div = 0,
414 .agc_control = NULL,
415 .spur_protect = 0,
416
417 .output_mode = OUTMODE_MPEG2_SERIAL,
418 };
419
420 static struct zl10353_config dvico_fusionhdtv_xc3028 = {
421 .demod_address = 0x0f,
422 .if2 = 45600,
423 .no_tuner = 1,
424 .disable_i2c_gate_ctrl = 1,
425 };
426
427 static struct stv0900_reg stv0900_ts_regs[] = {
428 { R0900_TSGENERAL, 0x00 },
429 { R0900_P1_TSSPEED, 0x40 },
430 { R0900_P2_TSSPEED, 0x40 },
431 { R0900_P1_TSCFGM, 0xc0 },
432 { R0900_P2_TSCFGM, 0xc0 },
433 { R0900_P1_TSCFGH, 0xe0 },
434 { R0900_P2_TSCFGH, 0xe0 },
435 { R0900_P1_TSCFGL, 0x20 },
436 { R0900_P2_TSCFGL, 0x20 },
437 { 0xffff, 0xff }, /* terminate */
438 };
439
440 static struct stv0900_config netup_stv0900_config = {
441 .demod_address = 0x68,
442 .demod_mode = 1, /* dual */
443 .xtal = 8000000,
444 .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
445 .diseqc_mode = 2,/* 2/3 PWM */
446 .ts_config_regs = stv0900_ts_regs,
447 .tun1_maddress = 0,/* 0x60 */
448 .tun2_maddress = 3,/* 0x63 */
449 .tun1_adc = 1,/* 1 Vpp */
450 .tun2_adc = 1,/* 1 Vpp */
451 };
452
453 static struct stv6110_config netup_stv6110_tunerconfig_a = {
454 .i2c_address = 0x60,
455 .mclk = 16000000,
456 .clk_div = 1,
457 .gain = 8, /* +16 dB - maximum gain */
458 };
459
460 static struct stv6110_config netup_stv6110_tunerconfig_b = {
461 .i2c_address = 0x63,
462 .mclk = 16000000,
463 .clk_div = 1,
464 .gain = 8, /* +16 dB - maximum gain */
465 };
466
467 static struct cx24116_config tbs_cx24116_config = {
468 .demod_address = 0x55,
469 };
470
471 static struct ds3000_config tevii_ds3000_config = {
472 .demod_address = 0x68,
473 };
474
475 static struct ts2020_config tevii_ts2020_config = {
476 .tuner_address = 0x60,
477 .clk_out_div = 1,
478 };
479
480 static struct cx24116_config dvbworld_cx24116_config = {
481 .demod_address = 0x05,
482 };
483
484 static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = {
485 .prod = LGS8GXX_PROD_LGS8GL5,
486 .demod_address = 0x19,
487 .serial_ts = 0,
488 .ts_clk_pol = 1,
489 .ts_clk_gated = 1,
490 .if_clk_freq = 30400, /* 30.4 MHz */
491 .if_freq = 5380, /* 5.38 MHz */
492 .if_neg_center = 1,
493 .ext_adc = 0,
494 .adc_signed = 0,
495 .if_neg_edge = 0,
496 };
497
498 static struct xc5000_config mygica_x8506_xc5000_config = {
499 .i2c_address = 0x61,
500 .if_khz = 5380,
501 };
502
503 static struct stv090x_config prof_8000_stv090x_config = {
504 .device = STV0903,
505 .demod_mode = STV090x_SINGLE,
506 .clk_mode = STV090x_CLK_EXT,
507 .xtal = 27000000,
508 .address = 0x6A,
509 .ts1_mode = STV090x_TSMODE_PARALLEL_PUNCTURED,
510 .repeater_level = STV090x_RPTLEVEL_64,
511 .adc1_range = STV090x_ADC_2Vpp,
512 .diseqc_envelope_mode = false,
513
514 .tuner_get_frequency = stb6100_get_frequency,
515 .tuner_set_frequency = stb6100_set_frequency,
516 .tuner_set_bandwidth = stb6100_set_bandwidth,
517 .tuner_get_bandwidth = stb6100_get_bandwidth,
518 };
519
520 static struct stb6100_config prof_8000_stb6100_config = {
521 .tuner_address = 0x60,
522 .refclock = 27000000,
523 };
524
525 static int p8000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
526 {
527 struct cx23885_tsport *port = fe->dvb->priv;
528 struct cx23885_dev *dev = port->dev;
529
530 if (voltage == SEC_VOLTAGE_18)
531 cx_write(MC417_RWD, 0x00001e00);
532 else if (voltage == SEC_VOLTAGE_13)
533 cx_write(MC417_RWD, 0x00001a00);
534 else
535 cx_write(MC417_RWD, 0x00001800);
536 return 0;
537 }
538
539 static int cx23885_dvb_set_frontend(struct dvb_frontend *fe)
540 {
541 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
542 struct cx23885_tsport *port = fe->dvb->priv;
543 struct cx23885_dev *dev = port->dev;
544
545 switch (dev->board) {
546 case CX23885_BOARD_HAUPPAUGE_HVR1275:
547 switch (p->modulation) {
548 case VSB_8:
549 cx23885_gpio_clear(dev, GPIO_5);
550 break;
551 case QAM_64:
552 case QAM_256:
553 default:
554 cx23885_gpio_set(dev, GPIO_5);
555 break;
556 }
557 break;
558 case CX23885_BOARD_MYGICA_X8506:
559 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
560 /* Select Digital TV */
561 cx23885_gpio_set(dev, GPIO_0);
562 break;
563 }
564 return 0;
565 }
566
567 static struct lgs8gxx_config magicpro_prohdtve2_lgs8g75_config = {
568 .prod = LGS8GXX_PROD_LGS8G75,
569 .demod_address = 0x19,
570 .serial_ts = 0,
571 .ts_clk_pol = 1,
572 .ts_clk_gated = 1,
573 .if_clk_freq = 30400, /* 30.4 MHz */
574 .if_freq = 6500, /* 6.50 MHz */
575 .if_neg_center = 1,
576 .ext_adc = 0,
577 .adc_signed = 1,
578 .adc_vpp = 2, /* 1.6 Vpp */
579 .if_neg_edge = 1,
580 };
581
582 static struct xc5000_config magicpro_prohdtve2_xc5000_config = {
583 .i2c_address = 0x61,
584 .if_khz = 6500,
585 };
586
587 static struct atbm8830_config mygica_x8558pro_atbm8830_cfg1 = {
588 .prod = ATBM8830_PROD_8830,
589 .demod_address = 0x44,
590 .serial_ts = 0,
591 .ts_sampling_edge = 1,
592 .ts_clk_gated = 0,
593 .osc_clk_freq = 30400, /* in kHz */
594 .if_freq = 0, /* zero IF */
595 .zif_swap_iq = 1,
596 .agc_min = 0x2E,
597 .agc_max = 0xFF,
598 .agc_hold_loop = 0,
599 };
600
601 static struct max2165_config mygic_x8558pro_max2165_cfg1 = {
602 .i2c_address = 0x60,
603 .osc_clk = 20
604 };
605
606 static struct atbm8830_config mygica_x8558pro_atbm8830_cfg2 = {
607 .prod = ATBM8830_PROD_8830,
608 .demod_address = 0x44,
609 .serial_ts = 1,
610 .ts_sampling_edge = 1,
611 .ts_clk_gated = 0,
612 .osc_clk_freq = 30400, /* in kHz */
613 .if_freq = 0, /* zero IF */
614 .zif_swap_iq = 1,
615 .agc_min = 0x2E,
616 .agc_max = 0xFF,
617 .agc_hold_loop = 0,
618 };
619
620 static struct max2165_config mygic_x8558pro_max2165_cfg2 = {
621 .i2c_address = 0x60,
622 .osc_clk = 20
623 };
624 static struct stv0367_config netup_stv0367_config[] = {
625 {
626 .demod_address = 0x1c,
627 .xtal = 27000000,
628 .if_khz = 4500,
629 .if_iq_mode = 0,
630 .ts_mode = 1,
631 .clk_pol = 0,
632 }, {
633 .demod_address = 0x1d,
634 .xtal = 27000000,
635 .if_khz = 4500,
636 .if_iq_mode = 0,
637 .ts_mode = 1,
638 .clk_pol = 0,
639 },
640 };
641
642 static struct xc5000_config netup_xc5000_config[] = {
643 {
644 .i2c_address = 0x61,
645 .if_khz = 4500,
646 }, {
647 .i2c_address = 0x64,
648 .if_khz = 4500,
649 },
650 };
651
652 static struct drxk_config terratec_drxk_config[] = {
653 {
654 .adr = 0x29,
655 .no_i2c_bridge = 1,
656 }, {
657 .adr = 0x2a,
658 .no_i2c_bridge = 1,
659 },
660 };
661
662 static struct mt2063_config terratec_mt2063_config[] = {
663 {
664 .tuner_address = 0x60,
665 }, {
666 .tuner_address = 0x67,
667 },
668 };
669
670 static const struct tda10071_config hauppauge_tda10071_config = {
671 .demod_i2c_addr = 0x05,
672 .tuner_i2c_addr = 0x54,
673 .i2c_wr_max = 64,
674 .ts_mode = TDA10071_TS_SERIAL,
675 .spec_inv = 0,
676 .xtal = 40444000, /* 40.444 MHz */
677 .pll_multiplier = 20,
678 };
679
680 static const struct a8293_config hauppauge_a8293_config = {
681 .i2c_addr = 0x0b,
682 };
683
684 static int netup_altera_fpga_rw(void *device, int flag, int data, int read)
685 {
686 struct cx23885_dev *dev = (struct cx23885_dev *)device;
687 unsigned long timeout = jiffies + msecs_to_jiffies(1);
688 uint32_t mem = 0;
689
690 mem = cx_read(MC417_RWD);
691 if (read)
692 cx_set(MC417_OEN, ALT_DATA);
693 else {
694 cx_clear(MC417_OEN, ALT_DATA);/* D0-D7 out */
695 mem &= ~ALT_DATA;
696 mem |= (data & ALT_DATA);
697 }
698
699 if (flag)
700 mem |= ALT_AD_RG;
701 else
702 mem &= ~ALT_AD_RG;
703
704 mem &= ~ALT_CS;
705 if (read)
706 mem = (mem & ~ALT_RD) | ALT_WR;
707 else
708 mem = (mem & ~ALT_WR) | ALT_RD;
709
710 cx_write(MC417_RWD, mem); /* start RW cycle */
711
712 for (;;) {
713 mem = cx_read(MC417_RWD);
714 if ((mem & ALT_RDY) == 0)
715 break;
716 if (time_after(jiffies, timeout))
717 break;
718 udelay(1);
719 }
720
721 cx_set(MC417_RWD, ALT_RD | ALT_WR | ALT_CS);
722 if (read)
723 return mem & ALT_DATA;
724
725 return 0;
726 };
727
728 static int dvb_register(struct cx23885_tsport *port)
729 {
730 struct cx23885_dev *dev = port->dev;
731 struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL;
732 struct videobuf_dvb_frontend *fe0, *fe1 = NULL;
733 int mfe_shared = 0; /* bus not shared by default */
734 int ret;
735
736 /* Get the first frontend */
737 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
738 if (!fe0)
739 return -EINVAL;
740
741 /* init struct videobuf_dvb */
742 fe0->dvb.name = dev->name;
743
744 /* multi-frontend gate control is undefined or defaults to fe0 */
745 port->frontends.gate = 0;
746
747 /* Sets the gate control callback to be used by i2c command calls */
748 port->gate_ctrl = cx23885_dvb_gate_ctrl;
749
750 /* init frontend */
751 switch (dev->board) {
752 case CX23885_BOARD_HAUPPAUGE_HVR1250:
753 i2c_bus = &dev->i2c_bus[0];
754 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
755 &hauppauge_generic_config,
756 &i2c_bus->i2c_adap);
757 if (fe0->dvb.frontend != NULL) {
758 dvb_attach(mt2131_attach, fe0->dvb.frontend,
759 &i2c_bus->i2c_adap,
760 &hauppauge_generic_tunerconfig, 0);
761 }
762 break;
763 case CX23885_BOARD_HAUPPAUGE_HVR1270:
764 case CX23885_BOARD_HAUPPAUGE_HVR1275:
765 i2c_bus = &dev->i2c_bus[0];
766 fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
767 &hauppauge_lgdt3305_config,
768 &i2c_bus->i2c_adap);
769 if (fe0->dvb.frontend != NULL) {
770 dvb_attach(tda18271_attach, fe0->dvb.frontend,
771 0x60, &dev->i2c_bus[1].i2c_adap,
772 &hauppauge_hvr127x_config);
773 }
774 break;
775 case CX23885_BOARD_HAUPPAUGE_HVR1255:
776 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
777 i2c_bus = &dev->i2c_bus[0];
778 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
779 &hcw_s5h1411_config,
780 &i2c_bus->i2c_adap);
781 if (fe0->dvb.frontend != NULL) {
782 dvb_attach(tda18271_attach, fe0->dvb.frontend,
783 0x60, &dev->i2c_bus[1].i2c_adap,
784 &hauppauge_tda18271_config);
785 }
786
787 tda18271_attach(&dev->ts1.analog_fe,
788 0x60, &dev->i2c_bus[1].i2c_adap,
789 &hauppauge_tda18271_config);
790
791 break;
792 case CX23885_BOARD_HAUPPAUGE_HVR1800:
793 i2c_bus = &dev->i2c_bus[0];
794 switch (alt_tuner) {
795 case 1:
796 fe0->dvb.frontend =
797 dvb_attach(s5h1409_attach,
798 &hauppauge_ezqam_config,
799 &i2c_bus->i2c_adap);
800 if (fe0->dvb.frontend != NULL) {
801 dvb_attach(tda829x_attach, fe0->dvb.frontend,
802 &dev->i2c_bus[1].i2c_adap, 0x42,
803 &tda829x_no_probe);
804 dvb_attach(tda18271_attach, fe0->dvb.frontend,
805 0x60, &dev->i2c_bus[1].i2c_adap,
806 &hauppauge_tda18271_config);
807 }
808 break;
809 case 0:
810 default:
811 fe0->dvb.frontend =
812 dvb_attach(s5h1409_attach,
813 &hauppauge_generic_config,
814 &i2c_bus->i2c_adap);
815 if (fe0->dvb.frontend != NULL)
816 dvb_attach(mt2131_attach, fe0->dvb.frontend,
817 &i2c_bus->i2c_adap,
818 &hauppauge_generic_tunerconfig, 0);
819 break;
820 }
821 break;
822 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
823 i2c_bus = &dev->i2c_bus[0];
824 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
825 &hauppauge_hvr1800lp_config,
826 &i2c_bus->i2c_adap);
827 if (fe0->dvb.frontend != NULL) {
828 dvb_attach(mt2131_attach, fe0->dvb.frontend,
829 &i2c_bus->i2c_adap,
830 &hauppauge_generic_tunerconfig, 0);
831 }
832 break;
833 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
834 i2c_bus = &dev->i2c_bus[0];
835 fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
836 &fusionhdtv_5_express,
837 &i2c_bus->i2c_adap);
838 if (fe0->dvb.frontend != NULL) {
839 dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
840 &i2c_bus->i2c_adap, 0x61,
841 TUNER_LG_TDVS_H06XF);
842 }
843 break;
844 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
845 i2c_bus = &dev->i2c_bus[1];
846 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
847 &hauppauge_hvr1500q_config,
848 &dev->i2c_bus[0].i2c_adap);
849 if (fe0->dvb.frontend != NULL)
850 dvb_attach(xc5000_attach, fe0->dvb.frontend,
851 &i2c_bus->i2c_adap,
852 &hauppauge_hvr1500q_tunerconfig);
853 break;
854 case CX23885_BOARD_HAUPPAUGE_HVR1500:
855 i2c_bus = &dev->i2c_bus[1];
856 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
857 &hauppauge_hvr1500_config,
858 &dev->i2c_bus[0].i2c_adap);
859 if (fe0->dvb.frontend != NULL) {
860 struct dvb_frontend *fe;
861 struct xc2028_config cfg = {
862 .i2c_adap = &i2c_bus->i2c_adap,
863 .i2c_addr = 0x61,
864 };
865 static struct xc2028_ctrl ctl = {
866 .fname = XC2028_DEFAULT_FIRMWARE,
867 .max_len = 64,
868 .demod = XC3028_FE_OREN538,
869 };
870
871 fe = dvb_attach(xc2028_attach,
872 fe0->dvb.frontend, &cfg);
873 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
874 fe->ops.tuner_ops.set_config(fe, &ctl);
875 }
876 break;
877 case CX23885_BOARD_HAUPPAUGE_HVR1200:
878 case CX23885_BOARD_HAUPPAUGE_HVR1700:
879 i2c_bus = &dev->i2c_bus[0];
880 fe0->dvb.frontend = dvb_attach(tda10048_attach,
881 &hauppauge_hvr1200_config,
882 &i2c_bus->i2c_adap);
883 if (fe0->dvb.frontend != NULL) {
884 dvb_attach(tda829x_attach, fe0->dvb.frontend,
885 &dev->i2c_bus[1].i2c_adap, 0x42,
886 &tda829x_no_probe);
887 dvb_attach(tda18271_attach, fe0->dvb.frontend,
888 0x60, &dev->i2c_bus[1].i2c_adap,
889 &hauppauge_hvr1200_tuner_config);
890 }
891 break;
892 case CX23885_BOARD_HAUPPAUGE_HVR1210:
893 i2c_bus = &dev->i2c_bus[0];
894 fe0->dvb.frontend = dvb_attach(tda10048_attach,
895 &hauppauge_hvr1210_config,
896 &i2c_bus->i2c_adap);
897 if (fe0->dvb.frontend != NULL) {
898 dvb_attach(tda18271_attach, fe0->dvb.frontend,
899 0x60, &dev->i2c_bus[1].i2c_adap,
900 &hauppauge_hvr1210_tuner_config);
901 }
902 break;
903 case CX23885_BOARD_HAUPPAUGE_HVR1400:
904 i2c_bus = &dev->i2c_bus[0];
905 fe0->dvb.frontend = dvb_attach(dib7000p_attach,
906 &i2c_bus->i2c_adap,
907 0x12, &hauppauge_hvr1400_dib7000_config);
908 if (fe0->dvb.frontend != NULL) {
909 struct dvb_frontend *fe;
910 struct xc2028_config cfg = {
911 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
912 .i2c_addr = 0x64,
913 };
914 static struct xc2028_ctrl ctl = {
915 .fname = XC3028L_DEFAULT_FIRMWARE,
916 .max_len = 64,
917 .demod = XC3028_FE_DIBCOM52,
918 /* This is true for all demods with
919 v36 firmware? */
920 .type = XC2028_D2633,
921 };
922
923 fe = dvb_attach(xc2028_attach,
924 fe0->dvb.frontend, &cfg);
925 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
926 fe->ops.tuner_ops.set_config(fe, &ctl);
927 }
928 break;
929 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
930 i2c_bus = &dev->i2c_bus[port->nr - 1];
931
932 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
933 &dvico_s5h1409_config,
934 &i2c_bus->i2c_adap);
935 if (fe0->dvb.frontend == NULL)
936 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
937 &dvico_s5h1411_config,
938 &i2c_bus->i2c_adap);
939 if (fe0->dvb.frontend != NULL)
940 dvb_attach(xc5000_attach, fe0->dvb.frontend,
941 &i2c_bus->i2c_adap,
942 &dvico_xc5000_tunerconfig);
943 break;
944 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: {
945 i2c_bus = &dev->i2c_bus[port->nr - 1];
946
947 fe0->dvb.frontend = dvb_attach(zl10353_attach,
948 &dvico_fusionhdtv_xc3028,
949 &i2c_bus->i2c_adap);
950 if (fe0->dvb.frontend != NULL) {
951 struct dvb_frontend *fe;
952 struct xc2028_config cfg = {
953 .i2c_adap = &i2c_bus->i2c_adap,
954 .i2c_addr = 0x61,
955 };
956 static struct xc2028_ctrl ctl = {
957 .fname = XC2028_DEFAULT_FIRMWARE,
958 .max_len = 64,
959 .demod = XC3028_FE_ZARLINK456,
960 };
961
962 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
963 &cfg);
964 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
965 fe->ops.tuner_ops.set_config(fe, &ctl);
966 }
967 break;
968 }
969 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
970 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
971 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
972 i2c_bus = &dev->i2c_bus[0];
973
974 fe0->dvb.frontend = dvb_attach(zl10353_attach,
975 &dvico_fusionhdtv_xc3028,
976 &i2c_bus->i2c_adap);
977 if (fe0->dvb.frontend != NULL) {
978 struct dvb_frontend *fe;
979 struct xc2028_config cfg = {
980 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
981 .i2c_addr = 0x61,
982 };
983 static struct xc2028_ctrl ctl = {
984 .fname = XC2028_DEFAULT_FIRMWARE,
985 .max_len = 64,
986 .demod = XC3028_FE_ZARLINK456,
987 };
988
989 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
990 &cfg);
991 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
992 fe->ops.tuner_ops.set_config(fe, &ctl);
993 }
994 break;
995 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
996 i2c_bus = &dev->i2c_bus[0];
997
998 fe0->dvb.frontend = dvb_attach(zl10353_attach,
999 &dvico_fusionhdtv_xc3028,
1000 &i2c_bus->i2c_adap);
1001 if (fe0->dvb.frontend != NULL) {
1002 struct dvb_frontend *fe;
1003 struct xc4000_config cfg = {
1004 .i2c_address = 0x61,
1005 .default_pm = 0,
1006 .dvb_amplitude = 134,
1007 .set_smoothedcvbs = 1,
1008 .if_khz = 4560
1009 };
1010
1011 fe = dvb_attach(xc4000_attach, fe0->dvb.frontend,
1012 &dev->i2c_bus[1].i2c_adap, &cfg);
1013 if (!fe) {
1014 printk(KERN_ERR "%s/2: xc4000 attach failed\n",
1015 dev->name);
1016 goto frontend_detach;
1017 }
1018 }
1019 break;
1020 case CX23885_BOARD_TBS_6920:
1021 i2c_bus = &dev->i2c_bus[1];
1022
1023 fe0->dvb.frontend = dvb_attach(cx24116_attach,
1024 &tbs_cx24116_config,
1025 &i2c_bus->i2c_adap);
1026 if (fe0->dvb.frontend != NULL)
1027 fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
1028
1029 break;
1030 case CX23885_BOARD_TEVII_S470:
1031 i2c_bus = &dev->i2c_bus[1];
1032
1033 fe0->dvb.frontend = dvb_attach(ds3000_attach,
1034 &tevii_ds3000_config,
1035 &i2c_bus->i2c_adap);
1036 if (fe0->dvb.frontend != NULL) {
1037 dvb_attach(ts2020_attach, fe0->dvb.frontend,
1038 &tevii_ts2020_config, &i2c_bus->i2c_adap);
1039 fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
1040 }
1041
1042 break;
1043 case CX23885_BOARD_DVBWORLD_2005:
1044 i2c_bus = &dev->i2c_bus[1];
1045
1046 fe0->dvb.frontend = dvb_attach(cx24116_attach,
1047 &dvbworld_cx24116_config,
1048 &i2c_bus->i2c_adap);
1049 break;
1050 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1051 i2c_bus = &dev->i2c_bus[0];
1052 switch (port->nr) {
1053 /* port B */
1054 case 1:
1055 fe0->dvb.frontend = dvb_attach(stv0900_attach,
1056 &netup_stv0900_config,
1057 &i2c_bus->i2c_adap, 0);
1058 if (fe0->dvb.frontend != NULL) {
1059 if (dvb_attach(stv6110_attach,
1060 fe0->dvb.frontend,
1061 &netup_stv6110_tunerconfig_a,
1062 &i2c_bus->i2c_adap)) {
1063 if (!dvb_attach(lnbh24_attach,
1064 fe0->dvb.frontend,
1065 &i2c_bus->i2c_adap,
1066 LNBH24_PCL | LNBH24_TTX,
1067 LNBH24_TEN, 0x09))
1068 printk(KERN_ERR
1069 "No LNBH24 found!\n");
1070
1071 }
1072 }
1073 break;
1074 /* port C */
1075 case 2:
1076 fe0->dvb.frontend = dvb_attach(stv0900_attach,
1077 &netup_stv0900_config,
1078 &i2c_bus->i2c_adap, 1);
1079 if (fe0->dvb.frontend != NULL) {
1080 if (dvb_attach(stv6110_attach,
1081 fe0->dvb.frontend,
1082 &netup_stv6110_tunerconfig_b,
1083 &i2c_bus->i2c_adap)) {
1084 if (!dvb_attach(lnbh24_attach,
1085 fe0->dvb.frontend,
1086 &i2c_bus->i2c_adap,
1087 LNBH24_PCL | LNBH24_TTX,
1088 LNBH24_TEN, 0x0a))
1089 printk(KERN_ERR
1090 "No LNBH24 found!\n");
1091
1092 }
1093 }
1094 break;
1095 }
1096 break;
1097 case CX23885_BOARD_MYGICA_X8506:
1098 i2c_bus = &dev->i2c_bus[0];
1099 i2c_bus2 = &dev->i2c_bus[1];
1100 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
1101 &mygica_x8506_lgs8gl5_config,
1102 &i2c_bus->i2c_adap);
1103 if (fe0->dvb.frontend != NULL) {
1104 dvb_attach(xc5000_attach,
1105 fe0->dvb.frontend,
1106 &i2c_bus2->i2c_adap,
1107 &mygica_x8506_xc5000_config);
1108 }
1109 break;
1110 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
1111 i2c_bus = &dev->i2c_bus[0];
1112 i2c_bus2 = &dev->i2c_bus[1];
1113 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
1114 &magicpro_prohdtve2_lgs8g75_config,
1115 &i2c_bus->i2c_adap);
1116 if (fe0->dvb.frontend != NULL) {
1117 dvb_attach(xc5000_attach,
1118 fe0->dvb.frontend,
1119 &i2c_bus2->i2c_adap,
1120 &magicpro_prohdtve2_xc5000_config);
1121 }
1122 break;
1123 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1124 i2c_bus = &dev->i2c_bus[0];
1125 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
1126 &hcw_s5h1411_config,
1127 &i2c_bus->i2c_adap);
1128 if (fe0->dvb.frontend != NULL)
1129 dvb_attach(tda18271_attach, fe0->dvb.frontend,
1130 0x60, &dev->i2c_bus[0].i2c_adap,
1131 &hauppauge_tda18271_config);
1132
1133 tda18271_attach(&dev->ts1.analog_fe,
1134 0x60, &dev->i2c_bus[1].i2c_adap,
1135 &hauppauge_tda18271_config);
1136
1137 break;
1138 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1139 i2c_bus = &dev->i2c_bus[0];
1140 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
1141 &hcw_s5h1411_config,
1142 &i2c_bus->i2c_adap);
1143 if (fe0->dvb.frontend != NULL)
1144 dvb_attach(tda18271_attach, fe0->dvb.frontend,
1145 0x60, &dev->i2c_bus[0].i2c_adap,
1146 &hauppauge_tda18271_config);
1147 break;
1148 case CX23885_BOARD_MYGICA_X8558PRO:
1149 switch (port->nr) {
1150 /* port B */
1151 case 1:
1152 i2c_bus = &dev->i2c_bus[0];
1153 fe0->dvb.frontend = dvb_attach(atbm8830_attach,
1154 &mygica_x8558pro_atbm8830_cfg1,
1155 &i2c_bus->i2c_adap);
1156 if (fe0->dvb.frontend != NULL) {
1157 dvb_attach(max2165_attach,
1158 fe0->dvb.frontend,
1159 &i2c_bus->i2c_adap,
1160 &mygic_x8558pro_max2165_cfg1);
1161 }
1162 break;
1163 /* port C */
1164 case 2:
1165 i2c_bus = &dev->i2c_bus[1];
1166 fe0->dvb.frontend = dvb_attach(atbm8830_attach,
1167 &mygica_x8558pro_atbm8830_cfg2,
1168 &i2c_bus->i2c_adap);
1169 if (fe0->dvb.frontend != NULL) {
1170 dvb_attach(max2165_attach,
1171 fe0->dvb.frontend,
1172 &i2c_bus->i2c_adap,
1173 &mygic_x8558pro_max2165_cfg2);
1174 }
1175 break;
1176 }
1177 break;
1178 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1179 i2c_bus = &dev->i2c_bus[0];
1180 mfe_shared = 1;/* MFE */
1181 port->frontends.gate = 0;/* not clear for me yet */
1182 /* ports B, C */
1183 /* MFE frontend 1 DVB-T */
1184 fe0->dvb.frontend = dvb_attach(stv0367ter_attach,
1185 &netup_stv0367_config[port->nr - 1],
1186 &i2c_bus->i2c_adap);
1187 if (fe0->dvb.frontend != NULL) {
1188 if (NULL == dvb_attach(xc5000_attach,
1189 fe0->dvb.frontend,
1190 &i2c_bus->i2c_adap,
1191 &netup_xc5000_config[port->nr - 1]))
1192 goto frontend_detach;
1193 /* load xc5000 firmware */
1194 fe0->dvb.frontend->ops.tuner_ops.init(fe0->dvb.frontend);
1195 }
1196 /* MFE frontend 2 */
1197 fe1 = videobuf_dvb_get_frontend(&port->frontends, 2);
1198 if (fe1 == NULL)
1199 goto frontend_detach;
1200 /* DVB-C init */
1201 fe1->dvb.frontend = dvb_attach(stv0367cab_attach,
1202 &netup_stv0367_config[port->nr - 1],
1203 &i2c_bus->i2c_adap);
1204 if (fe1->dvb.frontend != NULL) {
1205 fe1->dvb.frontend->id = 1;
1206 if (NULL == dvb_attach(xc5000_attach,
1207 fe1->dvb.frontend,
1208 &i2c_bus->i2c_adap,
1209 &netup_xc5000_config[port->nr - 1]))
1210 goto frontend_detach;
1211 }
1212 break;
1213 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
1214 i2c_bus = &dev->i2c_bus[0];
1215 i2c_bus2 = &dev->i2c_bus[1];
1216
1217 switch (port->nr) {
1218 /* port b */
1219 case 1:
1220 fe0->dvb.frontend = dvb_attach(drxk_attach,
1221 &terratec_drxk_config[0],
1222 &i2c_bus->i2c_adap);
1223 if (fe0->dvb.frontend != NULL) {
1224 if (!dvb_attach(mt2063_attach,
1225 fe0->dvb.frontend,
1226 &terratec_mt2063_config[0],
1227 &i2c_bus2->i2c_adap))
1228 goto frontend_detach;
1229 }
1230 break;
1231 /* port c */
1232 case 2:
1233 fe0->dvb.frontend = dvb_attach(drxk_attach,
1234 &terratec_drxk_config[1],
1235 &i2c_bus->i2c_adap);
1236 if (fe0->dvb.frontend != NULL) {
1237 if (!dvb_attach(mt2063_attach,
1238 fe0->dvb.frontend,
1239 &terratec_mt2063_config[1],
1240 &i2c_bus2->i2c_adap))
1241 goto frontend_detach;
1242 }
1243 break;
1244 }
1245 break;
1246 case CX23885_BOARD_TEVII_S471:
1247 i2c_bus = &dev->i2c_bus[1];
1248
1249 fe0->dvb.frontend = dvb_attach(ds3000_attach,
1250 &tevii_ds3000_config,
1251 &i2c_bus->i2c_adap);
1252 break;
1253 case CX23885_BOARD_PROF_8000:
1254 i2c_bus = &dev->i2c_bus[0];
1255
1256 fe0->dvb.frontend = dvb_attach(stv090x_attach,
1257 &prof_8000_stv090x_config,
1258 &i2c_bus->i2c_adap,
1259 STV090x_DEMODULATOR_0);
1260 if (fe0->dvb.frontend != NULL) {
1261 if (!dvb_attach(stb6100_attach,
1262 fe0->dvb.frontend,
1263 &prof_8000_stb6100_config,
1264 &i2c_bus->i2c_adap))
1265 goto frontend_detach;
1266
1267 fe0->dvb.frontend->ops.set_voltage = p8000_set_voltage;
1268 }
1269 break;
1270 case CX23885_BOARD_HAUPPAUGE_HVR4400:
1271 i2c_bus = &dev->i2c_bus[0];
1272 fe0->dvb.frontend = dvb_attach(tda10071_attach,
1273 &hauppauge_tda10071_config,
1274 &i2c_bus->i2c_adap);
1275 if (fe0->dvb.frontend != NULL) {
1276 dvb_attach(a8293_attach, fe0->dvb.frontend,
1277 &i2c_bus->i2c_adap,
1278 &hauppauge_a8293_config);
1279 }
1280 break;
1281 default:
1282 printk(KERN_INFO "%s: The frontend of your DVB/ATSC card "
1283 " isn't supported yet\n",
1284 dev->name);
1285 break;
1286 }
1287
1288 if ((NULL == fe0->dvb.frontend) || (fe1 && NULL == fe1->dvb.frontend)) {
1289 printk(KERN_ERR "%s: frontend initialization failed\n",
1290 dev->name);
1291 goto frontend_detach;
1292 }
1293
1294 /* define general-purpose callback pointer */
1295 fe0->dvb.frontend->callback = cx23885_tuner_callback;
1296 if (fe1)
1297 fe1->dvb.frontend->callback = cx23885_tuner_callback;
1298 #if 0
1299 /* Ensure all frontends negotiate bus access */
1300 fe0->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
1301 if (fe1)
1302 fe1->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
1303 #endif
1304
1305 /* Put the analog decoder in standby to keep it quiet */
1306 call_all(dev, core, s_power, 0);
1307
1308 if (fe0->dvb.frontend->ops.analog_ops.standby)
1309 fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend);
1310
1311 /* register everything */
1312 ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port,
1313 &dev->pci->dev, adapter_nr, mfe_shared);
1314 if (ret)
1315 goto frontend_detach;
1316
1317 /* init CI & MAC */
1318 switch (dev->board) {
1319 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: {
1320 static struct netup_card_info cinfo;
1321
1322 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
1323 memcpy(port->frontends.adapter.proposed_mac,
1324 cinfo.port[port->nr - 1].mac, 6);
1325 printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC=%pM\n",
1326 port->nr, port->frontends.adapter.proposed_mac);
1327
1328 netup_ci_init(port);
1329 break;
1330 }
1331 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
1332 struct altera_ci_config netup_ci_cfg = {
1333 .dev = dev,/* magic number to identify*/
1334 .adapter = &port->frontends.adapter,/* for CI */
1335 .demux = &fe0->dvb.demux,/* for hw pid filter */
1336 .fpga_rw = netup_altera_fpga_rw,
1337 };
1338
1339 altera_ci_init(&netup_ci_cfg, port->nr);
1340 break;
1341 }
1342 case CX23885_BOARD_TEVII_S470: {
1343 u8 eeprom[256]; /* 24C02 i2c eeprom */
1344
1345 if (port->nr != 1)
1346 break;
1347
1348 /* Read entire EEPROM */
1349 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
1350 tveeprom_read(&dev->i2c_bus[0].i2c_client, eeprom, sizeof(eeprom));
1351 printk(KERN_INFO "TeVii S470 MAC= %pM\n", eeprom + 0xa0);
1352 memcpy(port->frontends.adapter.proposed_mac, eeprom + 0xa0, 6);
1353 break;
1354 }
1355 }
1356
1357 return ret;
1358
1359 frontend_detach:
1360 port->gate_ctrl = NULL;
1361 videobuf_dvb_dealloc_frontends(&port->frontends);
1362 return -EINVAL;
1363 }
1364
1365 int cx23885_dvb_register(struct cx23885_tsport *port)
1366 {
1367
1368 struct videobuf_dvb_frontend *fe0;
1369 struct cx23885_dev *dev = port->dev;
1370 int err, i;
1371
1372 /* Here we need to allocate the correct number of frontends,
1373 * as reflected in the cards struct. The reality is that currently
1374 * no cx23885 boards support this - yet. But, if we don't modify this
1375 * code then the second frontend would never be allocated (later)
1376 * and fail with error before the attach in dvb_register().
1377 * Without these changes we risk an OOPS later. The changes here
1378 * are for safety, and should provide a good foundation for the
1379 * future addition of any multi-frontend cx23885 based boards.
1380 */
1381 printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
1382 port->num_frontends);
1383
1384 for (i = 1; i <= port->num_frontends; i++) {
1385 if (videobuf_dvb_alloc_frontend(
1386 &port->frontends, i) == NULL) {
1387 printk(KERN_ERR "%s() failed to alloc\n", __func__);
1388 return -ENOMEM;
1389 }
1390
1391 fe0 = videobuf_dvb_get_frontend(&port->frontends, i);
1392 if (!fe0)
1393 err = -EINVAL;
1394
1395 dprintk(1, "%s\n", __func__);
1396 dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n",
1397 dev->board,
1398 dev->name,
1399 dev->pci_bus,
1400 dev->pci_slot);
1401
1402 err = -ENODEV;
1403
1404 /* dvb stuff */
1405 /* We have to init the queue for each frontend on a port. */
1406 printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name);
1407 videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops,
1408 &dev->pci->dev, &port->slock,
1409 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP,
1410 sizeof(struct cx23885_buffer), port, NULL);
1411 }
1412 err = dvb_register(port);
1413 if (err != 0)
1414 printk(KERN_ERR "%s() dvb_register failed err = %d\n",
1415 __func__, err);
1416
1417 return err;
1418 }
1419
1420 int cx23885_dvb_unregister(struct cx23885_tsport *port)
1421 {
1422 struct videobuf_dvb_frontend *fe0;
1423
1424 /* FIXME: in an error condition where the we have
1425 * an expected number of frontends (attach problem)
1426 * then this might not clean up correctly, if 1
1427 * is invalid.
1428 * This comment only applies to future boards IF they
1429 * implement MFE support.
1430 */
1431 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
1432 if (fe0 && fe0->dvb.frontend)
1433 videobuf_dvb_unregister_bus(&port->frontends);
1434
1435 switch (port->dev->board) {
1436 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1437 netup_ci_exit(port);
1438 break;
1439 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1440 altera_ci_release(port->dev, port->nr);
1441 break;
1442 }
1443
1444 port->gate_ctrl = NULL;
1445
1446 return 0;
1447 }
1448
CRIS linux kernel tree