?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux 3.11-rc3
[cris-mirror.git] / drivers / net / ethernet / calxeda / xgmac.c
blob7cb148c495c900ad4385ed3c59db7f63f389821b
1 /*
2 * Copyright 2010-2011 Calxeda, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/kernel.h>
19 #include <linux/circ_buf.h>
20 #include <linux/interrupt.h>
21 #include <linux/etherdevice.h>
22 #include <linux/platform_device.h>
23 #include <linux/skbuff.h>
24 #include <linux/ethtool.h>
25 #include <linux/if.h>
26 #include <linux/crc32.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/slab.h>
29
30 /* XGMAC Register definitions */
31 #define XGMAC_CONTROL 0x00000000 /* MAC Configuration */
32 #define XGMAC_FRAME_FILTER 0x00000004 /* MAC Frame Filter */
33 #define XGMAC_FLOW_CTRL 0x00000018 /* MAC Flow Control */
34 #define XGMAC_VLAN_TAG 0x0000001C /* VLAN Tags */
35 #define XGMAC_VERSION 0x00000020 /* Version */
36 #define XGMAC_VLAN_INCL 0x00000024 /* VLAN tag for tx frames */
37 #define XGMAC_LPI_CTRL 0x00000028 /* LPI Control and Status */
38 #define XGMAC_LPI_TIMER 0x0000002C /* LPI Timers Control */
39 #define XGMAC_TX_PACE 0x00000030 /* Transmit Pace and Stretch */
40 #define XGMAC_VLAN_HASH 0x00000034 /* VLAN Hash Table */
41 #define XGMAC_DEBUG 0x00000038 /* Debug */
42 #define XGMAC_INT_STAT 0x0000003C /* Interrupt and Control */
43 #define XGMAC_ADDR_HIGH(reg) (0x00000040 + ((reg) * 8))
44 #define XGMAC_ADDR_LOW(reg) (0x00000044 + ((reg) * 8))
45 #define XGMAC_HASH(n) (0x00000300 + (n) * 4) /* HASH table regs */
46 #define XGMAC_NUM_HASH 16
47 #define XGMAC_OMR 0x00000400
48 #define XGMAC_REMOTE_WAKE 0x00000700 /* Remote Wake-Up Frm Filter */
49 #define XGMAC_PMT 0x00000704 /* PMT Control and Status */
50 #define XGMAC_MMC_CTRL 0x00000800 /* XGMAC MMC Control */
51 #define XGMAC_MMC_INTR_RX 0x00000804 /* Recieve Interrupt */
52 #define XGMAC_MMC_INTR_TX 0x00000808 /* Transmit Interrupt */
53 #define XGMAC_MMC_INTR_MASK_RX 0x0000080c /* Recieve Interrupt Mask */
54 #define XGMAC_MMC_INTR_MASK_TX 0x00000810 /* Transmit Interrupt Mask */
55
56 /* Hardware TX Statistics Counters */
57 #define XGMAC_MMC_TXOCTET_GB_LO 0x00000814
58 #define XGMAC_MMC_TXOCTET_GB_HI 0x00000818
59 #define XGMAC_MMC_TXFRAME_GB_LO 0x0000081C
60 #define XGMAC_MMC_TXFRAME_GB_HI 0x00000820
61 #define XGMAC_MMC_TXBCFRAME_G 0x00000824
62 #define XGMAC_MMC_TXMCFRAME_G 0x0000082C
63 #define XGMAC_MMC_TXUCFRAME_GB 0x00000864
64 #define XGMAC_MMC_TXMCFRAME_GB 0x0000086C
65 #define XGMAC_MMC_TXBCFRAME_GB 0x00000874
66 #define XGMAC_MMC_TXUNDERFLOW 0x0000087C
67 #define XGMAC_MMC_TXOCTET_G_LO 0x00000884
68 #define XGMAC_MMC_TXOCTET_G_HI 0x00000888
69 #define XGMAC_MMC_TXFRAME_G_LO 0x0000088C
70 #define XGMAC_MMC_TXFRAME_G_HI 0x00000890
71 #define XGMAC_MMC_TXPAUSEFRAME 0x00000894
72 #define XGMAC_MMC_TXVLANFRAME 0x0000089C
73
74 /* Hardware RX Statistics Counters */
75 #define XGMAC_MMC_RXFRAME_GB_LO 0x00000900
76 #define XGMAC_MMC_RXFRAME_GB_HI 0x00000904
77 #define XGMAC_MMC_RXOCTET_GB_LO 0x00000908
78 #define XGMAC_MMC_RXOCTET_GB_HI 0x0000090C
79 #define XGMAC_MMC_RXOCTET_G_LO 0x00000910
80 #define XGMAC_MMC_RXOCTET_G_HI 0x00000914
81 #define XGMAC_MMC_RXBCFRAME_G 0x00000918
82 #define XGMAC_MMC_RXMCFRAME_G 0x00000920
83 #define XGMAC_MMC_RXCRCERR 0x00000928
84 #define XGMAC_MMC_RXRUNT 0x00000930
85 #define XGMAC_MMC_RXJABBER 0x00000934
86 #define XGMAC_MMC_RXUCFRAME_G 0x00000970
87 #define XGMAC_MMC_RXLENGTHERR 0x00000978
88 #define XGMAC_MMC_RXPAUSEFRAME 0x00000988
89 #define XGMAC_MMC_RXOVERFLOW 0x00000990
90 #define XGMAC_MMC_RXVLANFRAME 0x00000998
91 #define XGMAC_MMC_RXWATCHDOG 0x000009a0
92
93 /* DMA Control and Status Registers */
94 #define XGMAC_DMA_BUS_MODE 0x00000f00 /* Bus Mode */
95 #define XGMAC_DMA_TX_POLL 0x00000f04 /* Transmit Poll Demand */
96 #define XGMAC_DMA_RX_POLL 0x00000f08 /* Received Poll Demand */
97 #define XGMAC_DMA_RX_BASE_ADDR 0x00000f0c /* Receive List Base */
98 #define XGMAC_DMA_TX_BASE_ADDR 0x00000f10 /* Transmit List Base */
99 #define XGMAC_DMA_STATUS 0x00000f14 /* Status Register */
100 #define XGMAC_DMA_CONTROL 0x00000f18 /* Ctrl (Operational Mode) */
101 #define XGMAC_DMA_INTR_ENA 0x00000f1c /* Interrupt Enable */
102 #define XGMAC_DMA_MISS_FRAME_CTR 0x00000f20 /* Missed Frame Counter */
103 #define XGMAC_DMA_RI_WDOG_TIMER 0x00000f24 /* RX Intr Watchdog Timer */
104 #define XGMAC_DMA_AXI_BUS 0x00000f28 /* AXI Bus Mode */
105 #define XGMAC_DMA_AXI_STATUS 0x00000f2C /* AXI Status */
106 #define XGMAC_DMA_HW_FEATURE 0x00000f58 /* Enabled Hardware Features */
107
108 #define XGMAC_ADDR_AE 0x80000000
109 #define XGMAC_MAX_FILTER_ADDR 31
110
111 /* PMT Control and Status */
112 #define XGMAC_PMT_POINTER_RESET 0x80000000
113 #define XGMAC_PMT_GLBL_UNICAST 0x00000200
114 #define XGMAC_PMT_WAKEUP_RX_FRM 0x00000040
115 #define XGMAC_PMT_MAGIC_PKT 0x00000020
116 #define XGMAC_PMT_WAKEUP_FRM_EN 0x00000004
117 #define XGMAC_PMT_MAGIC_PKT_EN 0x00000002
118 #define XGMAC_PMT_POWERDOWN 0x00000001
119
120 #define XGMAC_CONTROL_SPD 0x40000000 /* Speed control */
121 #define XGMAC_CONTROL_SPD_MASK 0x60000000
122 #define XGMAC_CONTROL_SPD_1G 0x60000000
123 #define XGMAC_CONTROL_SPD_2_5G 0x40000000
124 #define XGMAC_CONTROL_SPD_10G 0x00000000
125 #define XGMAC_CONTROL_SARC 0x10000000 /* Source Addr Insert/Replace */
126 #define XGMAC_CONTROL_SARK_MASK 0x18000000
127 #define XGMAC_CONTROL_CAR 0x04000000 /* CRC Addition/Replacement */
128 #define XGMAC_CONTROL_CAR_MASK 0x06000000
129 #define XGMAC_CONTROL_DP 0x01000000 /* Disable Padding */
130 #define XGMAC_CONTROL_WD 0x00800000 /* Disable Watchdog on rx */
131 #define XGMAC_CONTROL_JD 0x00400000 /* Jabber disable */
132 #define XGMAC_CONTROL_JE 0x00100000 /* Jumbo frame */
133 #define XGMAC_CONTROL_LM 0x00001000 /* Loop-back mode */
134 #define XGMAC_CONTROL_IPC 0x00000400 /* Checksum Offload */
135 #define XGMAC_CONTROL_ACS 0x00000080 /* Automatic Pad/FCS Strip */
136 #define XGMAC_CONTROL_DDIC 0x00000010 /* Disable Deficit Idle Count */
137 #define XGMAC_CONTROL_TE 0x00000008 /* Transmitter Enable */
138 #define XGMAC_CONTROL_RE 0x00000004 /* Receiver Enable */
139
140 /* XGMAC Frame Filter defines */
141 #define XGMAC_FRAME_FILTER_PR 0x00000001 /* Promiscuous Mode */
142 #define XGMAC_FRAME_FILTER_HUC 0x00000002 /* Hash Unicast */
143 #define XGMAC_FRAME_FILTER_HMC 0x00000004 /* Hash Multicast */
144 #define XGMAC_FRAME_FILTER_DAIF 0x00000008 /* DA Inverse Filtering */
145 #define XGMAC_FRAME_FILTER_PM 0x00000010 /* Pass all multicast */
146 #define XGMAC_FRAME_FILTER_DBF 0x00000020 /* Disable Broadcast frames */
147 #define XGMAC_FRAME_FILTER_SAIF 0x00000100 /* Inverse Filtering */
148 #define XGMAC_FRAME_FILTER_SAF 0x00000200 /* Source Address Filter */
149 #define XGMAC_FRAME_FILTER_HPF 0x00000400 /* Hash or perfect Filter */
150 #define XGMAC_FRAME_FILTER_VHF 0x00000800 /* VLAN Hash Filter */
151 #define XGMAC_FRAME_FILTER_VPF 0x00001000 /* VLAN Perfect Filter */
152 #define XGMAC_FRAME_FILTER_RA 0x80000000 /* Receive all mode */
153
154 /* XGMAC FLOW CTRL defines */
155 #define XGMAC_FLOW_CTRL_PT_MASK 0xffff0000 /* Pause Time Mask */
156 #define XGMAC_FLOW_CTRL_PT_SHIFT 16
157 #define XGMAC_FLOW_CTRL_DZQP 0x00000080 /* Disable Zero-Quanta Phase */
158 #define XGMAC_FLOW_CTRL_PLT 0x00000020 /* Pause Low Threshhold */
159 #define XGMAC_FLOW_CTRL_PLT_MASK 0x00000030 /* PLT MASK */
160 #define XGMAC_FLOW_CTRL_UP 0x00000008 /* Unicast Pause Frame Detect */
161 #define XGMAC_FLOW_CTRL_RFE 0x00000004 /* Rx Flow Control Enable */
162 #define XGMAC_FLOW_CTRL_TFE 0x00000002 /* Tx Flow Control Enable */
163 #define XGMAC_FLOW_CTRL_FCB_BPA 0x00000001 /* Flow Control Busy ... */
164
165 /* XGMAC_INT_STAT reg */
166 #define XGMAC_INT_STAT_PMTIM 0x00800000 /* PMT Interrupt Mask */
167 #define XGMAC_INT_STAT_PMT 0x0080 /* PMT Interrupt Status */
168 #define XGMAC_INT_STAT_LPI 0x0040 /* LPI Interrupt Status */
169
170 /* DMA Bus Mode register defines */
171 #define DMA_BUS_MODE_SFT_RESET 0x00000001 /* Software Reset */
172 #define DMA_BUS_MODE_DSL_MASK 0x0000007c /* Descriptor Skip Length */
173 #define DMA_BUS_MODE_DSL_SHIFT 2 /* (in DWORDS) */
174 #define DMA_BUS_MODE_ATDS 0x00000080 /* Alternate Descriptor Size */
175
176 /* Programmable burst length */
177 #define DMA_BUS_MODE_PBL_MASK 0x00003f00 /* Programmable Burst Len */
178 #define DMA_BUS_MODE_PBL_SHIFT 8
179 #define DMA_BUS_MODE_FB 0x00010000 /* Fixed burst */
180 #define DMA_BUS_MODE_RPBL_MASK 0x003e0000 /* Rx-Programmable Burst Len */
181 #define DMA_BUS_MODE_RPBL_SHIFT 17
182 #define DMA_BUS_MODE_USP 0x00800000
183 #define DMA_BUS_MODE_8PBL 0x01000000
184 #define DMA_BUS_MODE_AAL 0x02000000
185
186 /* DMA Bus Mode register defines */
187 #define DMA_BUS_PR_RATIO_MASK 0x0000c000 /* Rx/Tx priority ratio */
188 #define DMA_BUS_PR_RATIO_SHIFT 14
189 #define DMA_BUS_FB 0x00010000 /* Fixed Burst */
190
191 /* DMA Control register defines */
192 #define DMA_CONTROL_ST 0x00002000 /* Start/Stop Transmission */
193 #define DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */
194 #define DMA_CONTROL_DFF 0x01000000 /* Disable flush of rx frames */
195 #define DMA_CONTROL_OSF 0x00000004 /* Operate on 2nd tx frame */
196
197 /* DMA Normal interrupt */
198 #define DMA_INTR_ENA_NIE 0x00010000 /* Normal Summary */
199 #define DMA_INTR_ENA_AIE 0x00008000 /* Abnormal Summary */
200 #define DMA_INTR_ENA_ERE 0x00004000 /* Early Receive */
201 #define DMA_INTR_ENA_FBE 0x00002000 /* Fatal Bus Error */
202 #define DMA_INTR_ENA_ETE 0x00000400 /* Early Transmit */
203 #define DMA_INTR_ENA_RWE 0x00000200 /* Receive Watchdog */
204 #define DMA_INTR_ENA_RSE 0x00000100 /* Receive Stopped */
205 #define DMA_INTR_ENA_RUE 0x00000080 /* Receive Buffer Unavailable */
206 #define DMA_INTR_ENA_RIE 0x00000040 /* Receive Interrupt */
207 #define DMA_INTR_ENA_UNE 0x00000020 /* Tx Underflow */
208 #define DMA_INTR_ENA_OVE 0x00000010 /* Receive Overflow */
209 #define DMA_INTR_ENA_TJE 0x00000008 /* Transmit Jabber */
210 #define DMA_INTR_ENA_TUE 0x00000004 /* Transmit Buffer Unavail */
211 #define DMA_INTR_ENA_TSE 0x00000002 /* Transmit Stopped */
212 #define DMA_INTR_ENA_TIE 0x00000001 /* Transmit Interrupt */
213
214 #define DMA_INTR_NORMAL (DMA_INTR_ENA_NIE | DMA_INTR_ENA_RIE | \
215 DMA_INTR_ENA_TUE | DMA_INTR_ENA_TIE)
216
217 #define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \
218 DMA_INTR_ENA_RWE | DMA_INTR_ENA_RSE | \
219 DMA_INTR_ENA_RUE | DMA_INTR_ENA_UNE | \
220 DMA_INTR_ENA_OVE | DMA_INTR_ENA_TJE | \
221 DMA_INTR_ENA_TSE)
222
223 /* DMA default interrupt mask */
224 #define DMA_INTR_DEFAULT_MASK (DMA_INTR_NORMAL | DMA_INTR_ABNORMAL)
225
226 /* DMA Status register defines */
227 #define DMA_STATUS_GMI 0x08000000 /* MMC interrupt */
228 #define DMA_STATUS_GLI 0x04000000 /* GMAC Line interface int */
229 #define DMA_STATUS_EB_MASK 0x00380000 /* Error Bits Mask */
230 #define DMA_STATUS_EB_TX_ABORT 0x00080000 /* Error Bits - TX Abort */
231 #define DMA_STATUS_EB_RX_ABORT 0x00100000 /* Error Bits - RX Abort */
232 #define DMA_STATUS_TS_MASK 0x00700000 /* Transmit Process State */
233 #define DMA_STATUS_TS_SHIFT 20
234 #define DMA_STATUS_RS_MASK 0x000e0000 /* Receive Process State */
235 #define DMA_STATUS_RS_SHIFT 17
236 #define DMA_STATUS_NIS 0x00010000 /* Normal Interrupt Summary */
237 #define DMA_STATUS_AIS 0x00008000 /* Abnormal Interrupt Summary */
238 #define DMA_STATUS_ERI 0x00004000 /* Early Receive Interrupt */
239 #define DMA_STATUS_FBI 0x00002000 /* Fatal Bus Error Interrupt */
240 #define DMA_STATUS_ETI 0x00000400 /* Early Transmit Interrupt */
241 #define DMA_STATUS_RWT 0x00000200 /* Receive Watchdog Timeout */
242 #define DMA_STATUS_RPS 0x00000100 /* Receive Process Stopped */
243 #define DMA_STATUS_RU 0x00000080 /* Receive Buffer Unavailable */
244 #define DMA_STATUS_RI 0x00000040 /* Receive Interrupt */
245 #define DMA_STATUS_UNF 0x00000020 /* Transmit Underflow */
246 #define DMA_STATUS_OVF 0x00000010 /* Receive Overflow */
247 #define DMA_STATUS_TJT 0x00000008 /* Transmit Jabber Timeout */
248 #define DMA_STATUS_TU 0x00000004 /* Transmit Buffer Unavail */
249 #define DMA_STATUS_TPS 0x00000002 /* Transmit Process Stopped */
250 #define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */
251
252 /* Common MAC defines */
253 #define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
254 #define MAC_ENABLE_RX 0x00000004 /* Receiver Enable */
255
256 /* XGMAC Operation Mode Register */
257 #define XGMAC_OMR_TSF 0x00200000 /* TX FIFO Store and Forward */
258 #define XGMAC_OMR_FTF 0x00100000 /* Flush Transmit FIFO */
259 #define XGMAC_OMR_TTC 0x00020000 /* Transmit Threshhold Ctrl */
260 #define XGMAC_OMR_TTC_MASK 0x00030000
261 #define XGMAC_OMR_RFD 0x00006000 /* FC Deactivation Threshhold */
262 #define XGMAC_OMR_RFD_MASK 0x00007000 /* FC Deact Threshhold MASK */
263 #define XGMAC_OMR_RFA 0x00000600 /* FC Activation Threshhold */
264 #define XGMAC_OMR_RFA_MASK 0x00000E00 /* FC Act Threshhold MASK */
265 #define XGMAC_OMR_EFC 0x00000100 /* Enable Hardware FC */
266 #define XGMAC_OMR_FEF 0x00000080 /* Forward Error Frames */
267 #define XGMAC_OMR_DT 0x00000040 /* Drop TCP/IP csum Errors */
268 #define XGMAC_OMR_RSF 0x00000020 /* RX FIFO Store and Forward */
269 #define XGMAC_OMR_RTC_256 0x00000018 /* RX Threshhold Ctrl */
270 #define XGMAC_OMR_RTC_MASK 0x00000018 /* RX Threshhold Ctrl MASK */
271
272 /* XGMAC HW Features Register */
273 #define DMA_HW_FEAT_TXCOESEL 0x00010000 /* TX Checksum offload */
274
275 #define XGMAC_MMC_CTRL_CNT_FRZ 0x00000008
276
277 /* XGMAC Descriptor Defines */
278 #define MAX_DESC_BUF_SZ (0x2000 - 8)
279
280 #define RXDESC_EXT_STATUS 0x00000001
281 #define RXDESC_CRC_ERR 0x00000002
282 #define RXDESC_RX_ERR 0x00000008
283 #define RXDESC_RX_WDOG 0x00000010
284 #define RXDESC_FRAME_TYPE 0x00000020
285 #define RXDESC_GIANT_FRAME 0x00000080
286 #define RXDESC_LAST_SEG 0x00000100
287 #define RXDESC_FIRST_SEG 0x00000200
288 #define RXDESC_VLAN_FRAME 0x00000400
289 #define RXDESC_OVERFLOW_ERR 0x00000800
290 #define RXDESC_LENGTH_ERR 0x00001000
291 #define RXDESC_SA_FILTER_FAIL 0x00002000
292 #define RXDESC_DESCRIPTOR_ERR 0x00004000
293 #define RXDESC_ERROR_SUMMARY 0x00008000
294 #define RXDESC_FRAME_LEN_OFFSET 16
295 #define RXDESC_FRAME_LEN_MASK 0x3fff0000
296 #define RXDESC_DA_FILTER_FAIL 0x40000000
297
298 #define RXDESC1_END_RING 0x00008000
299
300 #define RXDESC_IP_PAYLOAD_MASK 0x00000003
301 #define RXDESC_IP_PAYLOAD_UDP 0x00000001
302 #define RXDESC_IP_PAYLOAD_TCP 0x00000002
303 #define RXDESC_IP_PAYLOAD_ICMP 0x00000003
304 #define RXDESC_IP_HEADER_ERR 0x00000008
305 #define RXDESC_IP_PAYLOAD_ERR 0x00000010
306 #define RXDESC_IPV4_PACKET 0x00000040
307 #define RXDESC_IPV6_PACKET 0x00000080
308 #define TXDESC_UNDERFLOW_ERR 0x00000001
309 #define TXDESC_JABBER_TIMEOUT 0x00000002
310 #define TXDESC_LOCAL_FAULT 0x00000004
311 #define TXDESC_REMOTE_FAULT 0x00000008
312 #define TXDESC_VLAN_FRAME 0x00000010
313 #define TXDESC_FRAME_FLUSHED 0x00000020
314 #define TXDESC_IP_HEADER_ERR 0x00000040
315 #define TXDESC_PAYLOAD_CSUM_ERR 0x00000080
316 #define TXDESC_ERROR_SUMMARY 0x00008000
317 #define TXDESC_SA_CTRL_INSERT 0x00040000
318 #define TXDESC_SA_CTRL_REPLACE 0x00080000
319 #define TXDESC_2ND_ADDR_CHAINED 0x00100000
320 #define TXDESC_END_RING 0x00200000
321 #define TXDESC_CSUM_IP 0x00400000
322 #define TXDESC_CSUM_IP_PAYLD 0x00800000
323 #define TXDESC_CSUM_ALL 0x00C00000
324 #define TXDESC_CRC_EN_REPLACE 0x01000000
325 #define TXDESC_CRC_EN_APPEND 0x02000000
326 #define TXDESC_DISABLE_PAD 0x04000000
327 #define TXDESC_FIRST_SEG 0x10000000
328 #define TXDESC_LAST_SEG 0x20000000
329 #define TXDESC_INTERRUPT 0x40000000
330
331 #define DESC_OWN 0x80000000
332 #define DESC_BUFFER1_SZ_MASK 0x00001fff
333 #define DESC_BUFFER2_SZ_MASK 0x1fff0000
334 #define DESC_BUFFER2_SZ_OFFSET 16
335
336 struct xgmac_dma_desc {
337 __le32 flags;
338 __le32 buf_size;
339 __le32 buf1_addr; /* Buffer 1 Address Pointer */
340 __le32 buf2_addr; /* Buffer 2 Address Pointer */
341 __le32 ext_status;
342 __le32 res[3];
343 };
344
345 struct xgmac_extra_stats {
346 /* Transmit errors */
347 unsigned long tx_jabber;
348 unsigned long tx_frame_flushed;
349 unsigned long tx_payload_error;
350 unsigned long tx_ip_header_error;
351 unsigned long tx_local_fault;
352 unsigned long tx_remote_fault;
353 /* Receive errors */
354 unsigned long rx_watchdog;
355 unsigned long rx_da_filter_fail;
356 unsigned long rx_sa_filter_fail;
357 unsigned long rx_payload_error;
358 unsigned long rx_ip_header_error;
359 /* Tx/Rx IRQ errors */
360 unsigned long tx_undeflow;
361 unsigned long tx_process_stopped;
362 unsigned long rx_buf_unav;
363 unsigned long rx_process_stopped;
364 unsigned long tx_early;
365 unsigned long fatal_bus_error;
366 };
367
368 struct xgmac_priv {
369 struct xgmac_dma_desc *dma_rx;
370 struct sk_buff **rx_skbuff;
371 unsigned int rx_tail;
372 unsigned int rx_head;
373
374 struct xgmac_dma_desc *dma_tx;
375 struct sk_buff **tx_skbuff;
376 unsigned int tx_head;
377 unsigned int tx_tail;
378 int tx_irq_cnt;
379
380 void __iomem *base;
381 unsigned int dma_buf_sz;
382 dma_addr_t dma_rx_phy;
383 dma_addr_t dma_tx_phy;
384
385 struct net_device *dev;
386 struct device *device;
387 struct napi_struct napi;
388
389 struct xgmac_extra_stats xstats;
390
391 spinlock_t stats_lock;
392 int pmt_irq;
393 char rx_pause;
394 char tx_pause;
395 int wolopts;
396 };
397
398 /* XGMAC Configuration Settings */
399 #define MAX_MTU 9000
400 #define PAUSE_TIME 0x400
401
402 #define DMA_RX_RING_SZ 256
403 #define DMA_TX_RING_SZ 128
404 /* minimum number of free TX descriptors required to wake up TX process */
405 #define TX_THRESH (DMA_TX_RING_SZ/4)
406
407 /* DMA descriptor ring helpers */
408 #define dma_ring_incr(n, s) (((n) + 1) & ((s) - 1))
409 #define dma_ring_space(h, t, s) CIRC_SPACE(h, t, s)
410 #define dma_ring_cnt(h, t, s) CIRC_CNT(h, t, s)
411
412 /* XGMAC Descriptor Access Helpers */
413 static inline void desc_set_buf_len(struct xgmac_dma_desc *p, u32 buf_sz)
414 {
415 if (buf_sz > MAX_DESC_BUF_SZ)
416 p->buf_size = cpu_to_le32(MAX_DESC_BUF_SZ |
417 (buf_sz - MAX_DESC_BUF_SZ) << DESC_BUFFER2_SZ_OFFSET);
418 else
419 p->buf_size = cpu_to_le32(buf_sz);
420 }
421
422 static inline int desc_get_buf_len(struct xgmac_dma_desc *p)
423 {
424 u32 len = cpu_to_le32(p->flags);
425 return (len & DESC_BUFFER1_SZ_MASK) +
426 ((len & DESC_BUFFER2_SZ_MASK) >> DESC_BUFFER2_SZ_OFFSET);
427 }
428
429 static inline void desc_init_rx_desc(struct xgmac_dma_desc *p, int ring_size,
430 int buf_sz)
431 {
432 struct xgmac_dma_desc *end = p + ring_size - 1;
433
434 memset(p, 0, sizeof(*p) * ring_size);
435
436 for (; p <= end; p++)
437 desc_set_buf_len(p, buf_sz);
438
439 end->buf_size |= cpu_to_le32(RXDESC1_END_RING);
440 }
441
442 static inline void desc_init_tx_desc(struct xgmac_dma_desc *p, u32 ring_size)
443 {
444 memset(p, 0, sizeof(*p) * ring_size);
445 p[ring_size - 1].flags = cpu_to_le32(TXDESC_END_RING);
446 }
447
448 static inline int desc_get_owner(struct xgmac_dma_desc *p)
449 {
450 return le32_to_cpu(p->flags) & DESC_OWN;
451 }
452
453 static inline void desc_set_rx_owner(struct xgmac_dma_desc *p)
454 {
455 /* Clear all fields and set the owner */
456 p->flags = cpu_to_le32(DESC_OWN);
457 }
458
459 static inline void desc_set_tx_owner(struct xgmac_dma_desc *p, u32 flags)
460 {
461 u32 tmpflags = le32_to_cpu(p->flags);
462 tmpflags &= TXDESC_END_RING;
463 tmpflags |= flags | DESC_OWN;
464 p->flags = cpu_to_le32(tmpflags);
465 }
466
467 static inline int desc_get_tx_ls(struct xgmac_dma_desc *p)
468 {
469 return le32_to_cpu(p->flags) & TXDESC_LAST_SEG;
470 }
471
472 static inline u32 desc_get_buf_addr(struct xgmac_dma_desc *p)
473 {
474 return le32_to_cpu(p->buf1_addr);
475 }
476
477 static inline void desc_set_buf_addr(struct xgmac_dma_desc *p,
478 u32 paddr, int len)
479 {
480 p->buf1_addr = cpu_to_le32(paddr);
481 if (len > MAX_DESC_BUF_SZ)
482 p->buf2_addr = cpu_to_le32(paddr + MAX_DESC_BUF_SZ);
483 }
484
485 static inline void desc_set_buf_addr_and_size(struct xgmac_dma_desc *p,
486 u32 paddr, int len)
487 {
488 desc_set_buf_len(p, len);
489 desc_set_buf_addr(p, paddr, len);
490 }
491
492 static inline int desc_get_rx_frame_len(struct xgmac_dma_desc *p)
493 {
494 u32 data = le32_to_cpu(p->flags);
495 u32 len = (data & RXDESC_FRAME_LEN_MASK) >> RXDESC_FRAME_LEN_OFFSET;
496 if (data & RXDESC_FRAME_TYPE)
497 len -= ETH_FCS_LEN;
498
499 return len;
500 }
501
502 static void xgmac_dma_flush_tx_fifo(void __iomem *ioaddr)
503 {
504 int timeout = 1000;
505 u32 reg = readl(ioaddr + XGMAC_OMR);
506 writel(reg | XGMAC_OMR_FTF, ioaddr + XGMAC_OMR);
507
508 while ((timeout-- > 0) && readl(ioaddr + XGMAC_OMR) & XGMAC_OMR_FTF)
509 udelay(1);
510 }
511
512 static int desc_get_tx_status(struct xgmac_priv *priv, struct xgmac_dma_desc *p)
513 {
514 struct xgmac_extra_stats *x = &priv->xstats;
515 u32 status = le32_to_cpu(p->flags);
516
517 if (!(status & TXDESC_ERROR_SUMMARY))
518 return 0;
519
520 netdev_dbg(priv->dev, "tx desc error = 0x%08x\n", status);
521 if (status & TXDESC_JABBER_TIMEOUT)
522 x->tx_jabber++;
523 if (status & TXDESC_FRAME_FLUSHED)
524 x->tx_frame_flushed++;
525 if (status & TXDESC_UNDERFLOW_ERR)
526 xgmac_dma_flush_tx_fifo(priv->base);
527 if (status & TXDESC_IP_HEADER_ERR)
528 x->tx_ip_header_error++;
529 if (status & TXDESC_LOCAL_FAULT)
530 x->tx_local_fault++;
531 if (status & TXDESC_REMOTE_FAULT)
532 x->tx_remote_fault++;
533 if (status & TXDESC_PAYLOAD_CSUM_ERR)
534 x->tx_payload_error++;
535
536 return -1;
537 }
538
539 static int desc_get_rx_status(struct xgmac_priv *priv, struct xgmac_dma_desc *p)
540 {
541 struct xgmac_extra_stats *x = &priv->xstats;
542 int ret = CHECKSUM_UNNECESSARY;
543 u32 status = le32_to_cpu(p->flags);
544 u32 ext_status = le32_to_cpu(p->ext_status);
545
546 if (status & RXDESC_DA_FILTER_FAIL) {
547 netdev_dbg(priv->dev, "XGMAC RX : Dest Address filter fail\n");
548 x->rx_da_filter_fail++;
549 return -1;
550 }
551
552 /* All frames should fit into a single buffer */
553 if (!(status & RXDESC_FIRST_SEG) || !(status & RXDESC_LAST_SEG))
554 return -1;
555
556 /* Check if packet has checksum already */
557 if ((status & RXDESC_FRAME_TYPE) && (status & RXDESC_EXT_STATUS) &&
558 !(ext_status & RXDESC_IP_PAYLOAD_MASK))
559 ret = CHECKSUM_NONE;
560
561 netdev_dbg(priv->dev, "rx status - frame type=%d, csum = %d, ext stat %08x\n",
562 (status & RXDESC_FRAME_TYPE) ? 1 : 0, ret, ext_status);
563
564 if (!(status & RXDESC_ERROR_SUMMARY))
565 return ret;
566
567 /* Handle any errors */
568 if (status & (RXDESC_DESCRIPTOR_ERR | RXDESC_OVERFLOW_ERR |
569 RXDESC_GIANT_FRAME | RXDESC_LENGTH_ERR | RXDESC_CRC_ERR))
570 return -1;
571
572 if (status & RXDESC_EXT_STATUS) {
573 if (ext_status & RXDESC_IP_HEADER_ERR)
574 x->rx_ip_header_error++;
575 if (ext_status & RXDESC_IP_PAYLOAD_ERR)
576 x->rx_payload_error++;
577 netdev_dbg(priv->dev, "IP checksum error - stat %08x\n",
578 ext_status);
579 return CHECKSUM_NONE;
580 }
581
582 return ret;
583 }
584
585 static inline void xgmac_mac_enable(void __iomem *ioaddr)
586 {
587 u32 value = readl(ioaddr + XGMAC_CONTROL);
588 value |= MAC_ENABLE_RX | MAC_ENABLE_TX;
589 writel(value, ioaddr + XGMAC_CONTROL);
590
591 value = readl(ioaddr + XGMAC_DMA_CONTROL);
592 value |= DMA_CONTROL_ST | DMA_CONTROL_SR;
593 writel(value, ioaddr + XGMAC_DMA_CONTROL);
594 }
595
596 static inline void xgmac_mac_disable(void __iomem *ioaddr)
597 {
598 u32 value = readl(ioaddr + XGMAC_DMA_CONTROL);
599 value &= ~(DMA_CONTROL_ST | DMA_CONTROL_SR);
600 writel(value, ioaddr + XGMAC_DMA_CONTROL);
601
602 value = readl(ioaddr + XGMAC_CONTROL);
603 value &= ~(MAC_ENABLE_TX | MAC_ENABLE_RX);
604 writel(value, ioaddr + XGMAC_CONTROL);
605 }
606
607 static void xgmac_set_mac_addr(void __iomem *ioaddr, unsigned char *addr,
608 int num)
609 {
610 u32 data;
611
612 data = (addr[5] << 8) | addr[4] | (num ? XGMAC_ADDR_AE : 0);
613 writel(data, ioaddr + XGMAC_ADDR_HIGH(num));
614 data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
615 writel(data, ioaddr + XGMAC_ADDR_LOW(num));
616 }
617
618 static void xgmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
619 int num)
620 {
621 u32 hi_addr, lo_addr;
622
623 /* Read the MAC address from the hardware */
624 hi_addr = readl(ioaddr + XGMAC_ADDR_HIGH(num));
625 lo_addr = readl(ioaddr + XGMAC_ADDR_LOW(num));
626
627 /* Extract the MAC address from the high and low words */
628 addr[0] = lo_addr & 0xff;
629 addr[1] = (lo_addr >> 8) & 0xff;
630 addr[2] = (lo_addr >> 16) & 0xff;
631 addr[3] = (lo_addr >> 24) & 0xff;
632 addr[4] = hi_addr & 0xff;
633 addr[5] = (hi_addr >> 8) & 0xff;
634 }
635
636 static int xgmac_set_flow_ctrl(struct xgmac_priv *priv, int rx, int tx)
637 {
638 u32 reg;
639 unsigned int flow = 0;
640
641 priv->rx_pause = rx;
642 priv->tx_pause = tx;
643
644 if (rx || tx) {
645 if (rx)
646 flow |= XGMAC_FLOW_CTRL_RFE;
647 if (tx)
648 flow |= XGMAC_FLOW_CTRL_TFE;
649
650 flow |= XGMAC_FLOW_CTRL_PLT | XGMAC_FLOW_CTRL_UP;
651 flow |= (PAUSE_TIME << XGMAC_FLOW_CTRL_PT_SHIFT);
652
653 writel(flow, priv->base + XGMAC_FLOW_CTRL);
654
655 reg = readl(priv->base + XGMAC_OMR);
656 reg |= XGMAC_OMR_EFC;
657 writel(reg, priv->base + XGMAC_OMR);
658 } else {
659 writel(0, priv->base + XGMAC_FLOW_CTRL);
660
661 reg = readl(priv->base + XGMAC_OMR);
662 reg &= ~XGMAC_OMR_EFC;
663 writel(reg, priv->base + XGMAC_OMR);
664 }
665
666 return 0;
667 }
668
669 static void xgmac_rx_refill(struct xgmac_priv *priv)
670 {
671 struct xgmac_dma_desc *p;
672 dma_addr_t paddr;
673 int bufsz = priv->dev->mtu + ETH_HLEN + ETH_FCS_LEN;
674
675 while (dma_ring_space(priv->rx_head, priv->rx_tail, DMA_RX_RING_SZ) > 1) {
676 int entry = priv->rx_head;
677 struct sk_buff *skb;
678
679 p = priv->dma_rx + entry;
680
681 if (priv->rx_skbuff[entry] == NULL) {
682 skb = netdev_alloc_skb_ip_align(priv->dev, bufsz);
683 if (unlikely(skb == NULL))
684 break;
685
686 priv->rx_skbuff[entry] = skb;
687 paddr = dma_map_single(priv->device, skb->data,
688 bufsz, DMA_FROM_DEVICE);
689 desc_set_buf_addr(p, paddr, priv->dma_buf_sz);
690 }
691
692 netdev_dbg(priv->dev, "rx ring: head %d, tail %d\n",
693 priv->rx_head, priv->rx_tail);
694
695 priv->rx_head = dma_ring_incr(priv->rx_head, DMA_RX_RING_SZ);
696 desc_set_rx_owner(p);
697 }
698 }
699
700 /**
701 * init_xgmac_dma_desc_rings - init the RX/TX descriptor rings
702 * @dev: net device structure
703 * Description: this function initializes the DMA RX/TX descriptors
704 * and allocates the socket buffers.
705 */
706 static int xgmac_dma_desc_rings_init(struct net_device *dev)
707 {
708 struct xgmac_priv *priv = netdev_priv(dev);
709 unsigned int bfsize;
710
711 /* Set the Buffer size according to the MTU;
712 * The total buffer size including any IP offset must be a multiple
713 * of 8 bytes.
714 */
715 bfsize = ALIGN(dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN, 8);
716
717 netdev_dbg(priv->dev, "mtu [%d] bfsize [%d]\n", dev->mtu, bfsize);
718
719 priv->rx_skbuff = kzalloc(sizeof(struct sk_buff *) * DMA_RX_RING_SZ,
720 GFP_KERNEL);
721 if (!priv->rx_skbuff)
722 return -ENOMEM;
723
724 priv->dma_rx = dma_alloc_coherent(priv->device,
725 DMA_RX_RING_SZ *
726 sizeof(struct xgmac_dma_desc),
727 &priv->dma_rx_phy,
728 GFP_KERNEL);
729 if (!priv->dma_rx)
730 goto err_dma_rx;
731
732 priv->tx_skbuff = kzalloc(sizeof(struct sk_buff *) * DMA_TX_RING_SZ,
733 GFP_KERNEL);
734 if (!priv->tx_skbuff)
735 goto err_tx_skb;
736
737 priv->dma_tx = dma_alloc_coherent(priv->device,
738 DMA_TX_RING_SZ *
739 sizeof(struct xgmac_dma_desc),
740 &priv->dma_tx_phy,
741 GFP_KERNEL);
742 if (!priv->dma_tx)
743 goto err_dma_tx;
744
745 netdev_dbg(priv->dev, "DMA desc rings: virt addr (Rx %p, "
746 "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n",
747 priv->dma_rx, priv->dma_tx,
748 (unsigned int)priv->dma_rx_phy, (unsigned int)priv->dma_tx_phy);
749
750 priv->rx_tail = 0;
751 priv->rx_head = 0;
752 priv->dma_buf_sz = bfsize;
753 desc_init_rx_desc(priv->dma_rx, DMA_RX_RING_SZ, priv->dma_buf_sz);
754 xgmac_rx_refill(priv);
755
756 priv->tx_tail = 0;
757 priv->tx_head = 0;
758 desc_init_tx_desc(priv->dma_tx, DMA_TX_RING_SZ);
759
760 writel(priv->dma_tx_phy, priv->base + XGMAC_DMA_TX_BASE_ADDR);
761 writel(priv->dma_rx_phy, priv->base + XGMAC_DMA_RX_BASE_ADDR);
762
763 return 0;
764
765 err_dma_tx:
766 kfree(priv->tx_skbuff);
767 err_tx_skb:
768 dma_free_coherent(priv->device,
769 DMA_RX_RING_SZ * sizeof(struct xgmac_dma_desc),
770 priv->dma_rx, priv->dma_rx_phy);
771 err_dma_rx:
772 kfree(priv->rx_skbuff);
773 return -ENOMEM;
774 }
775
776 static void xgmac_free_rx_skbufs(struct xgmac_priv *priv)
777 {
778 int i;
779 struct xgmac_dma_desc *p;
780
781 if (!priv->rx_skbuff)
782 return;
783
784 for (i = 0; i < DMA_RX_RING_SZ; i++) {
785 if (priv->rx_skbuff[i] == NULL)
786 continue;
787
788 p = priv->dma_rx + i;
789 dma_unmap_single(priv->device, desc_get_buf_addr(p),
790 priv->dma_buf_sz, DMA_FROM_DEVICE);
791 dev_kfree_skb_any(priv->rx_skbuff[i]);
792 priv->rx_skbuff[i] = NULL;
793 }
794 }
795
796 static void xgmac_free_tx_skbufs(struct xgmac_priv *priv)
797 {
798 int i, f;
799 struct xgmac_dma_desc *p;
800
801 if (!priv->tx_skbuff)
802 return;
803
804 for (i = 0; i < DMA_TX_RING_SZ; i++) {
805 if (priv->tx_skbuff[i] == NULL)
806 continue;
807
808 p = priv->dma_tx + i;
809 dma_unmap_single(priv->device, desc_get_buf_addr(p),
810 desc_get_buf_len(p), DMA_TO_DEVICE);
811
812 for (f = 0; f < skb_shinfo(priv->tx_skbuff[i])->nr_frags; f++) {
813 p = priv->dma_tx + i++;
814 dma_unmap_page(priv->device, desc_get_buf_addr(p),
815 desc_get_buf_len(p), DMA_TO_DEVICE);
816 }
817
818 dev_kfree_skb_any(priv->tx_skbuff[i]);
819 priv->tx_skbuff[i] = NULL;
820 }
821 }
822
823 static void xgmac_free_dma_desc_rings(struct xgmac_priv *priv)
824 {
825 /* Release the DMA TX/RX socket buffers */
826 xgmac_free_rx_skbufs(priv);
827 xgmac_free_tx_skbufs(priv);
828
829 /* Free the consistent memory allocated for descriptor rings */
830 if (priv->dma_tx) {
831 dma_free_coherent(priv->device,
832 DMA_TX_RING_SZ * sizeof(struct xgmac_dma_desc),
833 priv->dma_tx, priv->dma_tx_phy);
834 priv->dma_tx = NULL;
835 }
836 if (priv->dma_rx) {
837 dma_free_coherent(priv->device,
838 DMA_RX_RING_SZ * sizeof(struct xgmac_dma_desc),
839 priv->dma_rx, priv->dma_rx_phy);
840 priv->dma_rx = NULL;
841 }
842 kfree(priv->rx_skbuff);
843 priv->rx_skbuff = NULL;
844 kfree(priv->tx_skbuff);
845 priv->tx_skbuff = NULL;
846 }
847
848 /**
849 * xgmac_tx:
850 * @priv: private driver structure
851 * Description: it reclaims resources after transmission completes.
852 */
853 static void xgmac_tx_complete(struct xgmac_priv *priv)
854 {
855 int i;
856
857 while (dma_ring_cnt(priv->tx_head, priv->tx_tail, DMA_TX_RING_SZ)) {
858 unsigned int entry = priv->tx_tail;
859 struct sk_buff *skb = priv->tx_skbuff[entry];
860 struct xgmac_dma_desc *p = priv->dma_tx + entry;
861
862 /* Check if the descriptor is owned by the DMA. */
863 if (desc_get_owner(p))
864 break;
865
866 /* Verify tx error by looking at the last segment */
867 if (desc_get_tx_ls(p))
868 desc_get_tx_status(priv, p);
869
870 netdev_dbg(priv->dev, "tx ring: curr %d, dirty %d\n",
871 priv->tx_head, priv->tx_tail);
872
873 dma_unmap_single(priv->device, desc_get_buf_addr(p),
874 desc_get_buf_len(p), DMA_TO_DEVICE);
875
876 priv->tx_skbuff[entry] = NULL;
877 priv->tx_tail = dma_ring_incr(entry, DMA_TX_RING_SZ);
878
879 if (!skb) {
880 continue;
881 }
882
883 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
884 entry = priv->tx_tail = dma_ring_incr(priv->tx_tail,
885 DMA_TX_RING_SZ);
886 p = priv->dma_tx + priv->tx_tail;
887
888 dma_unmap_page(priv->device, desc_get_buf_addr(p),
889 desc_get_buf_len(p), DMA_TO_DEVICE);
890 }
891
892 dev_kfree_skb(skb);
893 }
894
895 if (dma_ring_space(priv->tx_head, priv->tx_tail, DMA_TX_RING_SZ) >
896 MAX_SKB_FRAGS)
897 netif_wake_queue(priv->dev);
898 }
899
900 /**
901 * xgmac_tx_err:
902 * @priv: pointer to the private device structure
903 * Description: it cleans the descriptors and restarts the transmission
904 * in case of errors.
905 */
906 static void xgmac_tx_err(struct xgmac_priv *priv)
907 {
908 u32 reg, value, inten;
909
910 netif_stop_queue(priv->dev);
911
912 inten = readl(priv->base + XGMAC_DMA_INTR_ENA);
913 writel(0, priv->base + XGMAC_DMA_INTR_ENA);
914
915 reg = readl(priv->base + XGMAC_DMA_CONTROL);
916 writel(reg & ~DMA_CONTROL_ST, priv->base + XGMAC_DMA_CONTROL);
917 do {
918 value = readl(priv->base + XGMAC_DMA_STATUS) & 0x700000;
919 } while (value && (value != 0x600000));
920
921 xgmac_free_tx_skbufs(priv);
922 desc_init_tx_desc(priv->dma_tx, DMA_TX_RING_SZ);
923 priv->tx_tail = 0;
924 priv->tx_head = 0;
925 writel(priv->dma_tx_phy, priv->base + XGMAC_DMA_TX_BASE_ADDR);
926 writel(reg | DMA_CONTROL_ST, priv->base + XGMAC_DMA_CONTROL);
927
928 writel(DMA_STATUS_TU | DMA_STATUS_TPS | DMA_STATUS_NIS | DMA_STATUS_AIS,
929 priv->base + XGMAC_DMA_STATUS);
930 writel(inten, priv->base + XGMAC_DMA_INTR_ENA);
931
932 netif_wake_queue(priv->dev);
933 }
934
935 static int xgmac_hw_init(struct net_device *dev)
936 {
937 u32 value, ctrl;
938 int limit;
939 struct xgmac_priv *priv = netdev_priv(dev);
940 void __iomem *ioaddr = priv->base;
941
942 /* Save the ctrl register value */
943 ctrl = readl(ioaddr + XGMAC_CONTROL) & XGMAC_CONTROL_SPD_MASK;
944
945 /* SW reset */
946 value = DMA_BUS_MODE_SFT_RESET;
947 writel(value, ioaddr + XGMAC_DMA_BUS_MODE);
948 limit = 15000;
949 while (limit-- &&
950 (readl(ioaddr + XGMAC_DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET))
951 cpu_relax();
952 if (limit < 0)
953 return -EBUSY;
954
955 value = (0x10 << DMA_BUS_MODE_PBL_SHIFT) |
956 (0x10 << DMA_BUS_MODE_RPBL_SHIFT) |
957 DMA_BUS_MODE_FB | DMA_BUS_MODE_ATDS | DMA_BUS_MODE_AAL;
958 writel(value, ioaddr + XGMAC_DMA_BUS_MODE);
959
960 /* Enable interrupts */
961 writel(DMA_INTR_DEFAULT_MASK, ioaddr + XGMAC_DMA_STATUS);
962 writel(DMA_INTR_DEFAULT_MASK, ioaddr + XGMAC_DMA_INTR_ENA);
963
964 /* Mask power mgt interrupt */
965 writel(XGMAC_INT_STAT_PMTIM, ioaddr + XGMAC_INT_STAT);
966
967 /* XGMAC requires AXI bus init. This is a 'magic number' for now */
968 writel(0x0077000E, ioaddr + XGMAC_DMA_AXI_BUS);
969
970 ctrl |= XGMAC_CONTROL_DDIC | XGMAC_CONTROL_JE | XGMAC_CONTROL_ACS |
971 XGMAC_CONTROL_CAR;
972 if (dev->features & NETIF_F_RXCSUM)
973 ctrl |= XGMAC_CONTROL_IPC;
974 writel(ctrl, ioaddr + XGMAC_CONTROL);
975
976 writel(DMA_CONTROL_OSF, ioaddr + XGMAC_DMA_CONTROL);
977
978 /* Set the HW DMA mode and the COE */
979 writel(XGMAC_OMR_TSF | XGMAC_OMR_RFD | XGMAC_OMR_RFA |
980 XGMAC_OMR_RTC_256,
981 ioaddr + XGMAC_OMR);
982
983 /* Reset the MMC counters */
984 writel(1, ioaddr + XGMAC_MMC_CTRL);
985 return 0;
986 }
987
988 /**
989 * xgmac_open - open entry point of the driver
990 * @dev : pointer to the device structure.
991 * Description:
992 * This function is the open entry point of the driver.
993 * Return value:
994 * 0 on success and an appropriate (-)ve integer as defined in errno.h
995 * file on failure.
996 */
997 static int xgmac_open(struct net_device *dev)
998 {
999 int ret;
1000 struct xgmac_priv *priv = netdev_priv(dev);
1001 void __iomem *ioaddr = priv->base;
1002
1003 /* Check that the MAC address is valid. If its not, refuse
1004 * to bring the device up. The user must specify an
1005 * address using the following linux command:
1006 * ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx */
1007 if (!is_valid_ether_addr(dev->dev_addr)) {
1008 eth_hw_addr_random(dev);
1009 netdev_dbg(priv->dev, "generated random MAC address %pM\n",
1010 dev->dev_addr);
1011 }
1012
1013 memset(&priv->xstats, 0, sizeof(struct xgmac_extra_stats));
1014
1015 /* Initialize the XGMAC and descriptors */
1016 xgmac_hw_init(dev);
1017 xgmac_set_mac_addr(ioaddr, dev->dev_addr, 0);
1018 xgmac_set_flow_ctrl(priv, priv->rx_pause, priv->tx_pause);
1019
1020 ret = xgmac_dma_desc_rings_init(dev);
1021 if (ret < 0)
1022 return ret;
1023
1024 /* Enable the MAC Rx/Tx */
1025 xgmac_mac_enable(ioaddr);
1026
1027 napi_enable(&priv->napi);
1028 netif_start_queue(dev);
1029
1030 return 0;
1031 }
1032
1033 /**
1034 * xgmac_release - close entry point of the driver
1035 * @dev : device pointer.
1036 * Description:
1037 * This is the stop entry point of the driver.
1038 */
1039 static int xgmac_stop(struct net_device *dev)
1040 {
1041 struct xgmac_priv *priv = netdev_priv(dev);
1042
1043 netif_stop_queue(dev);
1044
1045 if (readl(priv->base + XGMAC_DMA_INTR_ENA))
1046 napi_disable(&priv->napi);
1047
1048 writel(0, priv->base + XGMAC_DMA_INTR_ENA);
1049
1050 /* Disable the MAC core */
1051 xgmac_mac_disable(priv->base);
1052
1053 /* Release and free the Rx/Tx resources */
1054 xgmac_free_dma_desc_rings(priv);
1055
1056 return 0;
1057 }
1058
1059 /**
1060 * xgmac_xmit:
1061 * @skb : the socket buffer
1062 * @dev : device pointer
1063 * Description : Tx entry point of the driver.
1064 */
1065 static netdev_tx_t xgmac_xmit(struct sk_buff *skb, struct net_device *dev)
1066 {
1067 struct xgmac_priv *priv = netdev_priv(dev);
1068 unsigned int entry;
1069 int i;
1070 u32 irq_flag;
1071 int nfrags = skb_shinfo(skb)->nr_frags;
1072 struct xgmac_dma_desc *desc, *first;
1073 unsigned int desc_flags;
1074 unsigned int len;
1075 dma_addr_t paddr;
1076
1077 priv->tx_irq_cnt = (priv->tx_irq_cnt + 1) & (DMA_TX_RING_SZ/4 - 1);
1078 irq_flag = priv->tx_irq_cnt ? 0 : TXDESC_INTERRUPT;
1079
1080 desc_flags = (skb->ip_summed == CHECKSUM_PARTIAL) ?
1081 TXDESC_CSUM_ALL : 0;
1082 entry = priv->tx_head;
1083 desc = priv->dma_tx + entry;
1084 first = desc;
1085
1086 len = skb_headlen(skb);
1087 paddr = dma_map_single(priv->device, skb->data, len, DMA_TO_DEVICE);
1088 if (dma_mapping_error(priv->device, paddr)) {
1089 dev_kfree_skb(skb);
1090 return -EIO;
1091 }
1092 priv->tx_skbuff[entry] = skb;
1093 desc_set_buf_addr_and_size(desc, paddr, len);
1094
1095 for (i = 0; i < nfrags; i++) {
1096 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1097
1098 len = frag->size;
1099
1100 paddr = skb_frag_dma_map(priv->device, frag, 0, len,
1101 DMA_TO_DEVICE);
1102 if (dma_mapping_error(priv->device, paddr)) {
1103 dev_kfree_skb(skb);
1104 return -EIO;
1105 }
1106
1107 entry = dma_ring_incr(entry, DMA_TX_RING_SZ);
1108 desc = priv->dma_tx + entry;
1109 priv->tx_skbuff[entry] = NULL;
1110
1111 desc_set_buf_addr_and_size(desc, paddr, len);
1112 if (i < (nfrags - 1))
1113 desc_set_tx_owner(desc, desc_flags);
1114 }
1115
1116 /* Interrupt on completition only for the latest segment */
1117 if (desc != first)
1118 desc_set_tx_owner(desc, desc_flags |
1119 TXDESC_LAST_SEG | irq_flag);
1120 else
1121 desc_flags |= TXDESC_LAST_SEG | irq_flag;
1122
1123 /* Set owner on first desc last to avoid race condition */
1124 wmb();
1125 desc_set_tx_owner(first, desc_flags | TXDESC_FIRST_SEG);
1126
1127 priv->tx_head = dma_ring_incr(entry, DMA_TX_RING_SZ);
1128
1129 writel(1, priv->base + XGMAC_DMA_TX_POLL);
1130 if (dma_ring_space(priv->tx_head, priv->tx_tail, DMA_TX_RING_SZ) <
1131 MAX_SKB_FRAGS)
1132 netif_stop_queue(dev);
1133
1134 return NETDEV_TX_OK;
1135 }
1136
1137 static int xgmac_rx(struct xgmac_priv *priv, int limit)
1138 {
1139 unsigned int entry;
1140 unsigned int count = 0;
1141 struct xgmac_dma_desc *p;
1142
1143 while (count < limit) {
1144 int ip_checksum;
1145 struct sk_buff *skb;
1146 int frame_len;
1147
1148 if (!dma_ring_cnt(priv->rx_head, priv->rx_tail, DMA_RX_RING_SZ))
1149 break;
1150
1151 entry = priv->rx_tail;
1152 p = priv->dma_rx + entry;
1153 if (desc_get_owner(p))
1154 break;
1155
1156 count++;
1157 priv->rx_tail = dma_ring_incr(priv->rx_tail, DMA_RX_RING_SZ);
1158
1159 /* read the status of the incoming frame */
1160 ip_checksum = desc_get_rx_status(priv, p);
1161 if (ip_checksum < 0)
1162 continue;
1163
1164 skb = priv->rx_skbuff[entry];
1165 if (unlikely(!skb)) {
1166 netdev_err(priv->dev, "Inconsistent Rx descriptor chain\n");
1167 break;
1168 }
1169 priv->rx_skbuff[entry] = NULL;
1170
1171 frame_len = desc_get_rx_frame_len(p);
1172 netdev_dbg(priv->dev, "RX frame size %d, COE status: %d\n",
1173 frame_len, ip_checksum);
1174
1175 skb_put(skb, frame_len);
1176 dma_unmap_single(priv->device, desc_get_buf_addr(p),
1177 frame_len, DMA_FROM_DEVICE);
1178
1179 skb->protocol = eth_type_trans(skb, priv->dev);
1180 skb->ip_summed = ip_checksum;
1181 if (ip_checksum == CHECKSUM_NONE)
1182 netif_receive_skb(skb);
1183 else
1184 napi_gro_receive(&priv->napi, skb);
1185 }
1186
1187 xgmac_rx_refill(priv);
1188
1189 return count;
1190 }
1191
1192 /**
1193 * xgmac_poll - xgmac poll method (NAPI)
1194 * @napi : pointer to the napi structure.
1195 * @budget : maximum number of packets that the current CPU can receive from
1196 * all interfaces.
1197 * Description :
1198 * This function implements the the reception process.
1199 * Also it runs the TX completion thread
1200 */
1201 static int xgmac_poll(struct napi_struct *napi, int budget)
1202 {
1203 struct xgmac_priv *priv = container_of(napi,
1204 struct xgmac_priv, napi);
1205 int work_done = 0;
1206
1207 xgmac_tx_complete(priv);
1208 work_done = xgmac_rx(priv, budget);
1209
1210 if (work_done < budget) {
1211 napi_complete(napi);
1212 __raw_writel(DMA_INTR_DEFAULT_MASK, priv->base + XGMAC_DMA_INTR_ENA);
1213 }
1214 return work_done;
1215 }
1216
1217 /**
1218 * xgmac_tx_timeout
1219 * @dev : Pointer to net device structure
1220 * Description: this function is called when a packet transmission fails to
1221 * complete within a reasonable tmrate. The driver will mark the error in the
1222 * netdev structure and arrange for the device to be reset to a sane state
1223 * in order to transmit a new packet.
1224 */
1225 static void xgmac_tx_timeout(struct net_device *dev)
1226 {
1227 struct xgmac_priv *priv = netdev_priv(dev);
1228
1229 /* Clear Tx resources and restart transmitting again */
1230 xgmac_tx_err(priv);
1231 }
1232
1233 /**
1234 * xgmac_set_rx_mode - entry point for multicast addressing
1235 * @dev : pointer to the device structure
1236 * Description:
1237 * This function is a driver entry point which gets called by the kernel
1238 * whenever multicast addresses must be enabled/disabled.
1239 * Return value:
1240 * void.
1241 */
1242 static void xgmac_set_rx_mode(struct net_device *dev)
1243 {
1244 int i;
1245 struct xgmac_priv *priv = netdev_priv(dev);
1246 void __iomem *ioaddr = priv->base;
1247 unsigned int value = 0;
1248 u32 hash_filter[XGMAC_NUM_HASH];
1249 int reg = 1;
1250 struct netdev_hw_addr *ha;
1251 bool use_hash = false;
1252
1253 netdev_dbg(priv->dev, "# mcasts %d, # unicast %d\n",
1254 netdev_mc_count(dev), netdev_uc_count(dev));
1255
1256 if (dev->flags & IFF_PROMISC) {
1257 writel(XGMAC_FRAME_FILTER_PR, ioaddr + XGMAC_FRAME_FILTER);
1258 return;
1259 }
1260
1261 memset(hash_filter, 0, sizeof(hash_filter));
1262
1263 if (netdev_uc_count(dev) > XGMAC_MAX_FILTER_ADDR) {
1264 use_hash = true;
1265 value |= XGMAC_FRAME_FILTER_HUC | XGMAC_FRAME_FILTER_HPF;
1266 }
1267 netdev_for_each_uc_addr(ha, dev) {
1268 if (use_hash) {
1269 u32 bit_nr = ~ether_crc(ETH_ALEN, ha->addr) >> 23;
1270
1271 /* The most significant 4 bits determine the register to
1272 * use (H/L) while the other 5 bits determine the bit
1273 * within the register. */
1274 hash_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1275 } else {
1276 xgmac_set_mac_addr(ioaddr, ha->addr, reg);
1277 reg++;
1278 }
1279 }
1280
1281 if (dev->flags & IFF_ALLMULTI) {
1282 value |= XGMAC_FRAME_FILTER_PM;
1283 goto out;
1284 }
1285
1286 if ((netdev_mc_count(dev) + reg - 1) > XGMAC_MAX_FILTER_ADDR) {
1287 use_hash = true;
1288 value |= XGMAC_FRAME_FILTER_HMC | XGMAC_FRAME_FILTER_HPF;
1289 }
1290 netdev_for_each_mc_addr(ha, dev) {
1291 if (use_hash) {
1292 u32 bit_nr = ~ether_crc(ETH_ALEN, ha->addr) >> 23;
1293
1294 /* The most significant 4 bits determine the register to
1295 * use (H/L) while the other 5 bits determine the bit
1296 * within the register. */
1297 hash_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1298 } else {
1299 xgmac_set_mac_addr(ioaddr, ha->addr, reg);
1300 reg++;
1301 }
1302 }
1303
1304 out:
1305 for (i = 0; i < XGMAC_NUM_HASH; i++)
1306 writel(hash_filter[i], ioaddr + XGMAC_HASH(i));
1307
1308 writel(value, ioaddr + XGMAC_FRAME_FILTER);
1309 }
1310
1311 /**
1312 * xgmac_change_mtu - entry point to change MTU size for the device.
1313 * @dev : device pointer.
1314 * @new_mtu : the new MTU size for the device.
1315 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
1316 * to drive packet transmission. Ethernet has an MTU of 1500 octets
1317 * (ETH_DATA_LEN). This value can be changed with ifconfig.
1318 * Return value:
1319 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1320 * file on failure.
1321 */
1322 static int xgmac_change_mtu(struct net_device *dev, int new_mtu)
1323 {
1324 struct xgmac_priv *priv = netdev_priv(dev);
1325 int old_mtu;
1326
1327 if ((new_mtu < 46) || (new_mtu > MAX_MTU)) {
1328 netdev_err(priv->dev, "invalid MTU, max MTU is: %d\n", MAX_MTU);
1329 return -EINVAL;
1330 }
1331
1332 old_mtu = dev->mtu;
1333 dev->mtu = new_mtu;
1334
1335 /* return early if the buffer sizes will not change */
1336 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1337 return 0;
1338 if (old_mtu == new_mtu)
1339 return 0;
1340
1341 /* Stop everything, get ready to change the MTU */
1342 if (!netif_running(dev))
1343 return 0;
1344
1345 /* Bring the interface down and then back up */
1346 xgmac_stop(dev);
1347 return xgmac_open(dev);
1348 }
1349
1350 static irqreturn_t xgmac_pmt_interrupt(int irq, void *dev_id)
1351 {
1352 u32 intr_status;
1353 struct net_device *dev = (struct net_device *)dev_id;
1354 struct xgmac_priv *priv = netdev_priv(dev);
1355 void __iomem *ioaddr = priv->base;
1356
1357 intr_status = __raw_readl(ioaddr + XGMAC_INT_STAT);
1358 if (intr_status & XGMAC_INT_STAT_PMT) {
1359 netdev_dbg(priv->dev, "received Magic frame\n");
1360 /* clear the PMT bits 5 and 6 by reading the PMT */
1361 readl(ioaddr + XGMAC_PMT);
1362 }
1363 return IRQ_HANDLED;
1364 }
1365
1366 static irqreturn_t xgmac_interrupt(int irq, void *dev_id)
1367 {
1368 u32 intr_status;
1369 bool tx_err = false;
1370 struct net_device *dev = (struct net_device *)dev_id;
1371 struct xgmac_priv *priv = netdev_priv(dev);
1372 struct xgmac_extra_stats *x = &priv->xstats;
1373
1374 /* read the status register (CSR5) */
1375 intr_status = __raw_readl(priv->base + XGMAC_DMA_STATUS);
1376 intr_status &= __raw_readl(priv->base + XGMAC_DMA_INTR_ENA);
1377 __raw_writel(intr_status, priv->base + XGMAC_DMA_STATUS);
1378
1379 /* It displays the DMA process states (CSR5 register) */
1380 /* ABNORMAL interrupts */
1381 if (unlikely(intr_status & DMA_STATUS_AIS)) {
1382 if (intr_status & DMA_STATUS_TJT) {
1383 netdev_err(priv->dev, "transmit jabber\n");
1384 x->tx_jabber++;
1385 }
1386 if (intr_status & DMA_STATUS_RU)
1387 x->rx_buf_unav++;
1388 if (intr_status & DMA_STATUS_RPS) {
1389 netdev_err(priv->dev, "receive process stopped\n");
1390 x->rx_process_stopped++;
1391 }
1392 if (intr_status & DMA_STATUS_ETI) {
1393 netdev_err(priv->dev, "transmit early interrupt\n");
1394 x->tx_early++;
1395 }
1396 if (intr_status & DMA_STATUS_TPS) {
1397 netdev_err(priv->dev, "transmit process stopped\n");
1398 x->tx_process_stopped++;
1399 tx_err = true;
1400 }
1401 if (intr_status & DMA_STATUS_FBI) {
1402 netdev_err(priv->dev, "fatal bus error\n");
1403 x->fatal_bus_error++;
1404 tx_err = true;
1405 }
1406
1407 if (tx_err)
1408 xgmac_tx_err(priv);
1409 }
1410
1411 /* TX/RX NORMAL interrupts */
1412 if (intr_status & (DMA_STATUS_RI | DMA_STATUS_TU | DMA_STATUS_TI)) {
1413 __raw_writel(DMA_INTR_ABNORMAL, priv->base + XGMAC_DMA_INTR_ENA);
1414 napi_schedule(&priv->napi);
1415 }
1416
1417 return IRQ_HANDLED;
1418 }
1419
1420 #ifdef CONFIG_NET_POLL_CONTROLLER
1421 /* Polling receive - used by NETCONSOLE and other diagnostic tools
1422 * to allow network I/O with interrupts disabled. */
1423 static void xgmac_poll_controller(struct net_device *dev)
1424 {
1425 disable_irq(dev->irq);
1426 xgmac_interrupt(dev->irq, dev);
1427 enable_irq(dev->irq);
1428 }
1429 #endif
1430
1431 static struct rtnl_link_stats64 *
1432 xgmac_get_stats64(struct net_device *dev,
1433 struct rtnl_link_stats64 *storage)
1434 {
1435 struct xgmac_priv *priv = netdev_priv(dev);
1436 void __iomem *base = priv->base;
1437 u32 count;
1438
1439 spin_lock_bh(&priv->stats_lock);
1440 writel(XGMAC_MMC_CTRL_CNT_FRZ, base + XGMAC_MMC_CTRL);
1441
1442 storage->rx_bytes = readl(base + XGMAC_MMC_RXOCTET_G_LO);
1443 storage->rx_bytes |= (u64)(readl(base + XGMAC_MMC_RXOCTET_G_HI)) << 32;
1444
1445 storage->rx_packets = readl(base + XGMAC_MMC_RXFRAME_GB_LO);
1446 storage->multicast = readl(base + XGMAC_MMC_RXMCFRAME_G);
1447 storage->rx_crc_errors = readl(base + XGMAC_MMC_RXCRCERR);
1448 storage->rx_length_errors = readl(base + XGMAC_MMC_RXLENGTHERR);
1449 storage->rx_missed_errors = readl(base + XGMAC_MMC_RXOVERFLOW);
1450
1451 storage->tx_bytes = readl(base + XGMAC_MMC_TXOCTET_G_LO);
1452 storage->tx_bytes |= (u64)(readl(base + XGMAC_MMC_TXOCTET_G_HI)) << 32;
1453
1454 count = readl(base + XGMAC_MMC_TXFRAME_GB_LO);
1455 storage->tx_errors = count - readl(base + XGMAC_MMC_TXFRAME_G_LO);
1456 storage->tx_packets = count;
1457 storage->tx_fifo_errors = readl(base + XGMAC_MMC_TXUNDERFLOW);
1458
1459 writel(0, base + XGMAC_MMC_CTRL);
1460 spin_unlock_bh(&priv->stats_lock);
1461 return storage;
1462 }
1463
1464 static int xgmac_set_mac_address(struct net_device *dev, void *p)
1465 {
1466 struct xgmac_priv *priv = netdev_priv(dev);
1467 void __iomem *ioaddr = priv->base;
1468 struct sockaddr *addr = p;
1469
1470 if (!is_valid_ether_addr(addr->sa_data))
1471 return -EADDRNOTAVAIL;
1472
1473 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1474
1475 xgmac_set_mac_addr(ioaddr, dev->dev_addr, 0);
1476
1477 return 0;
1478 }
1479
1480 static int xgmac_set_features(struct net_device *dev, netdev_features_t features)
1481 {
1482 u32 ctrl;
1483 struct xgmac_priv *priv = netdev_priv(dev);
1484 void __iomem *ioaddr = priv->base;
1485 netdev_features_t changed = dev->features ^ features;
1486
1487 if (!(changed & NETIF_F_RXCSUM))
1488 return 0;
1489
1490 ctrl = readl(ioaddr + XGMAC_CONTROL);
1491 if (features & NETIF_F_RXCSUM)
1492 ctrl |= XGMAC_CONTROL_IPC;
1493 else
1494 ctrl &= ~XGMAC_CONTROL_IPC;
1495 writel(ctrl, ioaddr + XGMAC_CONTROL);
1496
1497 return 0;
1498 }
1499
1500 static const struct net_device_ops xgmac_netdev_ops = {
1501 .ndo_open = xgmac_open,
1502 .ndo_start_xmit = xgmac_xmit,
1503 .ndo_stop = xgmac_stop,
1504 .ndo_change_mtu = xgmac_change_mtu,
1505 .ndo_set_rx_mode = xgmac_set_rx_mode,
1506 .ndo_tx_timeout = xgmac_tx_timeout,
1507 .ndo_get_stats64 = xgmac_get_stats64,
1508 #ifdef CONFIG_NET_POLL_CONTROLLER
1509 .ndo_poll_controller = xgmac_poll_controller,
1510 #endif
1511 .ndo_set_mac_address = xgmac_set_mac_address,
1512 .ndo_set_features = xgmac_set_features,
1513 };
1514
1515 static int xgmac_ethtool_getsettings(struct net_device *dev,
1516 struct ethtool_cmd *cmd)
1517 {
1518 cmd->autoneg = 0;
1519 cmd->duplex = DUPLEX_FULL;
1520 ethtool_cmd_speed_set(cmd, 10000);
1521 cmd->supported = 0;
1522 cmd->advertising = 0;
1523 cmd->transceiver = XCVR_INTERNAL;
1524 return 0;
1525 }
1526
1527 static void xgmac_get_pauseparam(struct net_device *netdev,
1528 struct ethtool_pauseparam *pause)
1529 {
1530 struct xgmac_priv *priv = netdev_priv(netdev);
1531
1532 pause->rx_pause = priv->rx_pause;
1533 pause->tx_pause = priv->tx_pause;
1534 }
1535
1536 static int xgmac_set_pauseparam(struct net_device *netdev,
1537 struct ethtool_pauseparam *pause)
1538 {
1539 struct xgmac_priv *priv = netdev_priv(netdev);
1540
1541 if (pause->autoneg)
1542 return -EINVAL;
1543
1544 return xgmac_set_flow_ctrl(priv, pause->rx_pause, pause->tx_pause);
1545 }
1546
1547 struct xgmac_stats {
1548 char stat_string[ETH_GSTRING_LEN];
1549 int stat_offset;
1550 bool is_reg;
1551 };
1552
1553 #define XGMAC_STAT(m) \
1554 { #m, offsetof(struct xgmac_priv, xstats.m), false }
1555 #define XGMAC_HW_STAT(m, reg_offset) \
1556 { #m, reg_offset, true }
1557
1558 static const struct xgmac_stats xgmac_gstrings_stats[] = {
1559 XGMAC_STAT(tx_frame_flushed),
1560 XGMAC_STAT(tx_payload_error),
1561 XGMAC_STAT(tx_ip_header_error),
1562 XGMAC_STAT(tx_local_fault),
1563 XGMAC_STAT(tx_remote_fault),
1564 XGMAC_STAT(tx_early),
1565 XGMAC_STAT(tx_process_stopped),
1566 XGMAC_STAT(tx_jabber),
1567 XGMAC_STAT(rx_buf_unav),
1568 XGMAC_STAT(rx_process_stopped),
1569 XGMAC_STAT(rx_payload_error),
1570 XGMAC_STAT(rx_ip_header_error),
1571 XGMAC_STAT(rx_da_filter_fail),
1572 XGMAC_STAT(rx_sa_filter_fail),
1573 XGMAC_STAT(fatal_bus_error),
1574 XGMAC_HW_STAT(rx_watchdog, XGMAC_MMC_RXWATCHDOG),
1575 XGMAC_HW_STAT(tx_vlan, XGMAC_MMC_TXVLANFRAME),
1576 XGMAC_HW_STAT(rx_vlan, XGMAC_MMC_RXVLANFRAME),
1577 XGMAC_HW_STAT(tx_pause, XGMAC_MMC_TXPAUSEFRAME),
1578 XGMAC_HW_STAT(rx_pause, XGMAC_MMC_RXPAUSEFRAME),
1579 };
1580 #define XGMAC_STATS_LEN ARRAY_SIZE(xgmac_gstrings_stats)
1581
1582 static void xgmac_get_ethtool_stats(struct net_device *dev,
1583 struct ethtool_stats *dummy,
1584 u64 *data)
1585 {
1586 struct xgmac_priv *priv = netdev_priv(dev);
1587 void *p = priv;
1588 int i;
1589
1590 for (i = 0; i < XGMAC_STATS_LEN; i++) {
1591 if (xgmac_gstrings_stats[i].is_reg)
1592 *data++ = readl(priv->base +
1593 xgmac_gstrings_stats[i].stat_offset);
1594 else
1595 *data++ = *(u32 *)(p +
1596 xgmac_gstrings_stats[i].stat_offset);
1597 }
1598 }
1599
1600 static int xgmac_get_sset_count(struct net_device *netdev, int sset)
1601 {
1602 switch (sset) {
1603 case ETH_SS_STATS:
1604 return XGMAC_STATS_LEN;
1605 default:
1606 return -EINVAL;
1607 }
1608 }
1609
1610 static void xgmac_get_strings(struct net_device *dev, u32 stringset,
1611 u8 *data)
1612 {
1613 int i;
1614 u8 *p = data;
1615
1616 switch (stringset) {
1617 case ETH_SS_STATS:
1618 for (i = 0; i < XGMAC_STATS_LEN; i++) {
1619 memcpy(p, xgmac_gstrings_stats[i].stat_string,
1620 ETH_GSTRING_LEN);
1621 p += ETH_GSTRING_LEN;
1622 }
1623 break;
1624 default:
1625 WARN_ON(1);
1626 break;
1627 }
1628 }
1629
1630 static void xgmac_get_wol(struct net_device *dev,
1631 struct ethtool_wolinfo *wol)
1632 {
1633 struct xgmac_priv *priv = netdev_priv(dev);
1634
1635 if (device_can_wakeup(priv->device)) {
1636 wol->supported = WAKE_MAGIC | WAKE_UCAST;
1637 wol->wolopts = priv->wolopts;
1638 }
1639 }
1640
1641 static int xgmac_set_wol(struct net_device *dev,
1642 struct ethtool_wolinfo *wol)
1643 {
1644 struct xgmac_priv *priv = netdev_priv(dev);
1645 u32 support = WAKE_MAGIC | WAKE_UCAST;
1646
1647 if (!device_can_wakeup(priv->device))
1648 return -ENOTSUPP;
1649
1650 if (wol->wolopts & ~support)
1651 return -EINVAL;
1652
1653 priv->wolopts = wol->wolopts;
1654
1655 if (wol->wolopts) {
1656 device_set_wakeup_enable(priv->device, 1);
1657 enable_irq_wake(dev->irq);
1658 } else {
1659 device_set_wakeup_enable(priv->device, 0);
1660 disable_irq_wake(dev->irq);
1661 }
1662
1663 return 0;
1664 }
1665
1666 static const struct ethtool_ops xgmac_ethtool_ops = {
1667 .get_settings = xgmac_ethtool_getsettings,
1668 .get_link = ethtool_op_get_link,
1669 .get_pauseparam = xgmac_get_pauseparam,
1670 .set_pauseparam = xgmac_set_pauseparam,
1671 .get_ethtool_stats = xgmac_get_ethtool_stats,
1672 .get_strings = xgmac_get_strings,
1673 .get_wol = xgmac_get_wol,
1674 .set_wol = xgmac_set_wol,
1675 .get_sset_count = xgmac_get_sset_count,
1676 };
1677
1678 /**
1679 * xgmac_probe
1680 * @pdev: platform device pointer
1681 * Description: the driver is initialized through platform_device.
1682 */
1683 static int xgmac_probe(struct platform_device *pdev)
1684 {
1685 int ret = 0;
1686 struct resource *res;
1687 struct net_device *ndev = NULL;
1688 struct xgmac_priv *priv = NULL;
1689 u32 uid;
1690
1691 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1692 if (!res)
1693 return -ENODEV;
1694
1695 if (!request_mem_region(res->start, resource_size(res), pdev->name))
1696 return -EBUSY;
1697
1698 ndev = alloc_etherdev(sizeof(struct xgmac_priv));
1699 if (!ndev) {
1700 ret = -ENOMEM;
1701 goto err_alloc;
1702 }
1703
1704 SET_NETDEV_DEV(ndev, &pdev->dev);
1705 priv = netdev_priv(ndev);
1706 platform_set_drvdata(pdev, ndev);
1707 ether_setup(ndev);
1708 ndev->netdev_ops = &xgmac_netdev_ops;
1709 SET_ETHTOOL_OPS(ndev, &xgmac_ethtool_ops);
1710 spin_lock_init(&priv->stats_lock);
1711
1712 priv->device = &pdev->dev;
1713 priv->dev = ndev;
1714 priv->rx_pause = 1;
1715 priv->tx_pause = 1;
1716
1717 priv->base = ioremap(res->start, resource_size(res));
1718 if (!priv->base) {
1719 netdev_err(ndev, "ioremap failed\n");
1720 ret = -ENOMEM;
1721 goto err_io;
1722 }
1723
1724 uid = readl(priv->base + XGMAC_VERSION);
1725 netdev_info(ndev, "h/w version is 0x%x\n", uid);
1726
1727 writel(0, priv->base + XGMAC_DMA_INTR_ENA);
1728 ndev->irq = platform_get_irq(pdev, 0);
1729 if (ndev->irq == -ENXIO) {
1730 netdev_err(ndev, "No irq resource\n");
1731 ret = ndev->irq;
1732 goto err_irq;
1733 }
1734
1735 ret = request_irq(ndev->irq, xgmac_interrupt, 0,
1736 dev_name(&pdev->dev), ndev);
1737 if (ret < 0) {
1738 netdev_err(ndev, "Could not request irq %d - ret %d)\n",
1739 ndev->irq, ret);
1740 goto err_irq;
1741 }
1742
1743 priv->pmt_irq = platform_get_irq(pdev, 1);
1744 if (priv->pmt_irq == -ENXIO) {
1745 netdev_err(ndev, "No pmt irq resource\n");
1746 ret = priv->pmt_irq;
1747 goto err_pmt_irq;
1748 }
1749
1750 ret = request_irq(priv->pmt_irq, xgmac_pmt_interrupt, 0,
1751 dev_name(&pdev->dev), ndev);
1752 if (ret < 0) {
1753 netdev_err(ndev, "Could not request irq %d - ret %d)\n",
1754 priv->pmt_irq, ret);
1755 goto err_pmt_irq;
1756 }
1757
1758 device_set_wakeup_capable(&pdev->dev, 1);
1759 if (device_can_wakeup(priv->device))
1760 priv->wolopts = WAKE_MAGIC; /* Magic Frame as default */
1761
1762 ndev->hw_features = NETIF_F_SG | NETIF_F_FRAGLIST | NETIF_F_HIGHDMA;
1763 if (readl(priv->base + XGMAC_DMA_HW_FEATURE) & DMA_HW_FEAT_TXCOESEL)
1764 ndev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1765 NETIF_F_RXCSUM;
1766 ndev->features |= ndev->hw_features;
1767 ndev->priv_flags |= IFF_UNICAST_FLT;
1768
1769 /* Get the MAC address */
1770 xgmac_get_mac_addr(priv->base, ndev->dev_addr, 0);
1771 if (!is_valid_ether_addr(ndev->dev_addr))
1772 netdev_warn(ndev, "MAC address %pM not valid",
1773 ndev->dev_addr);
1774
1775 netif_napi_add(ndev, &priv->napi, xgmac_poll, 64);
1776 ret = register_netdev(ndev);
1777 if (ret)
1778 goto err_reg;
1779
1780 return 0;
1781
1782 err_reg:
1783 netif_napi_del(&priv->napi);
1784 free_irq(priv->pmt_irq, ndev);
1785 err_pmt_irq:
1786 free_irq(ndev->irq, ndev);
1787 err_irq:
1788 iounmap(priv->base);
1789 err_io:
1790 free_netdev(ndev);
1791 err_alloc:
1792 release_mem_region(res->start, resource_size(res));
1793 return ret;
1794 }
1795
1796 /**
1797 * xgmac_dvr_remove
1798 * @pdev: platform device pointer
1799 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
1800 * changes the link status, releases the DMA descriptor rings,
1801 * unregisters the MDIO bus and unmaps the allocated memory.
1802 */
1803 static int xgmac_remove(struct platform_device *pdev)
1804 {
1805 struct net_device *ndev = platform_get_drvdata(pdev);
1806 struct xgmac_priv *priv = netdev_priv(ndev);
1807 struct resource *res;
1808
1809 xgmac_mac_disable(priv->base);
1810
1811 /* Free the IRQ lines */
1812 free_irq(ndev->irq, ndev);
1813 free_irq(priv->pmt_irq, ndev);
1814
1815 unregister_netdev(ndev);
1816 netif_napi_del(&priv->napi);
1817
1818 iounmap(priv->base);
1819 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1820 release_mem_region(res->start, resource_size(res));
1821
1822 free_netdev(ndev);
1823
1824 return 0;
1825 }
1826
1827 #ifdef CONFIG_PM_SLEEP
1828 static void xgmac_pmt(void __iomem *ioaddr, unsigned long mode)
1829 {
1830 unsigned int pmt = 0;
1831
1832 if (mode & WAKE_MAGIC)
1833 pmt |= XGMAC_PMT_POWERDOWN | XGMAC_PMT_MAGIC_PKT_EN;
1834 if (mode & WAKE_UCAST)
1835 pmt |= XGMAC_PMT_POWERDOWN | XGMAC_PMT_GLBL_UNICAST;
1836
1837 writel(pmt, ioaddr + XGMAC_PMT);
1838 }
1839
1840 static int xgmac_suspend(struct device *dev)
1841 {
1842 struct net_device *ndev = platform_get_drvdata(to_platform_device(dev));
1843 struct xgmac_priv *priv = netdev_priv(ndev);
1844 u32 value;
1845
1846 if (!ndev || !netif_running(ndev))
1847 return 0;
1848
1849 netif_device_detach(ndev);
1850 napi_disable(&priv->napi);
1851 writel(0, priv->base + XGMAC_DMA_INTR_ENA);
1852
1853 if (device_may_wakeup(priv->device)) {
1854 /* Stop TX/RX DMA Only */
1855 value = readl(priv->base + XGMAC_DMA_CONTROL);
1856 value &= ~(DMA_CONTROL_ST | DMA_CONTROL_SR);
1857 writel(value, priv->base + XGMAC_DMA_CONTROL);
1858
1859 xgmac_pmt(priv->base, priv->wolopts);
1860 } else
1861 xgmac_mac_disable(priv->base);
1862
1863 return 0;
1864 }
1865
1866 static int xgmac_resume(struct device *dev)
1867 {
1868 struct net_device *ndev = platform_get_drvdata(to_platform_device(dev));
1869 struct xgmac_priv *priv = netdev_priv(ndev);
1870 void __iomem *ioaddr = priv->base;
1871
1872 if (!netif_running(ndev))
1873 return 0;
1874
1875 xgmac_pmt(ioaddr, 0);
1876
1877 /* Enable the MAC and DMA */
1878 xgmac_mac_enable(ioaddr);
1879 writel(DMA_INTR_DEFAULT_MASK, ioaddr + XGMAC_DMA_STATUS);
1880 writel(DMA_INTR_DEFAULT_MASK, ioaddr + XGMAC_DMA_INTR_ENA);
1881
1882 netif_device_attach(ndev);
1883 napi_enable(&priv->napi);
1884
1885 return 0;
1886 }
1887 #endif /* CONFIG_PM_SLEEP */
1888
1889 static SIMPLE_DEV_PM_OPS(xgmac_pm_ops, xgmac_suspend, xgmac_resume);
1890
1891 static const struct of_device_id xgmac_of_match[] = {
1892 { .compatible = "calxeda,hb-xgmac", },
1893 {},
1894 };
1895 MODULE_DEVICE_TABLE(of, xgmac_of_match);
1896
1897 static struct platform_driver xgmac_driver = {
1898 .driver = {
1899 .name = "calxedaxgmac",
1900 .of_match_table = xgmac_of_match,
1901 },
1902 .probe = xgmac_probe,
1903 .remove = xgmac_remove,
1904 .driver.pm = &xgmac_pm_ops,
1905 };
1906
1907 module_platform_driver(xgmac_driver);
1908
1909 MODULE_AUTHOR("Calxeda, Inc.");
1910 MODULE_DESCRIPTION("Calxeda 10G XGMAC driver");
1911 MODULE_LICENSE("GPL v2");
CRIS linux kernel tree