drivers/net/ethernet/freescale/gianfar_ptp.c

   1 /*
   2  * PTP 1588 clock using the eTSEC
   3  *
   4  * Copyright (C) 2010 OMICRON electronics GmbH
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *  GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, write to the Free Software
  18  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20
  21 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  22
  23 #include <linux/device.h>
  24 #include <linux/hrtimer.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/kernel.h>
  28 #include <linux/module.h>
  29 #include <linux/of.h>
  30 #include <linux/of_platform.h>
  31 #include <linux/timex.h>
  32 #include <linux/io.h>
  33
  34 #include <linux/ptp_clock_kernel.h>
  35
  36 #include "gianfar.h"
  37
  38 /*
  39  * gianfar ptp registers
  40  * Generated by regen.tcl on Thu May 13 01:38:57 PM CEST 2010
  41  */
  42 struct gianfar_ptp_registers {
  43         u32 tmr_ctrl;     /* Timer control register */
  44         u32 tmr_tevent;   /* Timestamp event register */
  45         u32 tmr_temask;   /* Timer event mask register */
  46         u32 tmr_pevent;   /* Timestamp event register */
  47         u32 tmr_pemask;   /* Timer event mask register */
  48         u32 tmr_stat;     /* Timestamp status register */
  49         u32 tmr_cnt_h;    /* Timer counter high register */
  50         u32 tmr_cnt_l;    /* Timer counter low register */
  51         u32 tmr_add;      /* Timer drift compensation addend register */
  52         u32 tmr_acc;      /* Timer accumulator register */
  53         u32 tmr_prsc;     /* Timer prescale */
  54         u8  res1[4];
  55         u32 tmroff_h;     /* Timer offset high */
  56         u32 tmroff_l;     /* Timer offset low */
  57         u8  res2[8];
  58         u32 tmr_alarm1_h; /* Timer alarm 1 high register */
  59         u32 tmr_alarm1_l; /* Timer alarm 1 high register */
  60         u32 tmr_alarm2_h; /* Timer alarm 2 high register */
  61         u32 tmr_alarm2_l; /* Timer alarm 2 high register */
  62         u8  res3[48];
  63         u32 tmr_fiper1;   /* Timer fixed period interval */
  64         u32 tmr_fiper2;   /* Timer fixed period interval */
  65         u32 tmr_fiper3;   /* Timer fixed period interval */
  66         u8  res4[20];
  67         u32 tmr_etts1_h;  /* Timestamp of general purpose external trigger */
  68         u32 tmr_etts1_l;  /* Timestamp of general purpose external trigger */
  69         u32 tmr_etts2_h;  /* Timestamp of general purpose external trigger */
  70         u32 tmr_etts2_l;  /* Timestamp of general purpose external trigger */
  71 };
  72
  73 /* Bit definitions for the TMR_CTRL register */
  74 #define ALM1P                 (1<<31) /* Alarm1 output polarity */
  75 #define ALM2P                 (1<<30) /* Alarm2 output polarity */
  76 #define FS                    (1<<28) /* FIPER start indication */
  77 #define PP1L                  (1<<27) /* Fiper1 pulse loopback mode enabled. */
  78 #define PP2L                  (1<<26) /* Fiper2 pulse loopback mode enabled. */
  79 #define TCLK_PERIOD_SHIFT     (16) /* 1588 timer reference clock period. */
  80 #define TCLK_PERIOD_MASK      (0x3ff)
  81 #define RTPE                  (1<<15) /* Record Tx Timestamp to PAL Enable. */
  82 #define FRD                   (1<<14) /* FIPER Realignment Disable */
  83 #define ESFDP                 (1<<11) /* External Tx/Rx SFD Polarity. */
  84 #define ESFDE                 (1<<10) /* External Tx/Rx SFD Enable. */
  85 #define ETEP2                 (1<<9) /* External trigger 2 edge polarity */
  86 #define ETEP1                 (1<<8) /* External trigger 1 edge polarity */
  87 #define COPH                  (1<<7) /* Generated clock output phase. */
  88 #define CIPH                  (1<<6) /* External oscillator input clock phase */
  89 #define TMSR                  (1<<5) /* Timer soft reset. */
  90 #define BYP                   (1<<3) /* Bypass drift compensated clock */
  91 #define TE                    (1<<2) /* 1588 timer enable. */
  92 #define CKSEL_SHIFT           (0)    /* 1588 Timer reference clock source */
  93 #define CKSEL_MASK            (0x3)
  94
  95 /* Bit definitions for the TMR_TEVENT register */
  96 #define ETS2                  (1<<25) /* External trigger 2 timestamp sampled */
  97 #define ETS1                  (1<<24) /* External trigger 1 timestamp sampled */
  98 #define ALM2                  (1<<17) /* Current time = alarm time register 2 */
  99 #define ALM1                  (1<<16) /* Current time = alarm time register 1 */
 100 #define PP1                   (1<<7)  /* periodic pulse generated on FIPER1 */
 101 #define PP2                   (1<<6)  /* periodic pulse generated on FIPER2 */
 102 #define PP3                   (1<<5)  /* periodic pulse generated on FIPER3 */
 103
 104 /* Bit definitions for the TMR_TEMASK register */
 105 #define ETS2EN                (1<<25) /* External trigger 2 timestamp enable */
 106 #define ETS1EN                (1<<24) /* External trigger 1 timestamp enable */
 107 #define ALM2EN                (1<<17) /* Timer ALM2 event enable */
 108 #define ALM1EN                (1<<16) /* Timer ALM1 event enable */
 109 #define PP1EN                 (1<<7) /* Periodic pulse event 1 enable */
 110 #define PP2EN                 (1<<6) /* Periodic pulse event 2 enable */
 111
 112 /* Bit definitions for the TMR_PEVENT register */
 113 #define TXP2                  (1<<9) /* PTP transmitted timestamp im TXTS2 */
 114 #define TXP1                  (1<<8) /* PTP transmitted timestamp in TXTS1 */
 115 #define RXP                   (1<<0) /* PTP frame has been received */
 116
 117 /* Bit definitions for the TMR_PEMASK register */
 118 #define TXP2EN                (1<<9) /* Transmit PTP packet event 2 enable */
 119 #define TXP1EN                (1<<8) /* Transmit PTP packet event 1 enable */
 120 #define RXPEN                 (1<<0) /* Receive PTP packet event enable */
 121
 122 /* Bit definitions for the TMR_STAT register */
 123 #define STAT_VEC_SHIFT        (0) /* Timer general purpose status vector */
 124 #define STAT_VEC_MASK         (0x3f)
 125
 126 /* Bit definitions for the TMR_PRSC register */
 127 #define PRSC_OCK_SHIFT        (0) /* Output clock division/prescale factor. */
 128 #define PRSC_OCK_MASK         (0xffff)
 129
 130
 131 #define DRIVER          "gianfar_ptp"
 132 #define DEFAULT_CKSEL   1
 133 #define N_EXT_TS        2
 134 #define REG_SIZE        sizeof(struct gianfar_ptp_registers)
 135
 136 struct etsects {
 137         struct gianfar_ptp_registers *regs;
 138         spinlock_t lock; /* protects regs */
 139         struct ptp_clock *clock;
 140         struct ptp_clock_info caps;
 141         struct resource *rsrc;
 142         int irq;
 143         u64 alarm_interval; /* for periodic alarm */
 144         u64 alarm_value;
 145         u32 tclk_period;  /* nanoseconds */
 146         u32 tmr_prsc;
 147         u32 tmr_add;
 148         u32 cksel;
 149         u32 tmr_fiper1;
 150         u32 tmr_fiper2;
 151 };
 152
 153 /*
 154  * Register access functions
 155  */
 156
 157 /* Caller must hold etsects->lock. */
 158 static u64 tmr_cnt_read(struct etsects *etsects)
 159 {
 160         u64 ns;
 161         u32 lo, hi;
 162
 163         lo = gfar_read(&etsects->regs->tmr_cnt_l);
 164         hi = gfar_read(&etsects->regs->tmr_cnt_h);
 165         ns = ((u64) hi) << 32;
 166         ns |= lo;
 167         return ns;
 168 }
 169
 170 /* Caller must hold etsects->lock. */
 171 static void tmr_cnt_write(struct etsects *etsects, u64 ns)
 172 {
 173         u32 hi = ns >> 32;
 174         u32 lo = ns & 0xffffffff;
 175
 176         gfar_write(&etsects->regs->tmr_cnt_l, lo);
 177         gfar_write(&etsects->regs->tmr_cnt_h, hi);
 178 }
 179
 180 /* Caller must hold etsects->lock. */
 181 static void set_alarm(struct etsects *etsects)
 182 {
 183         u64 ns;
 184         u32 lo, hi;
 185
 186         ns = tmr_cnt_read(etsects) + 1500000000ULL;
 187         ns = div_u64(ns, 1000000000UL) * 1000000000ULL;
 188         ns -= etsects->tclk_period;
 189         hi = ns >> 32;
 190         lo = ns & 0xffffffff;
 191         gfar_write(&etsects->regs->tmr_alarm1_l, lo);
 192         gfar_write(&etsects->regs->tmr_alarm1_h, hi);
 193 }
 194
 195 /* Caller must hold etsects->lock. */
 196 static void set_fipers(struct etsects *etsects)
 197 {
 198         set_alarm(etsects);
 199         gfar_write(&etsects->regs->tmr_fiper1, etsects->tmr_fiper1);
 200         gfar_write(&etsects->regs->tmr_fiper2, etsects->tmr_fiper2);
 201 }
 202
 203 /*
 204  * Interrupt service routine
 205  */
 206
 207 static irqreturn_t isr(int irq, void *priv)
 208 {
 209         struct etsects *etsects = priv;
 210         struct ptp_clock_event event;
 211         u64 ns;
 212         u32 ack = 0, lo, hi, mask, val;
 213
 214         val = gfar_read(&etsects->regs->tmr_tevent);
 215
 216         if (val & ETS1) {
 217                 ack |= ETS1;
 218                 hi = gfar_read(&etsects->regs->tmr_etts1_h);
 219                 lo = gfar_read(&etsects->regs->tmr_etts1_l);
 220                 event.type = PTP_CLOCK_EXTTS;
 221                 event.index = 0;
 222                 event.timestamp = ((u64) hi) << 32;
 223                 event.timestamp |= lo;
 224                 ptp_clock_event(etsects->clock, &event);
 225         }
 226
 227         if (val & ETS2) {
 228                 ack |= ETS2;
 229                 hi = gfar_read(&etsects->regs->tmr_etts2_h);
 230                 lo = gfar_read(&etsects->regs->tmr_etts2_l);
 231                 event.type = PTP_CLOCK_EXTTS;
 232                 event.index = 1;
 233                 event.timestamp = ((u64) hi) << 32;
 234                 event.timestamp |= lo;
 235                 ptp_clock_event(etsects->clock, &event);
 236         }
 237
 238         if (val & ALM2) {
 239                 ack |= ALM2;
 240                 if (etsects->alarm_value) {
 241                         event.type = PTP_CLOCK_ALARM;
 242                         event.index = 0;
 243                         event.timestamp = etsects->alarm_value;
 244                         ptp_clock_event(etsects->clock, &event);
 245                 }
 246                 if (etsects->alarm_interval) {
 247                         ns = etsects->alarm_value + etsects->alarm_interval;
 248                         hi = ns >> 32;
 249                         lo = ns & 0xffffffff;
 250                         spin_lock(&etsects->lock);
 251                         gfar_write(&etsects->regs->tmr_alarm2_l, lo);
 252                         gfar_write(&etsects->regs->tmr_alarm2_h, hi);
 253                         spin_unlock(&etsects->lock);
 254                         etsects->alarm_value = ns;
 255                 } else {
 256                         gfar_write(&etsects->regs->tmr_tevent, ALM2);
 257                         spin_lock(&etsects->lock);
 258                         mask = gfar_read(&etsects->regs->tmr_temask);
 259                         mask &= ~ALM2EN;
 260                         gfar_write(&etsects->regs->tmr_temask, mask);
 261                         spin_unlock(&etsects->lock);
 262                         etsects->alarm_value = 0;
 263                         etsects->alarm_interval = 0;
 264                 }
 265         }
 266
 267         if (val & PP1) {
 268                 ack |= PP1;
 269                 event.type = PTP_CLOCK_PPS;
 270                 ptp_clock_event(etsects->clock, &event);
 271         }
 272
 273         if (ack) {
 274                 gfar_write(&etsects->regs->tmr_tevent, ack);
 275                 return IRQ_HANDLED;
 276         } else
 277                 return IRQ_NONE;
 278 }
 279
 280 /*
 281  * PTP clock operations
 282  */
 283
 284 static int ptp_gianfar_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
 285 {
 286         u64 adj;
 287         u32 diff, tmr_add;
 288         int neg_adj = 0;
 289         struct etsects *etsects = container_of(ptp, struct etsects, caps);
 290
 291         if (ppb < 0) {
 292                 neg_adj = 1;
 293                 ppb = -ppb;
 294         }
 295         tmr_add = etsects->tmr_add;
 296         adj = tmr_add;
 297         adj *= ppb;
 298         diff = div_u64(adj, 1000000000ULL);
 299
 300         tmr_add = neg_adj ? tmr_add - diff : tmr_add + diff;
 301
 302         gfar_write(&etsects->regs->tmr_add, tmr_add);
 303
 304         return 0;
 305 }
 306
 307 static int ptp_gianfar_adjtime(struct ptp_clock_info *ptp, s64 delta)
 308 {
 309         s64 now;
 310         unsigned long flags;
 311         struct etsects *etsects = container_of(ptp, struct etsects, caps);
 312
 313         spin_lock_irqsave(&etsects->lock, flags);
 314
 315         now = tmr_cnt_read(etsects);
 316         now += delta;
 317         tmr_cnt_write(etsects, now);
 318
 319         spin_unlock_irqrestore(&etsects->lock, flags);
 320
 321         set_fipers(etsects);
 322
 323         return 0;
 324 }
 325
 326 static int ptp_gianfar_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
 327 {
 328         u64 ns;
 329         u32 remainder;
 330         unsigned long flags;
 331         struct etsects *etsects = container_of(ptp, struct etsects, caps);
 332
 333         spin_lock_irqsave(&etsects->lock, flags);
 334
 335         ns = tmr_cnt_read(etsects);
 336
 337         spin_unlock_irqrestore(&etsects->lock, flags);
 338
 339         ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
 340         ts->tv_nsec = remainder;
 341         return 0;
 342 }
 343
 344 static int ptp_gianfar_settime(struct ptp_clock_info *ptp,
 345                                const struct timespec *ts)
 346 {
 347         u64 ns;
 348         unsigned long flags;
 349         struct etsects *etsects = container_of(ptp, struct etsects, caps);
 350
 351         ns = ts->tv_sec * 1000000000ULL;
 352         ns += ts->tv_nsec;
 353
 354         spin_lock_irqsave(&etsects->lock, flags);
 355
 356         tmr_cnt_write(etsects, ns);
 357         set_fipers(etsects);
 358
 359         spin_unlock_irqrestore(&etsects->lock, flags);
 360
 361         return 0;
 362 }
 363
 364 static int ptp_gianfar_enable(struct ptp_clock_info *ptp,
 365                               struct ptp_clock_request *rq, int on)
 366 {
 367         struct etsects *etsects = container_of(ptp, struct etsects, caps);
 368         unsigned long flags;
 369         u32 bit, mask;
 370
 371         switch (rq->type) {
 372         case PTP_CLK_REQ_EXTTS:
 373                 switch (rq->extts.index) {
 374                 case 0:
 375                         bit = ETS1EN;
 376                         break;
 377                 case 1:
 378                         bit = ETS2EN;
 379                         break;
 380                 default:
 381                         return -EINVAL;
 382                 }
 383                 spin_lock_irqsave(&etsects->lock, flags);
 384                 mask = gfar_read(&etsects->regs->tmr_temask);
 385                 if (on)
 386                         mask |= bit;
 387                 else
 388                         mask &= ~bit;
 389                 gfar_write(&etsects->regs->tmr_temask, mask);
 390                 spin_unlock_irqrestore(&etsects->lock, flags);
 391                 return 0;
 392
 393         case PTP_CLK_REQ_PPS:
 394                 spin_lock_irqsave(&etsects->lock, flags);
 395                 mask = gfar_read(&etsects->regs->tmr_temask);
 396                 if (on)
 397                         mask |= PP1EN;
 398                 else
 399                         mask &= ~PP1EN;
 400                 gfar_write(&etsects->regs->tmr_temask, mask);
 401                 spin_unlock_irqrestore(&etsects->lock, flags);
 402                 return 0;
 403
 404         default:
 405                 break;
 406         }
 407
 408         return -EOPNOTSUPP;
 409 }
 410
 411 static struct ptp_clock_info ptp_gianfar_caps = {
 412         .owner          = THIS_MODULE,
 413         .name           = "gianfar clock",
 414         .max_adj        = 512000,
 415         .n_alarm        = 0,
 416         .n_ext_ts       = N_EXT_TS,
 417         .n_per_out      = 0,
 418         .pps            = 1,
 419         .adjfreq        = ptp_gianfar_adjfreq,
 420         .adjtime        = ptp_gianfar_adjtime,
 421         .gettime        = ptp_gianfar_gettime,
 422         .settime        = ptp_gianfar_settime,
 423         .enable         = ptp_gianfar_enable,
 424 };
 425
 426 /* OF device tree */
 427
 428 static int get_of_u32(struct device_node *node, char *str, u32 *val)
 429 {
 430         int plen;
 431         const u32 *prop = of_get_property(node, str, &plen);
 432
 433         if (!prop || plen != sizeof(*prop))
 434                 return -1;
 435         *val = *prop;
 436         return 0;
 437 }
 438
 439 static int gianfar_ptp_probe(struct platform_device *dev)
 440 {
 441         struct device_node *node = dev->dev.of_node;
 442         struct etsects *etsects;
 443         struct timespec now;
 444         int err = -ENOMEM;
 445         u32 tmr_ctrl;
 446         unsigned long flags;
 447
 448         etsects = kzalloc(sizeof(*etsects), GFP_KERNEL);
 449         if (!etsects)
 450                 goto no_memory;
 451
 452         err = -ENODEV;
 453
 454         etsects->caps = ptp_gianfar_caps;
 455         etsects->cksel = DEFAULT_CKSEL;
 456
 457         if (get_of_u32(node, "fsl,tclk-period", &etsects->tclk_period) ||
 458             get_of_u32(node, "fsl,tmr-prsc", &etsects->tmr_prsc) ||
 459             get_of_u32(node, "fsl,tmr-add", &etsects->tmr_add) ||
 460             get_of_u32(node, "fsl,tmr-fiper1", &etsects->tmr_fiper1) ||
 461             get_of_u32(node, "fsl,tmr-fiper2", &etsects->tmr_fiper2) ||
 462             get_of_u32(node, "fsl,max-adj", &etsects->caps.max_adj)) {
 463                 pr_err("device tree node missing required elements\n");
 464                 goto no_node;
 465         }
 466
 467         etsects->irq = platform_get_irq(dev, 0);
 468
 469         if (etsects->irq == NO_IRQ) {
 470                 pr_err("irq not in device tree\n");
 471                 goto no_node;
 472         }
 473         if (request_irq(etsects->irq, isr, 0, DRIVER, etsects)) {
 474                 pr_err("request_irq failed\n");
 475                 goto no_node;
 476         }
 477
 478         etsects->rsrc = platform_get_resource(dev, IORESOURCE_MEM, 0);
 479         if (!etsects->rsrc) {
 480                 pr_err("no resource\n");
 481                 goto no_resource;
 482         }
 483         if (request_resource(&iomem_resource, etsects->rsrc)) {
 484                 pr_err("resource busy\n");
 485                 goto no_resource;
 486         }
 487
 488         spin_lock_init(&etsects->lock);
 489
 490         etsects->regs = ioremap(etsects->rsrc->start,
 491                                 resource_size(etsects->rsrc));
 492         if (!etsects->regs) {
 493                 pr_err("ioremap ptp registers failed\n");
 494                 goto no_ioremap;
 495         }
 496         getnstimeofday(&now);
 497         ptp_gianfar_settime(&etsects->caps, &now);
 498
 499         tmr_ctrl =
 500           (etsects->tclk_period & TCLK_PERIOD_MASK) << TCLK_PERIOD_SHIFT |
 501           (etsects->cksel & CKSEL_MASK) << CKSEL_SHIFT;
 502
 503         spin_lock_irqsave(&etsects->lock, flags);
 504
 505         gfar_write(&etsects->regs->tmr_ctrl,   tmr_ctrl);
 506         gfar_write(&etsects->regs->tmr_add,    etsects->tmr_add);
 507         gfar_write(&etsects->regs->tmr_prsc,   etsects->tmr_prsc);
 508         gfar_write(&etsects->regs->tmr_fiper1, etsects->tmr_fiper1);
 509         gfar_write(&etsects->regs->tmr_fiper2, etsects->tmr_fiper2);
 510         set_alarm(etsects);
 511         gfar_write(&etsects->regs->tmr_ctrl,   tmr_ctrl|FS|RTPE|TE|FRD);
 512
 513         spin_unlock_irqrestore(&etsects->lock, flags);
 514
 515         etsects->clock = ptp_clock_register(&etsects->caps, &dev->dev);
 516         if (IS_ERR(etsects->clock)) {
 517                 err = PTR_ERR(etsects->clock);
 518                 goto no_clock;
 519         }
 520         gfar_phc_index = ptp_clock_index(etsects->clock);
 521
 522         platform_set_drvdata(dev, etsects);
 523
 524         return 0;
 525
 526 no_clock:
 527         iounmap(etsects->regs);
 528 no_ioremap:
 529         release_resource(etsects->rsrc);
 530 no_resource:
 531         free_irq(etsects->irq, etsects);
 532 no_node:
 533         kfree(etsects);
 534 no_memory:
 535         return err;
 536 }
 537
 538 static int gianfar_ptp_remove(struct platform_device *dev)
 539 {
 540         struct etsects *etsects = platform_get_drvdata(dev);
 541
 542         gfar_write(&etsects->regs->tmr_temask, 0);
 543         gfar_write(&etsects->regs->tmr_ctrl,   0);
 544
 545         gfar_phc_index = -1;
 546         ptp_clock_unregister(etsects->clock);
 547         iounmap(etsects->regs);
 548         release_resource(etsects->rsrc);
 549         free_irq(etsects->irq, etsects);
 550         kfree(etsects);
 551
 552         return 0;
 553 }
 554
 555 static struct of_device_id match_table[] = {
 556         { .compatible = "fsl,etsec-ptp" },
 557         {},
 558 };
 559
 560 static struct platform_driver gianfar_ptp_driver = {
 561         .driver = {
 562                 .name           = "gianfar_ptp",
 563                 .of_match_table = match_table,
 564                 .owner          = THIS_MODULE,
 565         },
 566         .probe       = gianfar_ptp_probe,
 567         .remove      = gianfar_ptp_remove,
 568 };
 569
 570 module_platform_driver(gianfar_ptp_driver);
 571
 572 MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
 573 MODULE_DESCRIPTION("PTP clock using the eTSEC");
 574 MODULE_LICENSE("GPL");