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Linux 3.11-rc3
[cris-mirror.git] / drivers / net / ethernet / intel / e1000e / 82571.c
blob4c303e2a7cb3f3aae1ed974d6a066168c7e82c4a
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /* 82571EB Gigabit Ethernet Controller
30 * 82571EB Gigabit Ethernet Controller (Copper)
31 * 82571EB Gigabit Ethernet Controller (Fiber)
32 * 82571EB Dual Port Gigabit Mezzanine Adapter
33 * 82571EB Quad Port Gigabit Mezzanine Adapter
34 * 82571PT Gigabit PT Quad Port Server ExpressModule
35 * 82572EI Gigabit Ethernet Controller (Copper)
36 * 82572EI Gigabit Ethernet Controller (Fiber)
37 * 82572EI Gigabit Ethernet Controller
38 * 82573V Gigabit Ethernet Controller (Copper)
39 * 82573E Gigabit Ethernet Controller (Copper)
40 * 82573L Gigabit Ethernet Controller
41 * 82574L Gigabit Network Connection
42 * 82583V Gigabit Network Connection
43 */
44
45 #include "e1000.h"
46
47 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
48 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
49 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
50 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
51 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
52 u16 words, u16 *data);
53 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
54 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
55 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
56 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
57 static s32 e1000_led_on_82574(struct e1000_hw *hw);
58 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
59 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
60 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
61 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
62 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
63 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active);
64 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active);
65
66 /**
67 * e1000_init_phy_params_82571 - Init PHY func ptrs.
68 * @hw: pointer to the HW structure
69 **/
70 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
71 {
72 struct e1000_phy_info *phy = &hw->phy;
73 s32 ret_val;
74
75 if (hw->phy.media_type != e1000_media_type_copper) {
76 phy->type = e1000_phy_none;
77 return 0;
78 }
79
80 phy->addr = 1;
81 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
82 phy->reset_delay_us = 100;
83
84 phy->ops.power_up = e1000_power_up_phy_copper;
85 phy->ops.power_down = e1000_power_down_phy_copper_82571;
86
87 switch (hw->mac.type) {
88 case e1000_82571:
89 case e1000_82572:
90 phy->type = e1000_phy_igp_2;
91 break;
92 case e1000_82573:
93 phy->type = e1000_phy_m88;
94 break;
95 case e1000_82574:
96 case e1000_82583:
97 phy->type = e1000_phy_bm;
98 phy->ops.acquire = e1000_get_hw_semaphore_82574;
99 phy->ops.release = e1000_put_hw_semaphore_82574;
100 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574;
101 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574;
102 break;
103 default:
104 return -E1000_ERR_PHY;
105 break;
106 }
107
108 /* This can only be done after all function pointers are setup. */
109 ret_val = e1000_get_phy_id_82571(hw);
110 if (ret_val) {
111 e_dbg("Error getting PHY ID\n");
112 return ret_val;
113 }
114
115 /* Verify phy id */
116 switch (hw->mac.type) {
117 case e1000_82571:
118 case e1000_82572:
119 if (phy->id != IGP01E1000_I_PHY_ID)
120 ret_val = -E1000_ERR_PHY;
121 break;
122 case e1000_82573:
123 if (phy->id != M88E1111_I_PHY_ID)
124 ret_val = -E1000_ERR_PHY;
125 break;
126 case e1000_82574:
127 case e1000_82583:
128 if (phy->id != BME1000_E_PHY_ID_R2)
129 ret_val = -E1000_ERR_PHY;
130 break;
131 default:
132 ret_val = -E1000_ERR_PHY;
133 break;
134 }
135
136 if (ret_val)
137 e_dbg("PHY ID unknown: type = 0x%08x\n", phy->id);
138
139 return ret_val;
140 }
141
142 /**
143 * e1000_init_nvm_params_82571 - Init NVM func ptrs.
144 * @hw: pointer to the HW structure
145 **/
146 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
147 {
148 struct e1000_nvm_info *nvm = &hw->nvm;
149 u32 eecd = er32(EECD);
150 u16 size;
151
152 nvm->opcode_bits = 8;
153 nvm->delay_usec = 1;
154 switch (nvm->override) {
155 case e1000_nvm_override_spi_large:
156 nvm->page_size = 32;
157 nvm->address_bits = 16;
158 break;
159 case e1000_nvm_override_spi_small:
160 nvm->page_size = 8;
161 nvm->address_bits = 8;
162 break;
163 default:
164 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
165 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
166 break;
167 }
168
169 switch (hw->mac.type) {
170 case e1000_82573:
171 case e1000_82574:
172 case e1000_82583:
173 if (((eecd >> 15) & 0x3) == 0x3) {
174 nvm->type = e1000_nvm_flash_hw;
175 nvm->word_size = 2048;
176 /* Autonomous Flash update bit must be cleared due
177 * to Flash update issue.
178 */
179 eecd &= ~E1000_EECD_AUPDEN;
180 ew32(EECD, eecd);
181 break;
182 }
183 /* Fall Through */
184 default:
185 nvm->type = e1000_nvm_eeprom_spi;
186 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
187 E1000_EECD_SIZE_EX_SHIFT);
188 /* Added to a constant, "size" becomes the left-shift value
189 * for setting word_size.
190 */
191 size += NVM_WORD_SIZE_BASE_SHIFT;
192
193 /* EEPROM access above 16k is unsupported */
194 if (size > 14)
195 size = 14;
196 nvm->word_size = 1 << size;
197 break;
198 }
199
200 /* Function Pointers */
201 switch (hw->mac.type) {
202 case e1000_82574:
203 case e1000_82583:
204 nvm->ops.acquire = e1000_get_hw_semaphore_82574;
205 nvm->ops.release = e1000_put_hw_semaphore_82574;
206 break;
207 default:
208 break;
209 }
210
211 return 0;
212 }
213
214 /**
215 * e1000_init_mac_params_82571 - Init MAC func ptrs.
216 * @hw: pointer to the HW structure
217 **/
218 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
219 {
220 struct e1000_mac_info *mac = &hw->mac;
221 u32 swsm = 0;
222 u32 swsm2 = 0;
223 bool force_clear_smbi = false;
224
225 /* Set media type and media-dependent function pointers */
226 switch (hw->adapter->pdev->device) {
227 case E1000_DEV_ID_82571EB_FIBER:
228 case E1000_DEV_ID_82572EI_FIBER:
229 case E1000_DEV_ID_82571EB_QUAD_FIBER:
230 hw->phy.media_type = e1000_media_type_fiber;
231 mac->ops.setup_physical_interface =
232 e1000_setup_fiber_serdes_link_82571;
233 mac->ops.check_for_link = e1000e_check_for_fiber_link;
234 mac->ops.get_link_up_info =
235 e1000e_get_speed_and_duplex_fiber_serdes;
236 break;
237 case E1000_DEV_ID_82571EB_SERDES:
238 case E1000_DEV_ID_82571EB_SERDES_DUAL:
239 case E1000_DEV_ID_82571EB_SERDES_QUAD:
240 case E1000_DEV_ID_82572EI_SERDES:
241 hw->phy.media_type = e1000_media_type_internal_serdes;
242 mac->ops.setup_physical_interface =
243 e1000_setup_fiber_serdes_link_82571;
244 mac->ops.check_for_link = e1000_check_for_serdes_link_82571;
245 mac->ops.get_link_up_info =
246 e1000e_get_speed_and_duplex_fiber_serdes;
247 break;
248 default:
249 hw->phy.media_type = e1000_media_type_copper;
250 mac->ops.setup_physical_interface =
251 e1000_setup_copper_link_82571;
252 mac->ops.check_for_link = e1000e_check_for_copper_link;
253 mac->ops.get_link_up_info = e1000e_get_speed_and_duplex_copper;
254 break;
255 }
256
257 /* Set mta register count */
258 mac->mta_reg_count = 128;
259 /* Set rar entry count */
260 mac->rar_entry_count = E1000_RAR_ENTRIES;
261 /* Adaptive IFS supported */
262 mac->adaptive_ifs = true;
263
264 /* MAC-specific function pointers */
265 switch (hw->mac.type) {
266 case e1000_82573:
267 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
268 mac->ops.check_mng_mode = e1000e_check_mng_mode_generic;
269 mac->ops.led_on = e1000e_led_on_generic;
270 mac->ops.blink_led = e1000e_blink_led_generic;
271
272 /* FWSM register */
273 mac->has_fwsm = true;
274 /* ARC supported; valid only if manageability features are
275 * enabled.
276 */
277 mac->arc_subsystem_valid = !!(er32(FWSM) &
278 E1000_FWSM_MODE_MASK);
279 break;
280 case e1000_82574:
281 case e1000_82583:
282 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
283 mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
284 mac->ops.led_on = e1000_led_on_82574;
285 break;
286 default:
287 mac->ops.check_mng_mode = e1000e_check_mng_mode_generic;
288 mac->ops.led_on = e1000e_led_on_generic;
289 mac->ops.blink_led = e1000e_blink_led_generic;
290
291 /* FWSM register */
292 mac->has_fwsm = true;
293 break;
294 }
295
296 /* Ensure that the inter-port SWSM.SMBI lock bit is clear before
297 * first NVM or PHY access. This should be done for single-port
298 * devices, and for one port only on dual-port devices so that
299 * for those devices we can still use the SMBI lock to synchronize
300 * inter-port accesses to the PHY & NVM.
301 */
302 switch (hw->mac.type) {
303 case e1000_82571:
304 case e1000_82572:
305 swsm2 = er32(SWSM2);
306
307 if (!(swsm2 & E1000_SWSM2_LOCK)) {
308 /* Only do this for the first interface on this card */
309 ew32(SWSM2, swsm2 | E1000_SWSM2_LOCK);
310 force_clear_smbi = true;
311 } else {
312 force_clear_smbi = false;
313 }
314 break;
315 default:
316 force_clear_smbi = true;
317 break;
318 }
319
320 if (force_clear_smbi) {
321 /* Make sure SWSM.SMBI is clear */
322 swsm = er32(SWSM);
323 if (swsm & E1000_SWSM_SMBI) {
324 /* This bit should not be set on a first interface, and
325 * indicates that the bootagent or EFI code has
326 * improperly left this bit enabled
327 */
328 e_dbg("Please update your 82571 Bootagent\n");
329 }
330 ew32(SWSM, swsm & ~E1000_SWSM_SMBI);
331 }
332
333 /* Initialize device specific counter of SMBI acquisition timeouts. */
334 hw->dev_spec.e82571.smb_counter = 0;
335
336 return 0;
337 }
338
339 static s32 e1000_get_variants_82571(struct e1000_adapter *adapter)
340 {
341 struct e1000_hw *hw = &adapter->hw;
342 static int global_quad_port_a; /* global port a indication */
343 struct pci_dev *pdev = adapter->pdev;
344 int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1;
345 s32 rc;
346
347 rc = e1000_init_mac_params_82571(hw);
348 if (rc)
349 return rc;
350
351 rc = e1000_init_nvm_params_82571(hw);
352 if (rc)
353 return rc;
354
355 rc = e1000_init_phy_params_82571(hw);
356 if (rc)
357 return rc;
358
359 /* tag quad port adapters first, it's used below */
360 switch (pdev->device) {
361 case E1000_DEV_ID_82571EB_QUAD_COPPER:
362 case E1000_DEV_ID_82571EB_QUAD_FIBER:
363 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
364 case E1000_DEV_ID_82571PT_QUAD_COPPER:
365 adapter->flags |= FLAG_IS_QUAD_PORT;
366 /* mark the first port */
367 if (global_quad_port_a == 0)
368 adapter->flags |= FLAG_IS_QUAD_PORT_A;
369 /* Reset for multiple quad port adapters */
370 global_quad_port_a++;
371 if (global_quad_port_a == 4)
372 global_quad_port_a = 0;
373 break;
374 default:
375 break;
376 }
377
378 switch (adapter->hw.mac.type) {
379 case e1000_82571:
380 /* these dual ports don't have WoL on port B at all */
381 if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) ||
382 (pdev->device == E1000_DEV_ID_82571EB_SERDES) ||
383 (pdev->device == E1000_DEV_ID_82571EB_COPPER)) &&
384 (is_port_b))
385 adapter->flags &= ~FLAG_HAS_WOL;
386 /* quad ports only support WoL on port A */
387 if (adapter->flags & FLAG_IS_QUAD_PORT &&
388 (!(adapter->flags & FLAG_IS_QUAD_PORT_A)))
389 adapter->flags &= ~FLAG_HAS_WOL;
390 /* Does not support WoL on any port */
391 if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD)
392 adapter->flags &= ~FLAG_HAS_WOL;
393 break;
394 case e1000_82573:
395 if (pdev->device == E1000_DEV_ID_82573L) {
396 adapter->flags |= FLAG_HAS_JUMBO_FRAMES;
397 adapter->max_hw_frame_size = DEFAULT_JUMBO;
398 }
399 break;
400 default:
401 break;
402 }
403
404 return 0;
405 }
406
407 /**
408 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
409 * @hw: pointer to the HW structure
410 *
411 * Reads the PHY registers and stores the PHY ID and possibly the PHY
412 * revision in the hardware structure.
413 **/
414 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
415 {
416 struct e1000_phy_info *phy = &hw->phy;
417 s32 ret_val;
418 u16 phy_id = 0;
419
420 switch (hw->mac.type) {
421 case e1000_82571:
422 case e1000_82572:
423 /* The 82571 firmware may still be configuring the PHY.
424 * In this case, we cannot access the PHY until the
425 * configuration is done. So we explicitly set the
426 * PHY ID.
427 */
428 phy->id = IGP01E1000_I_PHY_ID;
429 break;
430 case e1000_82573:
431 return e1000e_get_phy_id(hw);
432 break;
433 case e1000_82574:
434 case e1000_82583:
435 ret_val = e1e_rphy(hw, MII_PHYSID1, &phy_id);
436 if (ret_val)
437 return ret_val;
438
439 phy->id = (u32)(phy_id << 16);
440 usleep_range(20, 40);
441 ret_val = e1e_rphy(hw, MII_PHYSID2, &phy_id);
442 if (ret_val)
443 return ret_val;
444
445 phy->id |= (u32)(phy_id);
446 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
447 break;
448 default:
449 return -E1000_ERR_PHY;
450 break;
451 }
452
453 return 0;
454 }
455
456 /**
457 * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
458 * @hw: pointer to the HW structure
459 *
460 * Acquire the HW semaphore to access the PHY or NVM
461 **/
462 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
463 {
464 u32 swsm;
465 s32 sw_timeout = hw->nvm.word_size + 1;
466 s32 fw_timeout = hw->nvm.word_size + 1;
467 s32 i = 0;
468
469 /* If we have timedout 3 times on trying to acquire
470 * the inter-port SMBI semaphore, there is old code
471 * operating on the other port, and it is not
472 * releasing SMBI. Modify the number of times that
473 * we try for the semaphore to interwork with this
474 * older code.
475 */
476 if (hw->dev_spec.e82571.smb_counter > 2)
477 sw_timeout = 1;
478
479 /* Get the SW semaphore */
480 while (i < sw_timeout) {
481 swsm = er32(SWSM);
482 if (!(swsm & E1000_SWSM_SMBI))
483 break;
484
485 usleep_range(50, 100);
486 i++;
487 }
488
489 if (i == sw_timeout) {
490 e_dbg("Driver can't access device - SMBI bit is set.\n");
491 hw->dev_spec.e82571.smb_counter++;
492 }
493 /* Get the FW semaphore. */
494 for (i = 0; i < fw_timeout; i++) {
495 swsm = er32(SWSM);
496 ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
497
498 /* Semaphore acquired if bit latched */
499 if (er32(SWSM) & E1000_SWSM_SWESMBI)
500 break;
501
502 usleep_range(50, 100);
503 }
504
505 if (i == fw_timeout) {
506 /* Release semaphores */
507 e1000_put_hw_semaphore_82571(hw);
508 e_dbg("Driver can't access the NVM\n");
509 return -E1000_ERR_NVM;
510 }
511
512 return 0;
513 }
514
515 /**
516 * e1000_put_hw_semaphore_82571 - Release hardware semaphore
517 * @hw: pointer to the HW structure
518 *
519 * Release hardware semaphore used to access the PHY or NVM
520 **/
521 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
522 {
523 u32 swsm;
524
525 swsm = er32(SWSM);
526 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
527 ew32(SWSM, swsm);
528 }
529
530 /**
531 * e1000_get_hw_semaphore_82573 - Acquire hardware semaphore
532 * @hw: pointer to the HW structure
533 *
534 * Acquire the HW semaphore during reset.
535 *
536 **/
537 static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)
538 {
539 u32 extcnf_ctrl;
540 s32 i = 0;
541
542 extcnf_ctrl = er32(EXTCNF_CTRL);
543 do {
544 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
545 ew32(EXTCNF_CTRL, extcnf_ctrl);
546 extcnf_ctrl = er32(EXTCNF_CTRL);
547
548 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
549 break;
550
551 usleep_range(2000, 4000);
552 i++;
553 } while (i < MDIO_OWNERSHIP_TIMEOUT);
554
555 if (i == MDIO_OWNERSHIP_TIMEOUT) {
556 /* Release semaphores */
557 e1000_put_hw_semaphore_82573(hw);
558 e_dbg("Driver can't access the PHY\n");
559 return -E1000_ERR_PHY;
560 }
561
562 return 0;
563 }
564
565 /**
566 * e1000_put_hw_semaphore_82573 - Release hardware semaphore
567 * @hw: pointer to the HW structure
568 *
569 * Release hardware semaphore used during reset.
570 *
571 **/
572 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)
573 {
574 u32 extcnf_ctrl;
575
576 extcnf_ctrl = er32(EXTCNF_CTRL);
577 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
578 ew32(EXTCNF_CTRL, extcnf_ctrl);
579 }
580
581 static DEFINE_MUTEX(swflag_mutex);
582
583 /**
584 * e1000_get_hw_semaphore_82574 - Acquire hardware semaphore
585 * @hw: pointer to the HW structure
586 *
587 * Acquire the HW semaphore to access the PHY or NVM.
588 *
589 **/
590 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
591 {
592 s32 ret_val;
593
594 mutex_lock(&swflag_mutex);
595 ret_val = e1000_get_hw_semaphore_82573(hw);
596 if (ret_val)
597 mutex_unlock(&swflag_mutex);
598 return ret_val;
599 }
600
601 /**
602 * e1000_put_hw_semaphore_82574 - Release hardware semaphore
603 * @hw: pointer to the HW structure
604 *
605 * Release hardware semaphore used to access the PHY or NVM
606 *
607 **/
608 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
609 {
610 e1000_put_hw_semaphore_82573(hw);
611 mutex_unlock(&swflag_mutex);
612 }
613
614 /**
615 * e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state
616 * @hw: pointer to the HW structure
617 * @active: true to enable LPLU, false to disable
618 *
619 * Sets the LPLU D0 state according to the active flag.
620 * LPLU will not be activated unless the
621 * device autonegotiation advertisement meets standards of
622 * either 10 or 10/100 or 10/100/1000 at all duplexes.
623 * This is a function pointer entry point only called by
624 * PHY setup routines.
625 **/
626 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active)
627 {
628 u32 data = er32(POEMB);
629
630 if (active)
631 data |= E1000_PHY_CTRL_D0A_LPLU;
632 else
633 data &= ~E1000_PHY_CTRL_D0A_LPLU;
634
635 ew32(POEMB, data);
636 return 0;
637 }
638
639 /**
640 * e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3
641 * @hw: pointer to the HW structure
642 * @active: boolean used to enable/disable lplu
643 *
644 * The low power link up (lplu) state is set to the power management level D3
645 * when active is true, else clear lplu for D3. LPLU
646 * is used during Dx states where the power conservation is most important.
647 * During driver activity, SmartSpeed should be enabled so performance is
648 * maintained.
649 **/
650 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active)
651 {
652 u32 data = er32(POEMB);
653
654 if (!active) {
655 data &= ~E1000_PHY_CTRL_NOND0A_LPLU;
656 } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
657 (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||
658 (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {
659 data |= E1000_PHY_CTRL_NOND0A_LPLU;
660 }
661
662 ew32(POEMB, data);
663 return 0;
664 }
665
666 /**
667 * e1000_acquire_nvm_82571 - Request for access to the EEPROM
668 * @hw: pointer to the HW structure
669 *
670 * To gain access to the EEPROM, first we must obtain a hardware semaphore.
671 * Then for non-82573 hardware, set the EEPROM access request bit and wait
672 * for EEPROM access grant bit. If the access grant bit is not set, release
673 * hardware semaphore.
674 **/
675 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
676 {
677 s32 ret_val;
678
679 ret_val = e1000_get_hw_semaphore_82571(hw);
680 if (ret_val)
681 return ret_val;
682
683 switch (hw->mac.type) {
684 case e1000_82573:
685 break;
686 default:
687 ret_val = e1000e_acquire_nvm(hw);
688 break;
689 }
690
691 if (ret_val)
692 e1000_put_hw_semaphore_82571(hw);
693
694 return ret_val;
695 }
696
697 /**
698 * e1000_release_nvm_82571 - Release exclusive access to EEPROM
699 * @hw: pointer to the HW structure
700 *
701 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
702 **/
703 static void e1000_release_nvm_82571(struct e1000_hw *hw)
704 {
705 e1000e_release_nvm(hw);
706 e1000_put_hw_semaphore_82571(hw);
707 }
708
709 /**
710 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
711 * @hw: pointer to the HW structure
712 * @offset: offset within the EEPROM to be written to
713 * @words: number of words to write
714 * @data: 16 bit word(s) to be written to the EEPROM
715 *
716 * For non-82573 silicon, write data to EEPROM at offset using SPI interface.
717 *
718 * If e1000e_update_nvm_checksum is not called after this function, the
719 * EEPROM will most likely contain an invalid checksum.
720 **/
721 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
722 u16 *data)
723 {
724 s32 ret_val;
725
726 switch (hw->mac.type) {
727 case e1000_82573:
728 case e1000_82574:
729 case e1000_82583:
730 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
731 break;
732 case e1000_82571:
733 case e1000_82572:
734 ret_val = e1000e_write_nvm_spi(hw, offset, words, data);
735 break;
736 default:
737 ret_val = -E1000_ERR_NVM;
738 break;
739 }
740
741 return ret_val;
742 }
743
744 /**
745 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum
746 * @hw: pointer to the HW structure
747 *
748 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
749 * up to the checksum. Then calculates the EEPROM checksum and writes the
750 * value to the EEPROM.
751 **/
752 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
753 {
754 u32 eecd;
755 s32 ret_val;
756 u16 i;
757
758 ret_val = e1000e_update_nvm_checksum_generic(hw);
759 if (ret_val)
760 return ret_val;
761
762 /* If our nvm is an EEPROM, then we're done
763 * otherwise, commit the checksum to the flash NVM.
764 */
765 if (hw->nvm.type != e1000_nvm_flash_hw)
766 return 0;
767
768 /* Check for pending operations. */
769 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
770 usleep_range(1000, 2000);
771 if (!(er32(EECD) & E1000_EECD_FLUPD))
772 break;
773 }
774
775 if (i == E1000_FLASH_UPDATES)
776 return -E1000_ERR_NVM;
777
778 /* Reset the firmware if using STM opcode. */
779 if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {
780 /* The enabling of and the actual reset must be done
781 * in two write cycles.
782 */
783 ew32(HICR, E1000_HICR_FW_RESET_ENABLE);
784 e1e_flush();
785 ew32(HICR, E1000_HICR_FW_RESET);
786 }
787
788 /* Commit the write to flash */
789 eecd = er32(EECD) | E1000_EECD_FLUPD;
790 ew32(EECD, eecd);
791
792 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
793 usleep_range(1000, 2000);
794 if (!(er32(EECD) & E1000_EECD_FLUPD))
795 break;
796 }
797
798 if (i == E1000_FLASH_UPDATES)
799 return -E1000_ERR_NVM;
800
801 return 0;
802 }
803
804 /**
805 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
806 * @hw: pointer to the HW structure
807 *
808 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
809 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
810 **/
811 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
812 {
813 if (hw->nvm.type == e1000_nvm_flash_hw)
814 e1000_fix_nvm_checksum_82571(hw);
815
816 return e1000e_validate_nvm_checksum_generic(hw);
817 }
818
819 /**
820 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
821 * @hw: pointer to the HW structure
822 * @offset: offset within the EEPROM to be written to
823 * @words: number of words to write
824 * @data: 16 bit word(s) to be written to the EEPROM
825 *
826 * After checking for invalid values, poll the EEPROM to ensure the previous
827 * command has completed before trying to write the next word. After write
828 * poll for completion.
829 *
830 * If e1000e_update_nvm_checksum is not called after this function, the
831 * EEPROM will most likely contain an invalid checksum.
832 **/
833 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
834 u16 words, u16 *data)
835 {
836 struct e1000_nvm_info *nvm = &hw->nvm;
837 u32 i, eewr = 0;
838 s32 ret_val = 0;
839
840 /* A check for invalid values: offset too large, too many words,
841 * and not enough words.
842 */
843 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
844 (words == 0)) {
845 e_dbg("nvm parameter(s) out of bounds\n");
846 return -E1000_ERR_NVM;
847 }
848
849 for (i = 0; i < words; i++) {
850 eewr = ((data[i] << E1000_NVM_RW_REG_DATA) |
851 ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) |
852 E1000_NVM_RW_REG_START);
853
854 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
855 if (ret_val)
856 break;
857
858 ew32(EEWR, eewr);
859
860 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
861 if (ret_val)
862 break;
863 }
864
865 return ret_val;
866 }
867
868 /**
869 * e1000_get_cfg_done_82571 - Poll for configuration done
870 * @hw: pointer to the HW structure
871 *
872 * Reads the management control register for the config done bit to be set.
873 **/
874 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
875 {
876 s32 timeout = PHY_CFG_TIMEOUT;
877
878 while (timeout) {
879 if (er32(EEMNGCTL) & E1000_NVM_CFG_DONE_PORT_0)
880 break;
881 usleep_range(1000, 2000);
882 timeout--;
883 }
884 if (!timeout) {
885 e_dbg("MNG configuration cycle has not completed.\n");
886 return -E1000_ERR_RESET;
887 }
888
889 return 0;
890 }
891
892 /**
893 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
894 * @hw: pointer to the HW structure
895 * @active: true to enable LPLU, false to disable
896 *
897 * Sets the LPLU D0 state according to the active flag. When activating LPLU
898 * this function also disables smart speed and vice versa. LPLU will not be
899 * activated unless the device autonegotiation advertisement meets standards
900 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function
901 * pointer entry point only called by PHY setup routines.
902 **/
903 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
904 {
905 struct e1000_phy_info *phy = &hw->phy;
906 s32 ret_val;
907 u16 data;
908
909 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
910 if (ret_val)
911 return ret_val;
912
913 if (active) {
914 data |= IGP02E1000_PM_D0_LPLU;
915 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
916 if (ret_val)
917 return ret_val;
918
919 /* When LPLU is enabled, we should disable SmartSpeed */
920 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
921 if (ret_val)
922 return ret_val;
923 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
924 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
925 if (ret_val)
926 return ret_val;
927 } else {
928 data &= ~IGP02E1000_PM_D0_LPLU;
929 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
930 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
931 * during Dx states where the power conservation is most
932 * important. During driver activity we should enable
933 * SmartSpeed, so performance is maintained.
934 */
935 if (phy->smart_speed == e1000_smart_speed_on) {
936 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
937 &data);
938 if (ret_val)
939 return ret_val;
940
941 data |= IGP01E1000_PSCFR_SMART_SPEED;
942 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
943 data);
944 if (ret_val)
945 return ret_val;
946 } else if (phy->smart_speed == e1000_smart_speed_off) {
947 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
948 &data);
949 if (ret_val)
950 return ret_val;
951
952 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
953 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
954 data);
955 if (ret_val)
956 return ret_val;
957 }
958 }
959
960 return 0;
961 }
962
963 /**
964 * e1000_reset_hw_82571 - Reset hardware
965 * @hw: pointer to the HW structure
966 *
967 * This resets the hardware into a known state.
968 **/
969 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
970 {
971 u32 ctrl, ctrl_ext, eecd, tctl;
972 s32 ret_val;
973
974 /* Prevent the PCI-E bus from sticking if there is no TLP connection
975 * on the last TLP read/write transaction when MAC is reset.
976 */
977 ret_val = e1000e_disable_pcie_master(hw);
978 if (ret_val)
979 e_dbg("PCI-E Master disable polling has failed.\n");
980
981 e_dbg("Masking off all interrupts\n");
982 ew32(IMC, 0xffffffff);
983
984 ew32(RCTL, 0);
985 tctl = er32(TCTL);
986 tctl &= ~E1000_TCTL_EN;
987 ew32(TCTL, tctl);
988 e1e_flush();
989
990 usleep_range(10000, 20000);
991
992 /* Must acquire the MDIO ownership before MAC reset.
993 * Ownership defaults to firmware after a reset.
994 */
995 switch (hw->mac.type) {
996 case e1000_82573:
997 ret_val = e1000_get_hw_semaphore_82573(hw);
998 break;
999 case e1000_82574:
1000 case e1000_82583:
1001 ret_val = e1000_get_hw_semaphore_82574(hw);
1002 break;
1003 default:
1004 break;
1005 }
1006
1007 ctrl = er32(CTRL);
1008
1009 e_dbg("Issuing a global reset to MAC\n");
1010 ew32(CTRL, ctrl | E1000_CTRL_RST);
1011
1012 /* Must release MDIO ownership and mutex after MAC reset. */
1013 switch (hw->mac.type) {
1014 case e1000_82574:
1015 case e1000_82583:
1016 /* Release mutex only if the hw semaphore is acquired */
1017 if (!ret_val)
1018 e1000_put_hw_semaphore_82574(hw);
1019 break;
1020 default:
1021 break;
1022 }
1023
1024 if (hw->nvm.type == e1000_nvm_flash_hw) {
1025 usleep_range(10, 20);
1026 ctrl_ext = er32(CTRL_EXT);
1027 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1028 ew32(CTRL_EXT, ctrl_ext);
1029 e1e_flush();
1030 }
1031
1032 ret_val = e1000e_get_auto_rd_done(hw);
1033 if (ret_val)
1034 /* We don't want to continue accessing MAC registers. */
1035 return ret_val;
1036
1037 /* Phy configuration from NVM just starts after EECD_AUTO_RD is set.
1038 * Need to wait for Phy configuration completion before accessing
1039 * NVM and Phy.
1040 */
1041
1042 switch (hw->mac.type) {
1043 case e1000_82571:
1044 case e1000_82572:
1045 /* REQ and GNT bits need to be cleared when using AUTO_RD
1046 * to access the EEPROM.
1047 */
1048 eecd = er32(EECD);
1049 eecd &= ~(E1000_EECD_REQ | E1000_EECD_GNT);
1050 ew32(EECD, eecd);
1051 break;
1052 case e1000_82573:
1053 case e1000_82574:
1054 case e1000_82583:
1055 msleep(25);
1056 break;
1057 default:
1058 break;
1059 }
1060
1061 /* Clear any pending interrupt events. */
1062 ew32(IMC, 0xffffffff);
1063 er32(ICR);
1064
1065 if (hw->mac.type == e1000_82571) {
1066 /* Install any alternate MAC address into RAR0 */
1067 ret_val = e1000_check_alt_mac_addr_generic(hw);
1068 if (ret_val)
1069 return ret_val;
1070
1071 e1000e_set_laa_state_82571(hw, true);
1072 }
1073
1074 /* Reinitialize the 82571 serdes link state machine */
1075 if (hw->phy.media_type == e1000_media_type_internal_serdes)
1076 hw->mac.serdes_link_state = e1000_serdes_link_down;
1077
1078 return 0;
1079 }
1080
1081 /**
1082 * e1000_init_hw_82571 - Initialize hardware
1083 * @hw: pointer to the HW structure
1084 *
1085 * This inits the hardware readying it for operation.
1086 **/
1087 static s32 e1000_init_hw_82571(struct e1000_hw *hw)
1088 {
1089 struct e1000_mac_info *mac = &hw->mac;
1090 u32 reg_data;
1091 s32 ret_val;
1092 u16 i, rar_count = mac->rar_entry_count;
1093
1094 e1000_initialize_hw_bits_82571(hw);
1095
1096 /* Initialize identification LED */
1097 ret_val = mac->ops.id_led_init(hw);
1098 /* An error is not fatal and we should not stop init due to this */
1099 if (ret_val)
1100 e_dbg("Error initializing identification LED\n");
1101
1102 /* Disabling VLAN filtering */
1103 e_dbg("Initializing the IEEE VLAN\n");
1104 mac->ops.clear_vfta(hw);
1105
1106 /* Setup the receive address.
1107 * If, however, a locally administered address was assigned to the
1108 * 82571, we must reserve a RAR for it to work around an issue where
1109 * resetting one port will reload the MAC on the other port.
1110 */
1111 if (e1000e_get_laa_state_82571(hw))
1112 rar_count--;
1113 e1000e_init_rx_addrs(hw, rar_count);
1114
1115 /* Zero out the Multicast HASH table */
1116 e_dbg("Zeroing the MTA\n");
1117 for (i = 0; i < mac->mta_reg_count; i++)
1118 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1119
1120 /* Setup link and flow control */
1121 ret_val = mac->ops.setup_link(hw);
1122
1123 /* Set the transmit descriptor write-back policy */
1124 reg_data = er32(TXDCTL(0));
1125 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
1126 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
1127 ew32(TXDCTL(0), reg_data);
1128
1129 /* ...for both queues. */
1130 switch (mac->type) {
1131 case e1000_82573:
1132 e1000e_enable_tx_pkt_filtering(hw);
1133 /* fall through */
1134 case e1000_82574:
1135 case e1000_82583:
1136 reg_data = er32(GCR);
1137 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1138 ew32(GCR, reg_data);
1139 break;
1140 default:
1141 reg_data = er32(TXDCTL(1));
1142 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
1143 E1000_TXDCTL_FULL_TX_DESC_WB |
1144 E1000_TXDCTL_COUNT_DESC);
1145 ew32(TXDCTL(1), reg_data);
1146 break;
1147 }
1148
1149 /* Clear all of the statistics registers (clear on read). It is
1150 * important that we do this after we have tried to establish link
1151 * because the symbol error count will increment wildly if there
1152 * is no link.
1153 */
1154 e1000_clear_hw_cntrs_82571(hw);
1155
1156 return ret_val;
1157 }
1158
1159 /**
1160 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1161 * @hw: pointer to the HW structure
1162 *
1163 * Initializes required hardware-dependent bits needed for normal operation.
1164 **/
1165 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1166 {
1167 u32 reg;
1168
1169 /* Transmit Descriptor Control 0 */
1170 reg = er32(TXDCTL(0));
1171 reg |= (1 << 22);
1172 ew32(TXDCTL(0), reg);
1173
1174 /* Transmit Descriptor Control 1 */
1175 reg = er32(TXDCTL(1));
1176 reg |= (1 << 22);
1177 ew32(TXDCTL(1), reg);
1178
1179 /* Transmit Arbitration Control 0 */
1180 reg = er32(TARC(0));
1181 reg &= ~(0xF << 27); /* 30:27 */
1182 switch (hw->mac.type) {
1183 case e1000_82571:
1184 case e1000_82572:
1185 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1186 break;
1187 case e1000_82574:
1188 case e1000_82583:
1189 reg |= (1 << 26);
1190 break;
1191 default:
1192 break;
1193 }
1194 ew32(TARC(0), reg);
1195
1196 /* Transmit Arbitration Control 1 */
1197 reg = er32(TARC(1));
1198 switch (hw->mac.type) {
1199 case e1000_82571:
1200 case e1000_82572:
1201 reg &= ~((1 << 29) | (1 << 30));
1202 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1203 if (er32(TCTL) & E1000_TCTL_MULR)
1204 reg &= ~(1 << 28);
1205 else
1206 reg |= (1 << 28);
1207 ew32(TARC(1), reg);
1208 break;
1209 default:
1210 break;
1211 }
1212
1213 /* Device Control */
1214 switch (hw->mac.type) {
1215 case e1000_82573:
1216 case e1000_82574:
1217 case e1000_82583:
1218 reg = er32(CTRL);
1219 reg &= ~(1 << 29);
1220 ew32(CTRL, reg);
1221 break;
1222 default:
1223 break;
1224 }
1225
1226 /* Extended Device Control */
1227 switch (hw->mac.type) {
1228 case e1000_82573:
1229 case e1000_82574:
1230 case e1000_82583:
1231 reg = er32(CTRL_EXT);
1232 reg &= ~(1 << 23);
1233 reg |= (1 << 22);
1234 ew32(CTRL_EXT, reg);
1235 break;
1236 default:
1237 break;
1238 }
1239
1240 if (hw->mac.type == e1000_82571) {
1241 reg = er32(PBA_ECC);
1242 reg |= E1000_PBA_ECC_CORR_EN;
1243 ew32(PBA_ECC, reg);
1244 }
1245
1246 /* Workaround for hardware errata.
1247 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1248 */
1249 if ((hw->mac.type == e1000_82571) || (hw->mac.type == e1000_82572)) {
1250 reg = er32(CTRL_EXT);
1251 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1252 ew32(CTRL_EXT, reg);
1253 }
1254
1255 /* Disable IPv6 extension header parsing because some malformed
1256 * IPv6 headers can hang the Rx.
1257 */
1258 if (hw->mac.type <= e1000_82573) {
1259 reg = er32(RFCTL);
1260 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
1261 ew32(RFCTL, reg);
1262 }
1263
1264 /* PCI-Ex Control Registers */
1265 switch (hw->mac.type) {
1266 case e1000_82574:
1267 case e1000_82583:
1268 reg = er32(GCR);
1269 reg |= (1 << 22);
1270 ew32(GCR, reg);
1271
1272 /* Workaround for hardware errata.
1273 * apply workaround for hardware errata documented in errata
1274 * docs Fixes issue where some error prone or unreliable PCIe
1275 * completions are occurring, particularly with ASPM enabled.
1276 * Without fix, issue can cause Tx timeouts.
1277 */
1278 reg = er32(GCR2);
1279 reg |= 1;
1280 ew32(GCR2, reg);
1281 break;
1282 default:
1283 break;
1284 }
1285 }
1286
1287 /**
1288 * e1000_clear_vfta_82571 - Clear VLAN filter table
1289 * @hw: pointer to the HW structure
1290 *
1291 * Clears the register array which contains the VLAN filter table by
1292 * setting all the values to 0.
1293 **/
1294 static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1295 {
1296 u32 offset;
1297 u32 vfta_value = 0;
1298 u32 vfta_offset = 0;
1299 u32 vfta_bit_in_reg = 0;
1300
1301 switch (hw->mac.type) {
1302 case e1000_82573:
1303 case e1000_82574:
1304 case e1000_82583:
1305 if (hw->mng_cookie.vlan_id != 0) {
1306 /* The VFTA is a 4096b bit-field, each identifying
1307 * a single VLAN ID. The following operations
1308 * determine which 32b entry (i.e. offset) into the
1309 * array we want to set the VLAN ID (i.e. bit) of
1310 * the manageability unit.
1311 */
1312 vfta_offset = (hw->mng_cookie.vlan_id >>
1313 E1000_VFTA_ENTRY_SHIFT) &
1314 E1000_VFTA_ENTRY_MASK;
1315 vfta_bit_in_reg =
1316 1 << (hw->mng_cookie.vlan_id &
1317 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1318 }
1319 break;
1320 default:
1321 break;
1322 }
1323 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1324 /* If the offset we want to clear is the same offset of the
1325 * manageability VLAN ID, then clear all bits except that of
1326 * the manageability unit.
1327 */
1328 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1329 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1330 e1e_flush();
1331 }
1332 }
1333
1334 /**
1335 * e1000_check_mng_mode_82574 - Check manageability is enabled
1336 * @hw: pointer to the HW structure
1337 *
1338 * Reads the NVM Initialization Control Word 2 and returns true
1339 * (>0) if any manageability is enabled, else false (0).
1340 **/
1341 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1342 {
1343 u16 data;
1344
1345 e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1346 return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1347 }
1348
1349 /**
1350 * e1000_led_on_82574 - Turn LED on
1351 * @hw: pointer to the HW structure
1352 *
1353 * Turn LED on.
1354 **/
1355 static s32 e1000_led_on_82574(struct e1000_hw *hw)
1356 {
1357 u32 ctrl;
1358 u32 i;
1359
1360 ctrl = hw->mac.ledctl_mode2;
1361 if (!(E1000_STATUS_LU & er32(STATUS))) {
1362 /* If no link, then turn LED on by setting the invert bit
1363 * for each LED that's "on" (0x0E) in ledctl_mode2.
1364 */
1365 for (i = 0; i < 4; i++)
1366 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1367 E1000_LEDCTL_MODE_LED_ON)
1368 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1369 }
1370 ew32(LEDCTL, ctrl);
1371
1372 return 0;
1373 }
1374
1375 /**
1376 * e1000_check_phy_82574 - check 82574 phy hung state
1377 * @hw: pointer to the HW structure
1378 *
1379 * Returns whether phy is hung or not
1380 **/
1381 bool e1000_check_phy_82574(struct e1000_hw *hw)
1382 {
1383 u16 status_1kbt = 0;
1384 u16 receive_errors = 0;
1385 s32 ret_val;
1386
1387 /* Read PHY Receive Error counter first, if its is max - all F's then
1388 * read the Base1000T status register If both are max then PHY is hung.
1389 */
1390 ret_val = e1e_rphy(hw, E1000_RECEIVE_ERROR_COUNTER, &receive_errors);
1391 if (ret_val)
1392 return false;
1393 if (receive_errors == E1000_RECEIVE_ERROR_MAX) {
1394 ret_val = e1e_rphy(hw, E1000_BASE1000T_STATUS, &status_1kbt);
1395 if (ret_val)
1396 return false;
1397 if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
1398 E1000_IDLE_ERROR_COUNT_MASK)
1399 return true;
1400 }
1401
1402 return false;
1403 }
1404
1405 /**
1406 * e1000_setup_link_82571 - Setup flow control and link settings
1407 * @hw: pointer to the HW structure
1408 *
1409 * Determines which flow control settings to use, then configures flow
1410 * control. Calls the appropriate media-specific link configuration
1411 * function. Assuming the adapter has a valid link partner, a valid link
1412 * should be established. Assumes the hardware has previously been reset
1413 * and the transmitter and receiver are not enabled.
1414 **/
1415 static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1416 {
1417 /* 82573 does not have a word in the NVM to determine
1418 * the default flow control setting, so we explicitly
1419 * set it to full.
1420 */
1421 switch (hw->mac.type) {
1422 case e1000_82573:
1423 case e1000_82574:
1424 case e1000_82583:
1425 if (hw->fc.requested_mode == e1000_fc_default)
1426 hw->fc.requested_mode = e1000_fc_full;
1427 break;
1428 default:
1429 break;
1430 }
1431
1432 return e1000e_setup_link_generic(hw);
1433 }
1434
1435 /**
1436 * e1000_setup_copper_link_82571 - Configure copper link settings
1437 * @hw: pointer to the HW structure
1438 *
1439 * Configures the link for auto-neg or forced speed and duplex. Then we check
1440 * for link, once link is established calls to configure collision distance
1441 * and flow control are called.
1442 **/
1443 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1444 {
1445 u32 ctrl;
1446 s32 ret_val;
1447
1448 ctrl = er32(CTRL);
1449 ctrl |= E1000_CTRL_SLU;
1450 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1451 ew32(CTRL, ctrl);
1452
1453 switch (hw->phy.type) {
1454 case e1000_phy_m88:
1455 case e1000_phy_bm:
1456 ret_val = e1000e_copper_link_setup_m88(hw);
1457 break;
1458 case e1000_phy_igp_2:
1459 ret_val = e1000e_copper_link_setup_igp(hw);
1460 break;
1461 default:
1462 return -E1000_ERR_PHY;
1463 break;
1464 }
1465
1466 if (ret_val)
1467 return ret_val;
1468
1469 return e1000e_setup_copper_link(hw);
1470 }
1471
1472 /**
1473 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1474 * @hw: pointer to the HW structure
1475 *
1476 * Configures collision distance and flow control for fiber and serdes links.
1477 * Upon successful setup, poll for link.
1478 **/
1479 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1480 {
1481 switch (hw->mac.type) {
1482 case e1000_82571:
1483 case e1000_82572:
1484 /* If SerDes loopback mode is entered, there is no form
1485 * of reset to take the adapter out of that mode. So we
1486 * have to explicitly take the adapter out of loopback
1487 * mode. This prevents drivers from twiddling their thumbs
1488 * if another tool failed to take it out of loopback mode.
1489 */
1490 ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1491 break;
1492 default:
1493 break;
1494 }
1495
1496 return e1000e_setup_fiber_serdes_link(hw);
1497 }
1498
1499 /**
1500 * e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1501 * @hw: pointer to the HW structure
1502 *
1503 * Reports the link state as up or down.
1504 *
1505 * If autonegotiation is supported by the link partner, the link state is
1506 * determined by the result of autonegotiation. This is the most likely case.
1507 * If autonegotiation is not supported by the link partner, and the link
1508 * has a valid signal, force the link up.
1509 *
1510 * The link state is represented internally here by 4 states:
1511 *
1512 * 1) down
1513 * 2) autoneg_progress
1514 * 3) autoneg_complete (the link successfully autonegotiated)
1515 * 4) forced_up (the link has been forced up, it did not autonegotiate)
1516 *
1517 **/
1518 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1519 {
1520 struct e1000_mac_info *mac = &hw->mac;
1521 u32 rxcw;
1522 u32 ctrl;
1523 u32 status;
1524 u32 txcw;
1525 u32 i;
1526 s32 ret_val = 0;
1527
1528 ctrl = er32(CTRL);
1529 status = er32(STATUS);
1530 er32(RXCW);
1531 /* SYNCH bit and IV bit are sticky */
1532 usleep_range(10, 20);
1533 rxcw = er32(RXCW);
1534
1535 if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1536 /* Receiver is synchronized with no invalid bits. */
1537 switch (mac->serdes_link_state) {
1538 case e1000_serdes_link_autoneg_complete:
1539 if (!(status & E1000_STATUS_LU)) {
1540 /* We have lost link, retry autoneg before
1541 * reporting link failure
1542 */
1543 mac->serdes_link_state =
1544 e1000_serdes_link_autoneg_progress;
1545 mac->serdes_has_link = false;
1546 e_dbg("AN_UP -> AN_PROG\n");
1547 } else {
1548 mac->serdes_has_link = true;
1549 }
1550 break;
1551
1552 case e1000_serdes_link_forced_up:
1553 /* If we are receiving /C/ ordered sets, re-enable
1554 * auto-negotiation in the TXCW register and disable
1555 * forced link in the Device Control register in an
1556 * attempt to auto-negotiate with our link partner.
1557 */
1558 if (rxcw & E1000_RXCW_C) {
1559 /* Enable autoneg, and unforce link up */
1560 ew32(TXCW, mac->txcw);
1561 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
1562 mac->serdes_link_state =
1563 e1000_serdes_link_autoneg_progress;
1564 mac->serdes_has_link = false;
1565 e_dbg("FORCED_UP -> AN_PROG\n");
1566 } else {
1567 mac->serdes_has_link = true;
1568 }
1569 break;
1570
1571 case e1000_serdes_link_autoneg_progress:
1572 if (rxcw & E1000_RXCW_C) {
1573 /* We received /C/ ordered sets, meaning the
1574 * link partner has autonegotiated, and we can
1575 * trust the Link Up (LU) status bit.
1576 */
1577 if (status & E1000_STATUS_LU) {
1578 mac->serdes_link_state =
1579 e1000_serdes_link_autoneg_complete;
1580 e_dbg("AN_PROG -> AN_UP\n");
1581 mac->serdes_has_link = true;
1582 } else {
1583 /* Autoneg completed, but failed. */
1584 mac->serdes_link_state =
1585 e1000_serdes_link_down;
1586 e_dbg("AN_PROG -> DOWN\n");
1587 }
1588 } else {
1589 /* The link partner did not autoneg.
1590 * Force link up and full duplex, and change
1591 * state to forced.
1592 */
1593 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
1594 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1595 ew32(CTRL, ctrl);
1596
1597 /* Configure Flow Control after link up. */
1598 ret_val = e1000e_config_fc_after_link_up(hw);
1599 if (ret_val) {
1600 e_dbg("Error config flow control\n");
1601 break;
1602 }
1603 mac->serdes_link_state =
1604 e1000_serdes_link_forced_up;
1605 mac->serdes_has_link = true;
1606 e_dbg("AN_PROG -> FORCED_UP\n");
1607 }
1608 break;
1609
1610 case e1000_serdes_link_down:
1611 default:
1612 /* The link was down but the receiver has now gained
1613 * valid sync, so lets see if we can bring the link
1614 * up.
1615 */
1616 ew32(TXCW, mac->txcw);
1617 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
1618 mac->serdes_link_state =
1619 e1000_serdes_link_autoneg_progress;
1620 mac->serdes_has_link = false;
1621 e_dbg("DOWN -> AN_PROG\n");
1622 break;
1623 }
1624 } else {
1625 if (!(rxcw & E1000_RXCW_SYNCH)) {
1626 mac->serdes_has_link = false;
1627 mac->serdes_link_state = e1000_serdes_link_down;
1628 e_dbg("ANYSTATE -> DOWN\n");
1629 } else {
1630 /* Check several times, if SYNCH bit and CONFIG
1631 * bit both are consistently 1 then simply ignore
1632 * the IV bit and restart Autoneg
1633 */
1634 for (i = 0; i < AN_RETRY_COUNT; i++) {
1635 usleep_range(10, 20);
1636 rxcw = er32(RXCW);
1637 if ((rxcw & E1000_RXCW_SYNCH) &&
1638 (rxcw & E1000_RXCW_C))
1639 continue;
1640
1641 if (rxcw & E1000_RXCW_IV) {
1642 mac->serdes_has_link = false;
1643 mac->serdes_link_state =
1644 e1000_serdes_link_down;
1645 e_dbg("ANYSTATE -> DOWN\n");
1646 break;
1647 }
1648 }
1649
1650 if (i == AN_RETRY_COUNT) {
1651 txcw = er32(TXCW);
1652 txcw |= E1000_TXCW_ANE;
1653 ew32(TXCW, txcw);
1654 mac->serdes_link_state =
1655 e1000_serdes_link_autoneg_progress;
1656 mac->serdes_has_link = false;
1657 e_dbg("ANYSTATE -> AN_PROG\n");
1658 }
1659 }
1660 }
1661
1662 return ret_val;
1663 }
1664
1665 /**
1666 * e1000_valid_led_default_82571 - Verify a valid default LED config
1667 * @hw: pointer to the HW structure
1668 * @data: pointer to the NVM (EEPROM)
1669 *
1670 * Read the EEPROM for the current default LED configuration. If the
1671 * LED configuration is not valid, set to a valid LED configuration.
1672 **/
1673 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1674 {
1675 s32 ret_val;
1676
1677 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1678 if (ret_val) {
1679 e_dbg("NVM Read Error\n");
1680 return ret_val;
1681 }
1682
1683 switch (hw->mac.type) {
1684 case e1000_82573:
1685 case e1000_82574:
1686 case e1000_82583:
1687 if (*data == ID_LED_RESERVED_F746)
1688 *data = ID_LED_DEFAULT_82573;
1689 break;
1690 default:
1691 if (*data == ID_LED_RESERVED_0000 ||
1692 *data == ID_LED_RESERVED_FFFF)
1693 *data = ID_LED_DEFAULT;
1694 break;
1695 }
1696
1697 return 0;
1698 }
1699
1700 /**
1701 * e1000e_get_laa_state_82571 - Get locally administered address state
1702 * @hw: pointer to the HW structure
1703 *
1704 * Retrieve and return the current locally administered address state.
1705 **/
1706 bool e1000e_get_laa_state_82571(struct e1000_hw *hw)
1707 {
1708 if (hw->mac.type != e1000_82571)
1709 return false;
1710
1711 return hw->dev_spec.e82571.laa_is_present;
1712 }
1713
1714 /**
1715 * e1000e_set_laa_state_82571 - Set locally administered address state
1716 * @hw: pointer to the HW structure
1717 * @state: enable/disable locally administered address
1718 *
1719 * Enable/Disable the current locally administered address state.
1720 **/
1721 void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state)
1722 {
1723 if (hw->mac.type != e1000_82571)
1724 return;
1725
1726 hw->dev_spec.e82571.laa_is_present = state;
1727
1728 /* If workaround is activated... */
1729 if (state)
1730 /* Hold a copy of the LAA in RAR[14] This is done so that
1731 * between the time RAR[0] gets clobbered and the time it
1732 * gets fixed, the actual LAA is in one of the RARs and no
1733 * incoming packets directed to this port are dropped.
1734 * Eventually the LAA will be in RAR[0] and RAR[14].
1735 */
1736 hw->mac.ops.rar_set(hw, hw->mac.addr,
1737 hw->mac.rar_entry_count - 1);
1738 }
1739
1740 /**
1741 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1742 * @hw: pointer to the HW structure
1743 *
1744 * Verifies that the EEPROM has completed the update. After updating the
1745 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If
1746 * the checksum fix is not implemented, we need to set the bit and update
1747 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect,
1748 * we need to return bad checksum.
1749 **/
1750 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1751 {
1752 struct e1000_nvm_info *nvm = &hw->nvm;
1753 s32 ret_val;
1754 u16 data;
1755
1756 if (nvm->type != e1000_nvm_flash_hw)
1757 return 0;
1758
1759 /* Check bit 4 of word 10h. If it is 0, firmware is done updating
1760 * 10h-12h. Checksum may need to be fixed.
1761 */
1762 ret_val = e1000_read_nvm(hw, 0x10, 1, &data);
1763 if (ret_val)
1764 return ret_val;
1765
1766 if (!(data & 0x10)) {
1767 /* Read 0x23 and check bit 15. This bit is a 1
1768 * when the checksum has already been fixed. If
1769 * the checksum is still wrong and this bit is a
1770 * 1, we need to return bad checksum. Otherwise,
1771 * we need to set this bit to a 1 and update the
1772 * checksum.
1773 */
1774 ret_val = e1000_read_nvm(hw, 0x23, 1, &data);
1775 if (ret_val)
1776 return ret_val;
1777
1778 if (!(data & 0x8000)) {
1779 data |= 0x8000;
1780 ret_val = e1000_write_nvm(hw, 0x23, 1, &data);
1781 if (ret_val)
1782 return ret_val;
1783 ret_val = e1000e_update_nvm_checksum(hw);
1784 if (ret_val)
1785 return ret_val;
1786 }
1787 }
1788
1789 return 0;
1790 }
1791
1792 /**
1793 * e1000_read_mac_addr_82571 - Read device MAC address
1794 * @hw: pointer to the HW structure
1795 **/
1796 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1797 {
1798 if (hw->mac.type == e1000_82571) {
1799 s32 ret_val;
1800
1801 /* If there's an alternate MAC address place it in RAR0
1802 * so that it will override the Si installed default perm
1803 * address.
1804 */
1805 ret_val = e1000_check_alt_mac_addr_generic(hw);
1806 if (ret_val)
1807 return ret_val;
1808 }
1809
1810 return e1000_read_mac_addr_generic(hw);
1811 }
1812
1813 /**
1814 * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1815 * @hw: pointer to the HW structure
1816 *
1817 * In the case of a PHY power down to save power, or to turn off link during a
1818 * driver unload, or wake on lan is not enabled, remove the link.
1819 **/
1820 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1821 {
1822 struct e1000_phy_info *phy = &hw->phy;
1823 struct e1000_mac_info *mac = &hw->mac;
1824
1825 if (!phy->ops.check_reset_block)
1826 return;
1827
1828 /* If the management interface is not enabled, then power down */
1829 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1830 e1000_power_down_phy_copper(hw);
1831 }
1832
1833 /**
1834 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1835 * @hw: pointer to the HW structure
1836 *
1837 * Clears the hardware counters by reading the counter registers.
1838 **/
1839 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1840 {
1841 e1000e_clear_hw_cntrs_base(hw);
1842
1843 er32(PRC64);
1844 er32(PRC127);
1845 er32(PRC255);
1846 er32(PRC511);
1847 er32(PRC1023);
1848 er32(PRC1522);
1849 er32(PTC64);
1850 er32(PTC127);
1851 er32(PTC255);
1852 er32(PTC511);
1853 er32(PTC1023);
1854 er32(PTC1522);
1855
1856 er32(ALGNERRC);
1857 er32(RXERRC);
1858 er32(TNCRS);
1859 er32(CEXTERR);
1860 er32(TSCTC);
1861 er32(TSCTFC);
1862
1863 er32(MGTPRC);
1864 er32(MGTPDC);
1865 er32(MGTPTC);
1866
1867 er32(IAC);
1868 er32(ICRXOC);
1869
1870 er32(ICRXPTC);
1871 er32(ICRXATC);
1872 er32(ICTXPTC);
1873 er32(ICTXATC);
1874 er32(ICTXQEC);
1875 er32(ICTXQMTC);
1876 er32(ICRXDMTC);
1877 }
1878
1879 static const struct e1000_mac_operations e82571_mac_ops = {
1880 /* .check_mng_mode: mac type dependent */
1881 /* .check_for_link: media type dependent */
1882 .id_led_init = e1000e_id_led_init_generic,
1883 .cleanup_led = e1000e_cleanup_led_generic,
1884 .clear_hw_cntrs = e1000_clear_hw_cntrs_82571,
1885 .get_bus_info = e1000e_get_bus_info_pcie,
1886 .set_lan_id = e1000_set_lan_id_multi_port_pcie,
1887 /* .get_link_up_info: media type dependent */
1888 /* .led_on: mac type dependent */
1889 .led_off = e1000e_led_off_generic,
1890 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
1891 .write_vfta = e1000_write_vfta_generic,
1892 .clear_vfta = e1000_clear_vfta_82571,
1893 .reset_hw = e1000_reset_hw_82571,
1894 .init_hw = e1000_init_hw_82571,
1895 .setup_link = e1000_setup_link_82571,
1896 /* .setup_physical_interface: media type dependent */
1897 .setup_led = e1000e_setup_led_generic,
1898 .config_collision_dist = e1000e_config_collision_dist_generic,
1899 .read_mac_addr = e1000_read_mac_addr_82571,
1900 .rar_set = e1000e_rar_set_generic,
1901 };
1902
1903 static const struct e1000_phy_operations e82_phy_ops_igp = {
1904 .acquire = e1000_get_hw_semaphore_82571,
1905 .check_polarity = e1000_check_polarity_igp,
1906 .check_reset_block = e1000e_check_reset_block_generic,
1907 .commit = NULL,
1908 .force_speed_duplex = e1000e_phy_force_speed_duplex_igp,
1909 .get_cfg_done = e1000_get_cfg_done_82571,
1910 .get_cable_length = e1000e_get_cable_length_igp_2,
1911 .get_info = e1000e_get_phy_info_igp,
1912 .read_reg = e1000e_read_phy_reg_igp,
1913 .release = e1000_put_hw_semaphore_82571,
1914 .reset = e1000e_phy_hw_reset_generic,
1915 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1916 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1917 .write_reg = e1000e_write_phy_reg_igp,
1918 .cfg_on_link_up = NULL,
1919 };
1920
1921 static const struct e1000_phy_operations e82_phy_ops_m88 = {
1922 .acquire = e1000_get_hw_semaphore_82571,
1923 .check_polarity = e1000_check_polarity_m88,
1924 .check_reset_block = e1000e_check_reset_block_generic,
1925 .commit = e1000e_phy_sw_reset,
1926 .force_speed_duplex = e1000e_phy_force_speed_duplex_m88,
1927 .get_cfg_done = e1000e_get_cfg_done_generic,
1928 .get_cable_length = e1000e_get_cable_length_m88,
1929 .get_info = e1000e_get_phy_info_m88,
1930 .read_reg = e1000e_read_phy_reg_m88,
1931 .release = e1000_put_hw_semaphore_82571,
1932 .reset = e1000e_phy_hw_reset_generic,
1933 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1934 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1935 .write_reg = e1000e_write_phy_reg_m88,
1936 .cfg_on_link_up = NULL,
1937 };
1938
1939 static const struct e1000_phy_operations e82_phy_ops_bm = {
1940 .acquire = e1000_get_hw_semaphore_82571,
1941 .check_polarity = e1000_check_polarity_m88,
1942 .check_reset_block = e1000e_check_reset_block_generic,
1943 .commit = e1000e_phy_sw_reset,
1944 .force_speed_duplex = e1000e_phy_force_speed_duplex_m88,
1945 .get_cfg_done = e1000e_get_cfg_done_generic,
1946 .get_cable_length = e1000e_get_cable_length_m88,
1947 .get_info = e1000e_get_phy_info_m88,
1948 .read_reg = e1000e_read_phy_reg_bm2,
1949 .release = e1000_put_hw_semaphore_82571,
1950 .reset = e1000e_phy_hw_reset_generic,
1951 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1952 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1953 .write_reg = e1000e_write_phy_reg_bm2,
1954 .cfg_on_link_up = NULL,
1955 };
1956
1957 static const struct e1000_nvm_operations e82571_nvm_ops = {
1958 .acquire = e1000_acquire_nvm_82571,
1959 .read = e1000e_read_nvm_eerd,
1960 .release = e1000_release_nvm_82571,
1961 .reload = e1000e_reload_nvm_generic,
1962 .update = e1000_update_nvm_checksum_82571,
1963 .valid_led_default = e1000_valid_led_default_82571,
1964 .validate = e1000_validate_nvm_checksum_82571,
1965 .write = e1000_write_nvm_82571,
1966 };
1967
1968 const struct e1000_info e1000_82571_info = {
1969 .mac = e1000_82571,
1970 .flags = FLAG_HAS_HW_VLAN_FILTER
1971 | FLAG_HAS_JUMBO_FRAMES
1972 | FLAG_HAS_WOL
1973 | FLAG_APME_IN_CTRL3
1974 | FLAG_HAS_CTRLEXT_ON_LOAD
1975 | FLAG_HAS_SMART_POWER_DOWN
1976 | FLAG_RESET_OVERWRITES_LAA /* errata */
1977 | FLAG_TARC_SPEED_MODE_BIT /* errata */
1978 | FLAG_APME_CHECK_PORT_B,
1979 .flags2 = FLAG2_DISABLE_ASPM_L1 /* errata 13 */
1980 | FLAG2_DMA_BURST,
1981 .pba = 38,
1982 .max_hw_frame_size = DEFAULT_JUMBO,
1983 .get_variants = e1000_get_variants_82571,
1984 .mac_ops = &e82571_mac_ops,
1985 .phy_ops = &e82_phy_ops_igp,
1986 .nvm_ops = &e82571_nvm_ops,
1987 };
1988
1989 const struct e1000_info e1000_82572_info = {
1990 .mac = e1000_82572,
1991 .flags = FLAG_HAS_HW_VLAN_FILTER
1992 | FLAG_HAS_JUMBO_FRAMES
1993 | FLAG_HAS_WOL
1994 | FLAG_APME_IN_CTRL3
1995 | FLAG_HAS_CTRLEXT_ON_LOAD
1996 | FLAG_TARC_SPEED_MODE_BIT, /* errata */
1997 .flags2 = FLAG2_DISABLE_ASPM_L1 /* errata 13 */
1998 | FLAG2_DMA_BURST,
1999 .pba = 38,
2000 .max_hw_frame_size = DEFAULT_JUMBO,
2001 .get_variants = e1000_get_variants_82571,
2002 .mac_ops = &e82571_mac_ops,
2003 .phy_ops = &e82_phy_ops_igp,
2004 .nvm_ops = &e82571_nvm_ops,
2005 };
2006
2007 const struct e1000_info e1000_82573_info = {
2008 .mac = e1000_82573,
2009 .flags = FLAG_HAS_HW_VLAN_FILTER
2010 | FLAG_HAS_WOL
2011 | FLAG_APME_IN_CTRL3
2012 | FLAG_HAS_SMART_POWER_DOWN
2013 | FLAG_HAS_AMT
2014 | FLAG_HAS_SWSM_ON_LOAD,
2015 .flags2 = FLAG2_DISABLE_ASPM_L1
2016 | FLAG2_DISABLE_ASPM_L0S,
2017 .pba = 20,
2018 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
2019 .get_variants = e1000_get_variants_82571,
2020 .mac_ops = &e82571_mac_ops,
2021 .phy_ops = &e82_phy_ops_m88,
2022 .nvm_ops = &e82571_nvm_ops,
2023 };
2024
2025 const struct e1000_info e1000_82574_info = {
2026 .mac = e1000_82574,
2027 .flags = FLAG_HAS_HW_VLAN_FILTER
2028 | FLAG_HAS_MSIX
2029 | FLAG_HAS_JUMBO_FRAMES
2030 | FLAG_HAS_WOL
2031 | FLAG_HAS_HW_TIMESTAMP
2032 | FLAG_APME_IN_CTRL3
2033 | FLAG_HAS_SMART_POWER_DOWN
2034 | FLAG_HAS_AMT
2035 | FLAG_HAS_CTRLEXT_ON_LOAD,
2036 .flags2 = FLAG2_CHECK_PHY_HANG
2037 | FLAG2_DISABLE_ASPM_L0S
2038 | FLAG2_DISABLE_ASPM_L1
2039 | FLAG2_NO_DISABLE_RX
2040 | FLAG2_DMA_BURST,
2041 .pba = 32,
2042 .max_hw_frame_size = DEFAULT_JUMBO,
2043 .get_variants = e1000_get_variants_82571,
2044 .mac_ops = &e82571_mac_ops,
2045 .phy_ops = &e82_phy_ops_bm,
2046 .nvm_ops = &e82571_nvm_ops,
2047 };
2048
2049 const struct e1000_info e1000_82583_info = {
2050 .mac = e1000_82583,
2051 .flags = FLAG_HAS_HW_VLAN_FILTER
2052 | FLAG_HAS_WOL
2053 | FLAG_HAS_HW_TIMESTAMP
2054 | FLAG_APME_IN_CTRL3
2055 | FLAG_HAS_SMART_POWER_DOWN
2056 | FLAG_HAS_AMT
2057 | FLAG_HAS_JUMBO_FRAMES
2058 | FLAG_HAS_CTRLEXT_ON_LOAD,
2059 .flags2 = FLAG2_DISABLE_ASPM_L0S
2060 | FLAG2_NO_DISABLE_RX,
2061 .pba = 32,
2062 .max_hw_frame_size = DEFAULT_JUMBO,
2063 .get_variants = e1000_get_variants_82571,
2064 .mac_ops = &e82571_mac_ops,
2065 .phy_ops = &e82_phy_ops_bm,
2066 .nvm_ops = &e82571_nvm_ops,
2067 };
CRIS linux kernel tree