drivers/net/ethernet/intel/e1000e/defines.h

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2013 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 #ifndef _E1000_DEFINES_H_
  30 #define _E1000_DEFINES_H_
  31
  32 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
  33 #define REQ_TX_DESCRIPTOR_MULTIPLE  8
  34 #define REQ_RX_DESCRIPTOR_MULTIPLE  8
  35
  36 /* Definitions for power management and wakeup registers */
  37 /* Wake Up Control */
  38 #define E1000_WUC_APME       0x00000001 /* APM Enable */
  39 #define E1000_WUC_PME_EN     0x00000002 /* PME Enable */
  40 #define E1000_WUC_PHY_WAKE   0x00000100 /* if PHY supports wakeup */
  41
  42 /* Wake Up Filter Control */
  43 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
  44 #define E1000_WUFC_MAG  0x00000002 /* Magic Packet Wakeup Enable */
  45 #define E1000_WUFC_EX   0x00000004 /* Directed Exact Wakeup Enable */
  46 #define E1000_WUFC_MC   0x00000008 /* Directed Multicast Wakeup Enable */
  47 #define E1000_WUFC_BC   0x00000010 /* Broadcast Wakeup Enable */
  48 #define E1000_WUFC_ARP  0x00000020 /* ARP Request Packet Wakeup Enable */
  49
  50 /* Wake Up Status */
  51 #define E1000_WUS_LNKC         E1000_WUFC_LNKC
  52 #define E1000_WUS_MAG          E1000_WUFC_MAG
  53 #define E1000_WUS_EX           E1000_WUFC_EX
  54 #define E1000_WUS_MC           E1000_WUFC_MC
  55 #define E1000_WUS_BC           E1000_WUFC_BC
  56
  57 /* Extended Device Control */
  58 #define E1000_CTRL_EXT_LPCD  0x00000004     /* LCD Power Cycle Done */
  59 #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Definable Pin 3 */
  60 #define E1000_CTRL_EXT_FORCE_SMBUS 0x00000800 /* Force SMBus mode */
  61 #define E1000_CTRL_EXT_EE_RST    0x00002000 /* Reinitialize from EEPROM */
  62 #define E1000_CTRL_EXT_SPD_BYPS  0x00008000 /* Speed Select Bypass */
  63 #define E1000_CTRL_EXT_RO_DIS    0x00020000 /* Relaxed Ordering disable */
  64 #define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clock Gating */
  65 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
  66 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES  0x00C00000
  67 #define E1000_CTRL_EXT_EIAME          0x01000000
  68 #define E1000_CTRL_EXT_DRV_LOAD       0x10000000 /* Driver loaded bit for FW */
  69 #define E1000_CTRL_EXT_IAME             0x08000000 /* Int ACK Auto-mask */
  70 #define E1000_CTRL_EXT_PBA_CLR        0x80000000 /* PBA Clear */
  71 #define E1000_CTRL_EXT_LSECCK         0x00001000
  72 #define E1000_CTRL_EXT_PHYPDEN        0x00100000
  73
  74 /* Receive Descriptor bit definitions */
  75 #define E1000_RXD_STAT_DD       0x01    /* Descriptor Done */
  76 #define E1000_RXD_STAT_EOP      0x02    /* End of Packet */
  77 #define E1000_RXD_STAT_IXSM     0x04    /* Ignore checksum */
  78 #define E1000_RXD_STAT_VP       0x08    /* IEEE VLAN Packet */
  79 #define E1000_RXD_STAT_UDPCS    0x10    /* UDP xsum calculated */
  80 #define E1000_RXD_STAT_TCPCS    0x20    /* TCP xsum calculated */
  81 #define E1000_RXD_ERR_CE        0x01    /* CRC Error */
  82 #define E1000_RXD_ERR_SE        0x02    /* Symbol Error */
  83 #define E1000_RXD_ERR_SEQ       0x04    /* Sequence Error */
  84 #define E1000_RXD_ERR_CXE       0x10    /* Carrier Extension Error */
  85 #define E1000_RXD_ERR_TCPE      0x20    /* TCP/UDP Checksum Error */
  86 #define E1000_RXD_ERR_IPE       0x40    /* IP Checksum Error */
  87 #define E1000_RXD_ERR_RXE       0x80    /* Rx Data Error */
  88 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF  /* VLAN ID is in lower 12 bits */
  89
  90 #define E1000_RXDEXT_STATERR_TST   0x00000100   /* Time Stamp taken */
  91 #define E1000_RXDEXT_STATERR_CE    0x01000000
  92 #define E1000_RXDEXT_STATERR_SE    0x02000000
  93 #define E1000_RXDEXT_STATERR_SEQ   0x04000000
  94 #define E1000_RXDEXT_STATERR_CXE   0x10000000
  95 #define E1000_RXDEXT_STATERR_RXE   0x80000000
  96
  97 /* mask to determine if packets should be dropped due to frame errors */
  98 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \
  99         E1000_RXD_ERR_CE  |             \
 100         E1000_RXD_ERR_SE  |             \
 101         E1000_RXD_ERR_SEQ |             \
 102         E1000_RXD_ERR_CXE |             \
 103         E1000_RXD_ERR_RXE)
 104
 105 /* Same mask, but for extended and packet split descriptors */
 106 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
 107         E1000_RXDEXT_STATERR_CE  |      \
 108         E1000_RXDEXT_STATERR_SE  |      \
 109         E1000_RXDEXT_STATERR_SEQ |      \
 110         E1000_RXDEXT_STATERR_CXE |      \
 111         E1000_RXDEXT_STATERR_RXE)
 112
 113 #define E1000_MRQC_RSS_FIELD_MASK              0xFFFF0000
 114 #define E1000_MRQC_RSS_FIELD_IPV4_TCP          0x00010000
 115 #define E1000_MRQC_RSS_FIELD_IPV4              0x00020000
 116 #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX       0x00040000
 117 #define E1000_MRQC_RSS_FIELD_IPV6              0x00100000
 118 #define E1000_MRQC_RSS_FIELD_IPV6_TCP          0x00200000
 119
 120 #define E1000_RXDPS_HDRSTAT_HDRSP              0x00008000
 121
 122 /* Management Control */
 123 #define E1000_MANC_SMBUS_EN      0x00000001 /* SMBus Enabled - RO */
 124 #define E1000_MANC_ASF_EN        0x00000002 /* ASF Enabled - RO */
 125 #define E1000_MANC_ARP_EN        0x00002000 /* Enable ARP Request Filtering */
 126 #define E1000_MANC_RCV_TCO_EN    0x00020000 /* Receive TCO Packets Enabled */
 127 #define E1000_MANC_BLK_PHY_RST_ON_IDE   0x00040000 /* Block phy resets */
 128 /* Enable MAC address filtering */
 129 #define E1000_MANC_EN_MAC_ADDR_FILTER   0x00100000
 130 /* Enable MNG packets to host memory */
 131 #define E1000_MANC_EN_MNG2HOST   0x00200000
 132
 133 #define E1000_MANC2H_PORT_623    0x00000020 /* Port 0x26f */
 134 #define E1000_MANC2H_PORT_664    0x00000040 /* Port 0x298 */
 135 #define E1000_MDEF_PORT_623      0x00000800 /* Port 0x26f */
 136 #define E1000_MDEF_PORT_664      0x00000400 /* Port 0x298 */
 137
 138 /* Receive Control */
 139 #define E1000_RCTL_EN             0x00000002    /* enable */
 140 #define E1000_RCTL_SBP            0x00000004    /* store bad packet */
 141 #define E1000_RCTL_UPE            0x00000008    /* unicast promiscuous enable */
 142 #define E1000_RCTL_MPE            0x00000010    /* multicast promiscuous enab */
 143 #define E1000_RCTL_LPE            0x00000020    /* long packet enable */
 144 #define E1000_RCTL_LBM_NO         0x00000000    /* no loopback mode */
 145 #define E1000_RCTL_LBM_MAC        0x00000040    /* MAC loopback mode */
 146 #define E1000_RCTL_LBM_TCVR       0x000000C0    /* tcvr loopback mode */
 147 #define E1000_RCTL_DTYP_PS        0x00000400    /* Packet Split descriptor */
 148 #define E1000_RCTL_RDMTS_HALF     0x00000000    /* Rx desc min threshold size */
 149 #define E1000_RCTL_MO_SHIFT       12            /* multicast offset shift */
 150 #define E1000_RCTL_MO_3           0x00003000    /* multicast offset 15:4 */
 151 #define E1000_RCTL_BAM            0x00008000    /* broadcast enable */
 152 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
 153 #define E1000_RCTL_SZ_2048        0x00000000    /* Rx buffer size 2048 */
 154 #define E1000_RCTL_SZ_1024        0x00010000    /* Rx buffer size 1024 */
 155 #define E1000_RCTL_SZ_512         0x00020000    /* Rx buffer size 512 */
 156 #define E1000_RCTL_SZ_256         0x00030000    /* Rx buffer size 256 */
 157 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
 158 #define E1000_RCTL_SZ_16384       0x00010000    /* Rx buffer size 16384 */
 159 #define E1000_RCTL_SZ_8192        0x00020000    /* Rx buffer size 8192 */
 160 #define E1000_RCTL_SZ_4096        0x00030000    /* Rx buffer size 4096 */
 161 #define E1000_RCTL_VFE            0x00040000    /* vlan filter enable */
 162 #define E1000_RCTL_CFIEN          0x00080000    /* canonical form enable */
 163 #define E1000_RCTL_CFI            0x00100000    /* canonical form indicator */
 164 #define E1000_RCTL_DPF            0x00400000    /* Discard Pause Frames */
 165 #define E1000_RCTL_PMCF           0x00800000    /* pass MAC control frames */
 166 #define E1000_RCTL_BSEX           0x02000000    /* Buffer size extension */
 167 #define E1000_RCTL_SECRC          0x04000000    /* Strip Ethernet CRC */
 168
 169 /* Use byte values for the following shift parameters
 170  * Usage:
 171  *     psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
 172  *                  E1000_PSRCTL_BSIZE0_MASK) |
 173  *                ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
 174  *                  E1000_PSRCTL_BSIZE1_MASK) |
 175  *                ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
 176  *                  E1000_PSRCTL_BSIZE2_MASK) |
 177  *                ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
 178  *                  E1000_PSRCTL_BSIZE3_MASK))
 179  * where value0 = [128..16256],  default=256
 180  *       value1 = [1024..64512], default=4096
 181  *       value2 = [0..64512],    default=4096
 182  *       value3 = [0..64512],    default=0
 183  */
 184
 185 #define E1000_PSRCTL_BSIZE0_MASK   0x0000007F
 186 #define E1000_PSRCTL_BSIZE1_MASK   0x00003F00
 187 #define E1000_PSRCTL_BSIZE2_MASK   0x003F0000
 188 #define E1000_PSRCTL_BSIZE3_MASK   0x3F000000
 189
 190 #define E1000_PSRCTL_BSIZE0_SHIFT  7            /* Shift _right_ 7 */
 191 #define E1000_PSRCTL_BSIZE1_SHIFT  2            /* Shift _right_ 2 */
 192 #define E1000_PSRCTL_BSIZE2_SHIFT  6            /* Shift _left_ 6 */
 193 #define E1000_PSRCTL_BSIZE3_SHIFT 14            /* Shift _left_ 14 */
 194
 195 /* SWFW_SYNC Definitions */
 196 #define E1000_SWFW_EEP_SM   0x1
 197 #define E1000_SWFW_PHY0_SM  0x2
 198 #define E1000_SWFW_PHY1_SM  0x4
 199 #define E1000_SWFW_CSR_SM   0x8
 200
 201 /* Device Control */
 202 #define E1000_CTRL_FD       0x00000001  /* Full duplex.0=half; 1=full */
 203 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
 204 #define E1000_CTRL_LRST     0x00000008  /* Link reset. 0=normal,1=reset */
 205 #define E1000_CTRL_ASDE     0x00000020  /* Auto-speed detect enable */
 206 #define E1000_CTRL_SLU      0x00000040  /* Set link up (Force Link) */
 207 #define E1000_CTRL_ILOS     0x00000080  /* Invert Loss-Of Signal */
 208 #define E1000_CTRL_SPD_SEL  0x00000300  /* Speed Select Mask */
 209 #define E1000_CTRL_SPD_10   0x00000000  /* Force 10Mb */
 210 #define E1000_CTRL_SPD_100  0x00000100  /* Force 100Mb */
 211 #define E1000_CTRL_SPD_1000 0x00000200  /* Force 1Gb */
 212 #define E1000_CTRL_FRCSPD   0x00000800  /* Force Speed */
 213 #define E1000_CTRL_FRCDPX   0x00001000  /* Force Duplex */
 214 #define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */
 215 #define E1000_CTRL_LANPHYPC_VALUE    0x00020000 /* SW value of LANPHYPC */
 216 #define E1000_CTRL_MEHE     0x00080000  /* Memory Error Handling Enable */
 217 #define E1000_CTRL_SWDPIN0  0x00040000  /* SWDPIN 0 value */
 218 #define E1000_CTRL_SWDPIN1  0x00080000  /* SWDPIN 1 value */
 219 #define E1000_CTRL_ADVD3WUC 0x00100000  /* D3 WUC */
 220 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 /* PHY PM enable */
 221 #define E1000_CTRL_SWDPIO0  0x00400000  /* SWDPIN 0 Input or output */
 222 #define E1000_CTRL_RST      0x04000000  /* Global reset */
 223 #define E1000_CTRL_RFCE     0x08000000  /* Receive Flow Control enable */
 224 #define E1000_CTRL_TFCE     0x10000000  /* Transmit flow control enable */
 225 #define E1000_CTRL_VME      0x40000000  /* IEEE VLAN mode enable */
 226 #define E1000_CTRL_PHY_RST  0x80000000  /* PHY Reset */
 227
 228 #define E1000_PCS_LCTL_FORCE_FCTRL      0x80
 229
 230 #define E1000_PCS_LSTS_AN_COMPLETE      0x10000
 231
 232 /* Device Status */
 233 #define E1000_STATUS_FD         0x00000001      /* Full duplex.0=half,1=full */
 234 #define E1000_STATUS_LU         0x00000002      /* Link up.0=no,1=link */
 235 #define E1000_STATUS_FUNC_MASK  0x0000000C      /* PCI Function Mask */
 236 #define E1000_STATUS_FUNC_SHIFT 2
 237 #define E1000_STATUS_FUNC_1     0x00000004      /* Function 1 */
 238 #define E1000_STATUS_TXOFF      0x00000010      /* transmission paused */
 239 #define E1000_STATUS_SPEED_MASK 0x000000C0
 240 #define E1000_STATUS_SPEED_10   0x00000000      /* Speed 10Mb/s */
 241 #define E1000_STATUS_SPEED_100  0x00000040      /* Speed 100Mb/s */
 242 #define E1000_STATUS_SPEED_1000 0x00000080      /* Speed 1000Mb/s */
 243 #define E1000_STATUS_LAN_INIT_DONE 0x00000200   /* Lan Init Completion by NVM */
 244 #define E1000_STATUS_PHYRA      0x00000400      /* PHY Reset Asserted */
 245 #define E1000_STATUS_GIO_MASTER_ENABLE  0x00080000      /* Master Req status */
 246
 247 #define HALF_DUPLEX 1
 248 #define FULL_DUPLEX 2
 249
 250 #define ADVERTISE_10_HALF                 0x0001
 251 #define ADVERTISE_10_FULL                 0x0002
 252 #define ADVERTISE_100_HALF                0x0004
 253 #define ADVERTISE_100_FULL                0x0008
 254 #define ADVERTISE_1000_HALF               0x0010 /* Not used, just FYI */
 255 #define ADVERTISE_1000_FULL               0x0020
 256
 257 /* 1000/H is not supported, nor spec-compliant. */
 258 #define E1000_ALL_SPEED_DUPLEX  ( \
 259         ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
 260         ADVERTISE_100_FULL | ADVERTISE_1000_FULL)
 261 #define E1000_ALL_NOT_GIG       ( \
 262         ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
 263         ADVERTISE_100_FULL)
 264 #define E1000_ALL_100_SPEED     (ADVERTISE_100_HALF | ADVERTISE_100_FULL)
 265 #define E1000_ALL_10_SPEED      (ADVERTISE_10_HALF | ADVERTISE_10_FULL)
 266 #define E1000_ALL_HALF_DUPLEX   (ADVERTISE_10_HALF | ADVERTISE_100_HALF)
 267
 268 #define AUTONEG_ADVERTISE_SPEED_DEFAULT   E1000_ALL_SPEED_DUPLEX
 269
 270 /* LED Control */
 271 #define E1000_PHY_LED0_MODE_MASK          0x00000007
 272 #define E1000_PHY_LED0_IVRT               0x00000008
 273 #define E1000_PHY_LED0_MASK               0x0000001F
 274
 275 #define E1000_LEDCTL_LED0_MODE_MASK       0x0000000F
 276 #define E1000_LEDCTL_LED0_MODE_SHIFT      0
 277 #define E1000_LEDCTL_LED0_IVRT            0x00000040
 278 #define E1000_LEDCTL_LED0_BLINK           0x00000080
 279
 280 #define E1000_LEDCTL_MODE_LINK_UP       0x2
 281 #define E1000_LEDCTL_MODE_LED_ON        0xE
 282 #define E1000_LEDCTL_MODE_LED_OFF       0xF
 283
 284 /* Transmit Descriptor bit definitions */
 285 #define E1000_TXD_DTYP_D     0x00100000 /* Data Descriptor */
 286 #define E1000_TXD_POPTS_IXSM 0x01       /* Insert IP checksum */
 287 #define E1000_TXD_POPTS_TXSM 0x02       /* Insert TCP/UDP checksum */
 288 #define E1000_TXD_CMD_EOP    0x01000000 /* End of Packet */
 289 #define E1000_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */
 290 #define E1000_TXD_CMD_IC     0x04000000 /* Insert Checksum */
 291 #define E1000_TXD_CMD_RS     0x08000000 /* Report Status */
 292 #define E1000_TXD_CMD_RPS    0x10000000 /* Report Packet Sent */
 293 #define E1000_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */
 294 #define E1000_TXD_CMD_VLE    0x40000000 /* Add VLAN tag */
 295 #define E1000_TXD_CMD_IDE    0x80000000 /* Enable Tidv register */
 296 #define E1000_TXD_STAT_DD    0x00000001 /* Descriptor Done */
 297 #define E1000_TXD_STAT_EC    0x00000002 /* Excess Collisions */
 298 #define E1000_TXD_STAT_LC    0x00000004 /* Late Collisions */
 299 #define E1000_TXD_STAT_TU    0x00000008 /* Transmit underrun */
 300 #define E1000_TXD_CMD_TCP    0x01000000 /* TCP packet */
 301 #define E1000_TXD_CMD_IP     0x02000000 /* IP packet */
 302 #define E1000_TXD_CMD_TSE    0x04000000 /* TCP Seg enable */
 303 #define E1000_TXD_STAT_TC    0x00000004 /* Tx Underrun */
 304 #define E1000_TXD_EXTCMD_TSTAMP 0x00000010 /* IEEE1588 Timestamp packet */
 305
 306 /* Transmit Control */
 307 #define E1000_TCTL_EN     0x00000002    /* enable Tx */
 308 #define E1000_TCTL_PSP    0x00000008    /* pad short packets */
 309 #define E1000_TCTL_CT     0x00000ff0    /* collision threshold */
 310 #define E1000_TCTL_COLD   0x003ff000    /* collision distance */
 311 #define E1000_TCTL_RTLC   0x01000000    /* Re-transmit on late collision */
 312 #define E1000_TCTL_MULR   0x10000000    /* Multiple request support */
 313
 314 /* SerDes Control */
 315 #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
 316 #define E1000_SCTL_ENABLE_SERDES_LOOPBACK       0x0410
 317
 318 /* Receive Checksum Control */
 319 #define E1000_RXCSUM_TUOFL     0x00000200   /* TCP / UDP checksum offload */
 320 #define E1000_RXCSUM_IPPCSE    0x00001000   /* IP payload checksum enable */
 321 #define E1000_RXCSUM_PCSD      0x00002000   /* packet checksum disabled */
 322
 323 /* Header split receive */
 324 #define E1000_RFCTL_NFSW_DIS            0x00000040
 325 #define E1000_RFCTL_NFSR_DIS            0x00000080
 326 #define E1000_RFCTL_ACK_DIS             0x00001000
 327 #define E1000_RFCTL_EXTEN               0x00008000
 328 #define E1000_RFCTL_IPV6_EX_DIS         0x00010000
 329 #define E1000_RFCTL_NEW_IPV6_EXT_DIS    0x00020000
 330
 331 /* Collision related configuration parameters */
 332 #define E1000_COLLISION_THRESHOLD       15
 333 #define E1000_CT_SHIFT                  4
 334 #define E1000_COLLISION_DISTANCE        63
 335 #define E1000_COLD_SHIFT                12
 336
 337 /* Default values for the transmit IPG register */
 338 #define DEFAULT_82543_TIPG_IPGT_COPPER 8
 339
 340 #define E1000_TIPG_IPGT_MASK  0x000003FF
 341
 342 #define DEFAULT_82543_TIPG_IPGR1 8
 343 #define E1000_TIPG_IPGR1_SHIFT  10
 344
 345 #define DEFAULT_82543_TIPG_IPGR2 6
 346 #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
 347 #define E1000_TIPG_IPGR2_SHIFT  20
 348
 349 #define MAX_JUMBO_FRAME_SIZE    0x3F00
 350
 351 /* Extended Configuration Control and Size */
 352 #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP      0x00000020
 353 #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE       0x00000001
 354 #define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE       0x00000008
 355 #define E1000_EXTCNF_CTRL_SWFLAG                 0x00000020
 356 #define E1000_EXTCNF_CTRL_GATE_PHY_CFG           0x00000080
 357 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK   0x00FF0000
 358 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT          16
 359 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK   0x0FFF0000
 360 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT          16
 361
 362 #define E1000_PHY_CTRL_D0A_LPLU           0x00000002
 363 #define E1000_PHY_CTRL_NOND0A_LPLU        0x00000004
 364 #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
 365 #define E1000_PHY_CTRL_GBE_DISABLE        0x00000040
 366
 367 #define E1000_KABGTXD_BGSQLBIAS           0x00050000
 368
 369 /* Low Power IDLE Control */
 370 #define E1000_LPIC_LPIET_SHIFT          24      /* Low Power Idle Entry Time */
 371
 372 /* PBA constants */
 373 #define E1000_PBA_8K  0x0008    /* 8KB */
 374 #define E1000_PBA_16K 0x0010    /* 16KB */
 375
 376 #define E1000_PBA_RXA_MASK      0xFFFF
 377
 378 #define E1000_PBS_16K E1000_PBA_16K
 379
 380 /* Uncorrectable/correctable ECC Error counts and enable bits */
 381 #define E1000_PBECCSTS_CORR_ERR_CNT_MASK        0x000000FF
 382 #define E1000_PBECCSTS_UNCORR_ERR_CNT_MASK      0x0000FF00
 383 #define E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT     8
 384 #define E1000_PBECCSTS_ECC_ENABLE               0x00010000
 385
 386 #define IFS_MAX       80
 387 #define IFS_MIN       40
 388 #define IFS_RATIO     4
 389 #define IFS_STEP      10
 390 #define MIN_NUM_XMITS 1000
 391
 392 /* SW Semaphore Register */
 393 #define E1000_SWSM_SMBI         0x00000001 /* Driver Semaphore bit */
 394 #define E1000_SWSM_SWESMBI      0x00000002 /* FW Semaphore bit */
 395 #define E1000_SWSM_DRV_LOAD     0x00000008 /* Driver Loaded Bit */
 396
 397 #define E1000_SWSM2_LOCK        0x00000002 /* Secondary driver semaphore bit */
 398
 399 /* Interrupt Cause Read */
 400 #define E1000_ICR_TXDW          0x00000001 /* Transmit desc written back */
 401 #define E1000_ICR_LSC           0x00000004 /* Link Status Change */
 402 #define E1000_ICR_RXSEQ         0x00000008 /* Rx sequence error */
 403 #define E1000_ICR_RXDMT0        0x00000010 /* Rx desc min. threshold (0) */
 404 #define E1000_ICR_RXT0          0x00000080 /* Rx timer intr (ring 0) */
 405 #define E1000_ICR_ECCER         0x00400000 /* Uncorrectable ECC Error */
 406 /* If this bit asserted, the driver should claim the interrupt */
 407 #define E1000_ICR_INT_ASSERTED  0x80000000
 408 #define E1000_ICR_RXQ0          0x00100000 /* Rx Queue 0 Interrupt */
 409 #define E1000_ICR_RXQ1          0x00200000 /* Rx Queue 1 Interrupt */
 410 #define E1000_ICR_TXQ0          0x00400000 /* Tx Queue 0 Interrupt */
 411 #define E1000_ICR_TXQ1          0x00800000 /* Tx Queue 1 Interrupt */
 412 #define E1000_ICR_OTHER         0x01000000 /* Other Interrupts */
 413
 414 /* PBA ECC Register */
 415 #define E1000_PBA_ECC_COUNTER_MASK  0xFFF00000 /* ECC counter mask */
 416 #define E1000_PBA_ECC_COUNTER_SHIFT 20         /* ECC counter shift value */
 417 #define E1000_PBA_ECC_CORR_EN       0x00000001 /* ECC correction enable */
 418 #define E1000_PBA_ECC_STAT_CLR      0x00000002 /* Clear ECC error counter */
 419 #define E1000_PBA_ECC_INT_EN        0x00000004 /* Enable ICR bit 5 for ECC */
 420
 421 /* This defines the bits that are set in the Interrupt Mask
 422  * Set/Read Register.  Each bit is documented below:
 423  *   o RXT0   = Receiver Timer Interrupt (ring 0)
 424  *   o TXDW   = Transmit Descriptor Written Back
 425  *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
 426  *   o RXSEQ  = Receive Sequence Error
 427  *   o LSC    = Link Status Change
 428  */
 429 #define IMS_ENABLE_MASK ( \
 430         E1000_IMS_RXT0   |    \
 431         E1000_IMS_TXDW   |    \
 432         E1000_IMS_RXDMT0 |    \
 433         E1000_IMS_RXSEQ  |    \
 434         E1000_IMS_LSC)
 435
 436 /* Interrupt Mask Set */
 437 #define E1000_IMS_TXDW      E1000_ICR_TXDW      /* Transmit desc written back */
 438 #define E1000_IMS_LSC       E1000_ICR_LSC       /* Link Status Change */
 439 #define E1000_IMS_RXSEQ     E1000_ICR_RXSEQ     /* Rx sequence error */
 440 #define E1000_IMS_RXDMT0    E1000_ICR_RXDMT0    /* Rx desc min. threshold */
 441 #define E1000_IMS_RXT0      E1000_ICR_RXT0      /* Rx timer intr */
 442 #define E1000_IMS_ECCER     E1000_ICR_ECCER     /* Uncorrectable ECC Error */
 443 #define E1000_IMS_RXQ0      E1000_ICR_RXQ0      /* Rx Queue 0 Interrupt */
 444 #define E1000_IMS_RXQ1      E1000_ICR_RXQ1      /* Rx Queue 1 Interrupt */
 445 #define E1000_IMS_TXQ0      E1000_ICR_TXQ0      /* Tx Queue 0 Interrupt */
 446 #define E1000_IMS_TXQ1      E1000_ICR_TXQ1      /* Tx Queue 1 Interrupt */
 447 #define E1000_IMS_OTHER     E1000_ICR_OTHER     /* Other Interrupts */
 448
 449 /* Interrupt Cause Set */
 450 #define E1000_ICS_LSC       E1000_ICR_LSC       /* Link Status Change */
 451 #define E1000_ICS_RXSEQ     E1000_ICR_RXSEQ     /* Rx sequence error */
 452 #define E1000_ICS_RXDMT0    E1000_ICR_RXDMT0    /* Rx desc min. threshold */
 453
 454 /* Transmit Descriptor Control */
 455 #define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
 456 #define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
 457 #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
 458 #define E1000_TXDCTL_GRAN    0x01000000 /* TXDCTL Granularity */
 459 #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
 460 #define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */
 461 /* Enable the counting of desc. still to be processed. */
 462 #define E1000_TXDCTL_COUNT_DESC 0x00400000
 463
 464 /* Flow Control Constants */
 465 #define FLOW_CONTROL_ADDRESS_LOW  0x00C28001
 466 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
 467 #define FLOW_CONTROL_TYPE         0x8808
 468
 469 /* 802.1q VLAN Packet Size */
 470 #define E1000_VLAN_FILTER_TBL_SIZE 128  /* VLAN Filter Table (4096 bits) */
 471
 472 /* Receive Address
 473  * Number of high/low register pairs in the RAR. The RAR (Receive Address
 474  * Registers) holds the directed and multicast addresses that we monitor.
 475  * Technically, we have 16 spots.  However, we reserve one of these spots
 476  * (RAR[15]) for our directed address used by controllers with
 477  * manageability enabled, allowing us room for 15 multicast addresses.
 478  */
 479 #define E1000_RAR_ENTRIES     15
 480 #define E1000_RAH_AV  0x80000000        /* Receive descriptor valid */
 481 #define E1000_RAL_MAC_ADDR_LEN 4
 482 #define E1000_RAH_MAC_ADDR_LEN 2
 483
 484 /* Error Codes */
 485 #define E1000_ERR_NVM      1
 486 #define E1000_ERR_PHY      2
 487 #define E1000_ERR_CONFIG   3
 488 #define E1000_ERR_PARAM    4
 489 #define E1000_ERR_MAC_INIT 5
 490 #define E1000_ERR_PHY_TYPE 6
 491 #define E1000_ERR_RESET   9
 492 #define E1000_ERR_MASTER_REQUESTS_PENDING 10
 493 #define E1000_ERR_HOST_INTERFACE_COMMAND 11
 494 #define E1000_BLK_PHY_RESET   12
 495 #define E1000_ERR_SWFW_SYNC 13
 496 #define E1000_NOT_IMPLEMENTED 14
 497 #define E1000_ERR_INVALID_ARGUMENT  16
 498 #define E1000_ERR_NO_SPACE          17
 499 #define E1000_ERR_NVM_PBA_SECTION   18
 500
 501 /* Loop limit on how long we wait for auto-negotiation to complete */
 502 #define FIBER_LINK_UP_LIMIT               50
 503 #define COPPER_LINK_UP_LIMIT              10
 504 #define PHY_AUTO_NEG_LIMIT                45
 505 #define PHY_FORCE_LIMIT                   20
 506 /* Number of 100 microseconds we wait for PCI Express master disable */
 507 #define MASTER_DISABLE_TIMEOUT      800
 508 /* Number of milliseconds we wait for PHY configuration done after MAC reset */
 509 #define PHY_CFG_TIMEOUT             100
 510 /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
 511 #define MDIO_OWNERSHIP_TIMEOUT      10
 512 /* Number of milliseconds for NVM auto read done after MAC reset. */
 513 #define AUTO_READ_DONE_TIMEOUT      10
 514
 515 /* Flow Control */
 516 #define E1000_FCRTH_RTH  0x0000FFF8     /* Mask Bits[15:3] for RTH */
 517 #define E1000_FCRTL_RTL  0x0000FFF8     /* Mask Bits[15:3] for RTL */
 518 #define E1000_FCRTL_XONE 0x80000000     /* Enable XON frame transmission */
 519
 520 /* Transmit Configuration Word */
 521 #define E1000_TXCW_FD         0x00000020        /* TXCW full duplex */
 522 #define E1000_TXCW_PAUSE      0x00000080        /* TXCW sym pause request */
 523 #define E1000_TXCW_ASM_DIR    0x00000100        /* TXCW astm pause direction */
 524 #define E1000_TXCW_PAUSE_MASK 0x00000180        /* TXCW pause request mask */
 525 #define E1000_TXCW_ANE        0x80000000        /* Auto-neg enable */
 526
 527 /* Receive Configuration Word */
 528 #define E1000_RXCW_CW         0x0000ffff        /* RxConfigWord mask */
 529 #define E1000_RXCW_IV         0x08000000        /* Receive config invalid */
 530 #define E1000_RXCW_C          0x20000000        /* Receive config */
 531 #define E1000_RXCW_SYNCH      0x40000000        /* Receive config synch */
 532
 533 #define E1000_TSYNCTXCTL_VALID          0x00000001 /* Tx timestamp valid */
 534 #define E1000_TSYNCTXCTL_ENABLED        0x00000010 /* enable Tx timestamping */
 535
 536 #define E1000_TSYNCRXCTL_VALID          0x00000001 /* Rx timestamp valid */
 537 #define E1000_TSYNCRXCTL_TYPE_MASK      0x0000000E /* Rx type mask */
 538 #define E1000_TSYNCRXCTL_TYPE_L2_V2     0x00
 539 #define E1000_TSYNCRXCTL_TYPE_L4_V1     0x02
 540 #define E1000_TSYNCRXCTL_TYPE_L2_L4_V2  0x04
 541 #define E1000_TSYNCRXCTL_TYPE_ALL       0x08
 542 #define E1000_TSYNCRXCTL_TYPE_EVENT_V2  0x0A
 543 #define E1000_TSYNCRXCTL_ENABLED        0x00000010 /* enable Rx timestamping */
 544 #define E1000_TSYNCRXCTL_SYSCFI         0x00000020 /* Sys clock frequency */
 545
 546 #define E1000_RXMTRL_PTP_V1_SYNC_MESSAGE        0x00000000
 547 #define E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE   0x00010000
 548
 549 #define E1000_RXMTRL_PTP_V2_SYNC_MESSAGE        0x00000000
 550 #define E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE   0x01000000
 551
 552 #define E1000_TIMINCA_INCPERIOD_SHIFT   24
 553 #define E1000_TIMINCA_INCVALUE_MASK     0x00FFFFFF
 554
 555 /* PCI Express Control */
 556 #define E1000_GCR_RXD_NO_SNOOP          0x00000001
 557 #define E1000_GCR_RXDSCW_NO_SNOOP       0x00000002
 558 #define E1000_GCR_RXDSCR_NO_SNOOP       0x00000004
 559 #define E1000_GCR_TXD_NO_SNOOP          0x00000008
 560 #define E1000_GCR_TXDSCW_NO_SNOOP       0x00000010
 561 #define E1000_GCR_TXDSCR_NO_SNOOP       0x00000020
 562
 563 #define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP         | \
 564                            E1000_GCR_RXDSCW_NO_SNOOP      | \
 565                            E1000_GCR_RXDSCR_NO_SNOOP      | \
 566                            E1000_GCR_TXD_NO_SNOOP         | \
 567                            E1000_GCR_TXDSCW_NO_SNOOP      | \
 568                            E1000_GCR_TXDSCR_NO_SNOOP)
 569
 570 /* NVM Control */
 571 #define E1000_EECD_SK        0x00000001 /* NVM Clock */
 572 #define E1000_EECD_CS        0x00000002 /* NVM Chip Select */
 573 #define E1000_EECD_DI        0x00000004 /* NVM Data In */
 574 #define E1000_EECD_DO        0x00000008 /* NVM Data Out */
 575 #define E1000_EECD_REQ       0x00000040 /* NVM Access Request */
 576 #define E1000_EECD_GNT       0x00000080 /* NVM Access Grant */
 577 #define E1000_EECD_PRES      0x00000100 /* NVM Present */
 578 #define E1000_EECD_SIZE      0x00000200 /* NVM Size (0=64 word 1=256 word) */
 579 /* NVM Addressing bits based on type (0-small, 1-large) */
 580 #define E1000_EECD_ADDR_BITS 0x00000400
 581 #define E1000_NVM_GRANT_ATTEMPTS   1000 /* NVM # attempts to gain grant */
 582 #define E1000_EECD_AUTO_RD          0x00000200  /* NVM Auto Read done */
 583 #define E1000_EECD_SIZE_EX_MASK     0x00007800  /* NVM Size */
 584 #define E1000_EECD_SIZE_EX_SHIFT     11
 585 #define E1000_EECD_FLUPD     0x00080000 /* Update FLASH */
 586 #define E1000_EECD_AUPDEN    0x00100000 /* Enable Autonomous FLASH update */
 587 #define E1000_EECD_SEC1VAL   0x00400000 /* Sector One Valid */
 588 #define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES)
 589
 590 #define E1000_NVM_RW_REG_DATA   16      /* Offset to data in NVM r/w regs */
 591 #define E1000_NVM_RW_REG_DONE   2       /* Offset to READ/WRITE done bit */
 592 #define E1000_NVM_RW_REG_START  1       /* Start operation */
 593 #define E1000_NVM_RW_ADDR_SHIFT 2       /* Shift to the address bits */
 594 #define E1000_NVM_POLL_WRITE    1       /* Flag for polling write complete */
 595 #define E1000_NVM_POLL_READ     0       /* Flag for polling read complete */
 596 #define E1000_FLASH_UPDATES     2000
 597
 598 /* NVM Word Offsets */
 599 #define NVM_COMPAT                 0x0003
 600 #define NVM_ID_LED_SETTINGS        0x0004
 601 #define NVM_FUTURE_INIT_WORD1      0x0019
 602 #define NVM_COMPAT_VALID_CSUM      0x0001
 603 #define NVM_FUTURE_INIT_WORD1_VALID_CSUM        0x0040
 604
 605 #define NVM_INIT_CONTROL2_REG      0x000F
 606 #define NVM_INIT_CONTROL3_PORT_B   0x0014
 607 #define NVM_INIT_3GIO_3            0x001A
 608 #define NVM_INIT_CONTROL3_PORT_A   0x0024
 609 #define NVM_CFG                    0x0012
 610 #define NVM_ALT_MAC_ADDR_PTR       0x0037
 611 #define NVM_CHECKSUM_REG           0x003F
 612
 613 #define E1000_NVM_CFG_DONE_PORT_0  0x40000 /* MNG config cycle done */
 614 #define E1000_NVM_CFG_DONE_PORT_1  0x80000 /* ...for second port */
 615
 616 /* Mask bits for fields in Word 0x0f of the NVM */
 617 #define NVM_WORD0F_PAUSE_MASK       0x3000
 618 #define NVM_WORD0F_PAUSE            0x1000
 619 #define NVM_WORD0F_ASM_DIR          0x2000
 620
 621 /* Mask bits for fields in Word 0x1a of the NVM */
 622 #define NVM_WORD1A_ASPM_MASK  0x000C
 623
 624 /* Mask bits for fields in Word 0x03 of the EEPROM */
 625 #define NVM_COMPAT_LOM    0x0800
 626
 627 /* length of string needed to store PBA number */
 628 #define E1000_PBANUM_LENGTH             11
 629
 630 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
 631 #define NVM_SUM                    0xBABA
 632
 633 /* PBA (printed board assembly) number words */
 634 #define NVM_PBA_OFFSET_0           8
 635 #define NVM_PBA_OFFSET_1           9
 636 #define NVM_PBA_PTR_GUARD          0xFAFA
 637 #define NVM_WORD_SIZE_BASE_SHIFT   6
 638
 639 /* NVM Commands - SPI */
 640 #define NVM_MAX_RETRY_SPI          5000 /* Max wait of 5ms, for RDY signal */
 641 #define NVM_READ_OPCODE_SPI        0x03 /* NVM read opcode */
 642 #define NVM_WRITE_OPCODE_SPI       0x02 /* NVM write opcode */
 643 #define NVM_A8_OPCODE_SPI          0x08 /* opcode bit-3 = address bit-8 */
 644 #define NVM_WREN_OPCODE_SPI        0x06 /* NVM set Write Enable latch */
 645 #define NVM_RDSR_OPCODE_SPI        0x05 /* NVM read Status register */
 646
 647 /* SPI NVM Status Register */
 648 #define NVM_STATUS_RDY_SPI         0x01
 649
 650 /* Word definitions for ID LED Settings */
 651 #define ID_LED_RESERVED_0000 0x0000
 652 #define ID_LED_RESERVED_FFFF 0xFFFF
 653 #define ID_LED_DEFAULT       ((ID_LED_OFF1_ON2  << 12) | \
 654                               (ID_LED_OFF1_OFF2 <<  8) | \
 655                               (ID_LED_DEF1_DEF2 <<  4) | \
 656                               (ID_LED_DEF1_DEF2))
 657 #define ID_LED_DEF1_DEF2     0x1
 658 #define ID_LED_DEF1_ON2      0x2
 659 #define ID_LED_DEF1_OFF2     0x3
 660 #define ID_LED_ON1_DEF2      0x4
 661 #define ID_LED_ON1_ON2       0x5
 662 #define ID_LED_ON1_OFF2      0x6
 663 #define ID_LED_OFF1_DEF2     0x7
 664 #define ID_LED_OFF1_ON2      0x8
 665 #define ID_LED_OFF1_OFF2     0x9
 666
 667 #define IGP_ACTIVITY_LED_MASK   0xFFFFF0FF
 668 #define IGP_ACTIVITY_LED_ENABLE 0x0300
 669 #define IGP_LED3_MODE           0x07000000
 670
 671 /* PCI/PCI-X/PCI-EX Config space */
 672 #define PCI_HEADER_TYPE_REGISTER     0x0E
 673 #define PCIE_LINK_STATUS             0x12
 674
 675 #define PCI_HEADER_TYPE_MULTIFUNC    0x80
 676 #define PCIE_LINK_WIDTH_MASK         0x3F0
 677 #define PCIE_LINK_WIDTH_SHIFT        4
 678
 679 #define PHY_REVISION_MASK      0xFFFFFFF0
 680 #define MAX_PHY_REG_ADDRESS    0x1F  /* 5 bit address bus (0-0x1F) */
 681 #define MAX_PHY_MULTI_PAGE_REG 0xF
 682
 683 /* Bit definitions for valid PHY IDs.
 684  * I = Integrated
 685  * E = External
 686  */
 687 #define M88E1000_E_PHY_ID    0x01410C50
 688 #define M88E1000_I_PHY_ID    0x01410C30
 689 #define M88E1011_I_PHY_ID    0x01410C20
 690 #define IGP01E1000_I_PHY_ID  0x02A80380
 691 #define M88E1111_I_PHY_ID    0x01410CC0
 692 #define GG82563_E_PHY_ID     0x01410CA0
 693 #define IGP03E1000_E_PHY_ID  0x02A80390
 694 #define IFE_E_PHY_ID         0x02A80330
 695 #define IFE_PLUS_E_PHY_ID    0x02A80320
 696 #define IFE_C_E_PHY_ID       0x02A80310
 697 #define BME1000_E_PHY_ID     0x01410CB0
 698 #define BME1000_E_PHY_ID_R2  0x01410CB1
 699 #define I82577_E_PHY_ID      0x01540050
 700 #define I82578_E_PHY_ID      0x004DD040
 701 #define I82579_E_PHY_ID      0x01540090
 702 #define I217_E_PHY_ID        0x015400A0
 703
 704 /* M88E1000 Specific Registers */
 705 #define M88E1000_PHY_SPEC_CTRL     0x10  /* PHY Specific Control Register */
 706 #define M88E1000_PHY_SPEC_STATUS   0x11  /* PHY Specific Status Register */
 707 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14  /* Extended PHY Specific Control */
 708
 709 #define M88E1000_PHY_PAGE_SELECT   0x1D  /* Reg 29 for page number setting */
 710 #define M88E1000_PHY_GEN_CONTROL   0x1E  /* Its meaning depends on reg 29 */
 711
 712 /* M88E1000 PHY Specific Control Register */
 713 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
 714 #define M88E1000_PSCR_MDI_MANUAL_MODE  0x0000  /* MDI Crossover Mode bits 6:5 */
 715                                                /* Manual MDI configuration */
 716 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020  /* Manual MDIX configuration */
 717 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
 718 #define M88E1000_PSCR_AUTO_X_1000T     0x0040
 719 /* Auto crossover enabled all speeds */
 720 #define M88E1000_PSCR_AUTO_X_MODE      0x0060
 721 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
 722
 723 /* M88E1000 PHY Specific Status Register */
 724 #define M88E1000_PSSR_REV_POLARITY       0x0002 /* 1=Polarity reversed */
 725 #define M88E1000_PSSR_DOWNSHIFT          0x0020 /* 1=Downshifted */
 726 #define M88E1000_PSSR_MDIX               0x0040 /* 1=MDIX; 0=MDI */
 727 /* 0=<50M; 1=50-80M; 2=80-110M; 3=110-140M; 4=>140M */
 728 #define M88E1000_PSSR_CABLE_LENGTH       0x0380
 729 #define M88E1000_PSSR_SPEED              0xC000 /* Speed, bits 14:15 */
 730 #define M88E1000_PSSR_1000MBS            0x8000 /* 10=1000Mbs */
 731
 732 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
 733
 734 /* Number of times we will attempt to autonegotiate before downshifting if we
 735  * are the master
 736  */
 737 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
 738 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X   0x0000
 739 /* Number of times we will attempt to autonegotiate before downshifting if we
 740  * are the slave
 741  */
 742 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK  0x0300
 743 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X    0x0100
 744 #define M88E1000_EPSCR_TX_CLK_25      0x0070 /* 25  MHz TX_CLK */
 745
 746 /* M88EC018 Rev 2 specific DownShift settings */
 747 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK  0x0E00
 748 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X    0x0800
 749
 750 #define I82578_EPSCR_DOWNSHIFT_ENABLE          0x0020
 751 #define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK    0x001C
 752
 753 /* BME1000 PHY Specific Control Register */
 754 #define BME1000_PSCR_ENABLE_DOWNSHIFT   0x0800 /* 1 = enable downshift */
 755
 756 /* Bits...
 757  * 15-5: page
 758  * 4-0: register offset
 759  */
 760 #define GG82563_PAGE_SHIFT        5
 761 #define GG82563_REG(page, reg)    \
 762         (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
 763 #define GG82563_MIN_ALT_REG       30
 764
 765 /* GG82563 Specific Registers */
 766 #define GG82563_PHY_SPEC_CTRL           \
 767         GG82563_REG(0, 16) /* PHY Specific Control */
 768 #define GG82563_PHY_PAGE_SELECT         \
 769         GG82563_REG(0, 22) /* Page Select */
 770 #define GG82563_PHY_SPEC_CTRL_2         \
 771         GG82563_REG(0, 26) /* PHY Specific Control 2 */
 772 #define GG82563_PHY_PAGE_SELECT_ALT     \
 773         GG82563_REG(0, 29) /* Alternate Page Select */
 774
 775 #define GG82563_PHY_MAC_SPEC_CTRL       \
 776         GG82563_REG(2, 21) /* MAC Specific Control Register */
 777
 778 #define GG82563_PHY_DSP_DISTANCE    \
 779         GG82563_REG(5, 26) /* DSP Distance */
 780
 781 /* Page 193 - Port Control Registers */
 782 #define GG82563_PHY_KMRN_MODE_CTRL   \
 783         GG82563_REG(193, 16) /* Kumeran Mode Control */
 784 #define GG82563_PHY_PWR_MGMT_CTRL       \
 785         GG82563_REG(193, 20) /* Power Management Control */
 786
 787 /* Page 194 - KMRN Registers */
 788 #define GG82563_PHY_INBAND_CTRL         \
 789         GG82563_REG(194, 18) /* Inband Control */
 790
 791 /* MDI Control */
 792 #define E1000_MDIC_REG_MASK     0x001F0000
 793 #define E1000_MDIC_REG_SHIFT 16
 794 #define E1000_MDIC_PHY_SHIFT 21
 795 #define E1000_MDIC_OP_WRITE  0x04000000
 796 #define E1000_MDIC_OP_READ   0x08000000
 797 #define E1000_MDIC_READY     0x10000000
 798 #define E1000_MDIC_ERROR     0x40000000
 799
 800 /* SerDes Control */
 801 #define E1000_GEN_POLL_TIMEOUT          640
 802
 803 #endif /* _E1000_DEFINES_H_ */