drivers/net/ethernet/intel/e1000e/hw.h

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2013 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 #ifndef _E1000_HW_H_
  30 #define _E1000_HW_H_
  31
  32 #include "regs.h"
  33 #include "defines.h"
  34
  35 struct e1000_hw;
  36
  37 #define E1000_DEV_ID_82571EB_COPPER             0x105E
  38 #define E1000_DEV_ID_82571EB_FIBER              0x105F
  39 #define E1000_DEV_ID_82571EB_SERDES             0x1060
  40 #define E1000_DEV_ID_82571EB_QUAD_COPPER        0x10A4
  41 #define E1000_DEV_ID_82571PT_QUAD_COPPER        0x10D5
  42 #define E1000_DEV_ID_82571EB_QUAD_FIBER         0x10A5
  43 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP     0x10BC
  44 #define E1000_DEV_ID_82571EB_SERDES_DUAL        0x10D9
  45 #define E1000_DEV_ID_82571EB_SERDES_QUAD        0x10DA
  46 #define E1000_DEV_ID_82572EI_COPPER             0x107D
  47 #define E1000_DEV_ID_82572EI_FIBER              0x107E
  48 #define E1000_DEV_ID_82572EI_SERDES             0x107F
  49 #define E1000_DEV_ID_82572EI                    0x10B9
  50 #define E1000_DEV_ID_82573E                     0x108B
  51 #define E1000_DEV_ID_82573E_IAMT                0x108C
  52 #define E1000_DEV_ID_82573L                     0x109A
  53 #define E1000_DEV_ID_82574L                     0x10D3
  54 #define E1000_DEV_ID_82574LA                    0x10F6
  55 #define E1000_DEV_ID_82583V                     0x150C
  56 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT     0x1096
  57 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT     0x1098
  58 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT     0x10BA
  59 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT     0x10BB
  60 #define E1000_DEV_ID_ICH8_82567V_3              0x1501
  61 #define E1000_DEV_ID_ICH8_IGP_M_AMT             0x1049
  62 #define E1000_DEV_ID_ICH8_IGP_AMT               0x104A
  63 #define E1000_DEV_ID_ICH8_IGP_C                 0x104B
  64 #define E1000_DEV_ID_ICH8_IFE                   0x104C
  65 #define E1000_DEV_ID_ICH8_IFE_GT                0x10C4
  66 #define E1000_DEV_ID_ICH8_IFE_G                 0x10C5
  67 #define E1000_DEV_ID_ICH8_IGP_M                 0x104D
  68 #define E1000_DEV_ID_ICH9_IGP_AMT               0x10BD
  69 #define E1000_DEV_ID_ICH9_BM                    0x10E5
  70 #define E1000_DEV_ID_ICH9_IGP_M_AMT             0x10F5
  71 #define E1000_DEV_ID_ICH9_IGP_M                 0x10BF
  72 #define E1000_DEV_ID_ICH9_IGP_M_V               0x10CB
  73 #define E1000_DEV_ID_ICH9_IGP_C                 0x294C
  74 #define E1000_DEV_ID_ICH9_IFE                   0x10C0
  75 #define E1000_DEV_ID_ICH9_IFE_GT                0x10C3
  76 #define E1000_DEV_ID_ICH9_IFE_G                 0x10C2
  77 #define E1000_DEV_ID_ICH10_R_BM_LM              0x10CC
  78 #define E1000_DEV_ID_ICH10_R_BM_LF              0x10CD
  79 #define E1000_DEV_ID_ICH10_R_BM_V               0x10CE
  80 #define E1000_DEV_ID_ICH10_D_BM_LM              0x10DE
  81 #define E1000_DEV_ID_ICH10_D_BM_LF              0x10DF
  82 #define E1000_DEV_ID_ICH10_D_BM_V               0x1525
  83 #define E1000_DEV_ID_PCH_M_HV_LM                0x10EA
  84 #define E1000_DEV_ID_PCH_M_HV_LC                0x10EB
  85 #define E1000_DEV_ID_PCH_D_HV_DM                0x10EF
  86 #define E1000_DEV_ID_PCH_D_HV_DC                0x10F0
  87 #define E1000_DEV_ID_PCH2_LV_LM                 0x1502
  88 #define E1000_DEV_ID_PCH2_LV_V                  0x1503
  89 #define E1000_DEV_ID_PCH_LPT_I217_LM            0x153A
  90 #define E1000_DEV_ID_PCH_LPT_I217_V             0x153B
  91 #define E1000_DEV_ID_PCH_LPTLP_I218_LM          0x155A
  92 #define E1000_DEV_ID_PCH_LPTLP_I218_V           0x1559
  93
  94 #define E1000_REVISION_4        4
  95
  96 #define E1000_FUNC_1            1
  97
  98 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0       0
  99 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1       3
 100
 101 enum e1000_mac_type {
 102         e1000_82571,
 103         e1000_82572,
 104         e1000_82573,
 105         e1000_82574,
 106         e1000_82583,
 107         e1000_80003es2lan,
 108         e1000_ich8lan,
 109         e1000_ich9lan,
 110         e1000_ich10lan,
 111         e1000_pchlan,
 112         e1000_pch2lan,
 113         e1000_pch_lpt,
 114 };
 115
 116 enum e1000_media_type {
 117         e1000_media_type_unknown = 0,
 118         e1000_media_type_copper = 1,
 119         e1000_media_type_fiber = 2,
 120         e1000_media_type_internal_serdes = 3,
 121         e1000_num_media_types
 122 };
 123
 124 enum e1000_nvm_type {
 125         e1000_nvm_unknown = 0,
 126         e1000_nvm_none,
 127         e1000_nvm_eeprom_spi,
 128         e1000_nvm_flash_hw,
 129         e1000_nvm_flash_sw
 130 };
 131
 132 enum e1000_nvm_override {
 133         e1000_nvm_override_none = 0,
 134         e1000_nvm_override_spi_small,
 135         e1000_nvm_override_spi_large
 136 };
 137
 138 enum e1000_phy_type {
 139         e1000_phy_unknown = 0,
 140         e1000_phy_none,
 141         e1000_phy_m88,
 142         e1000_phy_igp,
 143         e1000_phy_igp_2,
 144         e1000_phy_gg82563,
 145         e1000_phy_igp_3,
 146         e1000_phy_ife,
 147         e1000_phy_bm,
 148         e1000_phy_82578,
 149         e1000_phy_82577,
 150         e1000_phy_82579,
 151         e1000_phy_i217,
 152 };
 153
 154 enum e1000_bus_width {
 155         e1000_bus_width_unknown = 0,
 156         e1000_bus_width_pcie_x1,
 157         e1000_bus_width_pcie_x2,
 158         e1000_bus_width_pcie_x4 = 4,
 159         e1000_bus_width_32,
 160         e1000_bus_width_64,
 161         e1000_bus_width_reserved
 162 };
 163
 164 enum e1000_1000t_rx_status {
 165         e1000_1000t_rx_status_not_ok = 0,
 166         e1000_1000t_rx_status_ok,
 167         e1000_1000t_rx_status_undefined = 0xFF
 168 };
 169
 170 enum e1000_rev_polarity {
 171         e1000_rev_polarity_normal = 0,
 172         e1000_rev_polarity_reversed,
 173         e1000_rev_polarity_undefined = 0xFF
 174 };
 175
 176 enum e1000_fc_mode {
 177         e1000_fc_none = 0,
 178         e1000_fc_rx_pause,
 179         e1000_fc_tx_pause,
 180         e1000_fc_full,
 181         e1000_fc_default = 0xFF
 182 };
 183
 184 enum e1000_ms_type {
 185         e1000_ms_hw_default = 0,
 186         e1000_ms_force_master,
 187         e1000_ms_force_slave,
 188         e1000_ms_auto
 189 };
 190
 191 enum e1000_smart_speed {
 192         e1000_smart_speed_default = 0,
 193         e1000_smart_speed_on,
 194         e1000_smart_speed_off
 195 };
 196
 197 enum e1000_serdes_link_state {
 198         e1000_serdes_link_down = 0,
 199         e1000_serdes_link_autoneg_progress,
 200         e1000_serdes_link_autoneg_complete,
 201         e1000_serdes_link_forced_up
 202 };
 203
 204 /* Receive Descriptor - Extended */
 205 union e1000_rx_desc_extended {
 206         struct {
 207                 __le64 buffer_addr;
 208                 __le64 reserved;
 209         } read;
 210         struct {
 211                 struct {
 212                         __le32 mrq;           /* Multiple Rx Queues */
 213                         union {
 214                                 __le32 rss;         /* RSS Hash */
 215                                 struct {
 216                                         __le16 ip_id;  /* IP id */
 217                                         __le16 csum;   /* Packet Checksum */
 218                                 } csum_ip;
 219                         } hi_dword;
 220                 } lower;
 221                 struct {
 222                         __le32 status_error;     /* ext status/error */
 223                         __le16 length;
 224                         __le16 vlan;         /* VLAN tag */
 225                 } upper;
 226         } wb;  /* writeback */
 227 };
 228
 229 #define MAX_PS_BUFFERS 4
 230 /* Receive Descriptor - Packet Split */
 231 union e1000_rx_desc_packet_split {
 232         struct {
 233                 /* one buffer for protocol header(s), three data buffers */
 234                 __le64 buffer_addr[MAX_PS_BUFFERS];
 235         } read;
 236         struct {
 237                 struct {
 238                         __le32 mrq;           /* Multiple Rx Queues */
 239                         union {
 240                                 __le32 rss;           /* RSS Hash */
 241                                 struct {
 242                                         __le16 ip_id;    /* IP id */
 243                                         __le16 csum;     /* Packet Checksum */
 244                                 } csum_ip;
 245                         } hi_dword;
 246                 } lower;
 247                 struct {
 248                         __le32 status_error;     /* ext status/error */
 249                         __le16 length0;   /* length of buffer 0 */
 250                         __le16 vlan;         /* VLAN tag */
 251                 } middle;
 252                 struct {
 253                         __le16 header_status;
 254                         __le16 length[3];       /* length of buffers 1-3 */
 255                 } upper;
 256                 __le64 reserved;
 257         } wb; /* writeback */
 258 };
 259
 260 /* Transmit Descriptor */
 261 struct e1000_tx_desc {
 262         __le64 buffer_addr;      /* Address of the descriptor's data buffer */
 263         union {
 264                 __le32 data;
 265                 struct {
 266                         __le16 length;    /* Data buffer length */
 267                         u8 cso; /* Checksum offset */
 268                         u8 cmd; /* Descriptor control */
 269                 } flags;
 270         } lower;
 271         union {
 272                 __le32 data;
 273                 struct {
 274                         u8 status;     /* Descriptor status */
 275                         u8 css; /* Checksum start */
 276                         __le16 special;
 277                 } fields;
 278         } upper;
 279 };
 280
 281 /* Offload Context Descriptor */
 282 struct e1000_context_desc {
 283         union {
 284                 __le32 ip_config;
 285                 struct {
 286                         u8 ipcss;      /* IP checksum start */
 287                         u8 ipcso;      /* IP checksum offset */
 288                         __le16 ipcse;     /* IP checksum end */
 289                 } ip_fields;
 290         } lower_setup;
 291         union {
 292                 __le32 tcp_config;
 293                 struct {
 294                         u8 tucss;      /* TCP checksum start */
 295                         u8 tucso;      /* TCP checksum offset */
 296                         __le16 tucse;     /* TCP checksum end */
 297                 } tcp_fields;
 298         } upper_setup;
 299         __le32 cmd_and_length;
 300         union {
 301                 __le32 data;
 302                 struct {
 303                         u8 status;     /* Descriptor status */
 304                         u8 hdr_len;    /* Header length */
 305                         __le16 mss;       /* Maximum segment size */
 306                 } fields;
 307         } tcp_seg_setup;
 308 };
 309
 310 /* Offload data descriptor */
 311 struct e1000_data_desc {
 312         __le64 buffer_addr;   /* Address of the descriptor's buffer address */
 313         union {
 314                 __le32 data;
 315                 struct {
 316                         __le16 length;    /* Data buffer length */
 317                         u8 typ_len_ext;
 318                         u8 cmd;
 319                 } flags;
 320         } lower;
 321         union {
 322                 __le32 data;
 323                 struct {
 324                         u8 status;     /* Descriptor status */
 325                         u8 popts;      /* Packet Options */
 326                         __le16 special;
 327                 } fields;
 328         } upper;
 329 };
 330
 331 /* Statistics counters collected by the MAC */
 332 struct e1000_hw_stats {
 333         u64 crcerrs;
 334         u64 algnerrc;
 335         u64 symerrs;
 336         u64 rxerrc;
 337         u64 mpc;
 338         u64 scc;
 339         u64 ecol;
 340         u64 mcc;
 341         u64 latecol;
 342         u64 colc;
 343         u64 dc;
 344         u64 tncrs;
 345         u64 sec;
 346         u64 cexterr;
 347         u64 rlec;
 348         u64 xonrxc;
 349         u64 xontxc;
 350         u64 xoffrxc;
 351         u64 xofftxc;
 352         u64 fcruc;
 353         u64 prc64;
 354         u64 prc127;
 355         u64 prc255;
 356         u64 prc511;
 357         u64 prc1023;
 358         u64 prc1522;
 359         u64 gprc;
 360         u64 bprc;
 361         u64 mprc;
 362         u64 gptc;
 363         u64 gorc;
 364         u64 gotc;
 365         u64 rnbc;
 366         u64 ruc;
 367         u64 rfc;
 368         u64 roc;
 369         u64 rjc;
 370         u64 mgprc;
 371         u64 mgpdc;
 372         u64 mgptc;
 373         u64 tor;
 374         u64 tot;
 375         u64 tpr;
 376         u64 tpt;
 377         u64 ptc64;
 378         u64 ptc127;
 379         u64 ptc255;
 380         u64 ptc511;
 381         u64 ptc1023;
 382         u64 ptc1522;
 383         u64 mptc;
 384         u64 bptc;
 385         u64 tsctc;
 386         u64 tsctfc;
 387         u64 iac;
 388         u64 icrxptc;
 389         u64 icrxatc;
 390         u64 ictxptc;
 391         u64 ictxatc;
 392         u64 ictxqec;
 393         u64 ictxqmtc;
 394         u64 icrxdmtc;
 395         u64 icrxoc;
 396 };
 397
 398 struct e1000_phy_stats {
 399         u32 idle_errors;
 400         u32 receive_errors;
 401 };
 402
 403 struct e1000_host_mng_dhcp_cookie {
 404         u32 signature;
 405         u8 status;
 406         u8 reserved0;
 407         u16 vlan_id;
 408         u32 reserved1;
 409         u16 reserved2;
 410         u8 reserved3;
 411         u8 checksum;
 412 };
 413
 414 /* Host Interface "Rev 1" */
 415 struct e1000_host_command_header {
 416         u8 command_id;
 417         u8 command_length;
 418         u8 command_options;
 419         u8 checksum;
 420 };
 421
 422 #define E1000_HI_MAX_DATA_LENGTH        252
 423 struct e1000_host_command_info {
 424         struct e1000_host_command_header command_header;
 425         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
 426 };
 427
 428 /* Host Interface "Rev 2" */
 429 struct e1000_host_mng_command_header {
 430         u8 command_id;
 431         u8 checksum;
 432         u16 reserved1;
 433         u16 reserved2;
 434         u16 command_length;
 435 };
 436
 437 #define E1000_HI_MAX_MNG_DATA_LENGTH    0x6F8
 438 struct e1000_host_mng_command_info {
 439         struct e1000_host_mng_command_header command_header;
 440         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
 441 };
 442
 443 #include "mac.h"
 444 #include "phy.h"
 445 #include "nvm.h"
 446 #include "manage.h"
 447
 448 /* Function pointers for the MAC. */
 449 struct e1000_mac_operations {
 450         s32  (*id_led_init)(struct e1000_hw *);
 451         s32  (*blink_led)(struct e1000_hw *);
 452         bool (*check_mng_mode)(struct e1000_hw *);
 453         s32  (*check_for_link)(struct e1000_hw *);
 454         s32  (*cleanup_led)(struct e1000_hw *);
 455         void (*clear_hw_cntrs)(struct e1000_hw *);
 456         void (*clear_vfta)(struct e1000_hw *);
 457         s32  (*get_bus_info)(struct e1000_hw *);
 458         void (*set_lan_id)(struct e1000_hw *);
 459         s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
 460         s32  (*led_on)(struct e1000_hw *);
 461         s32  (*led_off)(struct e1000_hw *);
 462         void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
 463         s32  (*reset_hw)(struct e1000_hw *);
 464         s32  (*init_hw)(struct e1000_hw *);
 465         s32  (*setup_link)(struct e1000_hw *);
 466         s32  (*setup_physical_interface)(struct e1000_hw *);
 467         s32  (*setup_led)(struct e1000_hw *);
 468         void (*write_vfta)(struct e1000_hw *, u32, u32);
 469         void (*config_collision_dist)(struct e1000_hw *);
 470         void (*rar_set)(struct e1000_hw *, u8 *, u32);
 471         s32  (*read_mac_addr)(struct e1000_hw *);
 472 };
 473
 474 /* When to use various PHY register access functions:
 475  *
 476  *                 Func   Caller
 477  *   Function      Does   Does    When to use
 478  *   ~~~~~~~~~~~~  ~~~~~  ~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 479  *   X_reg         L,P,A  n/a     for simple PHY reg accesses
 480  *   X_reg_locked  P,A    L       for multiple accesses of different regs
 481  *                                on different pages
 482  *   X_reg_page    A      L,P     for multiple accesses of different regs
 483  *                                on the same page
 484  *
 485  * Where X=[read|write], L=locking, P=sets page, A=register access
 486  *
 487  */
 488 struct e1000_phy_operations {
 489         s32  (*acquire)(struct e1000_hw *);
 490         s32  (*cfg_on_link_up)(struct e1000_hw *);
 491         s32  (*check_polarity)(struct e1000_hw *);
 492         s32  (*check_reset_block)(struct e1000_hw *);
 493         s32  (*commit)(struct e1000_hw *);
 494         s32  (*force_speed_duplex)(struct e1000_hw *);
 495         s32  (*get_cfg_done)(struct e1000_hw *hw);
 496         s32  (*get_cable_length)(struct e1000_hw *);
 497         s32  (*get_info)(struct e1000_hw *);
 498         s32  (*set_page)(struct e1000_hw *, u16);
 499         s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
 500         s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
 501         s32  (*read_reg_page)(struct e1000_hw *, u32, u16 *);
 502         void (*release)(struct e1000_hw *);
 503         s32  (*reset)(struct e1000_hw *);
 504         s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
 505         s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
 506         s32  (*write_reg)(struct e1000_hw *, u32, u16);
 507         s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
 508         s32  (*write_reg_page)(struct e1000_hw *, u32, u16);
 509         void (*power_up)(struct e1000_hw *);
 510         void (*power_down)(struct e1000_hw *);
 511 };
 512
 513 /* Function pointers for the NVM. */
 514 struct e1000_nvm_operations {
 515         s32  (*acquire)(struct e1000_hw *);
 516         s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
 517         void (*release)(struct e1000_hw *);
 518         void (*reload)(struct e1000_hw *);
 519         s32  (*update)(struct e1000_hw *);
 520         s32  (*valid_led_default)(struct e1000_hw *, u16 *);
 521         s32  (*validate)(struct e1000_hw *);
 522         s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
 523 };
 524
 525 struct e1000_mac_info {
 526         struct e1000_mac_operations ops;
 527         u8 addr[ETH_ALEN];
 528         u8 perm_addr[ETH_ALEN];
 529
 530         enum e1000_mac_type type;
 531
 532         u32 collision_delta;
 533         u32 ledctl_default;
 534         u32 ledctl_mode1;
 535         u32 ledctl_mode2;
 536         u32 mc_filter_type;
 537         u32 tx_packet_delta;
 538         u32 txcw;
 539
 540         u16 current_ifs_val;
 541         u16 ifs_max_val;
 542         u16 ifs_min_val;
 543         u16 ifs_ratio;
 544         u16 ifs_step_size;
 545         u16 mta_reg_count;
 546
 547         /* Maximum size of the MTA register table in all supported adapters */
 548 #define MAX_MTA_REG 128
 549         u32 mta_shadow[MAX_MTA_REG];
 550         u16 rar_entry_count;
 551
 552         u8 forced_speed_duplex;
 553
 554         bool adaptive_ifs;
 555         bool has_fwsm;
 556         bool arc_subsystem_valid;
 557         bool autoneg;
 558         bool autoneg_failed;
 559         bool get_link_status;
 560         bool in_ifs_mode;
 561         bool serdes_has_link;
 562         bool tx_pkt_filtering;
 563         enum e1000_serdes_link_state serdes_link_state;
 564 };
 565
 566 struct e1000_phy_info {
 567         struct e1000_phy_operations ops;
 568
 569         enum e1000_phy_type type;
 570
 571         enum e1000_1000t_rx_status local_rx;
 572         enum e1000_1000t_rx_status remote_rx;
 573         enum e1000_ms_type ms_type;
 574         enum e1000_ms_type original_ms_type;
 575         enum e1000_rev_polarity cable_polarity;
 576         enum e1000_smart_speed smart_speed;
 577
 578         u32 addr;
 579         u32 id;
 580         u32 reset_delay_us;     /* in usec */
 581         u32 revision;
 582
 583         enum e1000_media_type media_type;
 584
 585         u16 autoneg_advertised;
 586         u16 autoneg_mask;
 587         u16 cable_length;
 588         u16 max_cable_length;
 589         u16 min_cable_length;
 590
 591         u8 mdix;
 592
 593         bool disable_polarity_correction;
 594         bool is_mdix;
 595         bool polarity_correction;
 596         bool speed_downgraded;
 597         bool autoneg_wait_to_complete;
 598 };
 599
 600 struct e1000_nvm_info {
 601         struct e1000_nvm_operations ops;
 602
 603         enum e1000_nvm_type type;
 604         enum e1000_nvm_override override;
 605
 606         u32 flash_bank_size;
 607         u32 flash_base_addr;
 608
 609         u16 word_size;
 610         u16 delay_usec;
 611         u16 address_bits;
 612         u16 opcode_bits;
 613         u16 page_size;
 614 };
 615
 616 struct e1000_bus_info {
 617         enum e1000_bus_width width;
 618
 619         u16 func;
 620 };
 621
 622 struct e1000_fc_info {
 623         u32 high_water;          /* Flow control high-water mark */
 624         u32 low_water;           /* Flow control low-water mark */
 625         u16 pause_time;          /* Flow control pause timer */
 626         u16 refresh_time;        /* Flow control refresh timer */
 627         bool send_xon;           /* Flow control send XON */
 628         bool strict_ieee;        /* Strict IEEE mode */
 629         enum e1000_fc_mode current_mode; /* FC mode in effect */
 630         enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
 631 };
 632
 633 struct e1000_dev_spec_82571 {
 634         bool laa_is_present;
 635         u32 smb_counter;
 636 };
 637
 638 struct e1000_dev_spec_80003es2lan {
 639         bool mdic_wa_enable;
 640 };
 641
 642 struct e1000_shadow_ram {
 643         u16 value;
 644         bool modified;
 645 };
 646
 647 #define E1000_ICH8_SHADOW_RAM_WORDS             2048
 648
 649 struct e1000_dev_spec_ich8lan {
 650         bool kmrn_lock_loss_workaround_enabled;
 651         struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
 652         bool nvm_k1_enabled;
 653         bool eee_disable;
 654         u16 eee_lp_ability;
 655 };
 656
 657 struct e1000_hw {
 658         struct e1000_adapter *adapter;
 659
 660         void __iomem *hw_addr;
 661         void __iomem *flash_address;
 662
 663         struct e1000_mac_info mac;
 664         struct e1000_fc_info fc;
 665         struct e1000_phy_info phy;
 666         struct e1000_nvm_info nvm;
 667         struct e1000_bus_info bus;
 668         struct e1000_host_mng_dhcp_cookie mng_cookie;
 669
 670         union {
 671                 struct e1000_dev_spec_82571 e82571;
 672                 struct e1000_dev_spec_80003es2lan e80003es2lan;
 673                 struct e1000_dev_spec_ich8lan ich8lan;
 674         } dev_spec;
 675 };
 676
 677 #include "82571.h"
 678 #include "80003es2lan.h"
 679 #include "ich8lan.h"
 680
 681 #endif