1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
29 /* 82562G 10/100 Network Connection
30 * 82562G-2 10/100 Network Connection
31 * 82562GT 10/100 Network Connection
32 * 82562GT-2 10/100 Network Connection
33 * 82562V 10/100 Network Connection
34 * 82562V-2 10/100 Network Connection
35 * 82566DC-2 Gigabit Network Connection
36 * 82566DC Gigabit Network Connection
37 * 82566DM-2 Gigabit Network Connection
38 * 82566DM Gigabit Network Connection
39 * 82566MC Gigabit Network Connection
40 * 82566MM Gigabit Network Connection
41 * 82567LM Gigabit Network Connection
42 * 82567LF Gigabit Network Connection
43 * 82567V Gigabit Network Connection
44 * 82567LM-2 Gigabit Network Connection
45 * 82567LF-2 Gigabit Network Connection
46 * 82567V-2 Gigabit Network Connection
47 * 82567LF-3 Gigabit Network Connection
48 * 82567LM-3 Gigabit Network Connection
49 * 82567LM-4 Gigabit Network Connection
50 * 82577LM Gigabit Network Connection
51 * 82577LC Gigabit Network Connection
52 * 82578DM Gigabit Network Connection
53 * 82578DC Gigabit Network Connection
54 * 82579LM Gigabit Network Connection
55 * 82579V Gigabit Network Connection
60 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
61 /* Offset 04h HSFSTS */
62 union ich8_hws_flash_status
{
64 u16 flcdone
:1; /* bit 0 Flash Cycle Done */
65 u16 flcerr
:1; /* bit 1 Flash Cycle Error */
66 u16 dael
:1; /* bit 2 Direct Access error Log */
67 u16 berasesz
:2; /* bit 4:3 Sector Erase Size */
68 u16 flcinprog
:1; /* bit 5 flash cycle in Progress */
69 u16 reserved1
:2; /* bit 13:6 Reserved */
70 u16 reserved2
:6; /* bit 13:6 Reserved */
71 u16 fldesvalid
:1; /* bit 14 Flash Descriptor Valid */
72 u16 flockdn
:1; /* bit 15 Flash Config Lock-Down */
77 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
78 /* Offset 06h FLCTL */
79 union ich8_hws_flash_ctrl
{
81 u16 flcgo
:1; /* 0 Flash Cycle Go */
82 u16 flcycle
:2; /* 2:1 Flash Cycle */
83 u16 reserved
:5; /* 7:3 Reserved */
84 u16 fldbcount
:2; /* 9:8 Flash Data Byte Count */
85 u16 flockdn
:6; /* 15:10 Reserved */
90 /* ICH Flash Region Access Permissions */
91 union ich8_hws_flash_regacc
{
93 u32 grra
:8; /* 0:7 GbE region Read Access */
94 u32 grwa
:8; /* 8:15 GbE region Write Access */
95 u32 gmrag
:8; /* 23:16 GbE Master Read Access Grant */
96 u32 gmwag
:8; /* 31:24 GbE Master Write Access Grant */
101 /* ICH Flash Protected Region */
102 union ich8_flash_protected_range
{
104 u32 base
:13; /* 0:12 Protected Range Base */
105 u32 reserved1
:2; /* 13:14 Reserved */
106 u32 rpe
:1; /* 15 Read Protection Enable */
107 u32 limit
:13; /* 16:28 Protected Range Limit */
108 u32 reserved2
:2; /* 29:30 Reserved */
109 u32 wpe
:1; /* 31 Write Protection Enable */
114 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw
*hw
);
115 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw
*hw
);
116 static s32
e1000_erase_flash_bank_ich8lan(struct e1000_hw
*hw
, u32 bank
);
117 static s32
e1000_retry_write_flash_byte_ich8lan(struct e1000_hw
*hw
,
118 u32 offset
, u8 byte
);
119 static s32
e1000_read_flash_byte_ich8lan(struct e1000_hw
*hw
, u32 offset
,
121 static s32
e1000_read_flash_word_ich8lan(struct e1000_hw
*hw
, u32 offset
,
123 static s32
e1000_read_flash_data_ich8lan(struct e1000_hw
*hw
, u32 offset
,
125 static s32
e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw
*hw
);
126 static s32
e1000_cleanup_led_ich8lan(struct e1000_hw
*hw
);
127 static s32
e1000_led_on_ich8lan(struct e1000_hw
*hw
);
128 static s32
e1000_led_off_ich8lan(struct e1000_hw
*hw
);
129 static s32
e1000_id_led_init_pchlan(struct e1000_hw
*hw
);
130 static s32
e1000_setup_led_pchlan(struct e1000_hw
*hw
);
131 static s32
e1000_cleanup_led_pchlan(struct e1000_hw
*hw
);
132 static s32
e1000_led_on_pchlan(struct e1000_hw
*hw
);
133 static s32
e1000_led_off_pchlan(struct e1000_hw
*hw
);
134 static s32
e1000_set_lplu_state_pchlan(struct e1000_hw
*hw
, bool active
);
135 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw
*hw
);
136 static void e1000_lan_init_done_ich8lan(struct e1000_hw
*hw
);
137 static s32
e1000_k1_gig_workaround_hv(struct e1000_hw
*hw
, bool link
);
138 static s32
e1000_set_mdio_slow_mode_hv(struct e1000_hw
*hw
);
139 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw
*hw
);
140 static bool e1000_check_mng_mode_pchlan(struct e1000_hw
*hw
);
141 static void e1000_rar_set_pch2lan(struct e1000_hw
*hw
, u8
*addr
, u32 index
);
142 static void e1000_rar_set_pch_lpt(struct e1000_hw
*hw
, u8
*addr
, u32 index
);
143 static s32
e1000_k1_workaround_lv(struct e1000_hw
*hw
);
144 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw
*hw
, bool gate
);
145 static s32
e1000_setup_copper_link_pch_lpt(struct e1000_hw
*hw
);
147 static inline u16
__er16flash(struct e1000_hw
*hw
, unsigned long reg
)
149 return readw(hw
->flash_address
+ reg
);
152 static inline u32
__er32flash(struct e1000_hw
*hw
, unsigned long reg
)
154 return readl(hw
->flash_address
+ reg
);
157 static inline void __ew16flash(struct e1000_hw
*hw
, unsigned long reg
, u16 val
)
159 writew(val
, hw
->flash_address
+ reg
);
162 static inline void __ew32flash(struct e1000_hw
*hw
, unsigned long reg
, u32 val
)
164 writel(val
, hw
->flash_address
+ reg
);
167 #define er16flash(reg) __er16flash(hw, (reg))
168 #define er32flash(reg) __er32flash(hw, (reg))
169 #define ew16flash(reg, val) __ew16flash(hw, (reg), (val))
170 #define ew32flash(reg, val) __ew32flash(hw, (reg), (val))
173 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
174 * @hw: pointer to the HW structure
176 * Test access to the PHY registers by reading the PHY ID registers. If
177 * the PHY ID is already known (e.g. resume path) compare it with known ID,
178 * otherwise assume the read PHY ID is correct if it is valid.
180 * Assumes the sw/fw/hw semaphore is already acquired.
182 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw
*hw
)
189 for (retry_count
= 0; retry_count
< 2; retry_count
++) {
190 ret_val
= e1e_rphy_locked(hw
, MII_PHYSID1
, &phy_reg
);
191 if (ret_val
|| (phy_reg
== 0xFFFF))
193 phy_id
= (u32
)(phy_reg
<< 16);
195 ret_val
= e1e_rphy_locked(hw
, MII_PHYSID2
, &phy_reg
);
196 if (ret_val
|| (phy_reg
== 0xFFFF)) {
200 phy_id
|= (u32
)(phy_reg
& PHY_REVISION_MASK
);
205 if (hw
->phy
.id
== phy_id
)
209 hw
->phy
.revision
= (u32
)(phy_reg
& ~PHY_REVISION_MASK
);
213 /* In case the PHY needs to be in mdio slow mode,
214 * set slow mode and try to get the PHY id again.
216 hw
->phy
.ops
.release(hw
);
217 ret_val
= e1000_set_mdio_slow_mode_hv(hw
);
219 ret_val
= e1000e_get_phy_id(hw
);
220 hw
->phy
.ops
.acquire(hw
);
226 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
227 * @hw: pointer to the HW structure
229 * Workarounds/flow necessary for PHY initialization during driver load
232 static s32
e1000_init_phy_workarounds_pchlan(struct e1000_hw
*hw
)
234 u32 mac_reg
, fwsm
= er32(FWSM
);
238 /* Gate automatic PHY configuration by hardware on managed and
239 * non-managed 82579 and newer adapters.
241 e1000_gate_hw_phy_config_ich8lan(hw
, true);
243 ret_val
= hw
->phy
.ops
.acquire(hw
);
245 e_dbg("Failed to initialize PHY flow\n");
249 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
250 * inaccessible and resetting the PHY is not blocked, toggle the
251 * LANPHYPC Value bit to force the interconnect to PCIe mode.
253 switch (hw
->mac
.type
) {
255 if (e1000_phy_is_accessible_pchlan(hw
))
258 /* Before toggling LANPHYPC, see if PHY is accessible by
259 * forcing MAC to SMBus mode first.
261 mac_reg
= er32(CTRL_EXT
);
262 mac_reg
|= E1000_CTRL_EXT_FORCE_SMBUS
;
263 ew32(CTRL_EXT
, mac_reg
);
267 if (e1000_phy_is_accessible_pchlan(hw
)) {
268 if (hw
->mac
.type
== e1000_pch_lpt
) {
269 /* Unforce SMBus mode in PHY */
270 e1e_rphy_locked(hw
, CV_SMB_CTRL
, &phy_reg
);
271 phy_reg
&= ~CV_SMB_CTRL_FORCE_SMBUS
;
272 e1e_wphy_locked(hw
, CV_SMB_CTRL
, phy_reg
);
274 /* Unforce SMBus mode in MAC */
275 mac_reg
= er32(CTRL_EXT
);
276 mac_reg
&= ~E1000_CTRL_EXT_FORCE_SMBUS
;
277 ew32(CTRL_EXT
, mac_reg
);
284 if ((hw
->mac
.type
== e1000_pchlan
) &&
285 (fwsm
& E1000_ICH_FWSM_FW_VALID
))
288 if (hw
->phy
.ops
.check_reset_block(hw
)) {
289 e_dbg("Required LANPHYPC toggle blocked by ME\n");
293 e_dbg("Toggling LANPHYPC\n");
295 /* Set Phy Config Counter to 50msec */
296 mac_reg
= er32(FEXTNVM3
);
297 mac_reg
&= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK
;
298 mac_reg
|= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC
;
299 ew32(FEXTNVM3
, mac_reg
);
301 if (hw
->mac
.type
== e1000_pch_lpt
) {
302 /* Toggling LANPHYPC brings the PHY out of SMBus mode
303 * So ensure that the MAC is also out of SMBus mode
305 mac_reg
= er32(CTRL_EXT
);
306 mac_reg
&= ~E1000_CTRL_EXT_FORCE_SMBUS
;
307 ew32(CTRL_EXT
, mac_reg
);
310 /* Toggle LANPHYPC Value bit */
311 mac_reg
= er32(CTRL
);
312 mac_reg
|= E1000_CTRL_LANPHYPC_OVERRIDE
;
313 mac_reg
&= ~E1000_CTRL_LANPHYPC_VALUE
;
316 usleep_range(10, 20);
317 mac_reg
&= ~E1000_CTRL_LANPHYPC_OVERRIDE
;
320 if (hw
->mac
.type
< e1000_pch_lpt
) {
325 usleep_range(5000, 10000);
326 } while (!(er32(CTRL_EXT
) &
327 E1000_CTRL_EXT_LPCD
) && count
--);
334 hw
->phy
.ops
.release(hw
);
336 /* Reset the PHY before any access to it. Doing so, ensures
337 * that the PHY is in a known good state before we read/write
338 * PHY registers. The generic reset is sufficient here,
339 * because we haven't determined the PHY type yet.
341 ret_val
= e1000e_phy_hw_reset_generic(hw
);
344 /* Ungate automatic PHY configuration on non-managed 82579 */
345 if ((hw
->mac
.type
== e1000_pch2lan
) &&
346 !(fwsm
& E1000_ICH_FWSM_FW_VALID
)) {
347 usleep_range(10000, 20000);
348 e1000_gate_hw_phy_config_ich8lan(hw
, false);
355 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
356 * @hw: pointer to the HW structure
358 * Initialize family-specific PHY parameters and function pointers.
360 static s32
e1000_init_phy_params_pchlan(struct e1000_hw
*hw
)
362 struct e1000_phy_info
*phy
= &hw
->phy
;
366 phy
->reset_delay_us
= 100;
368 phy
->ops
.set_page
= e1000_set_page_igp
;
369 phy
->ops
.read_reg
= e1000_read_phy_reg_hv
;
370 phy
->ops
.read_reg_locked
= e1000_read_phy_reg_hv_locked
;
371 phy
->ops
.read_reg_page
= e1000_read_phy_reg_page_hv
;
372 phy
->ops
.set_d0_lplu_state
= e1000_set_lplu_state_pchlan
;
373 phy
->ops
.set_d3_lplu_state
= e1000_set_lplu_state_pchlan
;
374 phy
->ops
.write_reg
= e1000_write_phy_reg_hv
;
375 phy
->ops
.write_reg_locked
= e1000_write_phy_reg_hv_locked
;
376 phy
->ops
.write_reg_page
= e1000_write_phy_reg_page_hv
;
377 phy
->ops
.power_up
= e1000_power_up_phy_copper
;
378 phy
->ops
.power_down
= e1000_power_down_phy_copper_ich8lan
;
379 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
381 phy
->id
= e1000_phy_unknown
;
383 ret_val
= e1000_init_phy_workarounds_pchlan(hw
);
387 if (phy
->id
== e1000_phy_unknown
)
388 switch (hw
->mac
.type
) {
390 ret_val
= e1000e_get_phy_id(hw
);
393 if ((phy
->id
!= 0) && (phy
->id
!= PHY_REVISION_MASK
))
398 /* In case the PHY needs to be in mdio slow mode,
399 * set slow mode and try to get the PHY id again.
401 ret_val
= e1000_set_mdio_slow_mode_hv(hw
);
404 ret_val
= e1000e_get_phy_id(hw
);
409 phy
->type
= e1000e_get_phy_type_from_id(phy
->id
);
412 case e1000_phy_82577
:
413 case e1000_phy_82579
:
415 phy
->ops
.check_polarity
= e1000_check_polarity_82577
;
416 phy
->ops
.force_speed_duplex
=
417 e1000_phy_force_speed_duplex_82577
;
418 phy
->ops
.get_cable_length
= e1000_get_cable_length_82577
;
419 phy
->ops
.get_info
= e1000_get_phy_info_82577
;
420 phy
->ops
.commit
= e1000e_phy_sw_reset
;
422 case e1000_phy_82578
:
423 phy
->ops
.check_polarity
= e1000_check_polarity_m88
;
424 phy
->ops
.force_speed_duplex
= e1000e_phy_force_speed_duplex_m88
;
425 phy
->ops
.get_cable_length
= e1000e_get_cable_length_m88
;
426 phy
->ops
.get_info
= e1000e_get_phy_info_m88
;
429 ret_val
= -E1000_ERR_PHY
;
437 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
438 * @hw: pointer to the HW structure
440 * Initialize family-specific PHY parameters and function pointers.
442 static s32
e1000_init_phy_params_ich8lan(struct e1000_hw
*hw
)
444 struct e1000_phy_info
*phy
= &hw
->phy
;
449 phy
->reset_delay_us
= 100;
451 phy
->ops
.power_up
= e1000_power_up_phy_copper
;
452 phy
->ops
.power_down
= e1000_power_down_phy_copper_ich8lan
;
454 /* We may need to do this twice - once for IGP and if that fails,
455 * we'll set BM func pointers and try again
457 ret_val
= e1000e_determine_phy_address(hw
);
459 phy
->ops
.write_reg
= e1000e_write_phy_reg_bm
;
460 phy
->ops
.read_reg
= e1000e_read_phy_reg_bm
;
461 ret_val
= e1000e_determine_phy_address(hw
);
463 e_dbg("Cannot determine PHY addr. Erroring out\n");
469 while ((e1000_phy_unknown
== e1000e_get_phy_type_from_id(phy
->id
)) &&
471 usleep_range(1000, 2000);
472 ret_val
= e1000e_get_phy_id(hw
);
479 case IGP03E1000_E_PHY_ID
:
480 phy
->type
= e1000_phy_igp_3
;
481 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
482 phy
->ops
.read_reg_locked
= e1000e_read_phy_reg_igp_locked
;
483 phy
->ops
.write_reg_locked
= e1000e_write_phy_reg_igp_locked
;
484 phy
->ops
.get_info
= e1000e_get_phy_info_igp
;
485 phy
->ops
.check_polarity
= e1000_check_polarity_igp
;
486 phy
->ops
.force_speed_duplex
= e1000e_phy_force_speed_duplex_igp
;
489 case IFE_PLUS_E_PHY_ID
:
491 phy
->type
= e1000_phy_ife
;
492 phy
->autoneg_mask
= E1000_ALL_NOT_GIG
;
493 phy
->ops
.get_info
= e1000_get_phy_info_ife
;
494 phy
->ops
.check_polarity
= e1000_check_polarity_ife
;
495 phy
->ops
.force_speed_duplex
= e1000_phy_force_speed_duplex_ife
;
497 case BME1000_E_PHY_ID
:
498 phy
->type
= e1000_phy_bm
;
499 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
500 phy
->ops
.read_reg
= e1000e_read_phy_reg_bm
;
501 phy
->ops
.write_reg
= e1000e_write_phy_reg_bm
;
502 phy
->ops
.commit
= e1000e_phy_sw_reset
;
503 phy
->ops
.get_info
= e1000e_get_phy_info_m88
;
504 phy
->ops
.check_polarity
= e1000_check_polarity_m88
;
505 phy
->ops
.force_speed_duplex
= e1000e_phy_force_speed_duplex_m88
;
508 return -E1000_ERR_PHY
;
516 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
517 * @hw: pointer to the HW structure
519 * Initialize family-specific NVM parameters and function
522 static s32
e1000_init_nvm_params_ich8lan(struct e1000_hw
*hw
)
524 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
525 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
526 u32 gfpreg
, sector_base_addr
, sector_end_addr
;
529 /* Can't read flash registers if the register set isn't mapped. */
530 if (!hw
->flash_address
) {
531 e_dbg("ERROR: Flash registers not mapped\n");
532 return -E1000_ERR_CONFIG
;
535 nvm
->type
= e1000_nvm_flash_sw
;
537 gfpreg
= er32flash(ICH_FLASH_GFPREG
);
539 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
540 * Add 1 to sector_end_addr since this sector is included in
543 sector_base_addr
= gfpreg
& FLASH_GFPREG_BASE_MASK
;
544 sector_end_addr
= ((gfpreg
>> 16) & FLASH_GFPREG_BASE_MASK
) + 1;
546 /* flash_base_addr is byte-aligned */
547 nvm
->flash_base_addr
= sector_base_addr
<< FLASH_SECTOR_ADDR_SHIFT
;
549 /* find total size of the NVM, then cut in half since the total
550 * size represents two separate NVM banks.
552 nvm
->flash_bank_size
= ((sector_end_addr
- sector_base_addr
)
553 << FLASH_SECTOR_ADDR_SHIFT
);
554 nvm
->flash_bank_size
/= 2;
555 /* Adjust to word count */
556 nvm
->flash_bank_size
/= sizeof(u16
);
558 nvm
->word_size
= E1000_ICH8_SHADOW_RAM_WORDS
;
560 /* Clear shadow ram */
561 for (i
= 0; i
< nvm
->word_size
; i
++) {
562 dev_spec
->shadow_ram
[i
].modified
= false;
563 dev_spec
->shadow_ram
[i
].value
= 0xFFFF;
570 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
571 * @hw: pointer to the HW structure
573 * Initialize family-specific MAC parameters and function
576 static s32
e1000_init_mac_params_ich8lan(struct e1000_hw
*hw
)
578 struct e1000_mac_info
*mac
= &hw
->mac
;
580 /* Set media type function pointer */
581 hw
->phy
.media_type
= e1000_media_type_copper
;
583 /* Set mta register count */
584 mac
->mta_reg_count
= 32;
585 /* Set rar entry count */
586 mac
->rar_entry_count
= E1000_ICH_RAR_ENTRIES
;
587 if (mac
->type
== e1000_ich8lan
)
588 mac
->rar_entry_count
--;
590 mac
->has_fwsm
= true;
591 /* ARC subsystem not supported */
592 mac
->arc_subsystem_valid
= false;
593 /* Adaptive IFS supported */
594 mac
->adaptive_ifs
= true;
596 /* LED and other operations */
601 /* check management mode */
602 mac
->ops
.check_mng_mode
= e1000_check_mng_mode_ich8lan
;
604 mac
->ops
.id_led_init
= e1000e_id_led_init_generic
;
606 mac
->ops
.blink_led
= e1000e_blink_led_generic
;
608 mac
->ops
.setup_led
= e1000e_setup_led_generic
;
610 mac
->ops
.cleanup_led
= e1000_cleanup_led_ich8lan
;
611 /* turn on/off LED */
612 mac
->ops
.led_on
= e1000_led_on_ich8lan
;
613 mac
->ops
.led_off
= e1000_led_off_ich8lan
;
616 mac
->rar_entry_count
= E1000_PCH2_RAR_ENTRIES
;
617 mac
->ops
.rar_set
= e1000_rar_set_pch2lan
;
621 /* check management mode */
622 mac
->ops
.check_mng_mode
= e1000_check_mng_mode_pchlan
;
624 mac
->ops
.id_led_init
= e1000_id_led_init_pchlan
;
626 mac
->ops
.setup_led
= e1000_setup_led_pchlan
;
628 mac
->ops
.cleanup_led
= e1000_cleanup_led_pchlan
;
629 /* turn on/off LED */
630 mac
->ops
.led_on
= e1000_led_on_pchlan
;
631 mac
->ops
.led_off
= e1000_led_off_pchlan
;
637 if (mac
->type
== e1000_pch_lpt
) {
638 mac
->rar_entry_count
= E1000_PCH_LPT_RAR_ENTRIES
;
639 mac
->ops
.rar_set
= e1000_rar_set_pch_lpt
;
640 mac
->ops
.setup_physical_interface
=
641 e1000_setup_copper_link_pch_lpt
;
644 /* Enable PCS Lock-loss workaround for ICH8 */
645 if (mac
->type
== e1000_ich8lan
)
646 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw
, true);
652 * __e1000_access_emi_reg_locked - Read/write EMI register
653 * @hw: pointer to the HW structure
654 * @addr: EMI address to program
655 * @data: pointer to value to read/write from/to the EMI address
656 * @read: boolean flag to indicate read or write
658 * This helper function assumes the SW/FW/HW Semaphore is already acquired.
660 static s32
__e1000_access_emi_reg_locked(struct e1000_hw
*hw
, u16 address
,
661 u16
*data
, bool read
)
665 ret_val
= e1e_wphy_locked(hw
, I82579_EMI_ADDR
, address
);
670 ret_val
= e1e_rphy_locked(hw
, I82579_EMI_DATA
, data
);
672 ret_val
= e1e_wphy_locked(hw
, I82579_EMI_DATA
, *data
);
678 * e1000_read_emi_reg_locked - Read Extended Management Interface register
679 * @hw: pointer to the HW structure
680 * @addr: EMI address to program
681 * @data: value to be read from the EMI address
683 * Assumes the SW/FW/HW Semaphore is already acquired.
685 s32
e1000_read_emi_reg_locked(struct e1000_hw
*hw
, u16 addr
, u16
*data
)
687 return __e1000_access_emi_reg_locked(hw
, addr
, data
, true);
691 * e1000_write_emi_reg_locked - Write Extended Management Interface register
692 * @hw: pointer to the HW structure
693 * @addr: EMI address to program
694 * @data: value to be written to the EMI address
696 * Assumes the SW/FW/HW Semaphore is already acquired.
698 s32
e1000_write_emi_reg_locked(struct e1000_hw
*hw
, u16 addr
, u16 data
)
700 return __e1000_access_emi_reg_locked(hw
, addr
, &data
, false);
704 * e1000_set_eee_pchlan - Enable/disable EEE support
705 * @hw: pointer to the HW structure
707 * Enable/disable EEE based on setting in dev_spec structure, the duplex of
708 * the link and the EEE capabilities of the link partner. The LPI Control
709 * register bits will remain set only if/when link is up.
711 static s32
e1000_set_eee_pchlan(struct e1000_hw
*hw
)
713 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
715 u16 lpa
, pcs_status
, adv
, adv_addr
, lpi_ctrl
, data
;
717 switch (hw
->phy
.type
) {
718 case e1000_phy_82579
:
719 lpa
= I82579_EEE_LP_ABILITY
;
720 pcs_status
= I82579_EEE_PCS_STATUS
;
721 adv_addr
= I82579_EEE_ADVERTISEMENT
;
724 lpa
= I217_EEE_LP_ABILITY
;
725 pcs_status
= I217_EEE_PCS_STATUS
;
726 adv_addr
= I217_EEE_ADVERTISEMENT
;
732 ret_val
= hw
->phy
.ops
.acquire(hw
);
736 ret_val
= e1e_rphy_locked(hw
, I82579_LPI_CTRL
, &lpi_ctrl
);
740 /* Clear bits that enable EEE in various speeds */
741 lpi_ctrl
&= ~I82579_LPI_CTRL_ENABLE_MASK
;
743 /* Enable EEE if not disabled by user */
744 if (!dev_spec
->eee_disable
) {
745 /* Save off link partner's EEE ability */
746 ret_val
= e1000_read_emi_reg_locked(hw
, lpa
,
747 &dev_spec
->eee_lp_ability
);
751 /* Read EEE advertisement */
752 ret_val
= e1000_read_emi_reg_locked(hw
, adv_addr
, &adv
);
756 /* Enable EEE only for speeds in which the link partner is
757 * EEE capable and for which we advertise EEE.
759 if (adv
& dev_spec
->eee_lp_ability
& I82579_EEE_1000_SUPPORTED
)
760 lpi_ctrl
|= I82579_LPI_CTRL_1000_ENABLE
;
762 if (adv
& dev_spec
->eee_lp_ability
& I82579_EEE_100_SUPPORTED
) {
763 e1e_rphy_locked(hw
, MII_LPA
, &data
);
764 if (data
& LPA_100FULL
)
765 lpi_ctrl
|= I82579_LPI_CTRL_100_ENABLE
;
767 /* EEE is not supported in 100Half, so ignore
768 * partner's EEE in 100 ability if full-duplex
771 dev_spec
->eee_lp_ability
&=
772 ~I82579_EEE_100_SUPPORTED
;
776 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
777 ret_val
= e1000_read_emi_reg_locked(hw
, pcs_status
, &data
);
781 ret_val
= e1e_wphy_locked(hw
, I82579_LPI_CTRL
, lpi_ctrl
);
783 hw
->phy
.ops
.release(hw
);
789 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
790 * @hw: pointer to the HW structure
791 * @link: link up bool flag
793 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
794 * preventing further DMA write requests. Workaround the issue by disabling
795 * the de-assertion of the clock request when in 1Gpbs mode.
797 static s32
e1000_k1_workaround_lpt_lp(struct e1000_hw
*hw
, bool link
)
799 u32 fextnvm6
= er32(FEXTNVM6
);
802 if (link
&& (er32(STATUS
) & E1000_STATUS_SPEED_1000
)) {
805 ret_val
= hw
->phy
.ops
.acquire(hw
);
810 e1000e_read_kmrn_reg_locked(hw
, E1000_KMRNCTRLSTA_K1_CONFIG
,
816 e1000e_write_kmrn_reg_locked(hw
,
817 E1000_KMRNCTRLSTA_K1_CONFIG
,
819 ~E1000_KMRNCTRLSTA_K1_ENABLE
);
823 usleep_range(10, 20);
825 ew32(FEXTNVM6
, fextnvm6
| E1000_FEXTNVM6_REQ_PLL_CLK
);
828 e1000e_write_kmrn_reg_locked(hw
,
829 E1000_KMRNCTRLSTA_K1_CONFIG
,
832 hw
->phy
.ops
.release(hw
);
834 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
835 ew32(FEXTNVM6
, fextnvm6
& ~E1000_FEXTNVM6_REQ_PLL_CLK
);
842 * e1000_platform_pm_pch_lpt - Set platform power management values
843 * @hw: pointer to the HW structure
844 * @link: bool indicating link status
846 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
847 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
848 * when link is up (which must not exceed the maximum latency supported
849 * by the platform), otherwise specify there is no LTR requirement.
850 * Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
851 * latencies in the LTR Extended Capability Structure in the PCIe Extended
852 * Capability register set, on this device LTR is set by writing the
853 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
854 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
855 * message to the PMC.
857 static s32
e1000_platform_pm_pch_lpt(struct e1000_hw
*hw
, bool link
)
859 u32 reg
= link
<< (E1000_LTRV_REQ_SHIFT
+ E1000_LTRV_NOSNOOP_SHIFT
) |
860 link
<< E1000_LTRV_REQ_SHIFT
| E1000_LTRV_SEND
;
861 u16 lat_enc
= 0; /* latency encoded */
864 u16 speed
, duplex
, scale
= 0;
865 u16 max_snoop
, max_nosnoop
;
866 u16 max_ltr_enc
; /* max LTR latency encoded */
867 s64 lat_ns
; /* latency (ns) */
871 if (!hw
->adapter
->max_frame_size
) {
872 e_dbg("max_frame_size not set.\n");
873 return -E1000_ERR_CONFIG
;
876 hw
->mac
.ops
.get_link_up_info(hw
, &speed
, &duplex
);
878 e_dbg("Speed not set.\n");
879 return -E1000_ERR_CONFIG
;
882 /* Rx Packet Buffer Allocation size (KB) */
883 rxa
= er32(PBA
) & E1000_PBA_RXA_MASK
;
885 /* Determine the maximum latency tolerated by the device.
887 * Per the PCIe spec, the tolerated latencies are encoded as
888 * a 3-bit encoded scale (only 0-5 are valid) multiplied by
889 * a 10-bit value (0-1023) to provide a range from 1 ns to
890 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns,
891 * 1=2^5ns, 2=2^10ns,...5=2^25ns.
893 lat_ns
= ((s64
)rxa
* 1024 -
894 (2 * (s64
)hw
->adapter
->max_frame_size
)) * 8 * 1000;
898 do_div(lat_ns
, speed
);
901 while (value
> PCI_LTR_VALUE_MASK
) {
903 value
= DIV_ROUND_UP(value
, (1 << 5));
905 if (scale
> E1000_LTRV_SCALE_MAX
) {
906 e_dbg("Invalid LTR latency scale %d\n", scale
);
907 return -E1000_ERR_CONFIG
;
909 lat_enc
= (u16
)((scale
<< PCI_LTR_SCALE_SHIFT
) | value
);
911 /* Determine the maximum latency tolerated by the platform */
912 pci_read_config_word(hw
->adapter
->pdev
, E1000_PCI_LTR_CAP_LPT
,
914 pci_read_config_word(hw
->adapter
->pdev
,
915 E1000_PCI_LTR_CAP_LPT
+ 2, &max_nosnoop
);
916 max_ltr_enc
= max_t(u16
, max_snoop
, max_nosnoop
);
918 if (lat_enc
> max_ltr_enc
)
919 lat_enc
= max_ltr_enc
;
922 /* Set Snoop and No-Snoop latencies the same */
923 reg
|= lat_enc
| (lat_enc
<< E1000_LTRV_NOSNOOP_SHIFT
);
930 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
931 * @hw: pointer to the HW structure
933 * Checks to see of the link status of the hardware has changed. If a
934 * change in link status has been detected, then we read the PHY registers
935 * to get the current speed/duplex if link exists.
937 static s32
e1000_check_for_copper_link_ich8lan(struct e1000_hw
*hw
)
939 struct e1000_mac_info
*mac
= &hw
->mac
;
944 /* We only want to go out to the PHY registers to see if Auto-Neg
945 * has completed and/or if our link status has changed. The
946 * get_link_status flag is set upon receiving a Link Status
947 * Change or Rx Sequence Error interrupt.
949 if (!mac
->get_link_status
)
952 /* First we want to see if the MII Status Register reports
953 * link. If so, then we want to get the current speed/duplex
956 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
960 if (hw
->mac
.type
== e1000_pchlan
) {
961 ret_val
= e1000_k1_gig_workaround_hv(hw
, link
);
966 /* When connected at 10Mbps half-duplex, 82579 parts are excessively
967 * aggressive resulting in many collisions. To avoid this, increase
968 * the IPG and reduce Rx latency in the PHY.
970 if ((hw
->mac
.type
== e1000_pch2lan
) && link
) {
973 if (!(reg
& (E1000_STATUS_FD
| E1000_STATUS_SPEED_MASK
))) {
975 reg
&= ~E1000_TIPG_IPGT_MASK
;
979 /* Reduce Rx latency in analog PHY */
980 ret_val
= hw
->phy
.ops
.acquire(hw
);
985 e1000_write_emi_reg_locked(hw
, I82579_RX_CONFIG
, 0);
987 hw
->phy
.ops
.release(hw
);
994 /* Work-around I218 hang issue */
995 if ((hw
->adapter
->pdev
->device
== E1000_DEV_ID_PCH_LPTLP_I218_LM
) ||
996 (hw
->adapter
->pdev
->device
== E1000_DEV_ID_PCH_LPTLP_I218_V
)) {
997 ret_val
= e1000_k1_workaround_lpt_lp(hw
, link
);
1002 if (hw
->mac
.type
== e1000_pch_lpt
) {
1003 /* Set platform power management values for
1004 * Latency Tolerance Reporting (LTR)
1006 ret_val
= e1000_platform_pm_pch_lpt(hw
, link
);
1011 /* Clear link partner's EEE ability */
1012 hw
->dev_spec
.ich8lan
.eee_lp_ability
= 0;
1015 return 0; /* No link detected */
1017 mac
->get_link_status
= false;
1019 switch (hw
->mac
.type
) {
1021 ret_val
= e1000_k1_workaround_lv(hw
);
1026 if (hw
->phy
.type
== e1000_phy_82578
) {
1027 ret_val
= e1000_link_stall_workaround_hv(hw
);
1032 /* Workaround for PCHx parts in half-duplex:
1033 * Set the number of preambles removed from the packet
1034 * when it is passed from the PHY to the MAC to prevent
1035 * the MAC from misinterpreting the packet type.
1037 e1e_rphy(hw
, HV_KMRN_FIFO_CTRLSTA
, &phy_reg
);
1038 phy_reg
&= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK
;
1040 if ((er32(STATUS
) & E1000_STATUS_FD
) != E1000_STATUS_FD
)
1041 phy_reg
|= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT
);
1043 e1e_wphy(hw
, HV_KMRN_FIFO_CTRLSTA
, phy_reg
);
1049 /* Check if there was DownShift, must be checked
1050 * immediately after link-up
1052 e1000e_check_downshift(hw
);
1054 /* Enable/Disable EEE after link up */
1055 ret_val
= e1000_set_eee_pchlan(hw
);
1059 /* If we are forcing speed/duplex, then we simply return since
1060 * we have already determined whether we have link or not.
1063 return -E1000_ERR_CONFIG
;
1065 /* Auto-Neg is enabled. Auto Speed Detection takes care
1066 * of MAC speed/duplex configuration. So we only need to
1067 * configure Collision Distance in the MAC.
1069 mac
->ops
.config_collision_dist(hw
);
1071 /* Configure Flow Control now that Auto-Neg has completed.
1072 * First, we need to restore the desired flow control
1073 * settings because we may have had to re-autoneg with a
1074 * different link partner.
1076 ret_val
= e1000e_config_fc_after_link_up(hw
);
1078 e_dbg("Error configuring flow control\n");
1083 static s32
e1000_get_variants_ich8lan(struct e1000_adapter
*adapter
)
1085 struct e1000_hw
*hw
= &adapter
->hw
;
1088 rc
= e1000_init_mac_params_ich8lan(hw
);
1092 rc
= e1000_init_nvm_params_ich8lan(hw
);
1096 switch (hw
->mac
.type
) {
1099 case e1000_ich10lan
:
1100 rc
= e1000_init_phy_params_ich8lan(hw
);
1105 rc
= e1000_init_phy_params_pchlan(hw
);
1113 /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
1114 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
1116 if ((adapter
->hw
.phy
.type
== e1000_phy_ife
) ||
1117 ((adapter
->hw
.mac
.type
>= e1000_pch2lan
) &&
1118 (!(er32(CTRL_EXT
) & E1000_CTRL_EXT_LSECCK
)))) {
1119 adapter
->flags
&= ~FLAG_HAS_JUMBO_FRAMES
;
1120 adapter
->max_hw_frame_size
= ETH_FRAME_LEN
+ ETH_FCS_LEN
;
1122 hw
->mac
.ops
.blink_led
= NULL
;
1125 if ((adapter
->hw
.mac
.type
== e1000_ich8lan
) &&
1126 (adapter
->hw
.phy
.type
!= e1000_phy_ife
))
1127 adapter
->flags
|= FLAG_LSC_GIG_SPEED_DROP
;
1129 /* Enable workaround for 82579 w/ ME enabled */
1130 if ((adapter
->hw
.mac
.type
== e1000_pch2lan
) &&
1131 (er32(FWSM
) & E1000_ICH_FWSM_FW_VALID
))
1132 adapter
->flags2
|= FLAG2_PCIM2PCI_ARBITER_WA
;
1137 static DEFINE_MUTEX(nvm_mutex
);
1140 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1141 * @hw: pointer to the HW structure
1143 * Acquires the mutex for performing NVM operations.
1145 static s32
e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused
*hw
)
1147 mutex_lock(&nvm_mutex
);
1153 * e1000_release_nvm_ich8lan - Release NVM mutex
1154 * @hw: pointer to the HW structure
1156 * Releases the mutex used while performing NVM operations.
1158 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused
*hw
)
1160 mutex_unlock(&nvm_mutex
);
1164 * e1000_acquire_swflag_ich8lan - Acquire software control flag
1165 * @hw: pointer to the HW structure
1167 * Acquires the software control flag for performing PHY and select
1170 static s32
e1000_acquire_swflag_ich8lan(struct e1000_hw
*hw
)
1172 u32 extcnf_ctrl
, timeout
= PHY_CFG_TIMEOUT
;
1175 if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE
,
1176 &hw
->adapter
->state
)) {
1177 e_dbg("contention for Phy access\n");
1178 return -E1000_ERR_PHY
;
1182 extcnf_ctrl
= er32(EXTCNF_CTRL
);
1183 if (!(extcnf_ctrl
& E1000_EXTCNF_CTRL_SWFLAG
))
1191 e_dbg("SW has already locked the resource.\n");
1192 ret_val
= -E1000_ERR_CONFIG
;
1196 timeout
= SW_FLAG_TIMEOUT
;
1198 extcnf_ctrl
|= E1000_EXTCNF_CTRL_SWFLAG
;
1199 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
1202 extcnf_ctrl
= er32(EXTCNF_CTRL
);
1203 if (extcnf_ctrl
& E1000_EXTCNF_CTRL_SWFLAG
)
1211 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1212 er32(FWSM
), extcnf_ctrl
);
1213 extcnf_ctrl
&= ~E1000_EXTCNF_CTRL_SWFLAG
;
1214 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
1215 ret_val
= -E1000_ERR_CONFIG
;
1221 clear_bit(__E1000_ACCESS_SHARED_RESOURCE
, &hw
->adapter
->state
);
1227 * e1000_release_swflag_ich8lan - Release software control flag
1228 * @hw: pointer to the HW structure
1230 * Releases the software control flag for performing PHY and select
1233 static void e1000_release_swflag_ich8lan(struct e1000_hw
*hw
)
1237 extcnf_ctrl
= er32(EXTCNF_CTRL
);
1239 if (extcnf_ctrl
& E1000_EXTCNF_CTRL_SWFLAG
) {
1240 extcnf_ctrl
&= ~E1000_EXTCNF_CTRL_SWFLAG
;
1241 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
1243 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1246 clear_bit(__E1000_ACCESS_SHARED_RESOURCE
, &hw
->adapter
->state
);
1250 * e1000_check_mng_mode_ich8lan - Checks management mode
1251 * @hw: pointer to the HW structure
1253 * This checks if the adapter has any manageability enabled.
1254 * This is a function pointer entry point only called by read/write
1255 * routines for the PHY and NVM parts.
1257 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw
*hw
)
1262 return ((fwsm
& E1000_ICH_FWSM_FW_VALID
) &&
1263 ((fwsm
& E1000_FWSM_MODE_MASK
) ==
1264 (E1000_ICH_MNG_IAMT_MODE
<< E1000_FWSM_MODE_SHIFT
)));
1268 * e1000_check_mng_mode_pchlan - Checks management mode
1269 * @hw: pointer to the HW structure
1271 * This checks if the adapter has iAMT enabled.
1272 * This is a function pointer entry point only called by read/write
1273 * routines for the PHY and NVM parts.
1275 static bool e1000_check_mng_mode_pchlan(struct e1000_hw
*hw
)
1280 return (fwsm
& E1000_ICH_FWSM_FW_VALID
) &&
1281 (fwsm
& (E1000_ICH_MNG_IAMT_MODE
<< E1000_FWSM_MODE_SHIFT
));
1285 * e1000_rar_set_pch2lan - Set receive address register
1286 * @hw: pointer to the HW structure
1287 * @addr: pointer to the receive address
1288 * @index: receive address array register
1290 * Sets the receive address array register at index to the address passed
1291 * in by addr. For 82579, RAR[0] is the base address register that is to
1292 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1293 * Use SHRA[0-3] in place of those reserved for ME.
1295 static void e1000_rar_set_pch2lan(struct e1000_hw
*hw
, u8
*addr
, u32 index
)
1297 u32 rar_low
, rar_high
;
1299 /* HW expects these in little endian so we reverse the byte order
1300 * from network order (big endian) to little endian
1302 rar_low
= ((u32
)addr
[0] |
1303 ((u32
)addr
[1] << 8) |
1304 ((u32
)addr
[2] << 16) | ((u32
)addr
[3] << 24));
1306 rar_high
= ((u32
)addr
[4] | ((u32
)addr
[5] << 8));
1308 /* If MAC address zero, no need to set the AV bit */
1309 if (rar_low
|| rar_high
)
1310 rar_high
|= E1000_RAH_AV
;
1313 ew32(RAL(index
), rar_low
);
1315 ew32(RAH(index
), rar_high
);
1320 if (index
< hw
->mac
.rar_entry_count
) {
1323 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
1327 ew32(SHRAL(index
- 1), rar_low
);
1329 ew32(SHRAH(index
- 1), rar_high
);
1332 e1000_release_swflag_ich8lan(hw
);
1334 /* verify the register updates */
1335 if ((er32(SHRAL(index
- 1)) == rar_low
) &&
1336 (er32(SHRAH(index
- 1)) == rar_high
))
1339 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1340 (index
- 1), er32(FWSM
));
1344 e_dbg("Failed to write receive address at index %d\n", index
);
1348 * e1000_rar_set_pch_lpt - Set receive address registers
1349 * @hw: pointer to the HW structure
1350 * @addr: pointer to the receive address
1351 * @index: receive address array register
1353 * Sets the receive address register array at index to the address passed
1354 * in by addr. For LPT, RAR[0] is the base address register that is to
1355 * contain the MAC address. SHRA[0-10] are the shared receive address
1356 * registers that are shared between the Host and manageability engine (ME).
1358 static void e1000_rar_set_pch_lpt(struct e1000_hw
*hw
, u8
*addr
, u32 index
)
1360 u32 rar_low
, rar_high
;
1363 /* HW expects these in little endian so we reverse the byte order
1364 * from network order (big endian) to little endian
1366 rar_low
= ((u32
)addr
[0] | ((u32
)addr
[1] << 8) |
1367 ((u32
)addr
[2] << 16) | ((u32
)addr
[3] << 24));
1369 rar_high
= ((u32
)addr
[4] | ((u32
)addr
[5] << 8));
1371 /* If MAC address zero, no need to set the AV bit */
1372 if (rar_low
|| rar_high
)
1373 rar_high
|= E1000_RAH_AV
;
1376 ew32(RAL(index
), rar_low
);
1378 ew32(RAH(index
), rar_high
);
1383 /* The manageability engine (ME) can lock certain SHRAR registers that
1384 * it is using - those registers are unavailable for use.
1386 if (index
< hw
->mac
.rar_entry_count
) {
1387 wlock_mac
= er32(FWSM
) & E1000_FWSM_WLOCK_MAC_MASK
;
1388 wlock_mac
>>= E1000_FWSM_WLOCK_MAC_SHIFT
;
1390 /* Check if all SHRAR registers are locked */
1394 if ((wlock_mac
== 0) || (index
<= wlock_mac
)) {
1397 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
1402 ew32(SHRAL_PCH_LPT(index
- 1), rar_low
);
1404 ew32(SHRAH_PCH_LPT(index
- 1), rar_high
);
1407 e1000_release_swflag_ich8lan(hw
);
1409 /* verify the register updates */
1410 if ((er32(SHRAL_PCH_LPT(index
- 1)) == rar_low
) &&
1411 (er32(SHRAH_PCH_LPT(index
- 1)) == rar_high
))
1417 e_dbg("Failed to write receive address at index %d\n", index
);
1421 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
1422 * @hw: pointer to the HW structure
1424 * Checks if firmware is blocking the reset of the PHY.
1425 * This is a function pointer entry point only called by
1428 static s32
e1000_check_reset_block_ich8lan(struct e1000_hw
*hw
)
1434 return (fwsm
& E1000_ICH_FWSM_RSPCIPHY
) ? 0 : E1000_BLK_PHY_RESET
;
1438 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
1439 * @hw: pointer to the HW structure
1441 * Assumes semaphore already acquired.
1444 static s32
e1000_write_smbus_addr(struct e1000_hw
*hw
)
1447 u32 strap
= er32(STRAP
);
1448 u32 freq
= (strap
& E1000_STRAP_SMT_FREQ_MASK
) >>
1449 E1000_STRAP_SMT_FREQ_SHIFT
;
1452 strap
&= E1000_STRAP_SMBUS_ADDRESS_MASK
;
1454 ret_val
= e1000_read_phy_reg_hv_locked(hw
, HV_SMB_ADDR
, &phy_data
);
1458 phy_data
&= ~HV_SMB_ADDR_MASK
;
1459 phy_data
|= (strap
>> E1000_STRAP_SMBUS_ADDRESS_SHIFT
);
1460 phy_data
|= HV_SMB_ADDR_PEC_EN
| HV_SMB_ADDR_VALID
;
1462 if (hw
->phy
.type
== e1000_phy_i217
) {
1463 /* Restore SMBus frequency */
1465 phy_data
&= ~HV_SMB_ADDR_FREQ_MASK
;
1466 phy_data
|= (freq
& (1 << 0)) <<
1467 HV_SMB_ADDR_FREQ_LOW_SHIFT
;
1468 phy_data
|= (freq
& (1 << 1)) <<
1469 (HV_SMB_ADDR_FREQ_HIGH_SHIFT
- 1);
1471 e_dbg("Unsupported SMB frequency in PHY\n");
1475 return e1000_write_phy_reg_hv_locked(hw
, HV_SMB_ADDR
, phy_data
);
1479 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
1480 * @hw: pointer to the HW structure
1482 * SW should configure the LCD from the NVM extended configuration region
1483 * as a workaround for certain parts.
1485 static s32
e1000_sw_lcd_config_ich8lan(struct e1000_hw
*hw
)
1487 struct e1000_phy_info
*phy
= &hw
->phy
;
1488 u32 i
, data
, cnf_size
, cnf_base_addr
, sw_cfg_mask
;
1490 u16 word_addr
, reg_data
, reg_addr
, phy_page
= 0;
1492 /* Initialize the PHY from the NVM on ICH platforms. This
1493 * is needed due to an issue where the NVM configuration is
1494 * not properly autoloaded after power transitions.
1495 * Therefore, after each PHY reset, we will load the
1496 * configuration data out of the NVM manually.
1498 switch (hw
->mac
.type
) {
1500 if (phy
->type
!= e1000_phy_igp_3
)
1503 if ((hw
->adapter
->pdev
->device
== E1000_DEV_ID_ICH8_IGP_AMT
) ||
1504 (hw
->adapter
->pdev
->device
== E1000_DEV_ID_ICH8_IGP_C
)) {
1505 sw_cfg_mask
= E1000_FEXTNVM_SW_CONFIG
;
1512 sw_cfg_mask
= E1000_FEXTNVM_SW_CONFIG_ICH8M
;
1518 ret_val
= hw
->phy
.ops
.acquire(hw
);
1522 data
= er32(FEXTNVM
);
1523 if (!(data
& sw_cfg_mask
))
1526 /* Make sure HW does not configure LCD from PHY
1527 * extended configuration before SW configuration
1529 data
= er32(EXTCNF_CTRL
);
1530 if ((hw
->mac
.type
< e1000_pch2lan
) &&
1531 (data
& E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE
))
1534 cnf_size
= er32(EXTCNF_SIZE
);
1535 cnf_size
&= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK
;
1536 cnf_size
>>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT
;
1540 cnf_base_addr
= data
& E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK
;
1541 cnf_base_addr
>>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT
;
1543 if (((hw
->mac
.type
== e1000_pchlan
) &&
1544 !(data
& E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE
)) ||
1545 (hw
->mac
.type
> e1000_pchlan
)) {
1546 /* HW configures the SMBus address and LEDs when the
1547 * OEM and LCD Write Enable bits are set in the NVM.
1548 * When both NVM bits are cleared, SW will configure
1551 ret_val
= e1000_write_smbus_addr(hw
);
1555 data
= er32(LEDCTL
);
1556 ret_val
= e1000_write_phy_reg_hv_locked(hw
, HV_LED_CONFIG
,
1562 /* Configure LCD from extended configuration region. */
1564 /* cnf_base_addr is in DWORD */
1565 word_addr
= (u16
)(cnf_base_addr
<< 1);
1567 for (i
= 0; i
< cnf_size
; i
++) {
1568 ret_val
= e1000_read_nvm(hw
, (word_addr
+ i
* 2), 1, ®_data
);
1572 ret_val
= e1000_read_nvm(hw
, (word_addr
+ i
* 2 + 1),
1577 /* Save off the PHY page for future writes. */
1578 if (reg_addr
== IGP01E1000_PHY_PAGE_SELECT
) {
1579 phy_page
= reg_data
;
1583 reg_addr
&= PHY_REG_MASK
;
1584 reg_addr
|= phy_page
;
1586 ret_val
= e1e_wphy_locked(hw
, (u32
)reg_addr
, reg_data
);
1592 hw
->phy
.ops
.release(hw
);
1597 * e1000_k1_gig_workaround_hv - K1 Si workaround
1598 * @hw: pointer to the HW structure
1599 * @link: link up bool flag
1601 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1602 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
1603 * If link is down, the function will restore the default K1 setting located
1606 static s32
e1000_k1_gig_workaround_hv(struct e1000_hw
*hw
, bool link
)
1610 bool k1_enable
= hw
->dev_spec
.ich8lan
.nvm_k1_enabled
;
1612 if (hw
->mac
.type
!= e1000_pchlan
)
1615 /* Wrap the whole flow with the sw flag */
1616 ret_val
= hw
->phy
.ops
.acquire(hw
);
1620 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1622 if (hw
->phy
.type
== e1000_phy_82578
) {
1623 ret_val
= e1e_rphy_locked(hw
, BM_CS_STATUS
,
1628 status_reg
&= (BM_CS_STATUS_LINK_UP
|
1629 BM_CS_STATUS_RESOLVED
|
1630 BM_CS_STATUS_SPEED_MASK
);
1632 if (status_reg
== (BM_CS_STATUS_LINK_UP
|
1633 BM_CS_STATUS_RESOLVED
|
1634 BM_CS_STATUS_SPEED_1000
))
1638 if (hw
->phy
.type
== e1000_phy_82577
) {
1639 ret_val
= e1e_rphy_locked(hw
, HV_M_STATUS
, &status_reg
);
1643 status_reg
&= (HV_M_STATUS_LINK_UP
|
1644 HV_M_STATUS_AUTONEG_COMPLETE
|
1645 HV_M_STATUS_SPEED_MASK
);
1647 if (status_reg
== (HV_M_STATUS_LINK_UP
|
1648 HV_M_STATUS_AUTONEG_COMPLETE
|
1649 HV_M_STATUS_SPEED_1000
))
1653 /* Link stall fix for link up */
1654 ret_val
= e1e_wphy_locked(hw
, PHY_REG(770, 19), 0x0100);
1659 /* Link stall fix for link down */
1660 ret_val
= e1e_wphy_locked(hw
, PHY_REG(770, 19), 0x4100);
1665 ret_val
= e1000_configure_k1_ich8lan(hw
, k1_enable
);
1668 hw
->phy
.ops
.release(hw
);
1674 * e1000_configure_k1_ich8lan - Configure K1 power state
1675 * @hw: pointer to the HW structure
1676 * @enable: K1 state to configure
1678 * Configure the K1 power state based on the provided parameter.
1679 * Assumes semaphore already acquired.
1681 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1683 s32
e1000_configure_k1_ich8lan(struct e1000_hw
*hw
, bool k1_enable
)
1691 ret_val
= e1000e_read_kmrn_reg_locked(hw
, E1000_KMRNCTRLSTA_K1_CONFIG
,
1697 kmrn_reg
|= E1000_KMRNCTRLSTA_K1_ENABLE
;
1699 kmrn_reg
&= ~E1000_KMRNCTRLSTA_K1_ENABLE
;
1701 ret_val
= e1000e_write_kmrn_reg_locked(hw
, E1000_KMRNCTRLSTA_K1_CONFIG
,
1706 usleep_range(20, 40);
1707 ctrl_ext
= er32(CTRL_EXT
);
1708 ctrl_reg
= er32(CTRL
);
1710 reg
= ctrl_reg
& ~(E1000_CTRL_SPD_1000
| E1000_CTRL_SPD_100
);
1711 reg
|= E1000_CTRL_FRCSPD
;
1714 ew32(CTRL_EXT
, ctrl_ext
| E1000_CTRL_EXT_SPD_BYPS
);
1716 usleep_range(20, 40);
1717 ew32(CTRL
, ctrl_reg
);
1718 ew32(CTRL_EXT
, ctrl_ext
);
1720 usleep_range(20, 40);
1726 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1727 * @hw: pointer to the HW structure
1728 * @d0_state: boolean if entering d0 or d3 device state
1730 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1731 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
1732 * in NVM determines whether HW should configure LPLU and Gbe Disable.
1734 static s32
e1000_oem_bits_config_ich8lan(struct e1000_hw
*hw
, bool d0_state
)
1740 if (hw
->mac
.type
< e1000_pchlan
)
1743 ret_val
= hw
->phy
.ops
.acquire(hw
);
1747 if (hw
->mac
.type
== e1000_pchlan
) {
1748 mac_reg
= er32(EXTCNF_CTRL
);
1749 if (mac_reg
& E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE
)
1753 mac_reg
= er32(FEXTNVM
);
1754 if (!(mac_reg
& E1000_FEXTNVM_SW_CONFIG_ICH8M
))
1757 mac_reg
= er32(PHY_CTRL
);
1759 ret_val
= e1e_rphy_locked(hw
, HV_OEM_BITS
, &oem_reg
);
1763 oem_reg
&= ~(HV_OEM_BITS_GBE_DIS
| HV_OEM_BITS_LPLU
);
1766 if (mac_reg
& E1000_PHY_CTRL_GBE_DISABLE
)
1767 oem_reg
|= HV_OEM_BITS_GBE_DIS
;
1769 if (mac_reg
& E1000_PHY_CTRL_D0A_LPLU
)
1770 oem_reg
|= HV_OEM_BITS_LPLU
;
1772 if (mac_reg
& (E1000_PHY_CTRL_GBE_DISABLE
|
1773 E1000_PHY_CTRL_NOND0A_GBE_DISABLE
))
1774 oem_reg
|= HV_OEM_BITS_GBE_DIS
;
1776 if (mac_reg
& (E1000_PHY_CTRL_D0A_LPLU
|
1777 E1000_PHY_CTRL_NOND0A_LPLU
))
1778 oem_reg
|= HV_OEM_BITS_LPLU
;
1781 /* Set Restart auto-neg to activate the bits */
1782 if ((d0_state
|| (hw
->mac
.type
!= e1000_pchlan
)) &&
1783 !hw
->phy
.ops
.check_reset_block(hw
))
1784 oem_reg
|= HV_OEM_BITS_RESTART_AN
;
1786 ret_val
= e1e_wphy_locked(hw
, HV_OEM_BITS
, oem_reg
);
1789 hw
->phy
.ops
.release(hw
);
1795 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1796 * @hw: pointer to the HW structure
1798 static s32
e1000_set_mdio_slow_mode_hv(struct e1000_hw
*hw
)
1803 ret_val
= e1e_rphy(hw
, HV_KMRN_MODE_CTRL
, &data
);
1807 data
|= HV_KMRN_MDIO_SLOW
;
1809 ret_val
= e1e_wphy(hw
, HV_KMRN_MODE_CTRL
, data
);
1815 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1816 * done after every PHY reset.
1818 static s32
e1000_hv_phy_workarounds_ich8lan(struct e1000_hw
*hw
)
1823 if (hw
->mac
.type
!= e1000_pchlan
)
1826 /* Set MDIO slow mode before any other MDIO access */
1827 if (hw
->phy
.type
== e1000_phy_82577
) {
1828 ret_val
= e1000_set_mdio_slow_mode_hv(hw
);
1833 if (((hw
->phy
.type
== e1000_phy_82577
) &&
1834 ((hw
->phy
.revision
== 1) || (hw
->phy
.revision
== 2))) ||
1835 ((hw
->phy
.type
== e1000_phy_82578
) && (hw
->phy
.revision
== 1))) {
1836 /* Disable generation of early preamble */
1837 ret_val
= e1e_wphy(hw
, PHY_REG(769, 25), 0x4431);
1841 /* Preamble tuning for SSC */
1842 ret_val
= e1e_wphy(hw
, HV_KMRN_FIFO_CTRLSTA
, 0xA204);
1847 if (hw
->phy
.type
== e1000_phy_82578
) {
1848 /* Return registers to default by doing a soft reset then
1849 * writing 0x3140 to the control register.
1851 if (hw
->phy
.revision
< 2) {
1852 e1000e_phy_sw_reset(hw
);
1853 ret_val
= e1e_wphy(hw
, MII_BMCR
, 0x3140);
1858 ret_val
= hw
->phy
.ops
.acquire(hw
);
1863 ret_val
= e1000e_write_phy_reg_mdic(hw
, IGP01E1000_PHY_PAGE_SELECT
, 0);
1864 hw
->phy
.ops
.release(hw
);
1868 /* Configure the K1 Si workaround during phy reset assuming there is
1869 * link so that it disables K1 if link is in 1Gbps.
1871 ret_val
= e1000_k1_gig_workaround_hv(hw
, true);
1875 /* Workaround for link disconnects on a busy hub in half duplex */
1876 ret_val
= hw
->phy
.ops
.acquire(hw
);
1879 ret_val
= e1e_rphy_locked(hw
, BM_PORT_GEN_CFG
, &phy_data
);
1882 ret_val
= e1e_wphy_locked(hw
, BM_PORT_GEN_CFG
, phy_data
& 0x00FF);
1886 /* set MSE higher to enable link to stay up when noise is high */
1887 ret_val
= e1000_write_emi_reg_locked(hw
, I82577_MSE_THRESHOLD
, 0x0034);
1889 hw
->phy
.ops
.release(hw
);
1895 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1896 * @hw: pointer to the HW structure
1898 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw
*hw
)
1904 ret_val
= hw
->phy
.ops
.acquire(hw
);
1907 ret_val
= e1000_enable_phy_wakeup_reg_access_bm(hw
, &phy_reg
);
1911 /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1912 for (i
= 0; i
< (hw
->mac
.rar_entry_count
+ 4); i
++) {
1913 mac_reg
= er32(RAL(i
));
1914 hw
->phy
.ops
.write_reg_page(hw
, BM_RAR_L(i
),
1915 (u16
)(mac_reg
& 0xFFFF));
1916 hw
->phy
.ops
.write_reg_page(hw
, BM_RAR_M(i
),
1917 (u16
)((mac_reg
>> 16) & 0xFFFF));
1919 mac_reg
= er32(RAH(i
));
1920 hw
->phy
.ops
.write_reg_page(hw
, BM_RAR_H(i
),
1921 (u16
)(mac_reg
& 0xFFFF));
1922 hw
->phy
.ops
.write_reg_page(hw
, BM_RAR_CTRL(i
),
1923 (u16
)((mac_reg
& E1000_RAH_AV
)
1927 e1000_disable_phy_wakeup_reg_access_bm(hw
, &phy_reg
);
1930 hw
->phy
.ops
.release(hw
);
1934 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1936 * @hw: pointer to the HW structure
1937 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
1939 s32
e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw
*hw
, bool enable
)
1946 if (hw
->mac
.type
< e1000_pch2lan
)
1949 /* disable Rx path while enabling/disabling workaround */
1950 e1e_rphy(hw
, PHY_REG(769, 20), &phy_reg
);
1951 ret_val
= e1e_wphy(hw
, PHY_REG(769, 20), phy_reg
| (1 << 14));
1956 /* Write Rx addresses (rar_entry_count for RAL/H, +4 for
1957 * SHRAL/H) and initial CRC values to the MAC
1959 for (i
= 0; i
< (hw
->mac
.rar_entry_count
+ 4); i
++) {
1960 u8 mac_addr
[ETH_ALEN
] = { 0 };
1961 u32 addr_high
, addr_low
;
1963 addr_high
= er32(RAH(i
));
1964 if (!(addr_high
& E1000_RAH_AV
))
1966 addr_low
= er32(RAL(i
));
1967 mac_addr
[0] = (addr_low
& 0xFF);
1968 mac_addr
[1] = ((addr_low
>> 8) & 0xFF);
1969 mac_addr
[2] = ((addr_low
>> 16) & 0xFF);
1970 mac_addr
[3] = ((addr_low
>> 24) & 0xFF);
1971 mac_addr
[4] = (addr_high
& 0xFF);
1972 mac_addr
[5] = ((addr_high
>> 8) & 0xFF);
1974 ew32(PCH_RAICC(i
), ~ether_crc_le(ETH_ALEN
, mac_addr
));
1977 /* Write Rx addresses to the PHY */
1978 e1000_copy_rx_addrs_to_phy_ich8lan(hw
);
1980 /* Enable jumbo frame workaround in the MAC */
1981 mac_reg
= er32(FFLT_DBG
);
1982 mac_reg
&= ~(1 << 14);
1983 mac_reg
|= (7 << 15);
1984 ew32(FFLT_DBG
, mac_reg
);
1986 mac_reg
= er32(RCTL
);
1987 mac_reg
|= E1000_RCTL_SECRC
;
1988 ew32(RCTL
, mac_reg
);
1990 ret_val
= e1000e_read_kmrn_reg(hw
,
1991 E1000_KMRNCTRLSTA_CTRL_OFFSET
,
1995 ret_val
= e1000e_write_kmrn_reg(hw
,
1996 E1000_KMRNCTRLSTA_CTRL_OFFSET
,
2000 ret_val
= e1000e_read_kmrn_reg(hw
,
2001 E1000_KMRNCTRLSTA_HD_CTRL
,
2005 data
&= ~(0xF << 8);
2007 ret_val
= e1000e_write_kmrn_reg(hw
,
2008 E1000_KMRNCTRLSTA_HD_CTRL
,
2013 /* Enable jumbo frame workaround in the PHY */
2014 e1e_rphy(hw
, PHY_REG(769, 23), &data
);
2015 data
&= ~(0x7F << 5);
2016 data
|= (0x37 << 5);
2017 ret_val
= e1e_wphy(hw
, PHY_REG(769, 23), data
);
2020 e1e_rphy(hw
, PHY_REG(769, 16), &data
);
2022 ret_val
= e1e_wphy(hw
, PHY_REG(769, 16), data
);
2025 e1e_rphy(hw
, PHY_REG(776, 20), &data
);
2026 data
&= ~(0x3FF << 2);
2027 data
|= (0x1A << 2);
2028 ret_val
= e1e_wphy(hw
, PHY_REG(776, 20), data
);
2031 ret_val
= e1e_wphy(hw
, PHY_REG(776, 23), 0xF100);
2034 e1e_rphy(hw
, HV_PM_CTRL
, &data
);
2035 ret_val
= e1e_wphy(hw
, HV_PM_CTRL
, data
| (1 << 10));
2039 /* Write MAC register values back to h/w defaults */
2040 mac_reg
= er32(FFLT_DBG
);
2041 mac_reg
&= ~(0xF << 14);
2042 ew32(FFLT_DBG
, mac_reg
);
2044 mac_reg
= er32(RCTL
);
2045 mac_reg
&= ~E1000_RCTL_SECRC
;
2046 ew32(RCTL
, mac_reg
);
2048 ret_val
= e1000e_read_kmrn_reg(hw
,
2049 E1000_KMRNCTRLSTA_CTRL_OFFSET
,
2053 ret_val
= e1000e_write_kmrn_reg(hw
,
2054 E1000_KMRNCTRLSTA_CTRL_OFFSET
,
2058 ret_val
= e1000e_read_kmrn_reg(hw
,
2059 E1000_KMRNCTRLSTA_HD_CTRL
,
2063 data
&= ~(0xF << 8);
2065 ret_val
= e1000e_write_kmrn_reg(hw
,
2066 E1000_KMRNCTRLSTA_HD_CTRL
,
2071 /* Write PHY register values back to h/w defaults */
2072 e1e_rphy(hw
, PHY_REG(769, 23), &data
);
2073 data
&= ~(0x7F << 5);
2074 ret_val
= e1e_wphy(hw
, PHY_REG(769, 23), data
);
2077 e1e_rphy(hw
, PHY_REG(769, 16), &data
);
2079 ret_val
= e1e_wphy(hw
, PHY_REG(769, 16), data
);
2082 e1e_rphy(hw
, PHY_REG(776, 20), &data
);
2083 data
&= ~(0x3FF << 2);
2085 ret_val
= e1e_wphy(hw
, PHY_REG(776, 20), data
);
2088 ret_val
= e1e_wphy(hw
, PHY_REG(776, 23), 0x7E00);
2091 e1e_rphy(hw
, HV_PM_CTRL
, &data
);
2092 ret_val
= e1e_wphy(hw
, HV_PM_CTRL
, data
& ~(1 << 10));
2097 /* re-enable Rx path after enabling/disabling workaround */
2098 return e1e_wphy(hw
, PHY_REG(769, 20), phy_reg
& ~(1 << 14));
2102 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2103 * done after every PHY reset.
2105 static s32
e1000_lv_phy_workarounds_ich8lan(struct e1000_hw
*hw
)
2109 if (hw
->mac
.type
!= e1000_pch2lan
)
2112 /* Set MDIO slow mode before any other MDIO access */
2113 ret_val
= e1000_set_mdio_slow_mode_hv(hw
);
2117 ret_val
= hw
->phy
.ops
.acquire(hw
);
2120 /* set MSE higher to enable link to stay up when noise is high */
2121 ret_val
= e1000_write_emi_reg_locked(hw
, I82579_MSE_THRESHOLD
, 0x0034);
2124 /* drop link after 5 times MSE threshold was reached */
2125 ret_val
= e1000_write_emi_reg_locked(hw
, I82579_MSE_LINK_DOWN
, 0x0005);
2127 hw
->phy
.ops
.release(hw
);
2133 * e1000_k1_gig_workaround_lv - K1 Si workaround
2134 * @hw: pointer to the HW structure
2136 * Workaround to set the K1 beacon duration for 82579 parts
2138 static s32
e1000_k1_workaround_lv(struct e1000_hw
*hw
)
2145 if (hw
->mac
.type
!= e1000_pch2lan
)
2148 /* Set K1 beacon duration based on 1Gbps speed or otherwise */
2149 ret_val
= e1e_rphy(hw
, HV_M_STATUS
, &status_reg
);
2153 if ((status_reg
& (HV_M_STATUS_LINK_UP
| HV_M_STATUS_AUTONEG_COMPLETE
))
2154 == (HV_M_STATUS_LINK_UP
| HV_M_STATUS_AUTONEG_COMPLETE
)) {
2155 mac_reg
= er32(FEXTNVM4
);
2156 mac_reg
&= ~E1000_FEXTNVM4_BEACON_DURATION_MASK
;
2158 ret_val
= e1e_rphy(hw
, I82579_LPI_CTRL
, &phy_reg
);
2162 if (status_reg
& HV_M_STATUS_SPEED_1000
) {
2165 mac_reg
|= E1000_FEXTNVM4_BEACON_DURATION_8USEC
;
2166 phy_reg
&= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT
;
2167 /* LV 1G Packet drop issue wa */
2168 ret_val
= e1e_rphy(hw
, HV_PM_CTRL
, &pm_phy_reg
);
2171 pm_phy_reg
&= ~HV_PM_CTRL_PLL_STOP_IN_K1_GIGA
;
2172 ret_val
= e1e_wphy(hw
, HV_PM_CTRL
, pm_phy_reg
);
2176 mac_reg
|= E1000_FEXTNVM4_BEACON_DURATION_16USEC
;
2177 phy_reg
|= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT
;
2179 ew32(FEXTNVM4
, mac_reg
);
2180 ret_val
= e1e_wphy(hw
, I82579_LPI_CTRL
, phy_reg
);
2187 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2188 * @hw: pointer to the HW structure
2189 * @gate: boolean set to true to gate, false to ungate
2191 * Gate/ungate the automatic PHY configuration via hardware; perform
2192 * the configuration via software instead.
2194 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw
*hw
, bool gate
)
2198 if (hw
->mac
.type
< e1000_pch2lan
)
2201 extcnf_ctrl
= er32(EXTCNF_CTRL
);
2204 extcnf_ctrl
|= E1000_EXTCNF_CTRL_GATE_PHY_CFG
;
2206 extcnf_ctrl
&= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG
;
2208 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
2212 * e1000_lan_init_done_ich8lan - Check for PHY config completion
2213 * @hw: pointer to the HW structure
2215 * Check the appropriate indication the MAC has finished configuring the
2216 * PHY after a software reset.
2218 static void e1000_lan_init_done_ich8lan(struct e1000_hw
*hw
)
2220 u32 data
, loop
= E1000_ICH8_LAN_INIT_TIMEOUT
;
2222 /* Wait for basic configuration completes before proceeding */
2224 data
= er32(STATUS
);
2225 data
&= E1000_STATUS_LAN_INIT_DONE
;
2226 usleep_range(100, 200);
2227 } while ((!data
) && --loop
);
2229 /* If basic configuration is incomplete before the above loop
2230 * count reaches 0, loading the configuration from NVM will
2231 * leave the PHY in a bad state possibly resulting in no link.
2234 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
2236 /* Clear the Init Done bit for the next init event */
2237 data
= er32(STATUS
);
2238 data
&= ~E1000_STATUS_LAN_INIT_DONE
;
2243 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2244 * @hw: pointer to the HW structure
2246 static s32
e1000_post_phy_reset_ich8lan(struct e1000_hw
*hw
)
2251 if (hw
->phy
.ops
.check_reset_block(hw
))
2254 /* Allow time for h/w to get to quiescent state after reset */
2255 usleep_range(10000, 20000);
2257 /* Perform any necessary post-reset workarounds */
2258 switch (hw
->mac
.type
) {
2260 ret_val
= e1000_hv_phy_workarounds_ich8lan(hw
);
2265 ret_val
= e1000_lv_phy_workarounds_ich8lan(hw
);
2273 /* Clear the host wakeup bit after lcd reset */
2274 if (hw
->mac
.type
>= e1000_pchlan
) {
2275 e1e_rphy(hw
, BM_PORT_GEN_CFG
, ®
);
2276 reg
&= ~BM_WUC_HOST_WU_BIT
;
2277 e1e_wphy(hw
, BM_PORT_GEN_CFG
, reg
);
2280 /* Configure the LCD with the extended configuration region in NVM */
2281 ret_val
= e1000_sw_lcd_config_ich8lan(hw
);
2285 /* Configure the LCD with the OEM bits in NVM */
2286 ret_val
= e1000_oem_bits_config_ich8lan(hw
, true);
2288 if (hw
->mac
.type
== e1000_pch2lan
) {
2289 /* Ungate automatic PHY configuration on non-managed 82579 */
2290 if (!(er32(FWSM
) & E1000_ICH_FWSM_FW_VALID
)) {
2291 usleep_range(10000, 20000);
2292 e1000_gate_hw_phy_config_ich8lan(hw
, false);
2295 /* Set EEE LPI Update Timer to 200usec */
2296 ret_val
= hw
->phy
.ops
.acquire(hw
);
2299 ret_val
= e1000_write_emi_reg_locked(hw
,
2300 I82579_LPI_UPDATE_TIMER
,
2302 hw
->phy
.ops
.release(hw
);
2309 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2310 * @hw: pointer to the HW structure
2313 * This is a function pointer entry point called by drivers
2314 * or other shared routines.
2316 static s32
e1000_phy_hw_reset_ich8lan(struct e1000_hw
*hw
)
2320 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2321 if ((hw
->mac
.type
== e1000_pch2lan
) &&
2322 !(er32(FWSM
) & E1000_ICH_FWSM_FW_VALID
))
2323 e1000_gate_hw_phy_config_ich8lan(hw
, true);
2325 ret_val
= e1000e_phy_hw_reset_generic(hw
);
2329 return e1000_post_phy_reset_ich8lan(hw
);
2333 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2334 * @hw: pointer to the HW structure
2335 * @active: true to enable LPLU, false to disable
2337 * Sets the LPLU state according to the active flag. For PCH, if OEM write
2338 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2339 * the phy speed. This function will manually set the LPLU bit and restart
2340 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
2341 * since it configures the same bit.
2343 static s32
e1000_set_lplu_state_pchlan(struct e1000_hw
*hw
, bool active
)
2348 ret_val
= e1e_rphy(hw
, HV_OEM_BITS
, &oem_reg
);
2353 oem_reg
|= HV_OEM_BITS_LPLU
;
2355 oem_reg
&= ~HV_OEM_BITS_LPLU
;
2357 if (!hw
->phy
.ops
.check_reset_block(hw
))
2358 oem_reg
|= HV_OEM_BITS_RESTART_AN
;
2360 return e1e_wphy(hw
, HV_OEM_BITS
, oem_reg
);
2364 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2365 * @hw: pointer to the HW structure
2366 * @active: true to enable LPLU, false to disable
2368 * Sets the LPLU D0 state according to the active flag. When
2369 * activating LPLU this function also disables smart speed
2370 * and vice versa. LPLU will not be activated unless the
2371 * device autonegotiation advertisement meets standards of
2372 * either 10 or 10/100 or 10/100/1000 at all duplexes.
2373 * This is a function pointer entry point only called by
2374 * PHY setup routines.
2376 static s32
e1000_set_d0_lplu_state_ich8lan(struct e1000_hw
*hw
, bool active
)
2378 struct e1000_phy_info
*phy
= &hw
->phy
;
2383 if (phy
->type
== e1000_phy_ife
)
2386 phy_ctrl
= er32(PHY_CTRL
);
2389 phy_ctrl
|= E1000_PHY_CTRL_D0A_LPLU
;
2390 ew32(PHY_CTRL
, phy_ctrl
);
2392 if (phy
->type
!= e1000_phy_igp_3
)
2395 /* Call gig speed drop workaround on LPLU before accessing
2398 if (hw
->mac
.type
== e1000_ich8lan
)
2399 e1000e_gig_downshift_workaround_ich8lan(hw
);
2401 /* When LPLU is enabled, we should disable SmartSpeed */
2402 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, &data
);
2405 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
2406 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, data
);
2410 phy_ctrl
&= ~E1000_PHY_CTRL_D0A_LPLU
;
2411 ew32(PHY_CTRL
, phy_ctrl
);
2413 if (phy
->type
!= e1000_phy_igp_3
)
2416 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
2417 * during Dx states where the power conservation is most
2418 * important. During driver activity we should enable
2419 * SmartSpeed, so performance is maintained.
2421 if (phy
->smart_speed
== e1000_smart_speed_on
) {
2422 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
2427 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
2428 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
2432 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
2433 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
2438 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
2439 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
2450 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
2451 * @hw: pointer to the HW structure
2452 * @active: true to enable LPLU, false to disable
2454 * Sets the LPLU D3 state according to the active flag. When
2455 * activating LPLU this function also disables smart speed
2456 * and vice versa. LPLU will not be activated unless the
2457 * device autonegotiation advertisement meets standards of
2458 * either 10 or 10/100 or 10/100/1000 at all duplexes.
2459 * This is a function pointer entry point only called by
2460 * PHY setup routines.
2462 static s32
e1000_set_d3_lplu_state_ich8lan(struct e1000_hw
*hw
, bool active
)
2464 struct e1000_phy_info
*phy
= &hw
->phy
;
2469 phy_ctrl
= er32(PHY_CTRL
);
2472 phy_ctrl
&= ~E1000_PHY_CTRL_NOND0A_LPLU
;
2473 ew32(PHY_CTRL
, phy_ctrl
);
2475 if (phy
->type
!= e1000_phy_igp_3
)
2478 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
2479 * during Dx states where the power conservation is most
2480 * important. During driver activity we should enable
2481 * SmartSpeed, so performance is maintained.
2483 if (phy
->smart_speed
== e1000_smart_speed_on
) {
2484 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
2489 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
2490 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
2494 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
2495 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
2500 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
2501 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
2506 } else if ((phy
->autoneg_advertised
== E1000_ALL_SPEED_DUPLEX
) ||
2507 (phy
->autoneg_advertised
== E1000_ALL_NOT_GIG
) ||
2508 (phy
->autoneg_advertised
== E1000_ALL_10_SPEED
)) {
2509 phy_ctrl
|= E1000_PHY_CTRL_NOND0A_LPLU
;
2510 ew32(PHY_CTRL
, phy_ctrl
);
2512 if (phy
->type
!= e1000_phy_igp_3
)
2515 /* Call gig speed drop workaround on LPLU before accessing
2518 if (hw
->mac
.type
== e1000_ich8lan
)
2519 e1000e_gig_downshift_workaround_ich8lan(hw
);
2521 /* When LPLU is enabled, we should disable SmartSpeed */
2522 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, &data
);
2526 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
2527 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, data
);
2534 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
2535 * @hw: pointer to the HW structure
2536 * @bank: pointer to the variable that returns the active bank
2538 * Reads signature byte from the NVM using the flash access registers.
2539 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
2541 static s32
e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw
*hw
, u32
*bank
)
2544 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
2545 u32 bank1_offset
= nvm
->flash_bank_size
* sizeof(u16
);
2546 u32 act_offset
= E1000_ICH_NVM_SIG_WORD
* 2 + 1;
2550 switch (hw
->mac
.type
) {
2554 if ((eecd
& E1000_EECD_SEC1VAL_VALID_MASK
) ==
2555 E1000_EECD_SEC1VAL_VALID_MASK
) {
2556 if (eecd
& E1000_EECD_SEC1VAL
)
2563 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
2566 /* set bank to 0 in case flash read fails */
2570 ret_val
= e1000_read_flash_byte_ich8lan(hw
, act_offset
,
2574 if ((sig_byte
& E1000_ICH_NVM_VALID_SIG_MASK
) ==
2575 E1000_ICH_NVM_SIG_VALUE
) {
2581 ret_val
= e1000_read_flash_byte_ich8lan(hw
, act_offset
+
2586 if ((sig_byte
& E1000_ICH_NVM_VALID_SIG_MASK
) ==
2587 E1000_ICH_NVM_SIG_VALUE
) {
2592 e_dbg("ERROR: No valid NVM bank present\n");
2593 return -E1000_ERR_NVM
;
2598 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
2599 * @hw: pointer to the HW structure
2600 * @offset: The offset (in bytes) of the word(s) to read.
2601 * @words: Size of data to read in words
2602 * @data: Pointer to the word(s) to read at offset.
2604 * Reads a word(s) from the NVM using the flash access registers.
2606 static s32
e1000_read_nvm_ich8lan(struct e1000_hw
*hw
, u16 offset
, u16 words
,
2609 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
2610 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
2616 if ((offset
>= nvm
->word_size
) || (words
> nvm
->word_size
- offset
) ||
2618 e_dbg("nvm parameter(s) out of bounds\n");
2619 ret_val
= -E1000_ERR_NVM
;
2623 nvm
->ops
.acquire(hw
);
2625 ret_val
= e1000_valid_nvm_bank_detect_ich8lan(hw
, &bank
);
2627 e_dbg("Could not detect valid bank, assuming bank 0\n");
2631 act_offset
= (bank
) ? nvm
->flash_bank_size
: 0;
2632 act_offset
+= offset
;
2635 for (i
= 0; i
< words
; i
++) {
2636 if (dev_spec
->shadow_ram
[offset
+ i
].modified
) {
2637 data
[i
] = dev_spec
->shadow_ram
[offset
+ i
].value
;
2639 ret_val
= e1000_read_flash_word_ich8lan(hw
,
2648 nvm
->ops
.release(hw
);
2652 e_dbg("NVM read error: %d\n", ret_val
);
2658 * e1000_flash_cycle_init_ich8lan - Initialize flash
2659 * @hw: pointer to the HW structure
2661 * This function does initial flash setup so that a new read/write/erase cycle
2664 static s32
e1000_flash_cycle_init_ich8lan(struct e1000_hw
*hw
)
2666 union ich8_hws_flash_status hsfsts
;
2667 s32 ret_val
= -E1000_ERR_NVM
;
2669 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
2671 /* Check if the flash descriptor is valid */
2672 if (!hsfsts
.hsf_status
.fldesvalid
) {
2673 e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n");
2674 return -E1000_ERR_NVM
;
2677 /* Clear FCERR and DAEL in hw status by writing 1 */
2678 hsfsts
.hsf_status
.flcerr
= 1;
2679 hsfsts
.hsf_status
.dael
= 1;
2681 ew16flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
2683 /* Either we should have a hardware SPI cycle in progress
2684 * bit to check against, in order to start a new cycle or
2685 * FDONE bit should be changed in the hardware so that it
2686 * is 1 after hardware reset, which can then be used as an
2687 * indication whether a cycle is in progress or has been
2691 if (!hsfsts
.hsf_status
.flcinprog
) {
2692 /* There is no cycle running at present,
2693 * so we can start a cycle.
2694 * Begin by setting Flash Cycle Done.
2696 hsfsts
.hsf_status
.flcdone
= 1;
2697 ew16flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
2702 /* Otherwise poll for sometime so the current
2703 * cycle has a chance to end before giving up.
2705 for (i
= 0; i
< ICH_FLASH_READ_COMMAND_TIMEOUT
; i
++) {
2706 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
2707 if (!hsfsts
.hsf_status
.flcinprog
) {
2714 /* Successful in waiting for previous cycle to timeout,
2715 * now set the Flash Cycle Done.
2717 hsfsts
.hsf_status
.flcdone
= 1;
2718 ew16flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
2720 e_dbg("Flash controller busy, cannot get access\n");
2728 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2729 * @hw: pointer to the HW structure
2730 * @timeout: maximum time to wait for completion
2732 * This function starts a flash cycle and waits for its completion.
2734 static s32
e1000_flash_cycle_ich8lan(struct e1000_hw
*hw
, u32 timeout
)
2736 union ich8_hws_flash_ctrl hsflctl
;
2737 union ich8_hws_flash_status hsfsts
;
2740 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2741 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
2742 hsflctl
.hsf_ctrl
.flcgo
= 1;
2743 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
2745 /* wait till FDONE bit is set to 1 */
2747 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
2748 if (hsfsts
.hsf_status
.flcdone
)
2751 } while (i
++ < timeout
);
2753 if (hsfsts
.hsf_status
.flcdone
&& !hsfsts
.hsf_status
.flcerr
)
2756 return -E1000_ERR_NVM
;
2760 * e1000_read_flash_word_ich8lan - Read word from flash
2761 * @hw: pointer to the HW structure
2762 * @offset: offset to data location
2763 * @data: pointer to the location for storing the data
2765 * Reads the flash word at offset into data. Offset is converted
2766 * to bytes before read.
2768 static s32
e1000_read_flash_word_ich8lan(struct e1000_hw
*hw
, u32 offset
,
2771 /* Must convert offset into bytes. */
2774 return e1000_read_flash_data_ich8lan(hw
, offset
, 2, data
);
2778 * e1000_read_flash_byte_ich8lan - Read byte from flash
2779 * @hw: pointer to the HW structure
2780 * @offset: The offset of the byte to read.
2781 * @data: Pointer to a byte to store the value read.
2783 * Reads a single byte from the NVM using the flash access registers.
2785 static s32
e1000_read_flash_byte_ich8lan(struct e1000_hw
*hw
, u32 offset
,
2791 ret_val
= e1000_read_flash_data_ich8lan(hw
, offset
, 1, &word
);
2801 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
2802 * @hw: pointer to the HW structure
2803 * @offset: The offset (in bytes) of the byte or word to read.
2804 * @size: Size of data to read, 1=byte 2=word
2805 * @data: Pointer to the word to store the value read.
2807 * Reads a byte or word from the NVM using the flash access registers.
2809 static s32
e1000_read_flash_data_ich8lan(struct e1000_hw
*hw
, u32 offset
,
2812 union ich8_hws_flash_status hsfsts
;
2813 union ich8_hws_flash_ctrl hsflctl
;
2814 u32 flash_linear_addr
;
2816 s32 ret_val
= -E1000_ERR_NVM
;
2819 if (size
< 1 || size
> 2 || offset
> ICH_FLASH_LINEAR_ADDR_MASK
)
2820 return -E1000_ERR_NVM
;
2822 flash_linear_addr
= ((ICH_FLASH_LINEAR_ADDR_MASK
& offset
) +
2823 hw
->nvm
.flash_base_addr
);
2828 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
2832 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
2833 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2834 hsflctl
.hsf_ctrl
.fldbcount
= size
- 1;
2835 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_READ
;
2836 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
2838 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
2841 e1000_flash_cycle_ich8lan(hw
,
2842 ICH_FLASH_READ_COMMAND_TIMEOUT
);
2844 /* Check if FCERR is set to 1, if set to 1, clear it
2845 * and try the whole sequence a few more times, else
2846 * read in (shift in) the Flash Data0, the order is
2847 * least significant byte first msb to lsb
2850 flash_data
= er32flash(ICH_FLASH_FDATA0
);
2852 *data
= (u8
)(flash_data
& 0x000000FF);
2854 *data
= (u16
)(flash_data
& 0x0000FFFF);
2857 /* If we've gotten here, then things are probably
2858 * completely hosed, but if the error condition is
2859 * detected, it won't hurt to give it another try...
2860 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2862 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
2863 if (hsfsts
.hsf_status
.flcerr
) {
2864 /* Repeat for some time before giving up. */
2866 } else if (!hsfsts
.hsf_status
.flcdone
) {
2867 e_dbg("Timeout error - flash cycle did not complete.\n");
2871 } while (count
++ < ICH_FLASH_CYCLE_REPEAT_COUNT
);
2877 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
2878 * @hw: pointer to the HW structure
2879 * @offset: The offset (in bytes) of the word(s) to write.
2880 * @words: Size of data to write in words
2881 * @data: Pointer to the word(s) to write at offset.
2883 * Writes a byte or word to the NVM using the flash access registers.
2885 static s32
e1000_write_nvm_ich8lan(struct e1000_hw
*hw
, u16 offset
, u16 words
,
2888 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
2889 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
2892 if ((offset
>= nvm
->word_size
) || (words
> nvm
->word_size
- offset
) ||
2894 e_dbg("nvm parameter(s) out of bounds\n");
2895 return -E1000_ERR_NVM
;
2898 nvm
->ops
.acquire(hw
);
2900 for (i
= 0; i
< words
; i
++) {
2901 dev_spec
->shadow_ram
[offset
+ i
].modified
= true;
2902 dev_spec
->shadow_ram
[offset
+ i
].value
= data
[i
];
2905 nvm
->ops
.release(hw
);
2911 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2912 * @hw: pointer to the HW structure
2914 * The NVM checksum is updated by calling the generic update_nvm_checksum,
2915 * which writes the checksum to the shadow ram. The changes in the shadow
2916 * ram are then committed to the EEPROM by processing each bank at a time
2917 * checking for the modified bit and writing only the pending changes.
2918 * After a successful commit, the shadow ram is cleared and is ready for
2921 static s32
e1000_update_nvm_checksum_ich8lan(struct e1000_hw
*hw
)
2923 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
2924 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
2925 u32 i
, act_offset
, new_bank_offset
, old_bank_offset
, bank
;
2929 ret_val
= e1000e_update_nvm_checksum_generic(hw
);
2933 if (nvm
->type
!= e1000_nvm_flash_sw
)
2936 nvm
->ops
.acquire(hw
);
2938 /* We're writing to the opposite bank so if we're on bank 1,
2939 * write to bank 0 etc. We also need to erase the segment that
2940 * is going to be written
2942 ret_val
= e1000_valid_nvm_bank_detect_ich8lan(hw
, &bank
);
2944 e_dbg("Could not detect valid bank, assuming bank 0\n");
2949 new_bank_offset
= nvm
->flash_bank_size
;
2950 old_bank_offset
= 0;
2951 ret_val
= e1000_erase_flash_bank_ich8lan(hw
, 1);
2955 old_bank_offset
= nvm
->flash_bank_size
;
2956 new_bank_offset
= 0;
2957 ret_val
= e1000_erase_flash_bank_ich8lan(hw
, 0);
2962 for (i
= 0; i
< E1000_ICH8_SHADOW_RAM_WORDS
; i
++) {
2963 /* Determine whether to write the value stored
2964 * in the other NVM bank or a modified value stored
2967 if (dev_spec
->shadow_ram
[i
].modified
) {
2968 data
= dev_spec
->shadow_ram
[i
].value
;
2970 ret_val
= e1000_read_flash_word_ich8lan(hw
, i
+
2977 /* If the word is 0x13, then make sure the signature bits
2978 * (15:14) are 11b until the commit has completed.
2979 * This will allow us to write 10b which indicates the
2980 * signature is valid. We want to do this after the write
2981 * has completed so that we don't mark the segment valid
2982 * while the write is still in progress
2984 if (i
== E1000_ICH_NVM_SIG_WORD
)
2985 data
|= E1000_ICH_NVM_SIG_MASK
;
2987 /* Convert offset to bytes. */
2988 act_offset
= (i
+ new_bank_offset
) << 1;
2990 usleep_range(100, 200);
2991 /* Write the bytes to the new bank. */
2992 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
,
2998 usleep_range(100, 200);
2999 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
,
3006 /* Don't bother writing the segment valid bits if sector
3007 * programming failed.
3010 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3011 e_dbg("Flash commit failed.\n");
3015 /* Finally validate the new segment by setting bit 15:14
3016 * to 10b in word 0x13 , this can be done without an
3017 * erase as well since these bits are 11 to start with
3018 * and we need to change bit 14 to 0b
3020 act_offset
= new_bank_offset
+ E1000_ICH_NVM_SIG_WORD
;
3021 ret_val
= e1000_read_flash_word_ich8lan(hw
, act_offset
, &data
);
3026 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
,
3032 /* And invalidate the previously valid segment by setting
3033 * its signature word (0x13) high_byte to 0b. This can be
3034 * done without an erase because flash erase sets all bits
3035 * to 1's. We can write 1's to 0's without an erase
3037 act_offset
= (old_bank_offset
+ E1000_ICH_NVM_SIG_WORD
) * 2 + 1;
3038 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
, act_offset
, 0);
3042 /* Great! Everything worked, we can now clear the cached entries. */
3043 for (i
= 0; i
< E1000_ICH8_SHADOW_RAM_WORDS
; i
++) {
3044 dev_spec
->shadow_ram
[i
].modified
= false;
3045 dev_spec
->shadow_ram
[i
].value
= 0xFFFF;
3049 nvm
->ops
.release(hw
);
3051 /* Reload the EEPROM, or else modifications will not appear
3052 * until after the next adapter reset.
3055 nvm
->ops
.reload(hw
);
3056 usleep_range(10000, 20000);
3061 e_dbg("NVM update error: %d\n", ret_val
);
3067 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
3068 * @hw: pointer to the HW structure
3070 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
3071 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
3072 * calculated, in which case we need to calculate the checksum and set bit 6.
3074 static s32
e1000_validate_nvm_checksum_ich8lan(struct e1000_hw
*hw
)
3079 u16 valid_csum_mask
;
3081 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
3082 * the checksum needs to be fixed. This bit is an indication that
3083 * the NVM was prepared by OEM software and did not calculate
3084 * the checksum...a likely scenario.
3086 switch (hw
->mac
.type
) {
3089 valid_csum_mask
= NVM_COMPAT_VALID_CSUM
;
3092 word
= NVM_FUTURE_INIT_WORD1
;
3093 valid_csum_mask
= NVM_FUTURE_INIT_WORD1_VALID_CSUM
;
3097 ret_val
= e1000_read_nvm(hw
, word
, 1, &data
);
3101 if (!(data
& valid_csum_mask
)) {
3102 data
|= valid_csum_mask
;
3103 ret_val
= e1000_write_nvm(hw
, word
, 1, &data
);
3106 ret_val
= e1000e_update_nvm_checksum(hw
);
3111 return e1000e_validate_nvm_checksum_generic(hw
);
3115 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
3116 * @hw: pointer to the HW structure
3118 * To prevent malicious write/erase of the NVM, set it to be read-only
3119 * so that the hardware ignores all write/erase cycles of the NVM via
3120 * the flash control registers. The shadow-ram copy of the NVM will
3121 * still be updated, however any updates to this copy will not stick
3122 * across driver reloads.
3124 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw
*hw
)
3126 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
3127 union ich8_flash_protected_range pr0
;
3128 union ich8_hws_flash_status hsfsts
;
3131 nvm
->ops
.acquire(hw
);
3133 gfpreg
= er32flash(ICH_FLASH_GFPREG
);
3135 /* Write-protect GbE Sector of NVM */
3136 pr0
.regval
= er32flash(ICH_FLASH_PR0
);
3137 pr0
.range
.base
= gfpreg
& FLASH_GFPREG_BASE_MASK
;
3138 pr0
.range
.limit
= ((gfpreg
>> 16) & FLASH_GFPREG_BASE_MASK
);
3139 pr0
.range
.wpe
= true;
3140 ew32flash(ICH_FLASH_PR0
, pr0
.regval
);
3142 /* Lock down a subset of GbE Flash Control Registers, e.g.
3143 * PR0 to prevent the write-protection from being lifted.
3144 * Once FLOCKDN is set, the registers protected by it cannot
3145 * be written until FLOCKDN is cleared by a hardware reset.
3147 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
3148 hsfsts
.hsf_status
.flockdn
= true;
3149 ew32flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
3151 nvm
->ops
.release(hw
);
3155 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
3156 * @hw: pointer to the HW structure
3157 * @offset: The offset (in bytes) of the byte/word to read.
3158 * @size: Size of data to read, 1=byte 2=word
3159 * @data: The byte(s) to write to the NVM.
3161 * Writes one/two bytes to the NVM using the flash access registers.
3163 static s32
e1000_write_flash_data_ich8lan(struct e1000_hw
*hw
, u32 offset
,
3166 union ich8_hws_flash_status hsfsts
;
3167 union ich8_hws_flash_ctrl hsflctl
;
3168 u32 flash_linear_addr
;
3173 if (size
< 1 || size
> 2 || data
> size
* 0xff ||
3174 offset
> ICH_FLASH_LINEAR_ADDR_MASK
)
3175 return -E1000_ERR_NVM
;
3177 flash_linear_addr
= ((ICH_FLASH_LINEAR_ADDR_MASK
& offset
) +
3178 hw
->nvm
.flash_base_addr
);
3183 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
3187 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
3188 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3189 hsflctl
.hsf_ctrl
.fldbcount
= size
- 1;
3190 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_WRITE
;
3191 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
3193 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
3196 flash_data
= (u32
)data
& 0x00FF;
3198 flash_data
= (u32
)data
;
3200 ew32flash(ICH_FLASH_FDATA0
, flash_data
);
3202 /* check if FCERR is set to 1 , if set to 1, clear it
3203 * and try the whole sequence a few more times else done
3206 e1000_flash_cycle_ich8lan(hw
,
3207 ICH_FLASH_WRITE_COMMAND_TIMEOUT
);
3211 /* If we're here, then things are most likely
3212 * completely hosed, but if the error condition
3213 * is detected, it won't hurt to give it another
3214 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
3216 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
3217 if (hsfsts
.hsf_status
.flcerr
)
3218 /* Repeat for some time before giving up. */
3220 if (!hsfsts
.hsf_status
.flcdone
) {
3221 e_dbg("Timeout error - flash cycle did not complete.\n");
3224 } while (count
++ < ICH_FLASH_CYCLE_REPEAT_COUNT
);
3230 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
3231 * @hw: pointer to the HW structure
3232 * @offset: The index of the byte to read.
3233 * @data: The byte to write to the NVM.
3235 * Writes a single byte to the NVM using the flash access registers.
3237 static s32
e1000_write_flash_byte_ich8lan(struct e1000_hw
*hw
, u32 offset
,
3240 u16 word
= (u16
)data
;
3242 return e1000_write_flash_data_ich8lan(hw
, offset
, 1, word
);
3246 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
3247 * @hw: pointer to the HW structure
3248 * @offset: The offset of the byte to write.
3249 * @byte: The byte to write to the NVM.
3251 * Writes a single byte to the NVM using the flash access registers.
3252 * Goes through a retry algorithm before giving up.
3254 static s32
e1000_retry_write_flash_byte_ich8lan(struct e1000_hw
*hw
,
3255 u32 offset
, u8 byte
)
3258 u16 program_retries
;
3260 ret_val
= e1000_write_flash_byte_ich8lan(hw
, offset
, byte
);
3264 for (program_retries
= 0; program_retries
< 100; program_retries
++) {
3265 e_dbg("Retrying Byte %2.2X at offset %u\n", byte
, offset
);
3266 usleep_range(100, 200);
3267 ret_val
= e1000_write_flash_byte_ich8lan(hw
, offset
, byte
);
3271 if (program_retries
== 100)
3272 return -E1000_ERR_NVM
;
3278 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
3279 * @hw: pointer to the HW structure
3280 * @bank: 0 for first bank, 1 for second bank, etc.
3282 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
3283 * bank N is 4096 * N + flash_reg_addr.
3285 static s32
e1000_erase_flash_bank_ich8lan(struct e1000_hw
*hw
, u32 bank
)
3287 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
3288 union ich8_hws_flash_status hsfsts
;
3289 union ich8_hws_flash_ctrl hsflctl
;
3290 u32 flash_linear_addr
;
3291 /* bank size is in 16bit words - adjust to bytes */
3292 u32 flash_bank_size
= nvm
->flash_bank_size
* 2;
3295 s32 j
, iteration
, sector_size
;
3297 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
3299 /* Determine HW Sector size: Read BERASE bits of hw flash status
3301 * 00: The Hw sector is 256 bytes, hence we need to erase 16
3302 * consecutive sectors. The start index for the nth Hw sector
3303 * can be calculated as = bank * 4096 + n * 256
3304 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
3305 * The start index for the nth Hw sector can be calculated
3307 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
3308 * (ich9 only, otherwise error condition)
3309 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
3311 switch (hsfsts
.hsf_status
.berasesz
) {
3313 /* Hw sector size 256 */
3314 sector_size
= ICH_FLASH_SEG_SIZE_256
;
3315 iteration
= flash_bank_size
/ ICH_FLASH_SEG_SIZE_256
;
3318 sector_size
= ICH_FLASH_SEG_SIZE_4K
;
3322 sector_size
= ICH_FLASH_SEG_SIZE_8K
;
3326 sector_size
= ICH_FLASH_SEG_SIZE_64K
;
3330 return -E1000_ERR_NVM
;
3333 /* Start with the base address, then add the sector offset. */
3334 flash_linear_addr
= hw
->nvm
.flash_base_addr
;
3335 flash_linear_addr
+= (bank
) ? flash_bank_size
: 0;
3337 for (j
= 0; j
< iteration
; j
++) {
3339 u32 timeout
= ICH_FLASH_ERASE_COMMAND_TIMEOUT
;
3342 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
3346 /* Write a value 11 (block Erase) in Flash
3347 * Cycle field in hw flash control
3349 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
3350 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_ERASE
;
3351 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
3353 /* Write the last 24 bits of an index within the
3354 * block into Flash Linear address field in Flash
3357 flash_linear_addr
+= (j
* sector_size
);
3358 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
3360 ret_val
= e1000_flash_cycle_ich8lan(hw
, timeout
);
3364 /* Check if FCERR is set to 1. If 1,
3365 * clear it and try the whole sequence
3366 * a few more times else Done
3368 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
3369 if (hsfsts
.hsf_status
.flcerr
)
3370 /* repeat for some time before giving up */
3372 else if (!hsfsts
.hsf_status
.flcdone
)
3374 } while (++count
< ICH_FLASH_CYCLE_REPEAT_COUNT
);
3381 * e1000_valid_led_default_ich8lan - Set the default LED settings
3382 * @hw: pointer to the HW structure
3383 * @data: Pointer to the LED settings
3385 * Reads the LED default settings from the NVM to data. If the NVM LED
3386 * settings is all 0's or F's, set the LED default to a valid LED default
3389 static s32
e1000_valid_led_default_ich8lan(struct e1000_hw
*hw
, u16
*data
)
3393 ret_val
= e1000_read_nvm(hw
, NVM_ID_LED_SETTINGS
, 1, data
);
3395 e_dbg("NVM Read Error\n");
3399 if (*data
== ID_LED_RESERVED_0000
|| *data
== ID_LED_RESERVED_FFFF
)
3400 *data
= ID_LED_DEFAULT_ICH8LAN
;
3406 * e1000_id_led_init_pchlan - store LED configurations
3407 * @hw: pointer to the HW structure
3409 * PCH does not control LEDs via the LEDCTL register, rather it uses
3410 * the PHY LED configuration register.
3412 * PCH also does not have an "always on" or "always off" mode which
3413 * complicates the ID feature. Instead of using the "on" mode to indicate
3414 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
3415 * use "link_up" mode. The LEDs will still ID on request if there is no
3416 * link based on logic in e1000_led_[on|off]_pchlan().
3418 static s32
e1000_id_led_init_pchlan(struct e1000_hw
*hw
)
3420 struct e1000_mac_info
*mac
= &hw
->mac
;
3422 const u32 ledctl_on
= E1000_LEDCTL_MODE_LINK_UP
;
3423 const u32 ledctl_off
= E1000_LEDCTL_MODE_LINK_UP
| E1000_PHY_LED0_IVRT
;
3424 u16 data
, i
, temp
, shift
;
3426 /* Get default ID LED modes */
3427 ret_val
= hw
->nvm
.ops
.valid_led_default(hw
, &data
);
3431 mac
->ledctl_default
= er32(LEDCTL
);
3432 mac
->ledctl_mode1
= mac
->ledctl_default
;
3433 mac
->ledctl_mode2
= mac
->ledctl_default
;
3435 for (i
= 0; i
< 4; i
++) {
3436 temp
= (data
>> (i
<< 2)) & E1000_LEDCTL_LED0_MODE_MASK
;
3439 case ID_LED_ON1_DEF2
:
3440 case ID_LED_ON1_ON2
:
3441 case ID_LED_ON1_OFF2
:
3442 mac
->ledctl_mode1
&= ~(E1000_PHY_LED0_MASK
<< shift
);
3443 mac
->ledctl_mode1
|= (ledctl_on
<< shift
);
3445 case ID_LED_OFF1_DEF2
:
3446 case ID_LED_OFF1_ON2
:
3447 case ID_LED_OFF1_OFF2
:
3448 mac
->ledctl_mode1
&= ~(E1000_PHY_LED0_MASK
<< shift
);
3449 mac
->ledctl_mode1
|= (ledctl_off
<< shift
);
3456 case ID_LED_DEF1_ON2
:
3457 case ID_LED_ON1_ON2
:
3458 case ID_LED_OFF1_ON2
:
3459 mac
->ledctl_mode2
&= ~(E1000_PHY_LED0_MASK
<< shift
);
3460 mac
->ledctl_mode2
|= (ledctl_on
<< shift
);
3462 case ID_LED_DEF1_OFF2
:
3463 case ID_LED_ON1_OFF2
:
3464 case ID_LED_OFF1_OFF2
:
3465 mac
->ledctl_mode2
&= ~(E1000_PHY_LED0_MASK
<< shift
);
3466 mac
->ledctl_mode2
|= (ledctl_off
<< shift
);
3478 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
3479 * @hw: pointer to the HW structure
3481 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
3482 * register, so the the bus width is hard coded.
3484 static s32
e1000_get_bus_info_ich8lan(struct e1000_hw
*hw
)
3486 struct e1000_bus_info
*bus
= &hw
->bus
;
3489 ret_val
= e1000e_get_bus_info_pcie(hw
);
3491 /* ICH devices are "PCI Express"-ish. They have
3492 * a configuration space, but do not contain
3493 * PCI Express Capability registers, so bus width
3494 * must be hardcoded.
3496 if (bus
->width
== e1000_bus_width_unknown
)
3497 bus
->width
= e1000_bus_width_pcie_x1
;
3503 * e1000_reset_hw_ich8lan - Reset the hardware
3504 * @hw: pointer to the HW structure
3506 * Does a full reset of the hardware which includes a reset of the PHY and
3509 static s32
e1000_reset_hw_ich8lan(struct e1000_hw
*hw
)
3511 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
3516 /* Prevent the PCI-E bus from sticking if there is no TLP connection
3517 * on the last TLP read/write transaction when MAC is reset.
3519 ret_val
= e1000e_disable_pcie_master(hw
);
3521 e_dbg("PCI-E Master disable polling has failed.\n");
3523 e_dbg("Masking off all interrupts\n");
3524 ew32(IMC
, 0xffffffff);
3526 /* Disable the Transmit and Receive units. Then delay to allow
3527 * any pending transactions to complete before we hit the MAC
3528 * with the global reset.
3531 ew32(TCTL
, E1000_TCTL_PSP
);
3534 usleep_range(10000, 20000);
3536 /* Workaround for ICH8 bit corruption issue in FIFO memory */
3537 if (hw
->mac
.type
== e1000_ich8lan
) {
3538 /* Set Tx and Rx buffer allocation to 8k apiece. */
3539 ew32(PBA
, E1000_PBA_8K
);
3540 /* Set Packet Buffer Size to 16k. */
3541 ew32(PBS
, E1000_PBS_16K
);
3544 if (hw
->mac
.type
== e1000_pchlan
) {
3545 /* Save the NVM K1 bit setting */
3546 ret_val
= e1000_read_nvm(hw
, E1000_NVM_K1_CONFIG
, 1, &kum_cfg
);
3550 if (kum_cfg
& E1000_NVM_K1_ENABLE
)
3551 dev_spec
->nvm_k1_enabled
= true;
3553 dev_spec
->nvm_k1_enabled
= false;
3558 if (!hw
->phy
.ops
.check_reset_block(hw
)) {
3559 /* Full-chip reset requires MAC and PHY reset at the same
3560 * time to make sure the interface between MAC and the
3561 * external PHY is reset.
3563 ctrl
|= E1000_CTRL_PHY_RST
;
3565 /* Gate automatic PHY configuration by hardware on
3568 if ((hw
->mac
.type
== e1000_pch2lan
) &&
3569 !(er32(FWSM
) & E1000_ICH_FWSM_FW_VALID
))
3570 e1000_gate_hw_phy_config_ich8lan(hw
, true);
3572 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
3573 e_dbg("Issuing a global reset to ich8lan\n");
3574 ew32(CTRL
, (ctrl
| E1000_CTRL_RST
));
3575 /* cannot issue a flush here because it hangs the hardware */
3578 /* Set Phy Config Counter to 50msec */
3579 if (hw
->mac
.type
== e1000_pch2lan
) {
3580 reg
= er32(FEXTNVM3
);
3581 reg
&= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK
;
3582 reg
|= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC
;
3583 ew32(FEXTNVM3
, reg
);
3587 clear_bit(__E1000_ACCESS_SHARED_RESOURCE
, &hw
->adapter
->state
);
3589 if (ctrl
& E1000_CTRL_PHY_RST
) {
3590 ret_val
= hw
->phy
.ops
.get_cfg_done(hw
);
3594 ret_val
= e1000_post_phy_reset_ich8lan(hw
);
3599 /* For PCH, this write will make sure that any noise
3600 * will be detected as a CRC error and be dropped rather than show up
3601 * as a bad packet to the DMA engine.
3603 if (hw
->mac
.type
== e1000_pchlan
)
3604 ew32(CRC_OFFSET
, 0x65656565);
3606 ew32(IMC
, 0xffffffff);
3609 reg
= er32(KABGTXD
);
3610 reg
|= E1000_KABGTXD_BGSQLBIAS
;
3617 * e1000_init_hw_ich8lan - Initialize the hardware
3618 * @hw: pointer to the HW structure
3620 * Prepares the hardware for transmit and receive by doing the following:
3621 * - initialize hardware bits
3622 * - initialize LED identification
3623 * - setup receive address registers
3624 * - setup flow control
3625 * - setup transmit descriptors
3626 * - clear statistics
3628 static s32
e1000_init_hw_ich8lan(struct e1000_hw
*hw
)
3630 struct e1000_mac_info
*mac
= &hw
->mac
;
3631 u32 ctrl_ext
, txdctl
, snoop
;
3635 e1000_initialize_hw_bits_ich8lan(hw
);
3637 /* Initialize identification LED */
3638 ret_val
= mac
->ops
.id_led_init(hw
);
3639 /* An error is not fatal and we should not stop init due to this */
3641 e_dbg("Error initializing identification LED\n");
3643 /* Setup the receive address. */
3644 e1000e_init_rx_addrs(hw
, mac
->rar_entry_count
);
3646 /* Zero out the Multicast HASH table */
3647 e_dbg("Zeroing the MTA\n");
3648 for (i
= 0; i
< mac
->mta_reg_count
; i
++)
3649 E1000_WRITE_REG_ARRAY(hw
, E1000_MTA
, i
, 0);
3651 /* The 82578 Rx buffer will stall if wakeup is enabled in host and
3652 * the ME. Disable wakeup by clearing the host wakeup bit.
3653 * Reset the phy after disabling host wakeup to reset the Rx buffer.
3655 if (hw
->phy
.type
== e1000_phy_82578
) {
3656 e1e_rphy(hw
, BM_PORT_GEN_CFG
, &i
);
3657 i
&= ~BM_WUC_HOST_WU_BIT
;
3658 e1e_wphy(hw
, BM_PORT_GEN_CFG
, i
);
3659 ret_val
= e1000_phy_hw_reset_ich8lan(hw
);
3664 /* Setup link and flow control */
3665 ret_val
= mac
->ops
.setup_link(hw
);
3667 /* Set the transmit descriptor write-back policy for both queues */
3668 txdctl
= er32(TXDCTL(0));
3669 txdctl
= ((txdctl
& ~E1000_TXDCTL_WTHRESH
) |
3670 E1000_TXDCTL_FULL_TX_DESC_WB
);
3671 txdctl
= ((txdctl
& ~E1000_TXDCTL_PTHRESH
) |
3672 E1000_TXDCTL_MAX_TX_DESC_PREFETCH
);
3673 ew32(TXDCTL(0), txdctl
);
3674 txdctl
= er32(TXDCTL(1));
3675 txdctl
= ((txdctl
& ~E1000_TXDCTL_WTHRESH
) |
3676 E1000_TXDCTL_FULL_TX_DESC_WB
);
3677 txdctl
= ((txdctl
& ~E1000_TXDCTL_PTHRESH
) |
3678 E1000_TXDCTL_MAX_TX_DESC_PREFETCH
);
3679 ew32(TXDCTL(1), txdctl
);
3681 /* ICH8 has opposite polarity of no_snoop bits.
3682 * By default, we should use snoop behavior.
3684 if (mac
->type
== e1000_ich8lan
)
3685 snoop
= PCIE_ICH8_SNOOP_ALL
;
3687 snoop
= (u32
)~(PCIE_NO_SNOOP_ALL
);
3688 e1000e_set_pcie_no_snoop(hw
, snoop
);
3690 ctrl_ext
= er32(CTRL_EXT
);
3691 ctrl_ext
|= E1000_CTRL_EXT_RO_DIS
;
3692 ew32(CTRL_EXT
, ctrl_ext
);
3694 /* Clear all of the statistics registers (clear on read). It is
3695 * important that we do this after we have tried to establish link
3696 * because the symbol error count will increment wildly if there
3699 e1000_clear_hw_cntrs_ich8lan(hw
);
3705 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3706 * @hw: pointer to the HW structure
3708 * Sets/Clears required hardware bits necessary for correctly setting up the
3709 * hardware for transmit and receive.
3711 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw
*hw
)
3715 /* Extended Device Control */
3716 reg
= er32(CTRL_EXT
);
3718 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3719 if (hw
->mac
.type
>= e1000_pchlan
)
3720 reg
|= E1000_CTRL_EXT_PHYPDEN
;
3721 ew32(CTRL_EXT
, reg
);
3723 /* Transmit Descriptor Control 0 */
3724 reg
= er32(TXDCTL(0));
3726 ew32(TXDCTL(0), reg
);
3728 /* Transmit Descriptor Control 1 */
3729 reg
= er32(TXDCTL(1));
3731 ew32(TXDCTL(1), reg
);
3733 /* Transmit Arbitration Control 0 */
3734 reg
= er32(TARC(0));
3735 if (hw
->mac
.type
== e1000_ich8lan
)
3736 reg
|= (1 << 28) | (1 << 29);
3737 reg
|= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
3740 /* Transmit Arbitration Control 1 */
3741 reg
= er32(TARC(1));
3742 if (er32(TCTL
) & E1000_TCTL_MULR
)
3746 reg
|= (1 << 24) | (1 << 26) | (1 << 30);
3750 if (hw
->mac
.type
== e1000_ich8lan
) {
3756 /* work-around descriptor data corruption issue during nfs v2 udp
3757 * traffic, just disable the nfs filtering capability
3760 reg
|= (E1000_RFCTL_NFSW_DIS
| E1000_RFCTL_NFSR_DIS
);
3762 /* Disable IPv6 extension header parsing because some malformed
3763 * IPv6 headers can hang the Rx.
3765 if (hw
->mac
.type
== e1000_ich8lan
)
3766 reg
|= (E1000_RFCTL_IPV6_EX_DIS
| E1000_RFCTL_NEW_IPV6_EXT_DIS
);
3769 /* Enable ECC on Lynxpoint */
3770 if (hw
->mac
.type
== e1000_pch_lpt
) {
3771 reg
= er32(PBECCSTS
);
3772 reg
|= E1000_PBECCSTS_ECC_ENABLE
;
3773 ew32(PBECCSTS
, reg
);
3776 reg
|= E1000_CTRL_MEHE
;
3782 * e1000_setup_link_ich8lan - Setup flow control and link settings
3783 * @hw: pointer to the HW structure
3785 * Determines which flow control settings to use, then configures flow
3786 * control. Calls the appropriate media-specific link configuration
3787 * function. Assuming the adapter has a valid link partner, a valid link
3788 * should be established. Assumes the hardware has previously been reset
3789 * and the transmitter and receiver are not enabled.
3791 static s32
e1000_setup_link_ich8lan(struct e1000_hw
*hw
)
3795 if (hw
->phy
.ops
.check_reset_block(hw
))
3798 /* ICH parts do not have a word in the NVM to determine
3799 * the default flow control setting, so we explicitly
3802 if (hw
->fc
.requested_mode
== e1000_fc_default
) {
3803 /* Workaround h/w hang when Tx flow control enabled */
3804 if (hw
->mac
.type
== e1000_pchlan
)
3805 hw
->fc
.requested_mode
= e1000_fc_rx_pause
;
3807 hw
->fc
.requested_mode
= e1000_fc_full
;
3810 /* Save off the requested flow control mode for use later. Depending
3811 * on the link partner's capabilities, we may or may not use this mode.
3813 hw
->fc
.current_mode
= hw
->fc
.requested_mode
;
3815 e_dbg("After fix-ups FlowControl is now = %x\n", hw
->fc
.current_mode
);
3817 /* Continue to configure the copper link. */
3818 ret_val
= hw
->mac
.ops
.setup_physical_interface(hw
);
3822 ew32(FCTTV
, hw
->fc
.pause_time
);
3823 if ((hw
->phy
.type
== e1000_phy_82578
) ||
3824 (hw
->phy
.type
== e1000_phy_82579
) ||
3825 (hw
->phy
.type
== e1000_phy_i217
) ||
3826 (hw
->phy
.type
== e1000_phy_82577
)) {
3827 ew32(FCRTV_PCH
, hw
->fc
.refresh_time
);
3829 ret_val
= e1e_wphy(hw
, PHY_REG(BM_PORT_CTRL_PAGE
, 27),
3835 return e1000e_set_fc_watermarks(hw
);
3839 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3840 * @hw: pointer to the HW structure
3842 * Configures the kumeran interface to the PHY to wait the appropriate time
3843 * when polling the PHY, then call the generic setup_copper_link to finish
3844 * configuring the copper link.
3846 static s32
e1000_setup_copper_link_ich8lan(struct e1000_hw
*hw
)
3853 ctrl
|= E1000_CTRL_SLU
;
3854 ctrl
&= ~(E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
3857 /* Set the mac to wait the maximum time between each iteration
3858 * and increase the max iterations when polling the phy;
3859 * this fixes erroneous timeouts at 10Mbps.
3861 ret_val
= e1000e_write_kmrn_reg(hw
, E1000_KMRNCTRLSTA_TIMEOUTS
, 0xFFFF);
3864 ret_val
= e1000e_read_kmrn_reg(hw
, E1000_KMRNCTRLSTA_INBAND_PARAM
,
3869 ret_val
= e1000e_write_kmrn_reg(hw
, E1000_KMRNCTRLSTA_INBAND_PARAM
,
3874 switch (hw
->phy
.type
) {
3875 case e1000_phy_igp_3
:
3876 ret_val
= e1000e_copper_link_setup_igp(hw
);
3881 case e1000_phy_82578
:
3882 ret_val
= e1000e_copper_link_setup_m88(hw
);
3886 case e1000_phy_82577
:
3887 case e1000_phy_82579
:
3888 ret_val
= e1000_copper_link_setup_82577(hw
);
3893 ret_val
= e1e_rphy(hw
, IFE_PHY_MDIX_CONTROL
, ®_data
);
3897 reg_data
&= ~IFE_PMC_AUTO_MDIX
;
3899 switch (hw
->phy
.mdix
) {
3901 reg_data
&= ~IFE_PMC_FORCE_MDIX
;
3904 reg_data
|= IFE_PMC_FORCE_MDIX
;
3908 reg_data
|= IFE_PMC_AUTO_MDIX
;
3911 ret_val
= e1e_wphy(hw
, IFE_PHY_MDIX_CONTROL
, reg_data
);
3919 return e1000e_setup_copper_link(hw
);
3923 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
3924 * @hw: pointer to the HW structure
3926 * Calls the PHY specific link setup function and then calls the
3927 * generic setup_copper_link to finish configuring the link for
3928 * Lynxpoint PCH devices
3930 static s32
e1000_setup_copper_link_pch_lpt(struct e1000_hw
*hw
)
3936 ctrl
|= E1000_CTRL_SLU
;
3937 ctrl
&= ~(E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
3940 ret_val
= e1000_copper_link_setup_82577(hw
);
3944 return e1000e_setup_copper_link(hw
);
3948 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
3949 * @hw: pointer to the HW structure
3950 * @speed: pointer to store current link speed
3951 * @duplex: pointer to store the current link duplex
3953 * Calls the generic get_speed_and_duplex to retrieve the current link
3954 * information and then calls the Kumeran lock loss workaround for links at
3957 static s32
e1000_get_link_up_info_ich8lan(struct e1000_hw
*hw
, u16
*speed
,
3962 ret_val
= e1000e_get_speed_and_duplex_copper(hw
, speed
, duplex
);
3966 if ((hw
->mac
.type
== e1000_ich8lan
) &&
3967 (hw
->phy
.type
== e1000_phy_igp_3
) && (*speed
== SPEED_1000
)) {
3968 ret_val
= e1000_kmrn_lock_loss_workaround_ich8lan(hw
);
3975 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3976 * @hw: pointer to the HW structure
3978 * Work-around for 82566 Kumeran PCS lock loss:
3979 * On link status change (i.e. PCI reset, speed change) and link is up and
3981 * 0) if workaround is optionally disabled do nothing
3982 * 1) wait 1ms for Kumeran link to come up
3983 * 2) check Kumeran Diagnostic register PCS lock loss bit
3984 * 3) if not set the link is locked (all is good), otherwise...
3986 * 5) repeat up to 10 times
3987 * Note: this is only called for IGP3 copper when speed is 1gb.
3989 static s32
e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw
*hw
)
3991 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
3997 if (!dev_spec
->kmrn_lock_loss_workaround_enabled
)
4000 /* Make sure link is up before proceeding. If not just return.
4001 * Attempting this while link is negotiating fouled up link
4004 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
4008 for (i
= 0; i
< 10; i
++) {
4009 /* read once to clear */
4010 ret_val
= e1e_rphy(hw
, IGP3_KMRN_DIAG
, &data
);
4013 /* and again to get new status */
4014 ret_val
= e1e_rphy(hw
, IGP3_KMRN_DIAG
, &data
);
4018 /* check for PCS lock */
4019 if (!(data
& IGP3_KMRN_DIAG_PCS_LOCK_LOSS
))
4022 /* Issue PHY reset */
4023 e1000_phy_hw_reset(hw
);
4026 /* Disable GigE link negotiation */
4027 phy_ctrl
= er32(PHY_CTRL
);
4028 phy_ctrl
|= (E1000_PHY_CTRL_GBE_DISABLE
|
4029 E1000_PHY_CTRL_NOND0A_GBE_DISABLE
);
4030 ew32(PHY_CTRL
, phy_ctrl
);
4032 /* Call gig speed drop workaround on Gig disable before accessing
4035 e1000e_gig_downshift_workaround_ich8lan(hw
);
4037 /* unable to acquire PCS lock */
4038 return -E1000_ERR_PHY
;
4042 * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
4043 * @hw: pointer to the HW structure
4044 * @state: boolean value used to set the current Kumeran workaround state
4046 * If ICH8, set the current Kumeran workaround state (enabled - true
4047 * /disabled - false).
4049 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw
*hw
,
4052 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
4054 if (hw
->mac
.type
!= e1000_ich8lan
) {
4055 e_dbg("Workaround applies to ICH8 only.\n");
4059 dev_spec
->kmrn_lock_loss_workaround_enabled
= state
;
4063 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
4064 * @hw: pointer to the HW structure
4066 * Workaround for 82566 power-down on D3 entry:
4067 * 1) disable gigabit link
4068 * 2) write VR power-down enable
4070 * Continue if successful, else issue LCD reset and repeat
4072 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw
*hw
)
4078 if (hw
->phy
.type
!= e1000_phy_igp_3
)
4081 /* Try the workaround twice (if needed) */
4084 reg
= er32(PHY_CTRL
);
4085 reg
|= (E1000_PHY_CTRL_GBE_DISABLE
|
4086 E1000_PHY_CTRL_NOND0A_GBE_DISABLE
);
4087 ew32(PHY_CTRL
, reg
);
4089 /* Call gig speed drop workaround on Gig disable before
4090 * accessing any PHY registers
4092 if (hw
->mac
.type
== e1000_ich8lan
)
4093 e1000e_gig_downshift_workaround_ich8lan(hw
);
4095 /* Write VR power-down enable */
4096 e1e_rphy(hw
, IGP3_VR_CTRL
, &data
);
4097 data
&= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK
;
4098 e1e_wphy(hw
, IGP3_VR_CTRL
, data
| IGP3_VR_CTRL_MODE_SHUTDOWN
);
4100 /* Read it back and test */
4101 e1e_rphy(hw
, IGP3_VR_CTRL
, &data
);
4102 data
&= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK
;
4103 if ((data
== IGP3_VR_CTRL_MODE_SHUTDOWN
) || retry
)
4106 /* Issue PHY reset and repeat at most one more time */
4108 ew32(CTRL
, reg
| E1000_CTRL_PHY_RST
);
4114 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
4115 * @hw: pointer to the HW structure
4117 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
4118 * LPLU, Gig disable, MDIC PHY reset):
4119 * 1) Set Kumeran Near-end loopback
4120 * 2) Clear Kumeran Near-end loopback
4121 * Should only be called for ICH8[m] devices with any 1G Phy.
4123 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw
*hw
)
4128 if ((hw
->mac
.type
!= e1000_ich8lan
) || (hw
->phy
.type
== e1000_phy_ife
))
4131 ret_val
= e1000e_read_kmrn_reg(hw
, E1000_KMRNCTRLSTA_DIAG_OFFSET
,
4135 reg_data
|= E1000_KMRNCTRLSTA_DIAG_NELPBK
;
4136 ret_val
= e1000e_write_kmrn_reg(hw
, E1000_KMRNCTRLSTA_DIAG_OFFSET
,
4140 reg_data
&= ~E1000_KMRNCTRLSTA_DIAG_NELPBK
;
4141 e1000e_write_kmrn_reg(hw
, E1000_KMRNCTRLSTA_DIAG_OFFSET
, reg_data
);
4145 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
4146 * @hw: pointer to the HW structure
4148 * During S0 to Sx transition, it is possible the link remains at gig
4149 * instead of negotiating to a lower speed. Before going to Sx, set
4150 * 'Gig Disable' to force link speed negotiation to a lower speed based on
4151 * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
4152 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
4153 * needs to be written.
4154 * Parts that support (and are linked to a partner which support) EEE in
4155 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
4156 * than 10Mbps w/o EEE.
4158 void e1000_suspend_workarounds_ich8lan(struct e1000_hw
*hw
)
4160 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
4164 phy_ctrl
= er32(PHY_CTRL
);
4165 phy_ctrl
|= E1000_PHY_CTRL_GBE_DISABLE
;
4167 if (hw
->phy
.type
== e1000_phy_i217
) {
4168 u16 phy_reg
, device_id
= hw
->adapter
->pdev
->device
;
4170 if ((device_id
== E1000_DEV_ID_PCH_LPTLP_I218_LM
) ||
4171 (device_id
== E1000_DEV_ID_PCH_LPTLP_I218_V
)) {
4172 u32 fextnvm6
= er32(FEXTNVM6
);
4174 ew32(FEXTNVM6
, fextnvm6
& ~E1000_FEXTNVM6_REQ_PLL_CLK
);
4177 ret_val
= hw
->phy
.ops
.acquire(hw
);
4181 if (!dev_spec
->eee_disable
) {
4185 e1000_read_emi_reg_locked(hw
,
4186 I217_EEE_ADVERTISEMENT
,
4191 /* Disable LPLU if both link partners support 100BaseT
4192 * EEE and 100Full is advertised on both ends of the
4195 if ((eee_advert
& I82579_EEE_100_SUPPORTED
) &&
4196 (dev_spec
->eee_lp_ability
&
4197 I82579_EEE_100_SUPPORTED
) &&
4198 (hw
->phy
.autoneg_advertised
& ADVERTISE_100_FULL
))
4199 phy_ctrl
&= ~(E1000_PHY_CTRL_D0A_LPLU
|
4200 E1000_PHY_CTRL_NOND0A_LPLU
);
4203 /* For i217 Intel Rapid Start Technology support,
4204 * when the system is going into Sx and no manageability engine
4205 * is present, the driver must configure proxy to reset only on
4206 * power good. LPI (Low Power Idle) state must also reset only
4207 * on power good, as well as the MTA (Multicast table array).
4208 * The SMBus release must also be disabled on LCD reset.
4210 if (!(er32(FWSM
) & E1000_ICH_FWSM_FW_VALID
)) {
4211 /* Enable proxy to reset only on power good. */
4212 e1e_rphy_locked(hw
, I217_PROXY_CTRL
, &phy_reg
);
4213 phy_reg
|= I217_PROXY_CTRL_AUTO_DISABLE
;
4214 e1e_wphy_locked(hw
, I217_PROXY_CTRL
, phy_reg
);
4216 /* Set bit enable LPI (EEE) to reset only on
4219 e1e_rphy_locked(hw
, I217_SxCTRL
, &phy_reg
);
4220 phy_reg
|= I217_SxCTRL_ENABLE_LPI_RESET
;
4221 e1e_wphy_locked(hw
, I217_SxCTRL
, phy_reg
);
4223 /* Disable the SMB release on LCD reset. */
4224 e1e_rphy_locked(hw
, I217_MEMPWR
, &phy_reg
);
4225 phy_reg
&= ~I217_MEMPWR_DISABLE_SMB_RELEASE
;
4226 e1e_wphy_locked(hw
, I217_MEMPWR
, phy_reg
);
4229 /* Enable MTA to reset for Intel Rapid Start Technology
4232 e1e_rphy_locked(hw
, I217_CGFREG
, &phy_reg
);
4233 phy_reg
|= I217_CGFREG_ENABLE_MTA_RESET
;
4234 e1e_wphy_locked(hw
, I217_CGFREG
, phy_reg
);
4237 hw
->phy
.ops
.release(hw
);
4240 ew32(PHY_CTRL
, phy_ctrl
);
4242 if (hw
->mac
.type
== e1000_ich8lan
)
4243 e1000e_gig_downshift_workaround_ich8lan(hw
);
4245 if (hw
->mac
.type
>= e1000_pchlan
) {
4246 e1000_oem_bits_config_ich8lan(hw
, false);
4248 /* Reset PHY to activate OEM bits on 82577/8 */
4249 if (hw
->mac
.type
== e1000_pchlan
)
4250 e1000e_phy_hw_reset_generic(hw
);
4252 ret_val
= hw
->phy
.ops
.acquire(hw
);
4255 e1000_write_smbus_addr(hw
);
4256 hw
->phy
.ops
.release(hw
);
4261 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
4262 * @hw: pointer to the HW structure
4264 * During Sx to S0 transitions on non-managed devices or managed devices
4265 * on which PHY resets are not blocked, if the PHY registers cannot be
4266 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
4268 * On i217, setup Intel Rapid Start Technology.
4270 void e1000_resume_workarounds_pchlan(struct e1000_hw
*hw
)
4274 if (hw
->mac
.type
< e1000_pch2lan
)
4277 ret_val
= e1000_init_phy_workarounds_pchlan(hw
);
4279 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val
);
4283 /* For i217 Intel Rapid Start Technology support when the system
4284 * is transitioning from Sx and no manageability engine is present
4285 * configure SMBus to restore on reset, disable proxy, and enable
4286 * the reset on MTA (Multicast table array).
4288 if (hw
->phy
.type
== e1000_phy_i217
) {
4291 ret_val
= hw
->phy
.ops
.acquire(hw
);
4293 e_dbg("Failed to setup iRST\n");
4297 if (!(er32(FWSM
) & E1000_ICH_FWSM_FW_VALID
)) {
4298 /* Restore clear on SMB if no manageability engine
4301 ret_val
= e1e_rphy_locked(hw
, I217_MEMPWR
, &phy_reg
);
4304 phy_reg
|= I217_MEMPWR_DISABLE_SMB_RELEASE
;
4305 e1e_wphy_locked(hw
, I217_MEMPWR
, phy_reg
);
4308 e1e_wphy_locked(hw
, I217_PROXY_CTRL
, 0);
4310 /* Enable reset on MTA */
4311 ret_val
= e1e_rphy_locked(hw
, I217_CGFREG
, &phy_reg
);
4314 phy_reg
&= ~I217_CGFREG_ENABLE_MTA_RESET
;
4315 e1e_wphy_locked(hw
, I217_CGFREG
, phy_reg
);
4318 e_dbg("Error %d in resume workarounds\n", ret_val
);
4319 hw
->phy
.ops
.release(hw
);
4324 * e1000_cleanup_led_ich8lan - Restore the default LED operation
4325 * @hw: pointer to the HW structure
4327 * Return the LED back to the default configuration.
4329 static s32
e1000_cleanup_led_ich8lan(struct e1000_hw
*hw
)
4331 if (hw
->phy
.type
== e1000_phy_ife
)
4332 return e1e_wphy(hw
, IFE_PHY_SPECIAL_CONTROL_LED
, 0);
4334 ew32(LEDCTL
, hw
->mac
.ledctl_default
);
4339 * e1000_led_on_ich8lan - Turn LEDs on
4340 * @hw: pointer to the HW structure
4344 static s32
e1000_led_on_ich8lan(struct e1000_hw
*hw
)
4346 if (hw
->phy
.type
== e1000_phy_ife
)
4347 return e1e_wphy(hw
, IFE_PHY_SPECIAL_CONTROL_LED
,
4348 (IFE_PSCL_PROBE_MODE
| IFE_PSCL_PROBE_LEDS_ON
));
4350 ew32(LEDCTL
, hw
->mac
.ledctl_mode2
);
4355 * e1000_led_off_ich8lan - Turn LEDs off
4356 * @hw: pointer to the HW structure
4358 * Turn off the LEDs.
4360 static s32
e1000_led_off_ich8lan(struct e1000_hw
*hw
)
4362 if (hw
->phy
.type
== e1000_phy_ife
)
4363 return e1e_wphy(hw
, IFE_PHY_SPECIAL_CONTROL_LED
,
4364 (IFE_PSCL_PROBE_MODE
|
4365 IFE_PSCL_PROBE_LEDS_OFF
));
4367 ew32(LEDCTL
, hw
->mac
.ledctl_mode1
);
4372 * e1000_setup_led_pchlan - Configures SW controllable LED
4373 * @hw: pointer to the HW structure
4375 * This prepares the SW controllable LED for use.
4377 static s32
e1000_setup_led_pchlan(struct e1000_hw
*hw
)
4379 return e1e_wphy(hw
, HV_LED_CONFIG
, (u16
)hw
->mac
.ledctl_mode1
);
4383 * e1000_cleanup_led_pchlan - Restore the default LED operation
4384 * @hw: pointer to the HW structure
4386 * Return the LED back to the default configuration.
4388 static s32
e1000_cleanup_led_pchlan(struct e1000_hw
*hw
)
4390 return e1e_wphy(hw
, HV_LED_CONFIG
, (u16
)hw
->mac
.ledctl_default
);
4394 * e1000_led_on_pchlan - Turn LEDs on
4395 * @hw: pointer to the HW structure
4399 static s32
e1000_led_on_pchlan(struct e1000_hw
*hw
)
4401 u16 data
= (u16
)hw
->mac
.ledctl_mode2
;
4404 /* If no link, then turn LED on by setting the invert bit
4405 * for each LED that's mode is "link_up" in ledctl_mode2.
4407 if (!(er32(STATUS
) & E1000_STATUS_LU
)) {
4408 for (i
= 0; i
< 3; i
++) {
4409 led
= (data
>> (i
* 5)) & E1000_PHY_LED0_MASK
;
4410 if ((led
& E1000_PHY_LED0_MODE_MASK
) !=
4411 E1000_LEDCTL_MODE_LINK_UP
)
4413 if (led
& E1000_PHY_LED0_IVRT
)
4414 data
&= ~(E1000_PHY_LED0_IVRT
<< (i
* 5));
4416 data
|= (E1000_PHY_LED0_IVRT
<< (i
* 5));
4420 return e1e_wphy(hw
, HV_LED_CONFIG
, data
);
4424 * e1000_led_off_pchlan - Turn LEDs off
4425 * @hw: pointer to the HW structure
4427 * Turn off the LEDs.
4429 static s32
e1000_led_off_pchlan(struct e1000_hw
*hw
)
4431 u16 data
= (u16
)hw
->mac
.ledctl_mode1
;
4434 /* If no link, then turn LED off by clearing the invert bit
4435 * for each LED that's mode is "link_up" in ledctl_mode1.
4437 if (!(er32(STATUS
) & E1000_STATUS_LU
)) {
4438 for (i
= 0; i
< 3; i
++) {
4439 led
= (data
>> (i
* 5)) & E1000_PHY_LED0_MASK
;
4440 if ((led
& E1000_PHY_LED0_MODE_MASK
) !=
4441 E1000_LEDCTL_MODE_LINK_UP
)
4443 if (led
& E1000_PHY_LED0_IVRT
)
4444 data
&= ~(E1000_PHY_LED0_IVRT
<< (i
* 5));
4446 data
|= (E1000_PHY_LED0_IVRT
<< (i
* 5));
4450 return e1e_wphy(hw
, HV_LED_CONFIG
, data
);
4454 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
4455 * @hw: pointer to the HW structure
4457 * Read appropriate register for the config done bit for completion status
4458 * and configure the PHY through s/w for EEPROM-less parts.
4460 * NOTE: some silicon which is EEPROM-less will fail trying to read the
4461 * config done bit, so only an error is logged and continues. If we were
4462 * to return with error, EEPROM-less silicon would not be able to be reset
4465 static s32
e1000_get_cfg_done_ich8lan(struct e1000_hw
*hw
)
4471 e1000e_get_cfg_done_generic(hw
);
4473 /* Wait for indication from h/w that it has completed basic config */
4474 if (hw
->mac
.type
>= e1000_ich10lan
) {
4475 e1000_lan_init_done_ich8lan(hw
);
4477 ret_val
= e1000e_get_auto_rd_done(hw
);
4479 /* When auto config read does not complete, do not
4480 * return with an error. This can happen in situations
4481 * where there is no eeprom and prevents getting link.
4483 e_dbg("Auto Read Done did not complete\n");
4488 /* Clear PHY Reset Asserted bit */
4489 status
= er32(STATUS
);
4490 if (status
& E1000_STATUS_PHYRA
)
4491 ew32(STATUS
, status
& ~E1000_STATUS_PHYRA
);
4493 e_dbg("PHY Reset Asserted not set - needs delay\n");
4495 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
4496 if (hw
->mac
.type
<= e1000_ich9lan
) {
4497 if (!(er32(EECD
) & E1000_EECD_PRES
) &&
4498 (hw
->phy
.type
== e1000_phy_igp_3
)) {
4499 e1000e_phy_init_script_igp3(hw
);
4502 if (e1000_valid_nvm_bank_detect_ich8lan(hw
, &bank
)) {
4503 /* Maybe we should do a basic PHY config */
4504 e_dbg("EEPROM not present\n");
4505 ret_val
= -E1000_ERR_CONFIG
;
4513 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
4514 * @hw: pointer to the HW structure
4516 * In the case of a PHY power down to save power, or to turn off link during a
4517 * driver unload, or wake on lan is not enabled, remove the link.
4519 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw
*hw
)
4521 /* If the management interface is not enabled, then power down */
4522 if (!(hw
->mac
.ops
.check_mng_mode(hw
) ||
4523 hw
->phy
.ops
.check_reset_block(hw
)))
4524 e1000_power_down_phy_copper(hw
);
4528 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
4529 * @hw: pointer to the HW structure
4531 * Clears hardware counters specific to the silicon family and calls
4532 * clear_hw_cntrs_generic to clear all general purpose counters.
4534 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw
*hw
)
4539 e1000e_clear_hw_cntrs_base(hw
);
4555 /* Clear PHY statistics registers */
4556 if ((hw
->phy
.type
== e1000_phy_82578
) ||
4557 (hw
->phy
.type
== e1000_phy_82579
) ||
4558 (hw
->phy
.type
== e1000_phy_i217
) ||
4559 (hw
->phy
.type
== e1000_phy_82577
)) {
4560 ret_val
= hw
->phy
.ops
.acquire(hw
);
4563 ret_val
= hw
->phy
.ops
.set_page(hw
,
4564 HV_STATS_PAGE
<< IGP_PAGE_SHIFT
);
4567 hw
->phy
.ops
.read_reg_page(hw
, HV_SCC_UPPER
, &phy_data
);
4568 hw
->phy
.ops
.read_reg_page(hw
, HV_SCC_LOWER
, &phy_data
);
4569 hw
->phy
.ops
.read_reg_page(hw
, HV_ECOL_UPPER
, &phy_data
);
4570 hw
->phy
.ops
.read_reg_page(hw
, HV_ECOL_LOWER
, &phy_data
);
4571 hw
->phy
.ops
.read_reg_page(hw
, HV_MCC_UPPER
, &phy_data
);
4572 hw
->phy
.ops
.read_reg_page(hw
, HV_MCC_LOWER
, &phy_data
);
4573 hw
->phy
.ops
.read_reg_page(hw
, HV_LATECOL_UPPER
, &phy_data
);
4574 hw
->phy
.ops
.read_reg_page(hw
, HV_LATECOL_LOWER
, &phy_data
);
4575 hw
->phy
.ops
.read_reg_page(hw
, HV_COLC_UPPER
, &phy_data
);
4576 hw
->phy
.ops
.read_reg_page(hw
, HV_COLC_LOWER
, &phy_data
);
4577 hw
->phy
.ops
.read_reg_page(hw
, HV_DC_UPPER
, &phy_data
);
4578 hw
->phy
.ops
.read_reg_page(hw
, HV_DC_LOWER
, &phy_data
);
4579 hw
->phy
.ops
.read_reg_page(hw
, HV_TNCRS_UPPER
, &phy_data
);
4580 hw
->phy
.ops
.read_reg_page(hw
, HV_TNCRS_LOWER
, &phy_data
);
4582 hw
->phy
.ops
.release(hw
);
4586 static const struct e1000_mac_operations ich8_mac_ops
= {
4587 /* check_mng_mode dependent on mac type */
4588 .check_for_link
= e1000_check_for_copper_link_ich8lan
,
4589 /* cleanup_led dependent on mac type */
4590 .clear_hw_cntrs
= e1000_clear_hw_cntrs_ich8lan
,
4591 .get_bus_info
= e1000_get_bus_info_ich8lan
,
4592 .set_lan_id
= e1000_set_lan_id_single_port
,
4593 .get_link_up_info
= e1000_get_link_up_info_ich8lan
,
4594 /* led_on dependent on mac type */
4595 /* led_off dependent on mac type */
4596 .update_mc_addr_list
= e1000e_update_mc_addr_list_generic
,
4597 .reset_hw
= e1000_reset_hw_ich8lan
,
4598 .init_hw
= e1000_init_hw_ich8lan
,
4599 .setup_link
= e1000_setup_link_ich8lan
,
4600 .setup_physical_interface
= e1000_setup_copper_link_ich8lan
,
4601 /* id_led_init dependent on mac type */
4602 .config_collision_dist
= e1000e_config_collision_dist_generic
,
4603 .rar_set
= e1000e_rar_set_generic
,
4606 static const struct e1000_phy_operations ich8_phy_ops
= {
4607 .acquire
= e1000_acquire_swflag_ich8lan
,
4608 .check_reset_block
= e1000_check_reset_block_ich8lan
,
4610 .get_cfg_done
= e1000_get_cfg_done_ich8lan
,
4611 .get_cable_length
= e1000e_get_cable_length_igp_2
,
4612 .read_reg
= e1000e_read_phy_reg_igp
,
4613 .release
= e1000_release_swflag_ich8lan
,
4614 .reset
= e1000_phy_hw_reset_ich8lan
,
4615 .set_d0_lplu_state
= e1000_set_d0_lplu_state_ich8lan
,
4616 .set_d3_lplu_state
= e1000_set_d3_lplu_state_ich8lan
,
4617 .write_reg
= e1000e_write_phy_reg_igp
,
4620 static const struct e1000_nvm_operations ich8_nvm_ops
= {
4621 .acquire
= e1000_acquire_nvm_ich8lan
,
4622 .read
= e1000_read_nvm_ich8lan
,
4623 .release
= e1000_release_nvm_ich8lan
,
4624 .reload
= e1000e_reload_nvm_generic
,
4625 .update
= e1000_update_nvm_checksum_ich8lan
,
4626 .valid_led_default
= e1000_valid_led_default_ich8lan
,
4627 .validate
= e1000_validate_nvm_checksum_ich8lan
,
4628 .write
= e1000_write_nvm_ich8lan
,
4631 const struct e1000_info e1000_ich8_info
= {
4632 .mac
= e1000_ich8lan
,
4633 .flags
= FLAG_HAS_WOL
4635 | FLAG_HAS_CTRLEXT_ON_LOAD
4640 .max_hw_frame_size
= ETH_FRAME_LEN
+ ETH_FCS_LEN
,
4641 .get_variants
= e1000_get_variants_ich8lan
,
4642 .mac_ops
= &ich8_mac_ops
,
4643 .phy_ops
= &ich8_phy_ops
,
4644 .nvm_ops
= &ich8_nvm_ops
,
4647 const struct e1000_info e1000_ich9_info
= {
4648 .mac
= e1000_ich9lan
,
4649 .flags
= FLAG_HAS_JUMBO_FRAMES
4652 | FLAG_HAS_CTRLEXT_ON_LOAD
4657 .max_hw_frame_size
= DEFAULT_JUMBO
,
4658 .get_variants
= e1000_get_variants_ich8lan
,
4659 .mac_ops
= &ich8_mac_ops
,
4660 .phy_ops
= &ich8_phy_ops
,
4661 .nvm_ops
= &ich8_nvm_ops
,
4664 const struct e1000_info e1000_ich10_info
= {
4665 .mac
= e1000_ich10lan
,
4666 .flags
= FLAG_HAS_JUMBO_FRAMES
4669 | FLAG_HAS_CTRLEXT_ON_LOAD
4674 .max_hw_frame_size
= DEFAULT_JUMBO
,
4675 .get_variants
= e1000_get_variants_ich8lan
,
4676 .mac_ops
= &ich8_mac_ops
,
4677 .phy_ops
= &ich8_phy_ops
,
4678 .nvm_ops
= &ich8_nvm_ops
,
4681 const struct e1000_info e1000_pch_info
= {
4682 .mac
= e1000_pchlan
,
4683 .flags
= FLAG_IS_ICH
4685 | FLAG_HAS_CTRLEXT_ON_LOAD
4688 | FLAG_HAS_JUMBO_FRAMES
4689 | FLAG_DISABLE_FC_PAUSE_TIME
/* errata */
4691 .flags2
= FLAG2_HAS_PHY_STATS
,
4693 .max_hw_frame_size
= 4096,
4694 .get_variants
= e1000_get_variants_ich8lan
,
4695 .mac_ops
= &ich8_mac_ops
,
4696 .phy_ops
= &ich8_phy_ops
,
4697 .nvm_ops
= &ich8_nvm_ops
,
4700 const struct e1000_info e1000_pch2_info
= {
4701 .mac
= e1000_pch2lan
,
4702 .flags
= FLAG_IS_ICH
4704 | FLAG_HAS_HW_TIMESTAMP
4705 | FLAG_HAS_CTRLEXT_ON_LOAD
4708 | FLAG_HAS_JUMBO_FRAMES
4710 .flags2
= FLAG2_HAS_PHY_STATS
4713 .max_hw_frame_size
= 9018,
4714 .get_variants
= e1000_get_variants_ich8lan
,
4715 .mac_ops
= &ich8_mac_ops
,
4716 .phy_ops
= &ich8_phy_ops
,
4717 .nvm_ops
= &ich8_nvm_ops
,
4720 const struct e1000_info e1000_pch_lpt_info
= {
4721 .mac
= e1000_pch_lpt
,
4722 .flags
= FLAG_IS_ICH
4724 | FLAG_HAS_HW_TIMESTAMP
4725 | FLAG_HAS_CTRLEXT_ON_LOAD
4728 | FLAG_HAS_JUMBO_FRAMES
4730 .flags2
= FLAG2_HAS_PHY_STATS
4733 .max_hw_frame_size
= 9018,
4734 .get_variants
= e1000_get_variants_ich8lan
,
4735 .mac_ops
= &ich8_mac_ops
,
4736 .phy_ops
= &ich8_phy_ops
,
4737 .nvm_ops
= &ich8_nvm_ops
,