1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
32 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
34 #include <linux/types.h>
35 #include <linux/if_ether.h>
36 #include <linux/i2c.h>
38 #include "e1000_mac.h"
39 #include "e1000_82575.h"
40 #include "e1000_i210.h"
42 static s32
igb_get_invariants_82575(struct e1000_hw
*);
43 static s32
igb_acquire_phy_82575(struct e1000_hw
*);
44 static void igb_release_phy_82575(struct e1000_hw
*);
45 static s32
igb_acquire_nvm_82575(struct e1000_hw
*);
46 static void igb_release_nvm_82575(struct e1000_hw
*);
47 static s32
igb_check_for_link_82575(struct e1000_hw
*);
48 static s32
igb_get_cfg_done_82575(struct e1000_hw
*);
49 static s32
igb_init_hw_82575(struct e1000_hw
*);
50 static s32
igb_phy_hw_reset_sgmii_82575(struct e1000_hw
*);
51 static s32
igb_read_phy_reg_sgmii_82575(struct e1000_hw
*, u32
, u16
*);
52 static s32
igb_read_phy_reg_82580(struct e1000_hw
*, u32
, u16
*);
53 static s32
igb_write_phy_reg_82580(struct e1000_hw
*, u32
, u16
);
54 static s32
igb_reset_hw_82575(struct e1000_hw
*);
55 static s32
igb_reset_hw_82580(struct e1000_hw
*);
56 static s32
igb_set_d0_lplu_state_82575(struct e1000_hw
*, bool);
57 static s32
igb_set_d0_lplu_state_82580(struct e1000_hw
*, bool);
58 static s32
igb_set_d3_lplu_state_82580(struct e1000_hw
*, bool);
59 static s32
igb_setup_copper_link_82575(struct e1000_hw
*);
60 static s32
igb_setup_serdes_link_82575(struct e1000_hw
*);
61 static s32
igb_write_phy_reg_sgmii_82575(struct e1000_hw
*, u32
, u16
);
62 static void igb_clear_hw_cntrs_82575(struct e1000_hw
*);
63 static s32
igb_acquire_swfw_sync_82575(struct e1000_hw
*, u16
);
64 static s32
igb_get_pcs_speed_and_duplex_82575(struct e1000_hw
*, u16
*,
66 static s32
igb_get_phy_id_82575(struct e1000_hw
*);
67 static void igb_release_swfw_sync_82575(struct e1000_hw
*, u16
);
68 static bool igb_sgmii_active_82575(struct e1000_hw
*);
69 static s32
igb_reset_init_script_82575(struct e1000_hw
*);
70 static s32
igb_read_mac_addr_82575(struct e1000_hw
*);
71 static s32
igb_set_pcie_completion_timeout(struct e1000_hw
*hw
);
72 static s32
igb_reset_mdicnfg_82580(struct e1000_hw
*hw
);
73 static s32
igb_validate_nvm_checksum_82580(struct e1000_hw
*hw
);
74 static s32
igb_update_nvm_checksum_82580(struct e1000_hw
*hw
);
75 static s32
igb_validate_nvm_checksum_i350(struct e1000_hw
*hw
);
76 static s32
igb_update_nvm_checksum_i350(struct e1000_hw
*hw
);
77 static const u16 e1000_82580_rxpbs_table
[] =
78 { 36, 72, 144, 1, 2, 4, 8, 16,
80 #define E1000_82580_RXPBS_TABLE_SIZE \
81 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
84 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
85 * @hw: pointer to the HW structure
87 * Called to determine if the I2C pins are being used for I2C or as an
88 * external MDIO interface since the two options are mutually exclusive.
90 static bool igb_sgmii_uses_mdio_82575(struct e1000_hw
*hw
)
93 bool ext_mdio
= false;
95 switch (hw
->mac
.type
) {
98 reg
= rd32(E1000_MDIC
);
99 ext_mdio
= !!(reg
& E1000_MDIC_DEST
);
106 reg
= rd32(E1000_MDICNFG
);
107 ext_mdio
= !!(reg
& E1000_MDICNFG_EXT_MDIO
);
116 * igb_init_phy_params_82575 - Init PHY func ptrs.
117 * @hw: pointer to the HW structure
119 static s32
igb_init_phy_params_82575(struct e1000_hw
*hw
)
121 struct e1000_phy_info
*phy
= &hw
->phy
;
125 if (hw
->phy
.media_type
!= e1000_media_type_copper
) {
126 phy
->type
= e1000_phy_none
;
130 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
131 phy
->reset_delay_us
= 100;
133 ctrl_ext
= rd32(E1000_CTRL_EXT
);
135 if (igb_sgmii_active_82575(hw
)) {
136 phy
->ops
.reset
= igb_phy_hw_reset_sgmii_82575
;
137 ctrl_ext
|= E1000_CTRL_I2C_ENA
;
139 phy
->ops
.reset
= igb_phy_hw_reset
;
140 ctrl_ext
&= ~E1000_CTRL_I2C_ENA
;
143 wr32(E1000_CTRL_EXT
, ctrl_ext
);
144 igb_reset_mdicnfg_82580(hw
);
146 if (igb_sgmii_active_82575(hw
) && !igb_sgmii_uses_mdio_82575(hw
)) {
147 phy
->ops
.read_reg
= igb_read_phy_reg_sgmii_82575
;
148 phy
->ops
.write_reg
= igb_write_phy_reg_sgmii_82575
;
150 switch (hw
->mac
.type
) {
154 phy
->ops
.read_reg
= igb_read_phy_reg_82580
;
155 phy
->ops
.write_reg
= igb_write_phy_reg_82580
;
159 phy
->ops
.read_reg
= igb_read_phy_reg_gs40g
;
160 phy
->ops
.write_reg
= igb_write_phy_reg_gs40g
;
163 phy
->ops
.read_reg
= igb_read_phy_reg_igp
;
164 phy
->ops
.write_reg
= igb_write_phy_reg_igp
;
169 hw
->bus
.func
= (rd32(E1000_STATUS
) & E1000_STATUS_FUNC_MASK
) >>
170 E1000_STATUS_FUNC_SHIFT
;
172 /* Set phy->phy_addr and phy->id. */
173 ret_val
= igb_get_phy_id_82575(hw
);
177 /* Verify phy id and set remaining function pointers */
179 case M88E1545_E_PHY_ID
:
180 case I347AT4_E_PHY_ID
:
181 case M88E1112_E_PHY_ID
:
182 case M88E1111_I_PHY_ID
:
183 phy
->type
= e1000_phy_m88
;
184 phy
->ops
.check_polarity
= igb_check_polarity_m88
;
185 phy
->ops
.get_phy_info
= igb_get_phy_info_m88
;
186 if (phy
->id
!= M88E1111_I_PHY_ID
)
187 phy
->ops
.get_cable_length
=
188 igb_get_cable_length_m88_gen2
;
190 phy
->ops
.get_cable_length
= igb_get_cable_length_m88
;
191 phy
->ops
.force_speed_duplex
= igb_phy_force_speed_duplex_m88
;
193 case IGP03E1000_E_PHY_ID
:
194 phy
->type
= e1000_phy_igp_3
;
195 phy
->ops
.get_phy_info
= igb_get_phy_info_igp
;
196 phy
->ops
.get_cable_length
= igb_get_cable_length_igp_2
;
197 phy
->ops
.force_speed_duplex
= igb_phy_force_speed_duplex_igp
;
198 phy
->ops
.set_d0_lplu_state
= igb_set_d0_lplu_state_82575
;
199 phy
->ops
.set_d3_lplu_state
= igb_set_d3_lplu_state
;
201 case I82580_I_PHY_ID
:
203 phy
->type
= e1000_phy_82580
;
204 phy
->ops
.force_speed_duplex
=
205 igb_phy_force_speed_duplex_82580
;
206 phy
->ops
.get_cable_length
= igb_get_cable_length_82580
;
207 phy
->ops
.get_phy_info
= igb_get_phy_info_82580
;
208 phy
->ops
.set_d0_lplu_state
= igb_set_d0_lplu_state_82580
;
209 phy
->ops
.set_d3_lplu_state
= igb_set_d3_lplu_state_82580
;
212 phy
->type
= e1000_phy_i210
;
213 phy
->ops
.check_polarity
= igb_check_polarity_m88
;
214 phy
->ops
.get_phy_info
= igb_get_phy_info_m88
;
215 phy
->ops
.get_cable_length
= igb_get_cable_length_m88_gen2
;
216 phy
->ops
.set_d0_lplu_state
= igb_set_d0_lplu_state_82580
;
217 phy
->ops
.set_d3_lplu_state
= igb_set_d3_lplu_state_82580
;
218 phy
->ops
.force_speed_duplex
= igb_phy_force_speed_duplex_m88
;
221 ret_val
= -E1000_ERR_PHY
;
230 * igb_init_nvm_params_82575 - Init NVM func ptrs.
231 * @hw: pointer to the HW structure
233 static s32
igb_init_nvm_params_82575(struct e1000_hw
*hw
)
235 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
236 u32 eecd
= rd32(E1000_EECD
);
239 size
= (u16
)((eecd
& E1000_EECD_SIZE_EX_MASK
) >>
240 E1000_EECD_SIZE_EX_SHIFT
);
241 /* Added to a constant, "size" becomes the left-shift value
242 * for setting word_size.
244 size
+= NVM_WORD_SIZE_BASE_SHIFT
;
246 /* Just in case size is out of range, cap it to the largest
247 * EEPROM size supported
252 nvm
->word_size
= 1 << size
;
253 if (hw
->mac
.type
< e1000_i210
) {
254 nvm
->opcode_bits
= 8;
257 switch (nvm
->override
) {
258 case e1000_nvm_override_spi_large
:
260 nvm
->address_bits
= 16;
262 case e1000_nvm_override_spi_small
:
264 nvm
->address_bits
= 8;
267 nvm
->page_size
= eecd
& E1000_EECD_ADDR_BITS
? 32 : 8;
268 nvm
->address_bits
= eecd
& E1000_EECD_ADDR_BITS
?
272 if (nvm
->word_size
== (1 << 15))
273 nvm
->page_size
= 128;
275 nvm
->type
= e1000_nvm_eeprom_spi
;
277 nvm
->type
= e1000_nvm_flash_hw
;
280 /* NVM Function Pointers */
281 switch (hw
->mac
.type
) {
283 nvm
->ops
.validate
= igb_validate_nvm_checksum_82580
;
284 nvm
->ops
.update
= igb_update_nvm_checksum_82580
;
285 nvm
->ops
.acquire
= igb_acquire_nvm_82575
;
286 nvm
->ops
.release
= igb_release_nvm_82575
;
287 if (nvm
->word_size
< (1 << 15))
288 nvm
->ops
.read
= igb_read_nvm_eerd
;
290 nvm
->ops
.read
= igb_read_nvm_spi
;
291 nvm
->ops
.write
= igb_write_nvm_spi
;
295 nvm
->ops
.validate
= igb_validate_nvm_checksum_i350
;
296 nvm
->ops
.update
= igb_update_nvm_checksum_i350
;
297 nvm
->ops
.acquire
= igb_acquire_nvm_82575
;
298 nvm
->ops
.release
= igb_release_nvm_82575
;
299 if (nvm
->word_size
< (1 << 15))
300 nvm
->ops
.read
= igb_read_nvm_eerd
;
302 nvm
->ops
.read
= igb_read_nvm_spi
;
303 nvm
->ops
.write
= igb_write_nvm_spi
;
306 nvm
->ops
.validate
= igb_validate_nvm_checksum_i210
;
307 nvm
->ops
.update
= igb_update_nvm_checksum_i210
;
308 nvm
->ops
.acquire
= igb_acquire_nvm_i210
;
309 nvm
->ops
.release
= igb_release_nvm_i210
;
310 nvm
->ops
.read
= igb_read_nvm_srrd_i210
;
311 nvm
->ops
.write
= igb_write_nvm_srwr_i210
;
312 nvm
->ops
.valid_led_default
= igb_valid_led_default_i210
;
315 nvm
->ops
.acquire
= igb_acquire_nvm_i210
;
316 nvm
->ops
.release
= igb_release_nvm_i210
;
317 nvm
->ops
.read
= igb_read_nvm_i211
;
318 nvm
->ops
.valid_led_default
= igb_valid_led_default_i210
;
319 nvm
->ops
.validate
= NULL
;
320 nvm
->ops
.update
= NULL
;
321 nvm
->ops
.write
= NULL
;
324 nvm
->ops
.validate
= igb_validate_nvm_checksum
;
325 nvm
->ops
.update
= igb_update_nvm_checksum
;
326 nvm
->ops
.acquire
= igb_acquire_nvm_82575
;
327 nvm
->ops
.release
= igb_release_nvm_82575
;
328 if (nvm
->word_size
< (1 << 15))
329 nvm
->ops
.read
= igb_read_nvm_eerd
;
331 nvm
->ops
.read
= igb_read_nvm_spi
;
332 nvm
->ops
.write
= igb_write_nvm_spi
;
340 * igb_init_mac_params_82575 - Init MAC func ptrs.
341 * @hw: pointer to the HW structure
343 static s32
igb_init_mac_params_82575(struct e1000_hw
*hw
)
345 struct e1000_mac_info
*mac
= &hw
->mac
;
346 struct e1000_dev_spec_82575
*dev_spec
= &hw
->dev_spec
._82575
;
348 /* Set mta register count */
349 mac
->mta_reg_count
= 128;
350 /* Set rar entry count */
353 mac
->rar_entry_count
= E1000_RAR_ENTRIES_82576
;
356 mac
->rar_entry_count
= E1000_RAR_ENTRIES_82580
;
360 mac
->rar_entry_count
= E1000_RAR_ENTRIES_I350
;
363 mac
->rar_entry_count
= E1000_RAR_ENTRIES_82575
;
367 if (mac
->type
>= e1000_82580
)
368 mac
->ops
.reset_hw
= igb_reset_hw_82580
;
370 mac
->ops
.reset_hw
= igb_reset_hw_82575
;
372 if (mac
->type
>= e1000_i210
) {
373 mac
->ops
.acquire_swfw_sync
= igb_acquire_swfw_sync_i210
;
374 mac
->ops
.release_swfw_sync
= igb_release_swfw_sync_i210
;
377 mac
->ops
.acquire_swfw_sync
= igb_acquire_swfw_sync_82575
;
378 mac
->ops
.release_swfw_sync
= igb_release_swfw_sync_82575
;
381 /* Set if part includes ASF firmware */
382 mac
->asf_firmware_present
= true;
383 /* Set if manageability features are enabled. */
384 mac
->arc_subsystem_valid
=
385 (rd32(E1000_FWSM
) & E1000_FWSM_MODE_MASK
)
387 /* enable EEE on i350 parts and later parts */
388 if (mac
->type
>= e1000_i350
)
389 dev_spec
->eee_disable
= false;
391 dev_spec
->eee_disable
= true;
392 /* Allow a single clear of the SW semaphore on I210 and newer */
393 if (mac
->type
>= e1000_i210
)
394 dev_spec
->clear_semaphore_once
= true;
395 /* physical interface link setup */
396 mac
->ops
.setup_physical_interface
=
397 (hw
->phy
.media_type
== e1000_media_type_copper
)
398 ? igb_setup_copper_link_82575
399 : igb_setup_serdes_link_82575
;
405 * igb_set_sfp_media_type_82575 - derives SFP module media type.
406 * @hw: pointer to the HW structure
408 * The media type is chosen based on SFP module.
409 * compatibility flags retrieved from SFP ID EEPROM.
411 static s32
igb_set_sfp_media_type_82575(struct e1000_hw
*hw
)
413 s32 ret_val
= E1000_ERR_CONFIG
;
415 struct e1000_dev_spec_82575
*dev_spec
= &hw
->dev_spec
._82575
;
416 struct e1000_sfp_flags
*eth_flags
= &dev_spec
->eth_flags
;
417 u8 tranceiver_type
= 0;
420 /* Turn I2C interface ON and power on sfp cage */
421 ctrl_ext
= rd32(E1000_CTRL_EXT
);
422 ctrl_ext
&= ~E1000_CTRL_EXT_SDP3_DATA
;
423 wr32(E1000_CTRL_EXT
, ctrl_ext
| E1000_CTRL_I2C_ENA
);
427 /* Read SFP module data */
429 ret_val
= igb_read_sfp_data_byte(hw
,
430 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET
),
440 ret_val
= igb_read_sfp_data_byte(hw
,
441 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET
),
446 /* Check if there is some SFP module plugged and powered */
447 if ((tranceiver_type
== E1000_SFF_IDENTIFIER_SFP
) ||
448 (tranceiver_type
== E1000_SFF_IDENTIFIER_SFF
)) {
449 dev_spec
->module_plugged
= true;
450 if (eth_flags
->e1000_base_lx
|| eth_flags
->e1000_base_sx
) {
451 hw
->phy
.media_type
= e1000_media_type_internal_serdes
;
452 } else if (eth_flags
->e100_base_fx
) {
453 dev_spec
->sgmii_active
= true;
454 hw
->phy
.media_type
= e1000_media_type_internal_serdes
;
455 } else if (eth_flags
->e1000_base_t
) {
456 dev_spec
->sgmii_active
= true;
457 hw
->phy
.media_type
= e1000_media_type_copper
;
459 hw
->phy
.media_type
= e1000_media_type_unknown
;
460 hw_dbg("PHY module has not been recognized\n");
464 hw
->phy
.media_type
= e1000_media_type_unknown
;
468 /* Restore I2C interface setting */
469 wr32(E1000_CTRL_EXT
, ctrl_ext
);
473 static s32
igb_get_invariants_82575(struct e1000_hw
*hw
)
475 struct e1000_mac_info
*mac
= &hw
->mac
;
476 struct e1000_dev_spec_82575
* dev_spec
= &hw
->dev_spec
._82575
;
481 switch (hw
->device_id
) {
482 case E1000_DEV_ID_82575EB_COPPER
:
483 case E1000_DEV_ID_82575EB_FIBER_SERDES
:
484 case E1000_DEV_ID_82575GB_QUAD_COPPER
:
485 mac
->type
= e1000_82575
;
487 case E1000_DEV_ID_82576
:
488 case E1000_DEV_ID_82576_NS
:
489 case E1000_DEV_ID_82576_NS_SERDES
:
490 case E1000_DEV_ID_82576_FIBER
:
491 case E1000_DEV_ID_82576_SERDES
:
492 case E1000_DEV_ID_82576_QUAD_COPPER
:
493 case E1000_DEV_ID_82576_QUAD_COPPER_ET2
:
494 case E1000_DEV_ID_82576_SERDES_QUAD
:
495 mac
->type
= e1000_82576
;
497 case E1000_DEV_ID_82580_COPPER
:
498 case E1000_DEV_ID_82580_FIBER
:
499 case E1000_DEV_ID_82580_QUAD_FIBER
:
500 case E1000_DEV_ID_82580_SERDES
:
501 case E1000_DEV_ID_82580_SGMII
:
502 case E1000_DEV_ID_82580_COPPER_DUAL
:
503 case E1000_DEV_ID_DH89XXCC_SGMII
:
504 case E1000_DEV_ID_DH89XXCC_SERDES
:
505 case E1000_DEV_ID_DH89XXCC_BACKPLANE
:
506 case E1000_DEV_ID_DH89XXCC_SFP
:
507 mac
->type
= e1000_82580
;
509 case E1000_DEV_ID_I350_COPPER
:
510 case E1000_DEV_ID_I350_FIBER
:
511 case E1000_DEV_ID_I350_SERDES
:
512 case E1000_DEV_ID_I350_SGMII
:
513 mac
->type
= e1000_i350
;
515 case E1000_DEV_ID_I210_COPPER
:
516 case E1000_DEV_ID_I210_FIBER
:
517 case E1000_DEV_ID_I210_SERDES
:
518 case E1000_DEV_ID_I210_SGMII
:
519 mac
->type
= e1000_i210
;
521 case E1000_DEV_ID_I211_COPPER
:
522 mac
->type
= e1000_i211
;
524 case E1000_DEV_ID_I354_BACKPLANE_1GBPS
:
525 case E1000_DEV_ID_I354_SGMII
:
526 case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS
:
527 mac
->type
= e1000_i354
;
530 return -E1000_ERR_MAC_INIT
;
535 /* The 82575 uses bits 22:23 for link mode. The mode can be changed
536 * based on the EEPROM. We cannot rely upon device ID. There
537 * is no distinguishable difference between fiber and internal
538 * SerDes mode on the 82575. There can be an external PHY attached
539 * on the SGMII interface. For this, we'll set sgmii_active to true.
541 hw
->phy
.media_type
= e1000_media_type_copper
;
542 dev_spec
->sgmii_active
= false;
543 dev_spec
->module_plugged
= false;
545 ctrl_ext
= rd32(E1000_CTRL_EXT
);
547 link_mode
= ctrl_ext
& E1000_CTRL_EXT_LINK_MODE_MASK
;
549 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX
:
550 hw
->phy
.media_type
= e1000_media_type_internal_serdes
;
552 case E1000_CTRL_EXT_LINK_MODE_SGMII
:
553 /* Get phy control interface type set (MDIO vs. I2C)*/
554 if (igb_sgmii_uses_mdio_82575(hw
)) {
555 hw
->phy
.media_type
= e1000_media_type_copper
;
556 dev_spec
->sgmii_active
= true;
559 /* fall through for I2C based SGMII */
560 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES
:
561 /* read media type from SFP EEPROM */
562 ret_val
= igb_set_sfp_media_type_82575(hw
);
563 if ((ret_val
!= 0) ||
564 (hw
->phy
.media_type
== e1000_media_type_unknown
)) {
565 /* If media type was not identified then return media
566 * type defined by the CTRL_EXT settings.
568 hw
->phy
.media_type
= e1000_media_type_internal_serdes
;
570 if (link_mode
== E1000_CTRL_EXT_LINK_MODE_SGMII
) {
571 hw
->phy
.media_type
= e1000_media_type_copper
;
572 dev_spec
->sgmii_active
= true;
578 /* do not change link mode for 100BaseFX */
579 if (dev_spec
->eth_flags
.e100_base_fx
)
582 /* change current link mode setting */
583 ctrl_ext
&= ~E1000_CTRL_EXT_LINK_MODE_MASK
;
585 if (hw
->phy
.media_type
== e1000_media_type_copper
)
586 ctrl_ext
|= E1000_CTRL_EXT_LINK_MODE_SGMII
;
588 ctrl_ext
|= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES
;
590 wr32(E1000_CTRL_EXT
, ctrl_ext
);
597 /* mac initialization and operations */
598 ret_val
= igb_init_mac_params_82575(hw
);
602 /* NVM initialization */
603 ret_val
= igb_init_nvm_params_82575(hw
);
607 /* if part supports SR-IOV then initialize mailbox parameters */
611 igb_init_mbx_params_pf(hw
);
617 /* setup PHY parameters */
618 ret_val
= igb_init_phy_params_82575(hw
);
625 * igb_acquire_phy_82575 - Acquire rights to access PHY
626 * @hw: pointer to the HW structure
628 * Acquire access rights to the correct PHY. This is a
629 * function pointer entry point called by the api module.
631 static s32
igb_acquire_phy_82575(struct e1000_hw
*hw
)
633 u16 mask
= E1000_SWFW_PHY0_SM
;
635 if (hw
->bus
.func
== E1000_FUNC_1
)
636 mask
= E1000_SWFW_PHY1_SM
;
637 else if (hw
->bus
.func
== E1000_FUNC_2
)
638 mask
= E1000_SWFW_PHY2_SM
;
639 else if (hw
->bus
.func
== E1000_FUNC_3
)
640 mask
= E1000_SWFW_PHY3_SM
;
642 return hw
->mac
.ops
.acquire_swfw_sync(hw
, mask
);
646 * igb_release_phy_82575 - Release rights to access PHY
647 * @hw: pointer to the HW structure
649 * A wrapper to release access rights to the correct PHY. This is a
650 * function pointer entry point called by the api module.
652 static void igb_release_phy_82575(struct e1000_hw
*hw
)
654 u16 mask
= E1000_SWFW_PHY0_SM
;
656 if (hw
->bus
.func
== E1000_FUNC_1
)
657 mask
= E1000_SWFW_PHY1_SM
;
658 else if (hw
->bus
.func
== E1000_FUNC_2
)
659 mask
= E1000_SWFW_PHY2_SM
;
660 else if (hw
->bus
.func
== E1000_FUNC_3
)
661 mask
= E1000_SWFW_PHY3_SM
;
663 hw
->mac
.ops
.release_swfw_sync(hw
, mask
);
667 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
668 * @hw: pointer to the HW structure
669 * @offset: register offset to be read
670 * @data: pointer to the read data
672 * Reads the PHY register at offset using the serial gigabit media independent
673 * interface and stores the retrieved information in data.
675 static s32
igb_read_phy_reg_sgmii_82575(struct e1000_hw
*hw
, u32 offset
,
678 s32 ret_val
= -E1000_ERR_PARAM
;
680 if (offset
> E1000_MAX_SGMII_PHY_REG_ADDR
) {
681 hw_dbg("PHY Address %u is out of range\n", offset
);
685 ret_val
= hw
->phy
.ops
.acquire(hw
);
689 ret_val
= igb_read_phy_reg_i2c(hw
, offset
, data
);
691 hw
->phy
.ops
.release(hw
);
698 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
699 * @hw: pointer to the HW structure
700 * @offset: register offset to write to
701 * @data: data to write at register offset
703 * Writes the data to PHY register at the offset using the serial gigabit
704 * media independent interface.
706 static s32
igb_write_phy_reg_sgmii_82575(struct e1000_hw
*hw
, u32 offset
,
709 s32 ret_val
= -E1000_ERR_PARAM
;
712 if (offset
> E1000_MAX_SGMII_PHY_REG_ADDR
) {
713 hw_dbg("PHY Address %d is out of range\n", offset
);
717 ret_val
= hw
->phy
.ops
.acquire(hw
);
721 ret_val
= igb_write_phy_reg_i2c(hw
, offset
, data
);
723 hw
->phy
.ops
.release(hw
);
730 * igb_get_phy_id_82575 - Retrieve PHY addr and id
731 * @hw: pointer to the HW structure
733 * Retrieves the PHY address and ID for both PHY's which do and do not use
736 static s32
igb_get_phy_id_82575(struct e1000_hw
*hw
)
738 struct e1000_phy_info
*phy
= &hw
->phy
;
744 /* For SGMII PHYs, we try the list of possible addresses until
745 * we find one that works. For non-SGMII PHYs
746 * (e.g. integrated copper PHYs), an address of 1 should
747 * work. The result of this function should mean phy->phy_addr
748 * and phy->id are set correctly.
750 if (!(igb_sgmii_active_82575(hw
))) {
752 ret_val
= igb_get_phy_id(hw
);
756 if (igb_sgmii_uses_mdio_82575(hw
)) {
757 switch (hw
->mac
.type
) {
760 mdic
= rd32(E1000_MDIC
);
761 mdic
&= E1000_MDIC_PHY_MASK
;
762 phy
->addr
= mdic
>> E1000_MDIC_PHY_SHIFT
;
769 mdic
= rd32(E1000_MDICNFG
);
770 mdic
&= E1000_MDICNFG_PHY_MASK
;
771 phy
->addr
= mdic
>> E1000_MDICNFG_PHY_SHIFT
;
774 ret_val
= -E1000_ERR_PHY
;
778 ret_val
= igb_get_phy_id(hw
);
782 /* Power on sgmii phy if it is disabled */
783 ctrl_ext
= rd32(E1000_CTRL_EXT
);
784 wr32(E1000_CTRL_EXT
, ctrl_ext
& ~E1000_CTRL_EXT_SDP3_DATA
);
788 /* The address field in the I2CCMD register is 3 bits and 0 is invalid.
789 * Therefore, we need to test 1-7
791 for (phy
->addr
= 1; phy
->addr
< 8; phy
->addr
++) {
792 ret_val
= igb_read_phy_reg_sgmii_82575(hw
, PHY_ID1
, &phy_id
);
794 hw_dbg("Vendor ID 0x%08X read at address %u\n",
796 /* At the time of this writing, The M88 part is
797 * the only supported SGMII PHY product.
799 if (phy_id
== M88_VENDOR
)
802 hw_dbg("PHY address %u was unreadable\n", phy
->addr
);
806 /* A valid PHY type couldn't be found. */
807 if (phy
->addr
== 8) {
809 ret_val
= -E1000_ERR_PHY
;
812 ret_val
= igb_get_phy_id(hw
);
815 /* restore previous sfp cage power state */
816 wr32(E1000_CTRL_EXT
, ctrl_ext
);
823 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
824 * @hw: pointer to the HW structure
826 * Resets the PHY using the serial gigabit media independent interface.
828 static s32
igb_phy_hw_reset_sgmii_82575(struct e1000_hw
*hw
)
832 /* This isn't a true "hard" reset, but is the only reset
833 * available to us at this time.
836 hw_dbg("Soft resetting SGMII attached PHY...\n");
838 /* SFP documentation requires the following to configure the SPF module
839 * to work on SGMII. No further documentation is given.
841 ret_val
= hw
->phy
.ops
.write_reg(hw
, 0x1B, 0x8084);
845 ret_val
= igb_phy_sw_reset(hw
);
852 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
853 * @hw: pointer to the HW structure
854 * @active: true to enable LPLU, false to disable
856 * Sets the LPLU D0 state according to the active flag. When
857 * activating LPLU this function also disables smart speed
858 * and vice versa. LPLU will not be activated unless the
859 * device autonegotiation advertisement meets standards of
860 * either 10 or 10/100 or 10/100/1000 at all duplexes.
861 * This is a function pointer entry point only called by
862 * PHY setup routines.
864 static s32
igb_set_d0_lplu_state_82575(struct e1000_hw
*hw
, bool active
)
866 struct e1000_phy_info
*phy
= &hw
->phy
;
870 ret_val
= phy
->ops
.read_reg(hw
, IGP02E1000_PHY_POWER_MGMT
, &data
);
875 data
|= IGP02E1000_PM_D0_LPLU
;
876 ret_val
= phy
->ops
.write_reg(hw
, IGP02E1000_PHY_POWER_MGMT
,
881 /* When LPLU is enabled, we should disable SmartSpeed */
882 ret_val
= phy
->ops
.read_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
884 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
885 ret_val
= phy
->ops
.write_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
890 data
&= ~IGP02E1000_PM_D0_LPLU
;
891 ret_val
= phy
->ops
.write_reg(hw
, IGP02E1000_PHY_POWER_MGMT
,
893 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
894 * during Dx states where the power conservation is most
895 * important. During driver activity we should enable
896 * SmartSpeed, so performance is maintained.
898 if (phy
->smart_speed
== e1000_smart_speed_on
) {
899 ret_val
= phy
->ops
.read_reg(hw
,
900 IGP01E1000_PHY_PORT_CONFIG
, &data
);
904 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
905 ret_val
= phy
->ops
.write_reg(hw
,
906 IGP01E1000_PHY_PORT_CONFIG
, data
);
909 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
910 ret_val
= phy
->ops
.read_reg(hw
,
911 IGP01E1000_PHY_PORT_CONFIG
, &data
);
915 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
916 ret_val
= phy
->ops
.write_reg(hw
,
917 IGP01E1000_PHY_PORT_CONFIG
, data
);
928 * igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
929 * @hw: pointer to the HW structure
930 * @active: true to enable LPLU, false to disable
932 * Sets the LPLU D0 state according to the active flag. When
933 * activating LPLU this function also disables smart speed
934 * and vice versa. LPLU will not be activated unless the
935 * device autonegotiation advertisement meets standards of
936 * either 10 or 10/100 or 10/100/1000 at all duplexes.
937 * This is a function pointer entry point only called by
938 * PHY setup routines.
940 static s32
igb_set_d0_lplu_state_82580(struct e1000_hw
*hw
, bool active
)
942 struct e1000_phy_info
*phy
= &hw
->phy
;
946 data
= rd32(E1000_82580_PHY_POWER_MGMT
);
949 data
|= E1000_82580_PM_D0_LPLU
;
951 /* When LPLU is enabled, we should disable SmartSpeed */
952 data
&= ~E1000_82580_PM_SPD
;
954 data
&= ~E1000_82580_PM_D0_LPLU
;
956 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
957 * during Dx states where the power conservation is most
958 * important. During driver activity we should enable
959 * SmartSpeed, so performance is maintained.
961 if (phy
->smart_speed
== e1000_smart_speed_on
)
962 data
|= E1000_82580_PM_SPD
;
963 else if (phy
->smart_speed
== e1000_smart_speed_off
)
964 data
&= ~E1000_82580_PM_SPD
; }
966 wr32(E1000_82580_PHY_POWER_MGMT
, data
);
971 * igb_set_d3_lplu_state_82580 - Sets low power link up state for D3
972 * @hw: pointer to the HW structure
973 * @active: boolean used to enable/disable lplu
975 * Success returns 0, Failure returns 1
977 * The low power link up (lplu) state is set to the power management level D3
978 * and SmartSpeed is disabled when active is true, else clear lplu for D3
979 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
980 * is used during Dx states where the power conservation is most important.
981 * During driver activity, SmartSpeed should be enabled so performance is
984 static s32
igb_set_d3_lplu_state_82580(struct e1000_hw
*hw
, bool active
)
986 struct e1000_phy_info
*phy
= &hw
->phy
;
990 data
= rd32(E1000_82580_PHY_POWER_MGMT
);
993 data
&= ~E1000_82580_PM_D3_LPLU
;
994 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
995 * during Dx states where the power conservation is most
996 * important. During driver activity we should enable
997 * SmartSpeed, so performance is maintained.
999 if (phy
->smart_speed
== e1000_smart_speed_on
)
1000 data
|= E1000_82580_PM_SPD
;
1001 else if (phy
->smart_speed
== e1000_smart_speed_off
)
1002 data
&= ~E1000_82580_PM_SPD
;
1003 } else if ((phy
->autoneg_advertised
== E1000_ALL_SPEED_DUPLEX
) ||
1004 (phy
->autoneg_advertised
== E1000_ALL_NOT_GIG
) ||
1005 (phy
->autoneg_advertised
== E1000_ALL_10_SPEED
)) {
1006 data
|= E1000_82580_PM_D3_LPLU
;
1007 /* When LPLU is enabled, we should disable SmartSpeed */
1008 data
&= ~E1000_82580_PM_SPD
;
1011 wr32(E1000_82580_PHY_POWER_MGMT
, data
);
1016 * igb_acquire_nvm_82575 - Request for access to EEPROM
1017 * @hw: pointer to the HW structure
1019 * Acquire the necessary semaphores for exclusive access to the EEPROM.
1020 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
1021 * Return successful if access grant bit set, else clear the request for
1022 * EEPROM access and return -E1000_ERR_NVM (-1).
1024 static s32
igb_acquire_nvm_82575(struct e1000_hw
*hw
)
1028 ret_val
= hw
->mac
.ops
.acquire_swfw_sync(hw
, E1000_SWFW_EEP_SM
);
1032 ret_val
= igb_acquire_nvm(hw
);
1035 hw
->mac
.ops
.release_swfw_sync(hw
, E1000_SWFW_EEP_SM
);
1042 * igb_release_nvm_82575 - Release exclusive access to EEPROM
1043 * @hw: pointer to the HW structure
1045 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
1046 * then release the semaphores acquired.
1048 static void igb_release_nvm_82575(struct e1000_hw
*hw
)
1050 igb_release_nvm(hw
);
1051 hw
->mac
.ops
.release_swfw_sync(hw
, E1000_SWFW_EEP_SM
);
1055 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1056 * @hw: pointer to the HW structure
1057 * @mask: specifies which semaphore to acquire
1059 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
1060 * will also specify which port we're acquiring the lock for.
1062 static s32
igb_acquire_swfw_sync_82575(struct e1000_hw
*hw
, u16 mask
)
1066 u32 fwmask
= mask
<< 16;
1068 s32 i
= 0, timeout
= 200; /* FIXME: find real value to use here */
1070 while (i
< timeout
) {
1071 if (igb_get_hw_semaphore(hw
)) {
1072 ret_val
= -E1000_ERR_SWFW_SYNC
;
1076 swfw_sync
= rd32(E1000_SW_FW_SYNC
);
1077 if (!(swfw_sync
& (fwmask
| swmask
)))
1080 /* Firmware currently using resource (fwmask)
1081 * or other software thread using resource (swmask)
1083 igb_put_hw_semaphore(hw
);
1089 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
1090 ret_val
= -E1000_ERR_SWFW_SYNC
;
1094 swfw_sync
|= swmask
;
1095 wr32(E1000_SW_FW_SYNC
, swfw_sync
);
1097 igb_put_hw_semaphore(hw
);
1104 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
1105 * @hw: pointer to the HW structure
1106 * @mask: specifies which semaphore to acquire
1108 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
1109 * will also specify which port we're releasing the lock for.
1111 static void igb_release_swfw_sync_82575(struct e1000_hw
*hw
, u16 mask
)
1115 while (igb_get_hw_semaphore(hw
) != 0);
1118 swfw_sync
= rd32(E1000_SW_FW_SYNC
);
1120 wr32(E1000_SW_FW_SYNC
, swfw_sync
);
1122 igb_put_hw_semaphore(hw
);
1126 * igb_get_cfg_done_82575 - Read config done bit
1127 * @hw: pointer to the HW structure
1129 * Read the management control register for the config done bit for
1130 * completion status. NOTE: silicon which is EEPROM-less will fail trying
1131 * to read the config done bit, so an error is *ONLY* logged and returns
1132 * 0. If we were to return with error, EEPROM-less silicon
1133 * would not be able to be reset or change link.
1135 static s32
igb_get_cfg_done_82575(struct e1000_hw
*hw
)
1137 s32 timeout
= PHY_CFG_TIMEOUT
;
1139 u32 mask
= E1000_NVM_CFG_DONE_PORT_0
;
1141 if (hw
->bus
.func
== 1)
1142 mask
= E1000_NVM_CFG_DONE_PORT_1
;
1143 else if (hw
->bus
.func
== E1000_FUNC_2
)
1144 mask
= E1000_NVM_CFG_DONE_PORT_2
;
1145 else if (hw
->bus
.func
== E1000_FUNC_3
)
1146 mask
= E1000_NVM_CFG_DONE_PORT_3
;
1149 if (rd32(E1000_EEMNGCTL
) & mask
)
1155 hw_dbg("MNG configuration cycle has not completed.\n");
1157 /* If EEPROM is not marked present, init the PHY manually */
1158 if (((rd32(E1000_EECD
) & E1000_EECD_PRES
) == 0) &&
1159 (hw
->phy
.type
== e1000_phy_igp_3
))
1160 igb_phy_init_script_igp3(hw
);
1166 * igb_check_for_link_82575 - Check for link
1167 * @hw: pointer to the HW structure
1169 * If sgmii is enabled, then use the pcs register to determine link, otherwise
1170 * use the generic interface for determining link.
1172 static s32
igb_check_for_link_82575(struct e1000_hw
*hw
)
1177 if (hw
->phy
.media_type
!= e1000_media_type_copper
) {
1178 ret_val
= igb_get_pcs_speed_and_duplex_82575(hw
, &speed
,
1180 /* Use this flag to determine if link needs to be checked or
1181 * not. If we have link clear the flag so that we do not
1182 * continue to check for link.
1184 hw
->mac
.get_link_status
= !hw
->mac
.serdes_has_link
;
1186 /* Configure Flow Control now that Auto-Neg has completed.
1187 * First, we need to restore the desired flow control
1188 * settings because we may have had to re-autoneg with a
1189 * different link partner.
1191 ret_val
= igb_config_fc_after_link_up(hw
);
1193 hw_dbg("Error configuring flow control\n");
1195 ret_val
= igb_check_for_copper_link(hw
);
1202 * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1203 * @hw: pointer to the HW structure
1205 void igb_power_up_serdes_link_82575(struct e1000_hw
*hw
)
1210 if ((hw
->phy
.media_type
!= e1000_media_type_internal_serdes
) &&
1211 !igb_sgmii_active_82575(hw
))
1214 /* Enable PCS to turn on link */
1215 reg
= rd32(E1000_PCS_CFG0
);
1216 reg
|= E1000_PCS_CFG_PCS_EN
;
1217 wr32(E1000_PCS_CFG0
, reg
);
1219 /* Power up the laser */
1220 reg
= rd32(E1000_CTRL_EXT
);
1221 reg
&= ~E1000_CTRL_EXT_SDP3_DATA
;
1222 wr32(E1000_CTRL_EXT
, reg
);
1224 /* flush the write to verify completion */
1230 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1231 * @hw: pointer to the HW structure
1232 * @speed: stores the current speed
1233 * @duplex: stores the current duplex
1235 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1236 * duplex, then store the values in the pointers provided.
1238 static s32
igb_get_pcs_speed_and_duplex_82575(struct e1000_hw
*hw
, u16
*speed
,
1241 struct e1000_mac_info
*mac
= &hw
->mac
;
1244 /* Set up defaults for the return values of this function */
1245 mac
->serdes_has_link
= false;
1249 /* Read the PCS Status register for link state. For non-copper mode,
1250 * the status register is not accurate. The PCS status register is
1253 pcs
= rd32(E1000_PCS_LSTAT
);
1255 /* The link up bit determines when link is up on autoneg. The sync ok
1256 * gets set once both sides sync up and agree upon link. Stable link
1257 * can be determined by checking for both link up and link sync ok
1259 if ((pcs
& E1000_PCS_LSTS_LINK_OK
) && (pcs
& E1000_PCS_LSTS_SYNK_OK
)) {
1260 mac
->serdes_has_link
= true;
1262 /* Detect and store PCS speed */
1263 if (pcs
& E1000_PCS_LSTS_SPEED_1000
) {
1264 *speed
= SPEED_1000
;
1265 } else if (pcs
& E1000_PCS_LSTS_SPEED_100
) {
1271 /* Detect and store PCS duplex */
1272 if (pcs
& E1000_PCS_LSTS_DUPLEX_FULL
) {
1273 *duplex
= FULL_DUPLEX
;
1275 *duplex
= HALF_DUPLEX
;
1283 * igb_shutdown_serdes_link_82575 - Remove link during power down
1284 * @hw: pointer to the HW structure
1286 * In the case of fiber serdes, shut down optics and PCS on driver unload
1287 * when management pass thru is not enabled.
1289 void igb_shutdown_serdes_link_82575(struct e1000_hw
*hw
)
1293 if (hw
->phy
.media_type
!= e1000_media_type_internal_serdes
&&
1294 igb_sgmii_active_82575(hw
))
1297 if (!igb_enable_mng_pass_thru(hw
)) {
1298 /* Disable PCS to turn off link */
1299 reg
= rd32(E1000_PCS_CFG0
);
1300 reg
&= ~E1000_PCS_CFG_PCS_EN
;
1301 wr32(E1000_PCS_CFG0
, reg
);
1303 /* shutdown the laser */
1304 reg
= rd32(E1000_CTRL_EXT
);
1305 reg
|= E1000_CTRL_EXT_SDP3_DATA
;
1306 wr32(E1000_CTRL_EXT
, reg
);
1308 /* flush the write to verify completion */
1315 * igb_reset_hw_82575 - Reset hardware
1316 * @hw: pointer to the HW structure
1318 * This resets the hardware into a known state. This is a
1319 * function pointer entry point called by the api module.
1321 static s32
igb_reset_hw_82575(struct e1000_hw
*hw
)
1326 /* Prevent the PCI-E bus from sticking if there is no TLP connection
1327 * on the last TLP read/write transaction when MAC is reset.
1329 ret_val
= igb_disable_pcie_master(hw
);
1331 hw_dbg("PCI-E Master disable polling has failed.\n");
1333 /* set the completion timeout for interface */
1334 ret_val
= igb_set_pcie_completion_timeout(hw
);
1336 hw_dbg("PCI-E Set completion timeout has failed.\n");
1339 hw_dbg("Masking off all interrupts\n");
1340 wr32(E1000_IMC
, 0xffffffff);
1342 wr32(E1000_RCTL
, 0);
1343 wr32(E1000_TCTL
, E1000_TCTL_PSP
);
1348 ctrl
= rd32(E1000_CTRL
);
1350 hw_dbg("Issuing a global reset to MAC\n");
1351 wr32(E1000_CTRL
, ctrl
| E1000_CTRL_RST
);
1353 ret_val
= igb_get_auto_rd_done(hw
);
1355 /* When auto config read does not complete, do not
1356 * return with an error. This can happen in situations
1357 * where there is no eeprom and prevents getting link.
1359 hw_dbg("Auto Read Done did not complete\n");
1362 /* If EEPROM is not present, run manual init scripts */
1363 if ((rd32(E1000_EECD
) & E1000_EECD_PRES
) == 0)
1364 igb_reset_init_script_82575(hw
);
1366 /* Clear any pending interrupt events. */
1367 wr32(E1000_IMC
, 0xffffffff);
1368 icr
= rd32(E1000_ICR
);
1370 /* Install any alternate MAC address into RAR0 */
1371 ret_val
= igb_check_alt_mac_addr(hw
);
1377 * igb_init_hw_82575 - Initialize hardware
1378 * @hw: pointer to the HW structure
1380 * This inits the hardware readying it for operation.
1382 static s32
igb_init_hw_82575(struct e1000_hw
*hw
)
1384 struct e1000_mac_info
*mac
= &hw
->mac
;
1386 u16 i
, rar_count
= mac
->rar_entry_count
;
1388 /* Initialize identification LED */
1389 ret_val
= igb_id_led_init(hw
);
1391 hw_dbg("Error initializing identification LED\n");
1392 /* This is not fatal and we should not stop init due to this */
1395 /* Disabling VLAN filtering */
1396 hw_dbg("Initializing the IEEE VLAN\n");
1397 if ((hw
->mac
.type
== e1000_i350
) || (hw
->mac
.type
== e1000_i354
))
1398 igb_clear_vfta_i350(hw
);
1402 /* Setup the receive address */
1403 igb_init_rx_addrs(hw
, rar_count
);
1405 /* Zero out the Multicast HASH table */
1406 hw_dbg("Zeroing the MTA\n");
1407 for (i
= 0; i
< mac
->mta_reg_count
; i
++)
1408 array_wr32(E1000_MTA
, i
, 0);
1410 /* Zero out the Unicast HASH table */
1411 hw_dbg("Zeroing the UTA\n");
1412 for (i
= 0; i
< mac
->uta_reg_count
; i
++)
1413 array_wr32(E1000_UTA
, i
, 0);
1415 /* Setup link and flow control */
1416 ret_val
= igb_setup_link(hw
);
1418 /* Clear all of the statistics registers (clear on read). It is
1419 * important that we do this after we have tried to establish link
1420 * because the symbol error count will increment wildly if there
1423 igb_clear_hw_cntrs_82575(hw
);
1428 * igb_setup_copper_link_82575 - Configure copper link settings
1429 * @hw: pointer to the HW structure
1431 * Configures the link for auto-neg or forced speed and duplex. Then we check
1432 * for link, once link is established calls to configure collision distance
1433 * and flow control are called.
1435 static s32
igb_setup_copper_link_82575(struct e1000_hw
*hw
)
1441 ctrl
= rd32(E1000_CTRL
);
1442 ctrl
|= E1000_CTRL_SLU
;
1443 ctrl
&= ~(E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
1444 wr32(E1000_CTRL
, ctrl
);
1446 /* Clear Go Link Disconnect bit */
1447 if (hw
->mac
.type
>= e1000_82580
) {
1448 phpm_reg
= rd32(E1000_82580_PHY_POWER_MGMT
);
1449 phpm_reg
&= ~E1000_82580_PM_GO_LINKD
;
1450 wr32(E1000_82580_PHY_POWER_MGMT
, phpm_reg
);
1453 ret_val
= igb_setup_serdes_link_82575(hw
);
1457 if (igb_sgmii_active_82575(hw
) && !hw
->phy
.reset_disable
) {
1458 /* allow time for SFP cage time to power up phy */
1461 ret_val
= hw
->phy
.ops
.reset(hw
);
1463 hw_dbg("Error resetting the PHY.\n");
1467 switch (hw
->phy
.type
) {
1468 case e1000_phy_i210
:
1470 switch (hw
->phy
.id
) {
1471 case I347AT4_E_PHY_ID
:
1472 case M88E1112_E_PHY_ID
:
1473 case M88E1545_E_PHY_ID
:
1475 ret_val
= igb_copper_link_setup_m88_gen2(hw
);
1478 ret_val
= igb_copper_link_setup_m88(hw
);
1482 case e1000_phy_igp_3
:
1483 ret_val
= igb_copper_link_setup_igp(hw
);
1485 case e1000_phy_82580
:
1486 ret_val
= igb_copper_link_setup_82580(hw
);
1489 ret_val
= -E1000_ERR_PHY
;
1496 ret_val
= igb_setup_copper_link(hw
);
1502 * igb_setup_serdes_link_82575 - Setup link for serdes
1503 * @hw: pointer to the HW structure
1505 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1506 * used on copper connections where the serialized gigabit media independent
1507 * interface (sgmii), or serdes fiber is being used. Configures the link
1508 * for auto-negotiation or forces speed/duplex.
1510 static s32
igb_setup_serdes_link_82575(struct e1000_hw
*hw
)
1512 u32 ctrl_ext
, ctrl_reg
, reg
, anadv_reg
;
1514 s32 ret_val
= E1000_SUCCESS
;
1517 if ((hw
->phy
.media_type
!= e1000_media_type_internal_serdes
) &&
1518 !igb_sgmii_active_82575(hw
))
1522 /* On the 82575, SerDes loopback mode persists until it is
1523 * explicitly turned off or a power cycle is performed. A read to
1524 * the register does not indicate its status. Therefore, we ensure
1525 * loopback mode is disabled during initialization.
1527 wr32(E1000_SCTL
, E1000_SCTL_DISABLE_SERDES_LOOPBACK
);
1529 /* power on the sfp cage if present and turn on I2C */
1530 ctrl_ext
= rd32(E1000_CTRL_EXT
);
1531 ctrl_ext
&= ~E1000_CTRL_EXT_SDP3_DATA
;
1532 ctrl_ext
|= E1000_CTRL_I2C_ENA
;
1533 wr32(E1000_CTRL_EXT
, ctrl_ext
);
1535 ctrl_reg
= rd32(E1000_CTRL
);
1536 ctrl_reg
|= E1000_CTRL_SLU
;
1538 if (hw
->mac
.type
== e1000_82575
|| hw
->mac
.type
== e1000_82576
) {
1539 /* set both sw defined pins */
1540 ctrl_reg
|= E1000_CTRL_SWDPIN0
| E1000_CTRL_SWDPIN1
;
1542 /* Set switch control to serdes energy detect */
1543 reg
= rd32(E1000_CONNSW
);
1544 reg
|= E1000_CONNSW_ENRGSRC
;
1545 wr32(E1000_CONNSW
, reg
);
1548 reg
= rd32(E1000_PCS_LCTL
);
1550 /* default pcs_autoneg to the same setting as mac autoneg */
1551 pcs_autoneg
= hw
->mac
.autoneg
;
1553 switch (ctrl_ext
& E1000_CTRL_EXT_LINK_MODE_MASK
) {
1554 case E1000_CTRL_EXT_LINK_MODE_SGMII
:
1555 /* sgmii mode lets the phy handle forcing speed/duplex */
1557 /* autoneg time out should be disabled for SGMII mode */
1558 reg
&= ~(E1000_PCS_LCTL_AN_TIMEOUT
);
1560 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX
:
1561 /* disable PCS autoneg and support parallel detect only */
1562 pcs_autoneg
= false;
1564 if (hw
->mac
.type
== e1000_82575
||
1565 hw
->mac
.type
== e1000_82576
) {
1566 ret_val
= hw
->nvm
.ops
.read(hw
, NVM_COMPAT
, 1, &data
);
1568 printk(KERN_DEBUG
"NVM Read Error\n\n");
1572 if (data
& E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT
)
1573 pcs_autoneg
= false;
1576 /* non-SGMII modes only supports a speed of 1000/Full for the
1577 * link so it is best to just force the MAC and let the pcs
1578 * link either autoneg or be forced to 1000/Full
1580 ctrl_reg
|= E1000_CTRL_SPD_1000
| E1000_CTRL_FRCSPD
|
1581 E1000_CTRL_FD
| E1000_CTRL_FRCDPX
;
1583 /* set speed of 1000/Full if speed/duplex is forced */
1584 reg
|= E1000_PCS_LCTL_FSV_1000
| E1000_PCS_LCTL_FDV_FULL
;
1588 wr32(E1000_CTRL
, ctrl_reg
);
1590 /* New SerDes mode allows for forcing speed or autonegotiating speed
1591 * at 1gb. Autoneg should be default set by most drivers. This is the
1592 * mode that will be compatible with older link partners and switches.
1593 * However, both are supported by the hardware and some drivers/tools.
1595 reg
&= ~(E1000_PCS_LCTL_AN_ENABLE
| E1000_PCS_LCTL_FLV_LINK_UP
|
1596 E1000_PCS_LCTL_FSD
| E1000_PCS_LCTL_FORCE_LINK
);
1599 /* Set PCS register for autoneg */
1600 reg
|= E1000_PCS_LCTL_AN_ENABLE
| /* Enable Autoneg */
1601 E1000_PCS_LCTL_AN_RESTART
; /* Restart autoneg */
1603 /* Disable force flow control for autoneg */
1604 reg
&= ~E1000_PCS_LCTL_FORCE_FCTRL
;
1606 /* Configure flow control advertisement for autoneg */
1607 anadv_reg
= rd32(E1000_PCS_ANADV
);
1608 anadv_reg
&= ~(E1000_TXCW_ASM_DIR
| E1000_TXCW_PAUSE
);
1609 switch (hw
->fc
.requested_mode
) {
1611 case e1000_fc_rx_pause
:
1612 anadv_reg
|= E1000_TXCW_ASM_DIR
;
1613 anadv_reg
|= E1000_TXCW_PAUSE
;
1615 case e1000_fc_tx_pause
:
1616 anadv_reg
|= E1000_TXCW_ASM_DIR
;
1621 wr32(E1000_PCS_ANADV
, anadv_reg
);
1623 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg
);
1625 /* Set PCS register for forced link */
1626 reg
|= E1000_PCS_LCTL_FSD
; /* Force Speed */
1628 /* Force flow control for forced link */
1629 reg
|= E1000_PCS_LCTL_FORCE_FCTRL
;
1631 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg
);
1634 wr32(E1000_PCS_LCTL
, reg
);
1636 if (!pcs_autoneg
&& !igb_sgmii_active_82575(hw
))
1637 igb_force_mac_fc(hw
);
1643 * igb_sgmii_active_82575 - Return sgmii state
1644 * @hw: pointer to the HW structure
1646 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1647 * which can be enabled for use in the embedded applications. Simply
1648 * return the current state of the sgmii interface.
1650 static bool igb_sgmii_active_82575(struct e1000_hw
*hw
)
1652 struct e1000_dev_spec_82575
*dev_spec
= &hw
->dev_spec
._82575
;
1653 return dev_spec
->sgmii_active
;
1657 * igb_reset_init_script_82575 - Inits HW defaults after reset
1658 * @hw: pointer to the HW structure
1660 * Inits recommended HW defaults after a reset when there is no EEPROM
1661 * detected. This is only for the 82575.
1663 static s32
igb_reset_init_script_82575(struct e1000_hw
*hw
)
1665 if (hw
->mac
.type
== e1000_82575
) {
1666 hw_dbg("Running reset init script for 82575\n");
1667 /* SerDes configuration via SERDESCTRL */
1668 igb_write_8bit_ctrl_reg(hw
, E1000_SCTL
, 0x00, 0x0C);
1669 igb_write_8bit_ctrl_reg(hw
, E1000_SCTL
, 0x01, 0x78);
1670 igb_write_8bit_ctrl_reg(hw
, E1000_SCTL
, 0x1B, 0x23);
1671 igb_write_8bit_ctrl_reg(hw
, E1000_SCTL
, 0x23, 0x15);
1673 /* CCM configuration via CCMCTL register */
1674 igb_write_8bit_ctrl_reg(hw
, E1000_CCMCTL
, 0x14, 0x00);
1675 igb_write_8bit_ctrl_reg(hw
, E1000_CCMCTL
, 0x10, 0x00);
1677 /* PCIe lanes configuration */
1678 igb_write_8bit_ctrl_reg(hw
, E1000_GIOCTL
, 0x00, 0xEC);
1679 igb_write_8bit_ctrl_reg(hw
, E1000_GIOCTL
, 0x61, 0xDF);
1680 igb_write_8bit_ctrl_reg(hw
, E1000_GIOCTL
, 0x34, 0x05);
1681 igb_write_8bit_ctrl_reg(hw
, E1000_GIOCTL
, 0x2F, 0x81);
1683 /* PCIe PLL Configuration */
1684 igb_write_8bit_ctrl_reg(hw
, E1000_SCCTL
, 0x02, 0x47);
1685 igb_write_8bit_ctrl_reg(hw
, E1000_SCCTL
, 0x14, 0x00);
1686 igb_write_8bit_ctrl_reg(hw
, E1000_SCCTL
, 0x10, 0x00);
1693 * igb_read_mac_addr_82575 - Read device MAC address
1694 * @hw: pointer to the HW structure
1696 static s32
igb_read_mac_addr_82575(struct e1000_hw
*hw
)
1700 /* If there's an alternate MAC address place it in RAR0
1701 * so that it will override the Si installed default perm
1704 ret_val
= igb_check_alt_mac_addr(hw
);
1708 ret_val
= igb_read_mac_addr(hw
);
1715 * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1716 * @hw: pointer to the HW structure
1718 * In the case of a PHY power down to save power, or to turn off link during a
1719 * driver unload, or wake on lan is not enabled, remove the link.
1721 void igb_power_down_phy_copper_82575(struct e1000_hw
*hw
)
1723 /* If the management interface is not enabled, then power down */
1724 if (!(igb_enable_mng_pass_thru(hw
) || igb_check_reset_block(hw
)))
1725 igb_power_down_phy_copper(hw
);
1729 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
1730 * @hw: pointer to the HW structure
1732 * Clears the hardware counters by reading the counter registers.
1734 static void igb_clear_hw_cntrs_82575(struct e1000_hw
*hw
)
1736 igb_clear_hw_cntrs_base(hw
);
1742 rd32(E1000_PRC1023
);
1743 rd32(E1000_PRC1522
);
1748 rd32(E1000_PTC1023
);
1749 rd32(E1000_PTC1522
);
1751 rd32(E1000_ALGNERRC
);
1754 rd32(E1000_CEXTERR
);
1765 rd32(E1000_ICRXPTC
);
1766 rd32(E1000_ICRXATC
);
1767 rd32(E1000_ICTXPTC
);
1768 rd32(E1000_ICTXATC
);
1769 rd32(E1000_ICTXQEC
);
1770 rd32(E1000_ICTXQMTC
);
1771 rd32(E1000_ICRXDMTC
);
1778 rd32(E1000_HTCBDPC
);
1783 rd32(E1000_LENERRS
);
1785 /* This register should not be read in copper configurations */
1786 if (hw
->phy
.media_type
== e1000_media_type_internal_serdes
||
1787 igb_sgmii_active_82575(hw
))
1792 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1793 * @hw: pointer to the HW structure
1795 * After rx enable if managability is enabled then there is likely some
1796 * bad data at the start of the fifo and possibly in the DMA fifo. This
1797 * function clears the fifos and flushes any packets that came in as rx was
1800 void igb_rx_fifo_flush_82575(struct e1000_hw
*hw
)
1802 u32 rctl
, rlpml
, rxdctl
[4], rfctl
, temp_rctl
, rx_enabled
;
1805 if (hw
->mac
.type
!= e1000_82575
||
1806 !(rd32(E1000_MANC
) & E1000_MANC_RCV_TCO_EN
))
1809 /* Disable all RX queues */
1810 for (i
= 0; i
< 4; i
++) {
1811 rxdctl
[i
] = rd32(E1000_RXDCTL(i
));
1812 wr32(E1000_RXDCTL(i
),
1813 rxdctl
[i
] & ~E1000_RXDCTL_QUEUE_ENABLE
);
1815 /* Poll all queues to verify they have shut down */
1816 for (ms_wait
= 0; ms_wait
< 10; ms_wait
++) {
1819 for (i
= 0; i
< 4; i
++)
1820 rx_enabled
|= rd32(E1000_RXDCTL(i
));
1821 if (!(rx_enabled
& E1000_RXDCTL_QUEUE_ENABLE
))
1826 hw_dbg("Queue disable timed out after 10ms\n");
1828 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1829 * incoming packets are rejected. Set enable and wait 2ms so that
1830 * any packet that was coming in as RCTL.EN was set is flushed
1832 rfctl
= rd32(E1000_RFCTL
);
1833 wr32(E1000_RFCTL
, rfctl
& ~E1000_RFCTL_LEF
);
1835 rlpml
= rd32(E1000_RLPML
);
1836 wr32(E1000_RLPML
, 0);
1838 rctl
= rd32(E1000_RCTL
);
1839 temp_rctl
= rctl
& ~(E1000_RCTL_EN
| E1000_RCTL_SBP
);
1840 temp_rctl
|= E1000_RCTL_LPE
;
1842 wr32(E1000_RCTL
, temp_rctl
);
1843 wr32(E1000_RCTL
, temp_rctl
| E1000_RCTL_EN
);
1847 /* Enable RX queues that were previously enabled and restore our
1850 for (i
= 0; i
< 4; i
++)
1851 wr32(E1000_RXDCTL(i
), rxdctl
[i
]);
1852 wr32(E1000_RCTL
, rctl
);
1855 wr32(E1000_RLPML
, rlpml
);
1856 wr32(E1000_RFCTL
, rfctl
);
1858 /* Flush receive errors generated by workaround */
1865 * igb_set_pcie_completion_timeout - set pci-e completion timeout
1866 * @hw: pointer to the HW structure
1868 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1869 * however the hardware default for these parts is 500us to 1ms which is less
1870 * than the 10ms recommended by the pci-e spec. To address this we need to
1871 * increase the value to either 10ms to 200ms for capability version 1 config,
1872 * or 16ms to 55ms for version 2.
1874 static s32
igb_set_pcie_completion_timeout(struct e1000_hw
*hw
)
1876 u32 gcr
= rd32(E1000_GCR
);
1880 /* only take action if timeout value is defaulted to 0 */
1881 if (gcr
& E1000_GCR_CMPL_TMOUT_MASK
)
1884 /* if capabilities version is type 1 we can write the
1885 * timeout of 10ms to 200ms through the GCR register
1887 if (!(gcr
& E1000_GCR_CAP_VER2
)) {
1888 gcr
|= E1000_GCR_CMPL_TMOUT_10ms
;
1892 /* for version 2 capabilities we need to write the config space
1893 * directly in order to set the completion timeout value for
1896 ret_val
= igb_read_pcie_cap_reg(hw
, PCIE_DEVICE_CONTROL2
,
1901 pcie_devctl2
|= PCIE_DEVICE_CONTROL2_16ms
;
1903 ret_val
= igb_write_pcie_cap_reg(hw
, PCIE_DEVICE_CONTROL2
,
1906 /* disable completion timeout resend */
1907 gcr
&= ~E1000_GCR_CMPL_TMOUT_RESEND
;
1909 wr32(E1000_GCR
, gcr
);
1914 * igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
1915 * @hw: pointer to the hardware struct
1916 * @enable: state to enter, either enabled or disabled
1917 * @pf: Physical Function pool - do not set anti-spoofing for the PF
1919 * enables/disables L2 switch anti-spoofing functionality.
1921 void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw
*hw
, bool enable
, int pf
)
1923 u32 reg_val
, reg_offset
;
1925 switch (hw
->mac
.type
) {
1927 reg_offset
= E1000_DTXSWC
;
1931 reg_offset
= E1000_TXSWC
;
1937 reg_val
= rd32(reg_offset
);
1939 reg_val
|= (E1000_DTXSWC_MAC_SPOOF_MASK
|
1940 E1000_DTXSWC_VLAN_SPOOF_MASK
);
1941 /* The PF can spoof - it has to in order to
1942 * support emulation mode NICs
1944 reg_val
^= (1 << pf
| 1 << (pf
+ MAX_NUM_VFS
));
1946 reg_val
&= ~(E1000_DTXSWC_MAC_SPOOF_MASK
|
1947 E1000_DTXSWC_VLAN_SPOOF_MASK
);
1949 wr32(reg_offset
, reg_val
);
1953 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
1954 * @hw: pointer to the hardware struct
1955 * @enable: state to enter, either enabled or disabled
1957 * enables/disables L2 switch loopback functionality.
1959 void igb_vmdq_set_loopback_pf(struct e1000_hw
*hw
, bool enable
)
1963 switch (hw
->mac
.type
) {
1965 dtxswc
= rd32(E1000_DTXSWC
);
1967 dtxswc
|= E1000_DTXSWC_VMDQ_LOOPBACK_EN
;
1969 dtxswc
&= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN
;
1970 wr32(E1000_DTXSWC
, dtxswc
);
1974 dtxswc
= rd32(E1000_TXSWC
);
1976 dtxswc
|= E1000_DTXSWC_VMDQ_LOOPBACK_EN
;
1978 dtxswc
&= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN
;
1979 wr32(E1000_TXSWC
, dtxswc
);
1982 /* Currently no other hardware supports loopback */
1989 * igb_vmdq_set_replication_pf - enable or disable vmdq replication
1990 * @hw: pointer to the hardware struct
1991 * @enable: state to enter, either enabled or disabled
1993 * enables/disables replication of packets across multiple pools.
1995 void igb_vmdq_set_replication_pf(struct e1000_hw
*hw
, bool enable
)
1997 u32 vt_ctl
= rd32(E1000_VT_CTL
);
2000 vt_ctl
|= E1000_VT_CTL_VM_REPL_EN
;
2002 vt_ctl
&= ~E1000_VT_CTL_VM_REPL_EN
;
2004 wr32(E1000_VT_CTL
, vt_ctl
);
2008 * igb_read_phy_reg_82580 - Read 82580 MDI control register
2009 * @hw: pointer to the HW structure
2010 * @offset: register offset to be read
2011 * @data: pointer to the read data
2013 * Reads the MDI control register in the PHY at offset and stores the
2014 * information read to data.
2016 static s32
igb_read_phy_reg_82580(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
2020 ret_val
= hw
->phy
.ops
.acquire(hw
);
2024 ret_val
= igb_read_phy_reg_mdic(hw
, offset
, data
);
2026 hw
->phy
.ops
.release(hw
);
2033 * igb_write_phy_reg_82580 - Write 82580 MDI control register
2034 * @hw: pointer to the HW structure
2035 * @offset: register offset to write to
2036 * @data: data to write to register at offset
2038 * Writes data to MDI control register in the PHY at offset.
2040 static s32
igb_write_phy_reg_82580(struct e1000_hw
*hw
, u32 offset
, u16 data
)
2045 ret_val
= hw
->phy
.ops
.acquire(hw
);
2049 ret_val
= igb_write_phy_reg_mdic(hw
, offset
, data
);
2051 hw
->phy
.ops
.release(hw
);
2058 * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2059 * @hw: pointer to the HW structure
2061 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2062 * the values found in the EEPROM. This addresses an issue in which these
2063 * bits are not restored from EEPROM after reset.
2065 static s32
igb_reset_mdicnfg_82580(struct e1000_hw
*hw
)
2071 if (hw
->mac
.type
!= e1000_82580
)
2073 if (!igb_sgmii_active_82575(hw
))
2076 ret_val
= hw
->nvm
.ops
.read(hw
, NVM_INIT_CONTROL3_PORT_A
+
2077 NVM_82580_LAN_FUNC_OFFSET(hw
->bus
.func
), 1,
2080 hw_dbg("NVM Read Error\n");
2084 mdicnfg
= rd32(E1000_MDICNFG
);
2085 if (nvm_data
& NVM_WORD24_EXT_MDIO
)
2086 mdicnfg
|= E1000_MDICNFG_EXT_MDIO
;
2087 if (nvm_data
& NVM_WORD24_COM_MDIO
)
2088 mdicnfg
|= E1000_MDICNFG_COM_MDIO
;
2089 wr32(E1000_MDICNFG
, mdicnfg
);
2095 * igb_reset_hw_82580 - Reset hardware
2096 * @hw: pointer to the HW structure
2098 * This resets function or entire device (all ports, etc.)
2101 static s32
igb_reset_hw_82580(struct e1000_hw
*hw
)
2104 /* BH SW mailbox bit in SW_FW_SYNC */
2105 u16 swmbsw_mask
= E1000_SW_SYNCH_MB
;
2107 bool global_device_reset
= hw
->dev_spec
._82575
.global_device_reset
;
2110 hw
->dev_spec
._82575
.global_device_reset
= false;
2112 /* due to hw errata, global device reset doesn't always
2115 if (hw
->mac
.type
== e1000_82580
)
2116 global_device_reset
= false;
2118 /* Get current control state. */
2119 ctrl
= rd32(E1000_CTRL
);
2121 /* Prevent the PCI-E bus from sticking if there is no TLP connection
2122 * on the last TLP read/write transaction when MAC is reset.
2124 ret_val
= igb_disable_pcie_master(hw
);
2126 hw_dbg("PCI-E Master disable polling has failed.\n");
2128 hw_dbg("Masking off all interrupts\n");
2129 wr32(E1000_IMC
, 0xffffffff);
2130 wr32(E1000_RCTL
, 0);
2131 wr32(E1000_TCTL
, E1000_TCTL_PSP
);
2136 /* Determine whether or not a global dev reset is requested */
2137 if (global_device_reset
&&
2138 hw
->mac
.ops
.acquire_swfw_sync(hw
, swmbsw_mask
))
2139 global_device_reset
= false;
2141 if (global_device_reset
&&
2142 !(rd32(E1000_STATUS
) & E1000_STAT_DEV_RST_SET
))
2143 ctrl
|= E1000_CTRL_DEV_RST
;
2145 ctrl
|= E1000_CTRL_RST
;
2147 wr32(E1000_CTRL
, ctrl
);
2150 /* Add delay to insure DEV_RST has time to complete */
2151 if (global_device_reset
)
2154 ret_val
= igb_get_auto_rd_done(hw
);
2156 /* When auto config read does not complete, do not
2157 * return with an error. This can happen in situations
2158 * where there is no eeprom and prevents getting link.
2160 hw_dbg("Auto Read Done did not complete\n");
2163 /* clear global device reset status bit */
2164 wr32(E1000_STATUS
, E1000_STAT_DEV_RST_SET
);
2166 /* Clear any pending interrupt events. */
2167 wr32(E1000_IMC
, 0xffffffff);
2168 icr
= rd32(E1000_ICR
);
2170 ret_val
= igb_reset_mdicnfg_82580(hw
);
2172 hw_dbg("Could not reset MDICNFG based on EEPROM\n");
2174 /* Install any alternate MAC address into RAR0 */
2175 ret_val
= igb_check_alt_mac_addr(hw
);
2177 /* Release semaphore */
2178 if (global_device_reset
)
2179 hw
->mac
.ops
.release_swfw_sync(hw
, swmbsw_mask
);
2185 * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
2186 * @data: data received by reading RXPBS register
2188 * The 82580 uses a table based approach for packet buffer allocation sizes.
2189 * This function converts the retrieved value into the correct table value
2190 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2191 * 0x0 36 72 144 1 2 4 8 16
2192 * 0x8 35 70 140 rsv rsv rsv rsv rsv
2194 u16
igb_rxpbs_adjust_82580(u32 data
)
2198 if (data
< E1000_82580_RXPBS_TABLE_SIZE
)
2199 ret_val
= e1000_82580_rxpbs_table
[data
];
2205 * igb_validate_nvm_checksum_with_offset - Validate EEPROM
2207 * @hw: pointer to the HW structure
2208 * @offset: offset in words of the checksum protected region
2210 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2211 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2213 static s32
igb_validate_nvm_checksum_with_offset(struct e1000_hw
*hw
,
2220 for (i
= offset
; i
< ((NVM_CHECKSUM_REG
+ offset
) + 1); i
++) {
2221 ret_val
= hw
->nvm
.ops
.read(hw
, i
, 1, &nvm_data
);
2223 hw_dbg("NVM Read Error\n");
2226 checksum
+= nvm_data
;
2229 if (checksum
!= (u16
) NVM_SUM
) {
2230 hw_dbg("NVM Checksum Invalid\n");
2231 ret_val
= -E1000_ERR_NVM
;
2240 * igb_update_nvm_checksum_with_offset - Update EEPROM
2242 * @hw: pointer to the HW structure
2243 * @offset: offset in words of the checksum protected region
2245 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2246 * up to the checksum. Then calculates the EEPROM checksum and writes the
2247 * value to the EEPROM.
2249 static s32
igb_update_nvm_checksum_with_offset(struct e1000_hw
*hw
, u16 offset
)
2255 for (i
= offset
; i
< (NVM_CHECKSUM_REG
+ offset
); i
++) {
2256 ret_val
= hw
->nvm
.ops
.read(hw
, i
, 1, &nvm_data
);
2258 hw_dbg("NVM Read Error while updating checksum.\n");
2261 checksum
+= nvm_data
;
2263 checksum
= (u16
) NVM_SUM
- checksum
;
2264 ret_val
= hw
->nvm
.ops
.write(hw
, (NVM_CHECKSUM_REG
+ offset
), 1,
2267 hw_dbg("NVM Write Error while updating checksum.\n");
2274 * igb_validate_nvm_checksum_82580 - Validate EEPROM checksum
2275 * @hw: pointer to the HW structure
2277 * Calculates the EEPROM section checksum by reading/adding each word of
2278 * the EEPROM and then verifies that the sum of the EEPROM is
2281 static s32
igb_validate_nvm_checksum_82580(struct e1000_hw
*hw
)
2284 u16 eeprom_regions_count
= 1;
2288 ret_val
= hw
->nvm
.ops
.read(hw
, NVM_COMPATIBILITY_REG_3
, 1, &nvm_data
);
2290 hw_dbg("NVM Read Error\n");
2294 if (nvm_data
& NVM_COMPATIBILITY_BIT_MASK
) {
2295 /* if checksums compatibility bit is set validate checksums
2298 eeprom_regions_count
= 4;
2301 for (j
= 0; j
< eeprom_regions_count
; j
++) {
2302 nvm_offset
= NVM_82580_LAN_FUNC_OFFSET(j
);
2303 ret_val
= igb_validate_nvm_checksum_with_offset(hw
,
2314 * igb_update_nvm_checksum_82580 - Update EEPROM checksum
2315 * @hw: pointer to the HW structure
2317 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2318 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2319 * checksum and writes the value to the EEPROM.
2321 static s32
igb_update_nvm_checksum_82580(struct e1000_hw
*hw
)
2327 ret_val
= hw
->nvm
.ops
.read(hw
, NVM_COMPATIBILITY_REG_3
, 1, &nvm_data
);
2329 hw_dbg("NVM Read Error while updating checksum"
2330 " compatibility bit.\n");
2334 if ((nvm_data
& NVM_COMPATIBILITY_BIT_MASK
) == 0) {
2335 /* set compatibility bit to validate checksums appropriately */
2336 nvm_data
= nvm_data
| NVM_COMPATIBILITY_BIT_MASK
;
2337 ret_val
= hw
->nvm
.ops
.write(hw
, NVM_COMPATIBILITY_REG_3
, 1,
2340 hw_dbg("NVM Write Error while updating checksum"
2341 " compatibility bit.\n");
2346 for (j
= 0; j
< 4; j
++) {
2347 nvm_offset
= NVM_82580_LAN_FUNC_OFFSET(j
);
2348 ret_val
= igb_update_nvm_checksum_with_offset(hw
, nvm_offset
);
2358 * igb_validate_nvm_checksum_i350 - Validate EEPROM checksum
2359 * @hw: pointer to the HW structure
2361 * Calculates the EEPROM section checksum by reading/adding each word of
2362 * the EEPROM and then verifies that the sum of the EEPROM is
2365 static s32
igb_validate_nvm_checksum_i350(struct e1000_hw
*hw
)
2371 for (j
= 0; j
< 4; j
++) {
2372 nvm_offset
= NVM_82580_LAN_FUNC_OFFSET(j
);
2373 ret_val
= igb_validate_nvm_checksum_with_offset(hw
,
2384 * igb_update_nvm_checksum_i350 - Update EEPROM checksum
2385 * @hw: pointer to the HW structure
2387 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2388 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2389 * checksum and writes the value to the EEPROM.
2391 static s32
igb_update_nvm_checksum_i350(struct e1000_hw
*hw
)
2397 for (j
= 0; j
< 4; j
++) {
2398 nvm_offset
= NVM_82580_LAN_FUNC_OFFSET(j
);
2399 ret_val
= igb_update_nvm_checksum_with_offset(hw
, nvm_offset
);
2409 * __igb_access_emi_reg - Read/write EMI register
2410 * @hw: pointer to the HW structure
2411 * @addr: EMI address to program
2412 * @data: pointer to value to read/write from/to the EMI address
2413 * @read: boolean flag to indicate read or write
2415 static s32
__igb_access_emi_reg(struct e1000_hw
*hw
, u16 address
,
2416 u16
*data
, bool read
)
2418 s32 ret_val
= E1000_SUCCESS
;
2420 ret_val
= hw
->phy
.ops
.write_reg(hw
, E1000_EMIADD
, address
);
2425 ret_val
= hw
->phy
.ops
.read_reg(hw
, E1000_EMIDATA
, data
);
2427 ret_val
= hw
->phy
.ops
.write_reg(hw
, E1000_EMIDATA
, *data
);
2433 * igb_read_emi_reg - Read Extended Management Interface register
2434 * @hw: pointer to the HW structure
2435 * @addr: EMI address to program
2436 * @data: value to be read from the EMI address
2438 s32
igb_read_emi_reg(struct e1000_hw
*hw
, u16 addr
, u16
*data
)
2440 return __igb_access_emi_reg(hw
, addr
, data
, true);
2444 * igb_set_eee_i350 - Enable/disable EEE support
2445 * @hw: pointer to the HW structure
2447 * Enable/disable EEE based on setting in dev_spec structure.
2450 s32
igb_set_eee_i350(struct e1000_hw
*hw
)
2455 if ((hw
->mac
.type
< e1000_i350
) ||
2456 (hw
->phy
.media_type
!= e1000_media_type_copper
))
2458 ipcnfg
= rd32(E1000_IPCNFG
);
2459 eeer
= rd32(E1000_EEER
);
2461 /* enable or disable per user setting */
2462 if (!(hw
->dev_spec
._82575
.eee_disable
)) {
2463 u32 eee_su
= rd32(E1000_EEE_SU
);
2465 ipcnfg
|= (E1000_IPCNFG_EEE_1G_AN
| E1000_IPCNFG_EEE_100M_AN
);
2466 eeer
|= (E1000_EEER_TX_LPI_EN
| E1000_EEER_RX_LPI_EN
|
2469 /* This bit should not be set in normal operation. */
2470 if (eee_su
& E1000_EEE_SU_LPI_CLK_STP
)
2471 hw_dbg("LPI Clock Stop Bit should not be set!\n");
2474 ipcnfg
&= ~(E1000_IPCNFG_EEE_1G_AN
|
2475 E1000_IPCNFG_EEE_100M_AN
);
2476 eeer
&= ~(E1000_EEER_TX_LPI_EN
|
2477 E1000_EEER_RX_LPI_EN
|
2480 wr32(E1000_IPCNFG
, ipcnfg
);
2481 wr32(E1000_EEER
, eeer
);
2490 * igb_set_eee_i354 - Enable/disable EEE support
2491 * @hw: pointer to the HW structure
2493 * Enable/disable EEE legacy mode based on setting in dev_spec structure.
2496 s32
igb_set_eee_i354(struct e1000_hw
*hw
)
2498 struct e1000_phy_info
*phy
= &hw
->phy
;
2502 if ((hw
->phy
.media_type
!= e1000_media_type_copper
) ||
2503 (phy
->id
!= M88E1545_E_PHY_ID
))
2506 if (!hw
->dev_spec
._82575
.eee_disable
) {
2507 /* Switch to PHY page 18. */
2508 ret_val
= phy
->ops
.write_reg(hw
, E1000_M88E1545_PAGE_ADDR
, 18);
2512 ret_val
= phy
->ops
.read_reg(hw
, E1000_M88E1545_EEE_CTRL_1
,
2517 phy_data
|= E1000_M88E1545_EEE_CTRL_1_MS
;
2518 ret_val
= phy
->ops
.write_reg(hw
, E1000_M88E1545_EEE_CTRL_1
,
2523 /* Return the PHY to page 0. */
2524 ret_val
= phy
->ops
.write_reg(hw
, E1000_M88E1545_PAGE_ADDR
, 0);
2528 /* Turn on EEE advertisement. */
2529 ret_val
= igb_read_xmdio_reg(hw
, E1000_EEE_ADV_ADDR_I354
,
2530 E1000_EEE_ADV_DEV_I354
,
2535 phy_data
|= E1000_EEE_ADV_100_SUPPORTED
|
2536 E1000_EEE_ADV_1000_SUPPORTED
;
2537 ret_val
= igb_write_xmdio_reg(hw
, E1000_EEE_ADV_ADDR_I354
,
2538 E1000_EEE_ADV_DEV_I354
,
2541 /* Turn off EEE advertisement. */
2542 ret_val
= igb_read_xmdio_reg(hw
, E1000_EEE_ADV_ADDR_I354
,
2543 E1000_EEE_ADV_DEV_I354
,
2548 phy_data
&= ~(E1000_EEE_ADV_100_SUPPORTED
|
2549 E1000_EEE_ADV_1000_SUPPORTED
);
2550 ret_val
= igb_write_xmdio_reg(hw
, E1000_EEE_ADV_ADDR_I354
,
2551 E1000_EEE_ADV_DEV_I354
,
2560 * igb_get_eee_status_i354 - Get EEE status
2561 * @hw: pointer to the HW structure
2562 * @status: EEE status
2564 * Get EEE status by guessing based on whether Tx or Rx LPI indications have
2567 s32
igb_get_eee_status_i354(struct e1000_hw
*hw
, bool *status
)
2569 struct e1000_phy_info
*phy
= &hw
->phy
;
2573 /* Check if EEE is supported on this device. */
2574 if ((hw
->phy
.media_type
!= e1000_media_type_copper
) ||
2575 (phy
->id
!= M88E1545_E_PHY_ID
))
2578 ret_val
= igb_read_xmdio_reg(hw
, E1000_PCS_STATUS_ADDR_I354
,
2579 E1000_PCS_STATUS_DEV_I354
,
2584 *status
= phy_data
& (E1000_PCS_STATUS_TX_LPI_RCVD
|
2585 E1000_PCS_STATUS_RX_LPI_RCVD
) ? true : false;
2591 static const u8 e1000_emc_temp_data
[4] = {
2592 E1000_EMC_INTERNAL_DATA
,
2593 E1000_EMC_DIODE1_DATA
,
2594 E1000_EMC_DIODE2_DATA
,
2595 E1000_EMC_DIODE3_DATA
2597 static const u8 e1000_emc_therm_limit
[4] = {
2598 E1000_EMC_INTERNAL_THERM_LIMIT
,
2599 E1000_EMC_DIODE1_THERM_LIMIT
,
2600 E1000_EMC_DIODE2_THERM_LIMIT
,
2601 E1000_EMC_DIODE3_THERM_LIMIT
2605 * igb_get_thermal_sensor_data_generic - Gathers thermal sensor data
2606 * @hw: pointer to hardware structure
2608 * Updates the temperatures in mac.thermal_sensor_data
2610 s32
igb_get_thermal_sensor_data_generic(struct e1000_hw
*hw
)
2612 s32 status
= E1000_SUCCESS
;
2620 struct e1000_thermal_sensor_data
*data
= &hw
->mac
.thermal_sensor_data
;
2622 if ((hw
->mac
.type
!= e1000_i350
) || (hw
->bus
.func
!= 0))
2623 return E1000_NOT_IMPLEMENTED
;
2625 data
->sensor
[0].temp
= (rd32(E1000_THMJT
) & 0xFF);
2627 /* Return the internal sensor only if ETS is unsupported */
2628 hw
->nvm
.ops
.read(hw
, NVM_ETS_CFG
, 1, &ets_offset
);
2629 if ((ets_offset
== 0x0000) || (ets_offset
== 0xFFFF))
2632 hw
->nvm
.ops
.read(hw
, ets_offset
, 1, &ets_cfg
);
2633 if (((ets_cfg
& NVM_ETS_TYPE_MASK
) >> NVM_ETS_TYPE_SHIFT
)
2634 != NVM_ETS_TYPE_EMC
)
2635 return E1000_NOT_IMPLEMENTED
;
2637 num_sensors
= (ets_cfg
& NVM_ETS_NUM_SENSORS_MASK
);
2638 if (num_sensors
> E1000_MAX_SENSORS
)
2639 num_sensors
= E1000_MAX_SENSORS
;
2641 for (i
= 1; i
< num_sensors
; i
++) {
2642 hw
->nvm
.ops
.read(hw
, (ets_offset
+ i
), 1, &ets_sensor
);
2643 sensor_index
= ((ets_sensor
& NVM_ETS_DATA_INDEX_MASK
) >>
2644 NVM_ETS_DATA_INDEX_SHIFT
);
2645 sensor_location
= ((ets_sensor
& NVM_ETS_DATA_LOC_MASK
) >>
2646 NVM_ETS_DATA_LOC_SHIFT
);
2648 if (sensor_location
!= 0)
2649 hw
->phy
.ops
.read_i2c_byte(hw
,
2650 e1000_emc_temp_data
[sensor_index
],
2651 E1000_I2C_THERMAL_SENSOR_ADDR
,
2652 &data
->sensor
[i
].temp
);
2658 * igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds
2659 * @hw: pointer to hardware structure
2661 * Sets the thermal sensor thresholds according to the NVM map
2662 * and save off the threshold and location values into mac.thermal_sensor_data
2664 s32
igb_init_thermal_sensor_thresh_generic(struct e1000_hw
*hw
)
2666 s32 status
= E1000_SUCCESS
;
2670 u8 low_thresh_delta
;
2676 struct e1000_thermal_sensor_data
*data
= &hw
->mac
.thermal_sensor_data
;
2678 if ((hw
->mac
.type
!= e1000_i350
) || (hw
->bus
.func
!= 0))
2679 return E1000_NOT_IMPLEMENTED
;
2681 memset(data
, 0, sizeof(struct e1000_thermal_sensor_data
));
2683 data
->sensor
[0].location
= 0x1;
2684 data
->sensor
[0].caution_thresh
=
2685 (rd32(E1000_THHIGHTC
) & 0xFF);
2686 data
->sensor
[0].max_op_thresh
=
2687 (rd32(E1000_THLOWTC
) & 0xFF);
2689 /* Return the internal sensor only if ETS is unsupported */
2690 hw
->nvm
.ops
.read(hw
, NVM_ETS_CFG
, 1, &ets_offset
);
2691 if ((ets_offset
== 0x0000) || (ets_offset
== 0xFFFF))
2694 hw
->nvm
.ops
.read(hw
, ets_offset
, 1, &ets_cfg
);
2695 if (((ets_cfg
& NVM_ETS_TYPE_MASK
) >> NVM_ETS_TYPE_SHIFT
)
2696 != NVM_ETS_TYPE_EMC
)
2697 return E1000_NOT_IMPLEMENTED
;
2699 low_thresh_delta
= ((ets_cfg
& NVM_ETS_LTHRES_DELTA_MASK
) >>
2700 NVM_ETS_LTHRES_DELTA_SHIFT
);
2701 num_sensors
= (ets_cfg
& NVM_ETS_NUM_SENSORS_MASK
);
2703 for (i
= 1; i
<= num_sensors
; i
++) {
2704 hw
->nvm
.ops
.read(hw
, (ets_offset
+ i
), 1, &ets_sensor
);
2705 sensor_index
= ((ets_sensor
& NVM_ETS_DATA_INDEX_MASK
) >>
2706 NVM_ETS_DATA_INDEX_SHIFT
);
2707 sensor_location
= ((ets_sensor
& NVM_ETS_DATA_LOC_MASK
) >>
2708 NVM_ETS_DATA_LOC_SHIFT
);
2709 therm_limit
= ets_sensor
& NVM_ETS_DATA_HTHRESH_MASK
;
2711 hw
->phy
.ops
.write_i2c_byte(hw
,
2712 e1000_emc_therm_limit
[sensor_index
],
2713 E1000_I2C_THERMAL_SENSOR_ADDR
,
2716 if ((i
< E1000_MAX_SENSORS
) && (sensor_location
!= 0)) {
2717 data
->sensor
[i
].location
= sensor_location
;
2718 data
->sensor
[i
].caution_thresh
= therm_limit
;
2719 data
->sensor
[i
].max_op_thresh
= therm_limit
-
2726 static struct e1000_mac_operations e1000_mac_ops_82575
= {
2727 .init_hw
= igb_init_hw_82575
,
2728 .check_for_link
= igb_check_for_link_82575
,
2729 .rar_set
= igb_rar_set
,
2730 .read_mac_addr
= igb_read_mac_addr_82575
,
2731 .get_speed_and_duplex
= igb_get_speed_and_duplex_copper
,
2732 #ifdef CONFIG_IGB_HWMON
2733 .get_thermal_sensor_data
= igb_get_thermal_sensor_data_generic
,
2734 .init_thermal_sensor_thresh
= igb_init_thermal_sensor_thresh_generic
,
2738 static struct e1000_phy_operations e1000_phy_ops_82575
= {
2739 .acquire
= igb_acquire_phy_82575
,
2740 .get_cfg_done
= igb_get_cfg_done_82575
,
2741 .release
= igb_release_phy_82575
,
2742 .write_i2c_byte
= igb_write_i2c_byte
,
2743 .read_i2c_byte
= igb_read_i2c_byte
,
2746 static struct e1000_nvm_operations e1000_nvm_ops_82575
= {
2747 .acquire
= igb_acquire_nvm_82575
,
2748 .read
= igb_read_nvm_eerd
,
2749 .release
= igb_release_nvm_82575
,
2750 .write
= igb_write_nvm_spi
,
2753 const struct e1000_info e1000_82575_info
= {
2754 .get_invariants
= igb_get_invariants_82575
,
2755 .mac_ops
= &e1000_mac_ops_82575
,
2756 .phy_ops
= &e1000_phy_ops_82575
,
2757 .nvm_ops
= &e1000_nvm_ops_82575
,