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Linux 3.11-rc3
[cris-mirror.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_82599.c
blob0b82d38bc97daf6e67c6cd7a0d65caafa70ccd11
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31
32 #include "ixgbe.h"
33 #include "ixgbe_phy.h"
34 #include "ixgbe_mbx.h"
35
36 #define IXGBE_82599_MAX_TX_QUEUES 128
37 #define IXGBE_82599_MAX_RX_QUEUES 128
38 #define IXGBE_82599_RAR_ENTRIES 128
39 #define IXGBE_82599_MC_TBL_SIZE 128
40 #define IXGBE_82599_VFT_TBL_SIZE 128
41 #define IXGBE_82599_RX_PB_SIZE 512
42
43 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
44 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
45 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
46 static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
47 ixgbe_link_speed speed,
48 bool autoneg_wait_to_complete);
49 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
50 ixgbe_link_speed speed,
51 bool autoneg_wait_to_complete);
52 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
53 bool autoneg_wait_to_complete);
54 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
55 ixgbe_link_speed speed,
56 bool autoneg_wait_to_complete);
57 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
58 ixgbe_link_speed speed,
59 bool autoneg_wait_to_complete);
60 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
61
62 static bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
63 {
64 u32 fwsm, manc, factps;
65
66 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
67 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
68 return false;
69
70 manc = IXGBE_READ_REG(hw, IXGBE_MANC);
71 if (!(manc & IXGBE_MANC_RCV_TCO_EN))
72 return false;
73
74 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS);
75 if (factps & IXGBE_FACTPS_MNGCG)
76 return false;
77
78 return true;
79 }
80
81 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
82 {
83 struct ixgbe_mac_info *mac = &hw->mac;
84
85 /* enable the laser control functions for SFP+ fiber
86 * and MNG not enabled
87 */
88 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
89 !hw->mng_fw_enabled) {
90 mac->ops.disable_tx_laser =
91 &ixgbe_disable_tx_laser_multispeed_fiber;
92 mac->ops.enable_tx_laser =
93 &ixgbe_enable_tx_laser_multispeed_fiber;
94 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
95 } else {
96 mac->ops.disable_tx_laser = NULL;
97 mac->ops.enable_tx_laser = NULL;
98 mac->ops.flap_tx_laser = NULL;
99 }
100
101 if (hw->phy.multispeed_fiber) {
102 /* Set up dual speed SFP+ support */
103 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
104 } else {
105 if ((mac->ops.get_media_type(hw) ==
106 ixgbe_media_type_backplane) &&
107 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
108 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
109 !ixgbe_verify_lesm_fw_enabled_82599(hw))
110 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
111 else
112 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
113 }
114 }
115
116 static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
117 {
118 s32 ret_val = 0;
119 u16 list_offset, data_offset, data_value;
120 bool got_lock = false;
121
122 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
123 ixgbe_init_mac_link_ops_82599(hw);
124
125 hw->phy.ops.reset = NULL;
126
127 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
128 &data_offset);
129 if (ret_val != 0)
130 goto setup_sfp_out;
131
132 /* PHY config will finish before releasing the semaphore */
133 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
134 IXGBE_GSSR_MAC_CSR_SM);
135 if (ret_val != 0) {
136 ret_val = IXGBE_ERR_SWFW_SYNC;
137 goto setup_sfp_out;
138 }
139
140 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
141 while (data_value != 0xffff) {
142 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
143 IXGBE_WRITE_FLUSH(hw);
144 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
145 }
146
147 /* Release the semaphore */
148 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
149 /*
150 * Delay obtaining semaphore again to allow FW access,
151 * semaphore_delay is in ms usleep_range needs us.
152 */
153 usleep_range(hw->eeprom.semaphore_delay * 1000,
154 hw->eeprom.semaphore_delay * 2000);
155
156 /* Need SW/FW semaphore around AUTOC writes if LESM on,
157 * likewise reset_pipeline requires lock as it also writes
158 * AUTOC.
159 */
160 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
161 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
162 IXGBE_GSSR_MAC_CSR_SM);
163 if (ret_val)
164 goto setup_sfp_out;
165
166 got_lock = true;
167 }
168
169 /* Restart DSP and set SFI mode */
170 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((hw->mac.orig_autoc) |
171 IXGBE_AUTOC_LMS_10G_SERIAL));
172 hw->mac.cached_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
173 ret_val = ixgbe_reset_pipeline_82599(hw);
174
175 if (got_lock) {
176 hw->mac.ops.release_swfw_sync(hw,
177 IXGBE_GSSR_MAC_CSR_SM);
178 got_lock = false;
179 }
180
181 if (ret_val) {
182 hw_dbg(hw, " sfp module setup not complete\n");
183 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
184 goto setup_sfp_out;
185 }
186 }
187
188 setup_sfp_out:
189 return ret_val;
190 }
191
192 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
193 {
194 struct ixgbe_mac_info *mac = &hw->mac;
195
196 ixgbe_init_mac_link_ops_82599(hw);
197
198 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
199 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
200 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
201 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
202 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
203 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
204
205 return 0;
206 }
207
208 /**
209 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
210 * @hw: pointer to hardware structure
211 *
212 * Initialize any function pointers that were not able to be
213 * set during get_invariants because the PHY/SFP type was
214 * not known. Perform the SFP init if necessary.
215 *
216 **/
217 static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
218 {
219 struct ixgbe_mac_info *mac = &hw->mac;
220 struct ixgbe_phy_info *phy = &hw->phy;
221 s32 ret_val = 0;
222
223 /* Identify the PHY or SFP module */
224 ret_val = phy->ops.identify(hw);
225
226 /* Setup function pointers based on detected SFP module and speeds */
227 ixgbe_init_mac_link_ops_82599(hw);
228
229 /* If copper media, overwrite with copper function pointers */
230 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
231 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
232 mac->ops.get_link_capabilities =
233 &ixgbe_get_copper_link_capabilities_generic;
234 }
235
236 /* Set necessary function pointers based on phy type */
237 switch (hw->phy.type) {
238 case ixgbe_phy_tn:
239 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
240 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
241 phy->ops.get_firmware_version =
242 &ixgbe_get_phy_firmware_version_tnx;
243 break;
244 default:
245 break;
246 }
247
248 return ret_val;
249 }
250
251 /**
252 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
253 * @hw: pointer to hardware structure
254 * @speed: pointer to link speed
255 * @autoneg: true when autoneg or autotry is enabled
256 *
257 * Determines the link capabilities by reading the AUTOC register.
258 **/
259 static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
260 ixgbe_link_speed *speed,
261 bool *autoneg)
262 {
263 s32 status = 0;
264 u32 autoc = 0;
265
266 /* Determine 1G link capabilities off of SFP+ type */
267 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
268 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
269 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
270 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
271 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
272 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
273 *speed = IXGBE_LINK_SPEED_1GB_FULL;
274 *autoneg = true;
275 goto out;
276 }
277
278 /*
279 * Determine link capabilities based on the stored value of AUTOC,
280 * which represents EEPROM defaults. If AUTOC value has not been
281 * stored, use the current register value.
282 */
283 if (hw->mac.orig_link_settings_stored)
284 autoc = hw->mac.orig_autoc;
285 else
286 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
287
288 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
289 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
290 *speed = IXGBE_LINK_SPEED_1GB_FULL;
291 *autoneg = false;
292 break;
293
294 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
295 *speed = IXGBE_LINK_SPEED_10GB_FULL;
296 *autoneg = false;
297 break;
298
299 case IXGBE_AUTOC_LMS_1G_AN:
300 *speed = IXGBE_LINK_SPEED_1GB_FULL;
301 *autoneg = true;
302 break;
303
304 case IXGBE_AUTOC_LMS_10G_SERIAL:
305 *speed = IXGBE_LINK_SPEED_10GB_FULL;
306 *autoneg = false;
307 break;
308
309 case IXGBE_AUTOC_LMS_KX4_KX_KR:
310 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
311 *speed = IXGBE_LINK_SPEED_UNKNOWN;
312 if (autoc & IXGBE_AUTOC_KR_SUPP)
313 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
314 if (autoc & IXGBE_AUTOC_KX4_SUPP)
315 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
316 if (autoc & IXGBE_AUTOC_KX_SUPP)
317 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
318 *autoneg = true;
319 break;
320
321 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
322 *speed = IXGBE_LINK_SPEED_100_FULL;
323 if (autoc & IXGBE_AUTOC_KR_SUPP)
324 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
325 if (autoc & IXGBE_AUTOC_KX4_SUPP)
326 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
327 if (autoc & IXGBE_AUTOC_KX_SUPP)
328 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
329 *autoneg = true;
330 break;
331
332 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
333 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
334 *autoneg = false;
335 break;
336
337 default:
338 status = IXGBE_ERR_LINK_SETUP;
339 goto out;
340 break;
341 }
342
343 if (hw->phy.multispeed_fiber) {
344 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
345 IXGBE_LINK_SPEED_1GB_FULL;
346 *autoneg = true;
347 }
348
349 out:
350 return status;
351 }
352
353 /**
354 * ixgbe_get_media_type_82599 - Get media type
355 * @hw: pointer to hardware structure
356 *
357 * Returns the media type (fiber, copper, backplane)
358 **/
359 static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
360 {
361 enum ixgbe_media_type media_type;
362
363 /* Detect if there is a copper PHY attached. */
364 switch (hw->phy.type) {
365 case ixgbe_phy_cu_unknown:
366 case ixgbe_phy_tn:
367 media_type = ixgbe_media_type_copper;
368 goto out;
369 default:
370 break;
371 }
372
373 switch (hw->device_id) {
374 case IXGBE_DEV_ID_82599_KX4:
375 case IXGBE_DEV_ID_82599_KX4_MEZZ:
376 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
377 case IXGBE_DEV_ID_82599_KR:
378 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
379 case IXGBE_DEV_ID_82599_XAUI_LOM:
380 /* Default device ID is mezzanine card KX/KX4 */
381 media_type = ixgbe_media_type_backplane;
382 break;
383 case IXGBE_DEV_ID_82599_SFP:
384 case IXGBE_DEV_ID_82599_SFP_FCOE:
385 case IXGBE_DEV_ID_82599_SFP_EM:
386 case IXGBE_DEV_ID_82599_SFP_SF2:
387 case IXGBE_DEV_ID_82599_SFP_SF_QP:
388 case IXGBE_DEV_ID_82599EN_SFP:
389 media_type = ixgbe_media_type_fiber;
390 break;
391 case IXGBE_DEV_ID_82599_CX4:
392 media_type = ixgbe_media_type_cx4;
393 break;
394 case IXGBE_DEV_ID_82599_T3_LOM:
395 media_type = ixgbe_media_type_copper;
396 break;
397 case IXGBE_DEV_ID_82599_LS:
398 media_type = ixgbe_media_type_fiber_lco;
399 break;
400 default:
401 media_type = ixgbe_media_type_unknown;
402 break;
403 }
404 out:
405 return media_type;
406 }
407
408 /**
409 * ixgbe_start_mac_link_82599 - Setup MAC link settings
410 * @hw: pointer to hardware structure
411 * @autoneg_wait_to_complete: true when waiting for completion is needed
412 *
413 * Configures link settings based on values in the ixgbe_hw struct.
414 * Restarts the link. Performs autonegotiation if needed.
415 **/
416 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
417 bool autoneg_wait_to_complete)
418 {
419 u32 autoc_reg;
420 u32 links_reg;
421 u32 i;
422 s32 status = 0;
423 bool got_lock = false;
424
425 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
426 status = hw->mac.ops.acquire_swfw_sync(hw,
427 IXGBE_GSSR_MAC_CSR_SM);
428 if (status)
429 goto out;
430
431 got_lock = true;
432 }
433
434 /* Restart link */
435 ixgbe_reset_pipeline_82599(hw);
436
437 if (got_lock)
438 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
439
440 /* Only poll for autoneg to complete if specified to do so */
441 if (autoneg_wait_to_complete) {
442 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
443 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
444 IXGBE_AUTOC_LMS_KX4_KX_KR ||
445 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
446 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
447 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
448 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
449 links_reg = 0; /* Just in case Autoneg time = 0 */
450 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
451 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
452 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
453 break;
454 msleep(100);
455 }
456 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
457 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
458 hw_dbg(hw, "Autoneg did not complete.\n");
459 }
460 }
461 }
462
463 /* Add delay to filter out noises during initial link setup */
464 msleep(50);
465
466 out:
467 return status;
468 }
469
470 /**
471 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
472 * @hw: pointer to hardware structure
473 *
474 * The base drivers may require better control over SFP+ module
475 * PHY states. This includes selectively shutting down the Tx
476 * laser on the PHY, effectively halting physical link.
477 **/
478 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
479 {
480 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
481
482 /* Disable tx laser; allow 100us to go dark per spec */
483 esdp_reg |= IXGBE_ESDP_SDP3;
484 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
485 IXGBE_WRITE_FLUSH(hw);
486 udelay(100);
487 }
488
489 /**
490 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
491 * @hw: pointer to hardware structure
492 *
493 * The base drivers may require better control over SFP+ module
494 * PHY states. This includes selectively turning on the Tx
495 * laser on the PHY, effectively starting physical link.
496 **/
497 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
498 {
499 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
500
501 /* Enable tx laser; allow 100ms to light up */
502 esdp_reg &= ~IXGBE_ESDP_SDP3;
503 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
504 IXGBE_WRITE_FLUSH(hw);
505 msleep(100);
506 }
507
508 /**
509 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
510 * @hw: pointer to hardware structure
511 *
512 * When the driver changes the link speeds that it can support,
513 * it sets autotry_restart to true to indicate that we need to
514 * initiate a new autotry session with the link partner. To do
515 * so, we set the speed then disable and re-enable the tx laser, to
516 * alert the link partner that it also needs to restart autotry on its
517 * end. This is consistent with true clause 37 autoneg, which also
518 * involves a loss of signal.
519 **/
520 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
521 {
522 if (hw->mac.autotry_restart) {
523 ixgbe_disable_tx_laser_multispeed_fiber(hw);
524 ixgbe_enable_tx_laser_multispeed_fiber(hw);
525 hw->mac.autotry_restart = false;
526 }
527 }
528
529 /**
530 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
531 * @hw: pointer to hardware structure
532 * @speed: new link speed
533 * @autoneg_wait_to_complete: true when waiting for completion is needed
534 *
535 * Set the link speed in the AUTOC register and restarts link.
536 **/
537 static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
538 ixgbe_link_speed speed,
539 bool autoneg_wait_to_complete)
540 {
541 s32 status = 0;
542 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
543 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
544 u32 speedcnt = 0;
545 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
546 u32 i = 0;
547 bool link_up = false;
548 bool autoneg = false;
549
550 /* Mask off requested but non-supported speeds */
551 status = hw->mac.ops.get_link_capabilities(hw, &link_speed,
552 &autoneg);
553 if (status != 0)
554 return status;
555
556 speed &= link_speed;
557
558 /*
559 * Try each speed one by one, highest priority first. We do this in
560 * software because 10gb fiber doesn't support speed autonegotiation.
561 */
562 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
563 speedcnt++;
564 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
565
566 /* If we already have link at this speed, just jump out */
567 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
568 false);
569 if (status != 0)
570 return status;
571
572 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
573 goto out;
574
575 /* Set the module link speed */
576 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
577 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
578 IXGBE_WRITE_FLUSH(hw);
579
580 /* Allow module to change analog characteristics (1G->10G) */
581 msleep(40);
582
583 status = ixgbe_setup_mac_link_82599(hw,
584 IXGBE_LINK_SPEED_10GB_FULL,
585 autoneg_wait_to_complete);
586 if (status != 0)
587 return status;
588
589 /* Flap the tx laser if it has not already been done */
590 if (hw->mac.ops.flap_tx_laser)
591 hw->mac.ops.flap_tx_laser(hw);
592
593 /*
594 * Wait for the controller to acquire link. Per IEEE 802.3ap,
595 * Section 73.10.2, we may have to wait up to 500ms if KR is
596 * attempted. 82599 uses the same timing for 10g SFI.
597 */
598 for (i = 0; i < 5; i++) {
599 /* Wait for the link partner to also set speed */
600 msleep(100);
601
602 /* If we have link, just jump out */
603 status = hw->mac.ops.check_link(hw, &link_speed,
604 &link_up, false);
605 if (status != 0)
606 return status;
607
608 if (link_up)
609 goto out;
610 }
611 }
612
613 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
614 speedcnt++;
615 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
616 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
617
618 /* If we already have link at this speed, just jump out */
619 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
620 false);
621 if (status != 0)
622 return status;
623
624 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
625 goto out;
626
627 /* Set the module link speed */
628 esdp_reg &= ~IXGBE_ESDP_SDP5;
629 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
630 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
631 IXGBE_WRITE_FLUSH(hw);
632
633 /* Allow module to change analog characteristics (10G->1G) */
634 msleep(40);
635
636 status = ixgbe_setup_mac_link_82599(hw,
637 IXGBE_LINK_SPEED_1GB_FULL,
638 autoneg_wait_to_complete);
639 if (status != 0)
640 return status;
641
642 /* Flap the tx laser if it has not already been done */
643 if (hw->mac.ops.flap_tx_laser)
644 hw->mac.ops.flap_tx_laser(hw);
645
646 /* Wait for the link partner to also set speed */
647 msleep(100);
648
649 /* If we have link, just jump out */
650 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
651 false);
652 if (status != 0)
653 return status;
654
655 if (link_up)
656 goto out;
657 }
658
659 /*
660 * We didn't get link. Configure back to the highest speed we tried,
661 * (if there was more than one). We call ourselves back with just the
662 * single highest speed that the user requested.
663 */
664 if (speedcnt > 1)
665 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
666 highest_link_speed,
667 autoneg_wait_to_complete);
668
669 out:
670 /* Set autoneg_advertised value based on input link speed */
671 hw->phy.autoneg_advertised = 0;
672
673 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
674 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
675
676 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
677 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
678
679 return status;
680 }
681
682 /**
683 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
684 * @hw: pointer to hardware structure
685 * @speed: new link speed
686 * @autoneg_wait_to_complete: true when waiting for completion is needed
687 *
688 * Implements the Intel SmartSpeed algorithm.
689 **/
690 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
691 ixgbe_link_speed speed,
692 bool autoneg_wait_to_complete)
693 {
694 s32 status = 0;
695 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
696 s32 i, j;
697 bool link_up = false;
698 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
699
700 /* Set autoneg_advertised value based on input link speed */
701 hw->phy.autoneg_advertised = 0;
702
703 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
704 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
705
706 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
707 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
708
709 if (speed & IXGBE_LINK_SPEED_100_FULL)
710 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
711
712 /*
713 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
714 * autoneg advertisement if link is unable to be established at the
715 * highest negotiated rate. This can sometimes happen due to integrity
716 * issues with the physical media connection.
717 */
718
719 /* First, try to get link with full advertisement */
720 hw->phy.smart_speed_active = false;
721 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
722 status = ixgbe_setup_mac_link_82599(hw, speed,
723 autoneg_wait_to_complete);
724 if (status != 0)
725 goto out;
726
727 /*
728 * Wait for the controller to acquire link. Per IEEE 802.3ap,
729 * Section 73.10.2, we may have to wait up to 500ms if KR is
730 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
731 * Table 9 in the AN MAS.
732 */
733 for (i = 0; i < 5; i++) {
734 mdelay(100);
735
736 /* If we have link, just jump out */
737 status = hw->mac.ops.check_link(hw, &link_speed,
738 &link_up, false);
739 if (status != 0)
740 goto out;
741
742 if (link_up)
743 goto out;
744 }
745 }
746
747 /*
748 * We didn't get link. If we advertised KR plus one of KX4/KX
749 * (or BX4/BX), then disable KR and try again.
750 */
751 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
752 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
753 goto out;
754
755 /* Turn SmartSpeed on to disable KR support */
756 hw->phy.smart_speed_active = true;
757 status = ixgbe_setup_mac_link_82599(hw, speed,
758 autoneg_wait_to_complete);
759 if (status != 0)
760 goto out;
761
762 /*
763 * Wait for the controller to acquire link. 600ms will allow for
764 * the AN link_fail_inhibit_timer as well for multiple cycles of
765 * parallel detect, both 10g and 1g. This allows for the maximum
766 * connect attempts as defined in the AN MAS table 73-7.
767 */
768 for (i = 0; i < 6; i++) {
769 mdelay(100);
770
771 /* If we have link, just jump out */
772 status = hw->mac.ops.check_link(hw, &link_speed,
773 &link_up, false);
774 if (status != 0)
775 goto out;
776
777 if (link_up)
778 goto out;
779 }
780
781 /* We didn't get link. Turn SmartSpeed back off. */
782 hw->phy.smart_speed_active = false;
783 status = ixgbe_setup_mac_link_82599(hw, speed,
784 autoneg_wait_to_complete);
785
786 out:
787 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
788 hw_dbg(hw, "Smartspeed has downgraded the link speed from "
789 "the maximum advertised\n");
790 return status;
791 }
792
793 /**
794 * ixgbe_setup_mac_link_82599 - Set MAC link speed
795 * @hw: pointer to hardware structure
796 * @speed: new link speed
797 * @autoneg_wait_to_complete: true when waiting for completion is needed
798 *
799 * Set the link speed in the AUTOC register and restarts link.
800 **/
801 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
802 ixgbe_link_speed speed,
803 bool autoneg_wait_to_complete)
804 {
805 s32 status = 0;
806 u32 autoc, pma_pmd_1g, link_mode, start_autoc;
807 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
808 u32 orig_autoc = 0;
809 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
810 u32 links_reg;
811 u32 i;
812 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
813 bool got_lock = false;
814 bool autoneg = false;
815
816 /* Check to see if speed passed in is supported. */
817 status = hw->mac.ops.get_link_capabilities(hw, &link_capabilities,
818 &autoneg);
819 if (status != 0)
820 goto out;
821
822 speed &= link_capabilities;
823
824 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
825 status = IXGBE_ERR_LINK_SETUP;
826 goto out;
827 }
828
829 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
830 if (hw->mac.orig_link_settings_stored)
831 autoc = hw->mac.orig_autoc;
832 else
833 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
834
835 orig_autoc = autoc;
836 start_autoc = hw->mac.cached_autoc;
837 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
838 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
839
840 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
841 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
842 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
843 /* Set KX4/KX/KR support according to speed requested */
844 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
845 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
846 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
847 autoc |= IXGBE_AUTOC_KX4_SUPP;
848 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
849 (hw->phy.smart_speed_active == false))
850 autoc |= IXGBE_AUTOC_KR_SUPP;
851 }
852 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
853 autoc |= IXGBE_AUTOC_KX_SUPP;
854 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
855 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
856 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
857 /* Switch from 1G SFI to 10G SFI if requested */
858 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
859 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
860 autoc &= ~IXGBE_AUTOC_LMS_MASK;
861 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
862 }
863 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
864 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
865 /* Switch from 10G SFI to 1G SFI if requested */
866 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
867 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
868 autoc &= ~IXGBE_AUTOC_LMS_MASK;
869 if (autoneg)
870 autoc |= IXGBE_AUTOC_LMS_1G_AN;
871 else
872 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
873 }
874 }
875
876 if (autoc != start_autoc) {
877 /* Need SW/FW semaphore around AUTOC writes if LESM is on,
878 * likewise reset_pipeline requires us to hold this lock as
879 * it also writes to AUTOC.
880 */
881 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
882 status = hw->mac.ops.acquire_swfw_sync(hw,
883 IXGBE_GSSR_MAC_CSR_SM);
884 if (status != 0)
885 goto out;
886
887 got_lock = true;
888 }
889
890 /* Restart link */
891 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
892 hw->mac.cached_autoc = autoc;
893 ixgbe_reset_pipeline_82599(hw);
894
895 if (got_lock)
896 hw->mac.ops.release_swfw_sync(hw,
897 IXGBE_GSSR_MAC_CSR_SM);
898
899 /* Only poll for autoneg to complete if specified to do so */
900 if (autoneg_wait_to_complete) {
901 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
902 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
903 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
904 links_reg = 0; /*Just in case Autoneg time=0*/
905 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
906 links_reg =
907 IXGBE_READ_REG(hw, IXGBE_LINKS);
908 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
909 break;
910 msleep(100);
911 }
912 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
913 status =
914 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
915 hw_dbg(hw, "Autoneg did not "
916 "complete.\n");
917 }
918 }
919 }
920
921 /* Add delay to filter out noises during initial link setup */
922 msleep(50);
923 }
924
925 out:
926 return status;
927 }
928
929 /**
930 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
931 * @hw: pointer to hardware structure
932 * @speed: new link speed
933 * @autoneg_wait_to_complete: true if waiting is needed to complete
934 *
935 * Restarts link on PHY and MAC based on settings passed in.
936 **/
937 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
938 ixgbe_link_speed speed,
939 bool autoneg_wait_to_complete)
940 {
941 s32 status;
942
943 /* Setup the PHY according to input speed */
944 status = hw->phy.ops.setup_link_speed(hw, speed,
945 autoneg_wait_to_complete);
946 /* Set up MAC */
947 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
948
949 return status;
950 }
951
952 /**
953 * ixgbe_reset_hw_82599 - Perform hardware reset
954 * @hw: pointer to hardware structure
955 *
956 * Resets the hardware by resetting the transmit and receive units, masks
957 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
958 * reset.
959 **/
960 static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
961 {
962 ixgbe_link_speed link_speed;
963 s32 status;
964 u32 ctrl, i, autoc2;
965 u32 curr_lms;
966 bool link_up = false;
967
968 /* Call adapter stop to disable tx/rx and clear interrupts */
969 status = hw->mac.ops.stop_adapter(hw);
970 if (status != 0)
971 goto reset_hw_out;
972
973 /* flush pending Tx transactions */
974 ixgbe_clear_tx_pending(hw);
975
976 /* PHY ops must be identified and initialized prior to reset */
977
978 /* Identify PHY and related function pointers */
979 status = hw->phy.ops.init(hw);
980
981 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
982 goto reset_hw_out;
983
984 /* Setup SFP module if there is one present. */
985 if (hw->phy.sfp_setup_needed) {
986 status = hw->mac.ops.setup_sfp(hw);
987 hw->phy.sfp_setup_needed = false;
988 }
989
990 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
991 goto reset_hw_out;
992
993 /* Reset PHY */
994 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
995 hw->phy.ops.reset(hw);
996
997 /* remember AUTOC from before we reset */
998 if (hw->mac.cached_autoc)
999 curr_lms = hw->mac.cached_autoc & IXGBE_AUTOC_LMS_MASK;
1000 else
1001 curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) &
1002 IXGBE_AUTOC_LMS_MASK;
1003
1004 mac_reset_top:
1005 /*
1006 * Issue global reset to the MAC. Needs to be SW reset if link is up.
1007 * If link reset is used when link is up, it might reset the PHY when
1008 * mng is using it. If link is down or the flag to force full link
1009 * reset is set, then perform link reset.
1010 */
1011 ctrl = IXGBE_CTRL_LNK_RST;
1012 if (!hw->force_full_reset) {
1013 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1014 if (link_up)
1015 ctrl = IXGBE_CTRL_RST;
1016 }
1017
1018 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1019 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1020 IXGBE_WRITE_FLUSH(hw);
1021
1022 /* Poll for reset bit to self-clear indicating reset is complete */
1023 for (i = 0; i < 10; i++) {
1024 udelay(1);
1025 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1026 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1027 break;
1028 }
1029
1030 if (ctrl & IXGBE_CTRL_RST_MASK) {
1031 status = IXGBE_ERR_RESET_FAILED;
1032 hw_dbg(hw, "Reset polling failed to complete.\n");
1033 }
1034
1035 msleep(50);
1036
1037 /*
1038 * Double resets are required for recovery from certain error
1039 * conditions. Between resets, it is necessary to stall to allow time
1040 * for any pending HW events to complete.
1041 */
1042 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1043 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1044 goto mac_reset_top;
1045 }
1046
1047 /*
1048 * Store the original AUTOC/AUTOC2 values if they have not been
1049 * stored off yet. Otherwise restore the stored original
1050 * values since the reset operation sets back to defaults.
1051 */
1052 hw->mac.cached_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1053 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1054
1055 /* Enable link if disabled in NVM */
1056 if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
1057 autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
1058 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1059 IXGBE_WRITE_FLUSH(hw);
1060 }
1061
1062 if (hw->mac.orig_link_settings_stored == false) {
1063 hw->mac.orig_autoc = hw->mac.cached_autoc;
1064 hw->mac.orig_autoc2 = autoc2;
1065 hw->mac.orig_link_settings_stored = true;
1066 } else {
1067
1068 /* If MNG FW is running on a multi-speed device that
1069 * doesn't autoneg with out driver support we need to
1070 * leave LMS in the state it was before we MAC reset.
1071 * Likewise if we support WoL we don't want change the
1072 * LMS state either.
1073 */
1074 if ((hw->phy.multispeed_fiber && hw->mng_fw_enabled) ||
1075 hw->wol_enabled)
1076 hw->mac.orig_autoc =
1077 (hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) |
1078 curr_lms;
1079
1080 if (hw->mac.cached_autoc != hw->mac.orig_autoc) {
1081 /* Need SW/FW semaphore around AUTOC writes if LESM is
1082 * on, likewise reset_pipeline requires us to hold
1083 * this lock as it also writes to AUTOC.
1084 */
1085 bool got_lock = false;
1086 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
1087 status = hw->mac.ops.acquire_swfw_sync(hw,
1088 IXGBE_GSSR_MAC_CSR_SM);
1089 if (status)
1090 goto reset_hw_out;
1091
1092 got_lock = true;
1093 }
1094
1095 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
1096 hw->mac.cached_autoc = hw->mac.orig_autoc;
1097 ixgbe_reset_pipeline_82599(hw);
1098
1099 if (got_lock)
1100 hw->mac.ops.release_swfw_sync(hw,
1101 IXGBE_GSSR_MAC_CSR_SM);
1102 }
1103
1104 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1105 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1106 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1107 autoc2 |= (hw->mac.orig_autoc2 &
1108 IXGBE_AUTOC2_UPPER_MASK);
1109 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1110 }
1111 }
1112
1113 /* Store the permanent mac address */
1114 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1115
1116 /*
1117 * Store MAC address from RAR0, clear receive address registers, and
1118 * clear the multicast table. Also reset num_rar_entries to 128,
1119 * since we modify this value when programming the SAN MAC address.
1120 */
1121 hw->mac.num_rar_entries = 128;
1122 hw->mac.ops.init_rx_addrs(hw);
1123
1124 /* Store the permanent SAN mac address */
1125 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1126
1127 /* Add the SAN MAC address to the RAR only if it's a valid address */
1128 if (is_valid_ether_addr(hw->mac.san_addr)) {
1129 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1130 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1131
1132 /* Save the SAN MAC RAR index */
1133 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
1134
1135 /* Reserve the last RAR for the SAN MAC address */
1136 hw->mac.num_rar_entries--;
1137 }
1138
1139 /* Store the alternative WWNN/WWPN prefix */
1140 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1141 &hw->mac.wwpn_prefix);
1142
1143 reset_hw_out:
1144 return status;
1145 }
1146
1147 /**
1148 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1149 * @hw: pointer to hardware structure
1150 **/
1151 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1152 {
1153 int i;
1154 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1155 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1156
1157 /*
1158 * Before starting reinitialization process,
1159 * FDIRCMD.CMD must be zero.
1160 */
1161 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1162 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1163 IXGBE_FDIRCMD_CMD_MASK))
1164 break;
1165 udelay(10);
1166 }
1167 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1168 hw_dbg(hw, "Flow Director previous command isn't complete, "
1169 "aborting table re-initialization.\n");
1170 return IXGBE_ERR_FDIR_REINIT_FAILED;
1171 }
1172
1173 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1174 IXGBE_WRITE_FLUSH(hw);
1175 /*
1176 * 82599 adapters flow director init flow cannot be restarted,
1177 * Workaround 82599 silicon errata by performing the following steps
1178 * before re-writing the FDIRCTRL control register with the same value.
1179 * - write 1 to bit 8 of FDIRCMD register &
1180 * - write 0 to bit 8 of FDIRCMD register
1181 */
1182 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1183 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1184 IXGBE_FDIRCMD_CLEARHT));
1185 IXGBE_WRITE_FLUSH(hw);
1186 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1187 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1188 ~IXGBE_FDIRCMD_CLEARHT));
1189 IXGBE_WRITE_FLUSH(hw);
1190 /*
1191 * Clear FDIR Hash register to clear any leftover hashes
1192 * waiting to be programmed.
1193 */
1194 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1195 IXGBE_WRITE_FLUSH(hw);
1196
1197 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1198 IXGBE_WRITE_FLUSH(hw);
1199
1200 /* Poll init-done after we write FDIRCTRL register */
1201 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1202 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1203 IXGBE_FDIRCTRL_INIT_DONE)
1204 break;
1205 usleep_range(1000, 2000);
1206 }
1207 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1208 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1209 return IXGBE_ERR_FDIR_REINIT_FAILED;
1210 }
1211
1212 /* Clear FDIR statistics registers (read to clear) */
1213 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1214 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1215 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1216 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1217 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1218
1219 return 0;
1220 }
1221
1222 /**
1223 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1224 * @hw: pointer to hardware structure
1225 * @fdirctrl: value to write to flow director control register
1226 **/
1227 static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1228 {
1229 int i;
1230
1231 /* Prime the keys for hashing */
1232 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1233 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1234
1235 /*
1236 * Poll init-done after we write the register. Estimated times:
1237 * 10G: PBALLOC = 11b, timing is 60us
1238 * 1G: PBALLOC = 11b, timing is 600us
1239 * 100M: PBALLOC = 11b, timing is 6ms
1240 *
1241 * Multiple these timings by 4 if under full Rx load
1242 *
1243 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1244 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1245 * this might not finish in our poll time, but we can live with that
1246 * for now.
1247 */
1248 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1249 IXGBE_WRITE_FLUSH(hw);
1250 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1251 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1252 IXGBE_FDIRCTRL_INIT_DONE)
1253 break;
1254 usleep_range(1000, 2000);
1255 }
1256
1257 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1258 hw_dbg(hw, "Flow Director poll time exceeded!\n");
1259 }
1260
1261 /**
1262 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1263 * @hw: pointer to hardware structure
1264 * @fdirctrl: value to write to flow director control register, initially
1265 * contains just the value of the Rx packet buffer allocation
1266 **/
1267 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1268 {
1269 /*
1270 * Continue setup of fdirctrl register bits:
1271 * Move the flexible bytes to use the ethertype - shift 6 words
1272 * Set the maximum length per hash bucket to 0xA filters
1273 * Send interrupt when 64 filters are left
1274 */
1275 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1276 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1277 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1278
1279 /* write hashes and fdirctrl register, poll for completion */
1280 ixgbe_fdir_enable_82599(hw, fdirctrl);
1281
1282 return 0;
1283 }
1284
1285 /**
1286 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1287 * @hw: pointer to hardware structure
1288 * @fdirctrl: value to write to flow director control register, initially
1289 * contains just the value of the Rx packet buffer allocation
1290 **/
1291 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1292 {
1293 /*
1294 * Continue setup of fdirctrl register bits:
1295 * Turn perfect match filtering on
1296 * Report hash in RSS field of Rx wb descriptor
1297 * Initialize the drop queue
1298 * Move the flexible bytes to use the ethertype - shift 6 words
1299 * Set the maximum length per hash bucket to 0xA filters
1300 * Send interrupt when 64 (0x4 * 16) filters are left
1301 */
1302 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
1303 IXGBE_FDIRCTRL_REPORT_STATUS |
1304 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
1305 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1306 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1307 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1308
1309 /* write hashes and fdirctrl register, poll for completion */
1310 ixgbe_fdir_enable_82599(hw, fdirctrl);
1311
1312 return 0;
1313 }
1314
1315 /*
1316 * These defines allow us to quickly generate all of the necessary instructions
1317 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1318 * for values 0 through 15
1319 */
1320 #define IXGBE_ATR_COMMON_HASH_KEY \
1321 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1322 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1323 do { \
1324 u32 n = (_n); \
1325 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1326 common_hash ^= lo_hash_dword >> n; \
1327 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1328 bucket_hash ^= lo_hash_dword >> n; \
1329 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1330 sig_hash ^= lo_hash_dword << (16 - n); \
1331 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1332 common_hash ^= hi_hash_dword >> n; \
1333 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1334 bucket_hash ^= hi_hash_dword >> n; \
1335 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1336 sig_hash ^= hi_hash_dword << (16 - n); \
1337 } while (0);
1338
1339 /**
1340 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1341 * @stream: input bitstream to compute the hash on
1342 *
1343 * This function is almost identical to the function above but contains
1344 * several optomizations such as unwinding all of the loops, letting the
1345 * compiler work out all of the conditional ifs since the keys are static
1346 * defines, and computing two keys at once since the hashed dword stream
1347 * will be the same for both keys.
1348 **/
1349 static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1350 union ixgbe_atr_hash_dword common)
1351 {
1352 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1353 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1354
1355 /* record the flow_vm_vlan bits as they are a key part to the hash */
1356 flow_vm_vlan = ntohl(input.dword);
1357
1358 /* generate common hash dword */
1359 hi_hash_dword = ntohl(common.dword);
1360
1361 /* low dword is word swapped version of common */
1362 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1363
1364 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1365 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1366
1367 /* Process bits 0 and 16 */
1368 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1369
1370 /*
1371 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1372 * delay this because bit 0 of the stream should not be processed
1373 * so we do not add the vlan until after bit 0 was processed
1374 */
1375 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1376
1377 /* Process remaining 30 bit of the key */
1378 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1379 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1380 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1381 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1382 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1383 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1384 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1385 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1386 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1387 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1388 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1389 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1390 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1391 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1392 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1393
1394 /* combine common_hash result with signature and bucket hashes */
1395 bucket_hash ^= common_hash;
1396 bucket_hash &= IXGBE_ATR_HASH_MASK;
1397
1398 sig_hash ^= common_hash << 16;
1399 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1400
1401 /* return completed signature hash */
1402 return sig_hash ^ bucket_hash;
1403 }
1404
1405 /**
1406 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1407 * @hw: pointer to hardware structure
1408 * @input: unique input dword
1409 * @common: compressed common input dword
1410 * @queue: queue index to direct traffic to
1411 **/
1412 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1413 union ixgbe_atr_hash_dword input,
1414 union ixgbe_atr_hash_dword common,
1415 u8 queue)
1416 {
1417 u64 fdirhashcmd;
1418 u32 fdircmd;
1419
1420 /*
1421 * Get the flow_type in order to program FDIRCMD properly
1422 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1423 */
1424 switch (input.formatted.flow_type) {
1425 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1426 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1427 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1428 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1429 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1430 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
1431 break;
1432 default:
1433 hw_dbg(hw, " Error on flow type input\n");
1434 return IXGBE_ERR_CONFIG;
1435 }
1436
1437 /* configure FDIRCMD register */
1438 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1439 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1440 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1441 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1442
1443 /*
1444 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1445 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1446 */
1447 fdirhashcmd = (u64)fdircmd << 32;
1448 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1449 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1450
1451 hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1452
1453 return 0;
1454 }
1455
1456 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1457 do { \
1458 u32 n = (_n); \
1459 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1460 bucket_hash ^= lo_hash_dword >> n; \
1461 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1462 bucket_hash ^= hi_hash_dword >> n; \
1463 } while (0);
1464
1465 /**
1466 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1467 * @atr_input: input bitstream to compute the hash on
1468 * @input_mask: mask for the input bitstream
1469 *
1470 * This function serves two main purposes. First it applys the input_mask
1471 * to the atr_input resulting in a cleaned up atr_input data stream.
1472 * Secondly it computes the hash and stores it in the bkt_hash field at
1473 * the end of the input byte stream. This way it will be available for
1474 * future use without needing to recompute the hash.
1475 **/
1476 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
1477 union ixgbe_atr_input *input_mask)
1478 {
1479
1480 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1481 u32 bucket_hash = 0;
1482
1483 /* Apply masks to input data */
1484 input->dword_stream[0] &= input_mask->dword_stream[0];
1485 input->dword_stream[1] &= input_mask->dword_stream[1];
1486 input->dword_stream[2] &= input_mask->dword_stream[2];
1487 input->dword_stream[3] &= input_mask->dword_stream[3];
1488 input->dword_stream[4] &= input_mask->dword_stream[4];
1489 input->dword_stream[5] &= input_mask->dword_stream[5];
1490 input->dword_stream[6] &= input_mask->dword_stream[6];
1491 input->dword_stream[7] &= input_mask->dword_stream[7];
1492 input->dword_stream[8] &= input_mask->dword_stream[8];
1493 input->dword_stream[9] &= input_mask->dword_stream[9];
1494 input->dword_stream[10] &= input_mask->dword_stream[10];
1495
1496 /* record the flow_vm_vlan bits as they are a key part to the hash */
1497 flow_vm_vlan = ntohl(input->dword_stream[0]);
1498
1499 /* generate common hash dword */
1500 hi_hash_dword = ntohl(input->dword_stream[1] ^
1501 input->dword_stream[2] ^
1502 input->dword_stream[3] ^
1503 input->dword_stream[4] ^
1504 input->dword_stream[5] ^
1505 input->dword_stream[6] ^
1506 input->dword_stream[7] ^
1507 input->dword_stream[8] ^
1508 input->dword_stream[9] ^
1509 input->dword_stream[10]);
1510
1511 /* low dword is word swapped version of common */
1512 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1513
1514 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1515 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1516
1517 /* Process bits 0 and 16 */
1518 IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
1519
1520 /*
1521 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1522 * delay this because bit 0 of the stream should not be processed
1523 * so we do not add the vlan until after bit 0 was processed
1524 */
1525 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1526
1527 /* Process remaining 30 bit of the key */
1528 IXGBE_COMPUTE_BKT_HASH_ITERATION(1);
1529 IXGBE_COMPUTE_BKT_HASH_ITERATION(2);
1530 IXGBE_COMPUTE_BKT_HASH_ITERATION(3);
1531 IXGBE_COMPUTE_BKT_HASH_ITERATION(4);
1532 IXGBE_COMPUTE_BKT_HASH_ITERATION(5);
1533 IXGBE_COMPUTE_BKT_HASH_ITERATION(6);
1534 IXGBE_COMPUTE_BKT_HASH_ITERATION(7);
1535 IXGBE_COMPUTE_BKT_HASH_ITERATION(8);
1536 IXGBE_COMPUTE_BKT_HASH_ITERATION(9);
1537 IXGBE_COMPUTE_BKT_HASH_ITERATION(10);
1538 IXGBE_COMPUTE_BKT_HASH_ITERATION(11);
1539 IXGBE_COMPUTE_BKT_HASH_ITERATION(12);
1540 IXGBE_COMPUTE_BKT_HASH_ITERATION(13);
1541 IXGBE_COMPUTE_BKT_HASH_ITERATION(14);
1542 IXGBE_COMPUTE_BKT_HASH_ITERATION(15);
1543
1544 /*
1545 * Limit hash to 13 bits since max bucket count is 8K.
1546 * Store result at the end of the input stream.
1547 */
1548 input->formatted.bkt_hash = bucket_hash & 0x1FFF;
1549 }
1550
1551 /**
1552 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1553 * @input_mask: mask to be bit swapped
1554 *
1555 * The source and destination port masks for flow director are bit swapped
1556 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1557 * generate a correctly swapped value we need to bit swap the mask and that
1558 * is what is accomplished by this function.
1559 **/
1560 static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
1561 {
1562 u32 mask = ntohs(input_mask->formatted.dst_port);
1563 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1564 mask |= ntohs(input_mask->formatted.src_port);
1565 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1566 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1567 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1568 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1569 }
1570
1571 /*
1572 * These two macros are meant to address the fact that we have registers
1573 * that are either all or in part big-endian. As a result on big-endian
1574 * systems we will end up byte swapping the value to little-endian before
1575 * it is byte swapped again and written to the hardware in the original
1576 * big-endian format.
1577 */
1578 #define IXGBE_STORE_AS_BE32(_value) \
1579 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1580 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1581
1582 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1583 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value)))
1584
1585 #define IXGBE_STORE_AS_BE16(_value) \
1586 ntohs(((u16)(_value) >> 8) | ((u16)(_value) << 8))
1587
1588 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
1589 union ixgbe_atr_input *input_mask)
1590 {
1591 /* mask IPv6 since it is currently not supported */
1592 u32 fdirm = IXGBE_FDIRM_DIPv6;
1593 u32 fdirtcpm;
1594
1595 /*
1596 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1597 * are zero, then assume a full mask for that field. Also assume that
1598 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1599 * cannot be masked out in this implementation.
1600 *
1601 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1602 * point in time.
1603 */
1604
1605 /* verify bucket hash is cleared on hash generation */
1606 if (input_mask->formatted.bkt_hash)
1607 hw_dbg(hw, " bucket hash should always be 0 in mask\n");
1608
1609 /* Program FDIRM and verify partial masks */
1610 switch (input_mask->formatted.vm_pool & 0x7F) {
1611 case 0x0:
1612 fdirm |= IXGBE_FDIRM_POOL;
1613 case 0x7F:
1614 break;
1615 default:
1616 hw_dbg(hw, " Error on vm pool mask\n");
1617 return IXGBE_ERR_CONFIG;
1618 }
1619
1620 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
1621 case 0x0:
1622 fdirm |= IXGBE_FDIRM_L4P;
1623 if (input_mask->formatted.dst_port ||
1624 input_mask->formatted.src_port) {
1625 hw_dbg(hw, " Error on src/dst port mask\n");
1626 return IXGBE_ERR_CONFIG;
1627 }
1628 case IXGBE_ATR_L4TYPE_MASK:
1629 break;
1630 default:
1631 hw_dbg(hw, " Error on flow type mask\n");
1632 return IXGBE_ERR_CONFIG;
1633 }
1634
1635 switch (ntohs(input_mask->formatted.vlan_id) & 0xEFFF) {
1636 case 0x0000:
1637 /* mask VLAN ID, fall through to mask VLAN priority */
1638 fdirm |= IXGBE_FDIRM_VLANID;
1639 case 0x0FFF:
1640 /* mask VLAN priority */
1641 fdirm |= IXGBE_FDIRM_VLANP;
1642 break;
1643 case 0xE000:
1644 /* mask VLAN ID only, fall through */
1645 fdirm |= IXGBE_FDIRM_VLANID;
1646 case 0xEFFF:
1647 /* no VLAN fields masked */
1648 break;
1649 default:
1650 hw_dbg(hw, " Error on VLAN mask\n");
1651 return IXGBE_ERR_CONFIG;
1652 }
1653
1654 switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1655 case 0x0000:
1656 /* Mask Flex Bytes, fall through */
1657 fdirm |= IXGBE_FDIRM_FLEX;
1658 case 0xFFFF:
1659 break;
1660 default:
1661 hw_dbg(hw, " Error on flexible byte mask\n");
1662 return IXGBE_ERR_CONFIG;
1663 }
1664
1665 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1666 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1667
1668 /* store the TCP/UDP port masks, bit reversed from port layout */
1669 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
1670
1671 /* write both the same so that UDP and TCP use the same mask */
1672 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1673 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1674
1675 /* store source and destination IP masks (big-enian) */
1676 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1677 ~input_mask->formatted.src_ip[0]);
1678 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1679 ~input_mask->formatted.dst_ip[0]);
1680
1681 return 0;
1682 }
1683
1684 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1685 union ixgbe_atr_input *input,
1686 u16 soft_id, u8 queue)
1687 {
1688 u32 fdirport, fdirvlan, fdirhash, fdircmd;
1689
1690 /* currently IPv6 is not supported, must be programmed with 0 */
1691 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
1692 input->formatted.src_ip[0]);
1693 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
1694 input->formatted.src_ip[1]);
1695 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
1696 input->formatted.src_ip[2]);
1697
1698 /* record the source address (big-endian) */
1699 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1700
1701 /* record the first 32 bits of the destination address (big-endian) */
1702 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
1703
1704 /* record source and destination port (little-endian)*/
1705 fdirport = ntohs(input->formatted.dst_port);
1706 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1707 fdirport |= ntohs(input->formatted.src_port);
1708 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1709
1710 /* record vlan (little-endian) and flex_bytes(big-endian) */
1711 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
1712 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1713 fdirvlan |= ntohs(input->formatted.vlan_id);
1714 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1715
1716 /* configure FDIRHASH register */
1717 fdirhash = input->formatted.bkt_hash;
1718 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1719 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1720
1721 /*
1722 * flush all previous writes to make certain registers are
1723 * programmed prior to issuing the command
1724 */
1725 IXGBE_WRITE_FLUSH(hw);
1726
1727 /* configure FDIRCMD register */
1728 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1729 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1730 if (queue == IXGBE_FDIR_DROP_QUEUE)
1731 fdircmd |= IXGBE_FDIRCMD_DROP;
1732 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1733 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1734 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1735
1736 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1737
1738 return 0;
1739 }
1740
1741 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
1742 union ixgbe_atr_input *input,
1743 u16 soft_id)
1744 {
1745 u32 fdirhash;
1746 u32 fdircmd = 0;
1747 u32 retry_count;
1748 s32 err = 0;
1749
1750 /* configure FDIRHASH register */
1751 fdirhash = input->formatted.bkt_hash;
1752 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1753 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1754
1755 /* flush hash to HW */
1756 IXGBE_WRITE_FLUSH(hw);
1757
1758 /* Query if filter is present */
1759 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1760
1761 for (retry_count = 10; retry_count; retry_count--) {
1762 /* allow 10us for query to process */
1763 udelay(10);
1764 /* verify query completed successfully */
1765 fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
1766 if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK))
1767 break;
1768 }
1769
1770 if (!retry_count)
1771 err = IXGBE_ERR_FDIR_REINIT_FAILED;
1772
1773 /* if filter exists in hardware then remove it */
1774 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1775 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1776 IXGBE_WRITE_FLUSH(hw);
1777 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1778 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1779 }
1780
1781 return err;
1782 }
1783
1784 /**
1785 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1786 * @hw: pointer to hardware structure
1787 * @reg: analog register to read
1788 * @val: read value
1789 *
1790 * Performs read operation to Omer analog register specified.
1791 **/
1792 static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1793 {
1794 u32 core_ctl;
1795
1796 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1797 (reg << 8));
1798 IXGBE_WRITE_FLUSH(hw);
1799 udelay(10);
1800 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1801 *val = (u8)core_ctl;
1802
1803 return 0;
1804 }
1805
1806 /**
1807 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1808 * @hw: pointer to hardware structure
1809 * @reg: atlas register to write
1810 * @val: value to write
1811 *
1812 * Performs write operation to Omer analog register specified.
1813 **/
1814 static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1815 {
1816 u32 core_ctl;
1817
1818 core_ctl = (reg << 8) | val;
1819 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1820 IXGBE_WRITE_FLUSH(hw);
1821 udelay(10);
1822
1823 return 0;
1824 }
1825
1826 /**
1827 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1828 * @hw: pointer to hardware structure
1829 *
1830 * Starts the hardware using the generic start_hw function
1831 * and the generation start_hw function.
1832 * Then performs revision-specific operations, if any.
1833 **/
1834 static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1835 {
1836 s32 ret_val = 0;
1837
1838 ret_val = ixgbe_start_hw_generic(hw);
1839 if (ret_val != 0)
1840 goto out;
1841
1842 ret_val = ixgbe_start_hw_gen2(hw);
1843 if (ret_val != 0)
1844 goto out;
1845
1846 /* We need to run link autotry after the driver loads */
1847 hw->mac.autotry_restart = true;
1848 hw->mac.rx_pb_size = IXGBE_82599_RX_PB_SIZE;
1849
1850 if (ret_val == 0)
1851 ret_val = ixgbe_verify_fw_version_82599(hw);
1852 out:
1853 return ret_val;
1854 }
1855
1856 /**
1857 * ixgbe_identify_phy_82599 - Get physical layer module
1858 * @hw: pointer to hardware structure
1859 *
1860 * Determines the physical layer module found on the current adapter.
1861 * If PHY already detected, maintains current PHY type in hw struct,
1862 * otherwise executes the PHY detection routine.
1863 **/
1864 static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1865 {
1866 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1867
1868 /* Detect PHY if not unknown - returns success if already detected. */
1869 status = ixgbe_identify_phy_generic(hw);
1870 if (status != 0) {
1871 /* 82599 10GBASE-T requires an external PHY */
1872 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
1873 goto out;
1874 else
1875 status = ixgbe_identify_sfp_module_generic(hw);
1876 }
1877
1878 /* Set PHY type none if no PHY detected */
1879 if (hw->phy.type == ixgbe_phy_unknown) {
1880 hw->phy.type = ixgbe_phy_none;
1881 status = 0;
1882 }
1883
1884 /* Return error if SFP module has been detected but is not supported */
1885 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
1886 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1887
1888 out:
1889 return status;
1890 }
1891
1892 /**
1893 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1894 * @hw: pointer to hardware structure
1895 *
1896 * Determines physical layer capabilities of the current configuration.
1897 **/
1898 static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1899 {
1900 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1901 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1902 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1903 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1904 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1905 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1906 u16 ext_ability = 0;
1907 u8 comp_codes_10g = 0;
1908 u8 comp_codes_1g = 0;
1909
1910 hw->phy.ops.identify(hw);
1911
1912 switch (hw->phy.type) {
1913 case ixgbe_phy_tn:
1914 case ixgbe_phy_cu_unknown:
1915 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
1916 &ext_ability);
1917 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
1918 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1919 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
1920 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1921 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
1922 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1923 goto out;
1924 default:
1925 break;
1926 }
1927
1928 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1929 case IXGBE_AUTOC_LMS_1G_AN:
1930 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1931 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
1932 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
1933 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1934 goto out;
1935 } else
1936 /* SFI mode so read SFP module */
1937 goto sfp_check;
1938 break;
1939 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1940 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
1941 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1942 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
1943 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1944 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
1945 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
1946 goto out;
1947 break;
1948 case IXGBE_AUTOC_LMS_10G_SERIAL:
1949 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
1950 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1951 goto out;
1952 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
1953 goto sfp_check;
1954 break;
1955 case IXGBE_AUTOC_LMS_KX4_KX_KR:
1956 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
1957 if (autoc & IXGBE_AUTOC_KX_SUPP)
1958 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1959 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1960 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1961 if (autoc & IXGBE_AUTOC_KR_SUPP)
1962 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1963 goto out;
1964 break;
1965 default:
1966 goto out;
1967 break;
1968 }
1969
1970 sfp_check:
1971 /* SFP check must be done last since DA modules are sometimes used to
1972 * test KR mode - we need to id KR mode correctly before SFP module.
1973 * Call identify_sfp because the pluggable module may have changed */
1974 hw->phy.ops.identify_sfp(hw);
1975 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1976 goto out;
1977
1978 switch (hw->phy.type) {
1979 case ixgbe_phy_sfp_passive_tyco:
1980 case ixgbe_phy_sfp_passive_unknown:
1981 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1982 break;
1983 case ixgbe_phy_sfp_ftl_active:
1984 case ixgbe_phy_sfp_active_unknown:
1985 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1986 break;
1987 case ixgbe_phy_sfp_avago:
1988 case ixgbe_phy_sfp_ftl:
1989 case ixgbe_phy_sfp_intel:
1990 case ixgbe_phy_sfp_unknown:
1991 hw->phy.ops.read_i2c_eeprom(hw,
1992 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1993 hw->phy.ops.read_i2c_eeprom(hw,
1994 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1995 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1996 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1997 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1998 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1999 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
2000 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
2001 break;
2002 default:
2003 break;
2004 }
2005
2006 out:
2007 return physical_layer;
2008 }
2009
2010 /**
2011 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2012 * @hw: pointer to hardware structure
2013 * @regval: register value to write to RXCTRL
2014 *
2015 * Enables the Rx DMA unit for 82599
2016 **/
2017 static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2018 {
2019 /*
2020 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2021 * If traffic is incoming before we enable the Rx unit, it could hang
2022 * the Rx DMA unit. Therefore, make sure the security engine is
2023 * completely disabled prior to enabling the Rx unit.
2024 */
2025 hw->mac.ops.disable_rx_buff(hw);
2026
2027 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2028
2029 hw->mac.ops.enable_rx_buff(hw);
2030
2031 return 0;
2032 }
2033
2034 /**
2035 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2036 * @hw: pointer to hardware structure
2037 *
2038 * Verifies that installed the firmware version is 0.6 or higher
2039 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2040 *
2041 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2042 * if the FW version is not supported.
2043 **/
2044 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2045 {
2046 s32 status = IXGBE_ERR_EEPROM_VERSION;
2047 u16 fw_offset, fw_ptp_cfg_offset;
2048 u16 fw_version = 0;
2049
2050 /* firmware check is only necessary for SFI devices */
2051 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2052 status = 0;
2053 goto fw_version_out;
2054 }
2055
2056 /* get the offset to the Firmware Module block */
2057 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2058
2059 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2060 goto fw_version_out;
2061
2062 /* get the offset to the Pass Through Patch Configuration block */
2063 hw->eeprom.ops.read(hw, (fw_offset +
2064 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2065 &fw_ptp_cfg_offset);
2066
2067 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2068 goto fw_version_out;
2069
2070 /* get the firmware version */
2071 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2072 IXGBE_FW_PATCH_VERSION_4),
2073 &fw_version);
2074
2075 if (fw_version > 0x5)
2076 status = 0;
2077
2078 fw_version_out:
2079 return status;
2080 }
2081
2082 /**
2083 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2084 * @hw: pointer to hardware structure
2085 *
2086 * Returns true if the LESM FW module is present and enabled. Otherwise
2087 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
2088 **/
2089 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2090 {
2091 bool lesm_enabled = false;
2092 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2093 s32 status;
2094
2095 /* get the offset to the Firmware Module block */
2096 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2097
2098 if ((status != 0) ||
2099 (fw_offset == 0) || (fw_offset == 0xFFFF))
2100 goto out;
2101
2102 /* get the offset to the LESM Parameters block */
2103 status = hw->eeprom.ops.read(hw, (fw_offset +
2104 IXGBE_FW_LESM_PARAMETERS_PTR),
2105 &fw_lesm_param_offset);
2106
2107 if ((status != 0) ||
2108 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2109 goto out;
2110
2111 /* get the lesm state word */
2112 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2113 IXGBE_FW_LESM_STATE_1),
2114 &fw_lesm_state);
2115
2116 if ((status == 0) &&
2117 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2118 lesm_enabled = true;
2119
2120 out:
2121 return lesm_enabled;
2122 }
2123
2124 /**
2125 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2126 * fastest available method
2127 *
2128 * @hw: pointer to hardware structure
2129 * @offset: offset of word in EEPROM to read
2130 * @words: number of words
2131 * @data: word(s) read from the EEPROM
2132 *
2133 * Retrieves 16 bit word(s) read from EEPROM
2134 **/
2135 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2136 u16 words, u16 *data)
2137 {
2138 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2139 s32 ret_val = IXGBE_ERR_CONFIG;
2140
2141 /*
2142 * If EEPROM is detected and can be addressed using 14 bits,
2143 * use EERD otherwise use bit bang
2144 */
2145 if ((eeprom->type == ixgbe_eeprom_spi) &&
2146 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
2147 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2148 data);
2149 else
2150 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2151 words,
2152 data);
2153
2154 return ret_val;
2155 }
2156
2157 /**
2158 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2159 * fastest available method
2160 *
2161 * @hw: pointer to hardware structure
2162 * @offset: offset of word in the EEPROM to read
2163 * @data: word read from the EEPROM
2164 *
2165 * Reads a 16 bit word from the EEPROM
2166 **/
2167 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2168 u16 offset, u16 *data)
2169 {
2170 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2171 s32 ret_val = IXGBE_ERR_CONFIG;
2172
2173 /*
2174 * If EEPROM is detected and can be addressed using 14 bits,
2175 * use EERD otherwise use bit bang
2176 */
2177 if ((eeprom->type == ixgbe_eeprom_spi) &&
2178 (offset <= IXGBE_EERD_MAX_ADDR))
2179 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2180 else
2181 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2182
2183 return ret_val;
2184 }
2185
2186 /**
2187 * ixgbe_reset_pipeline_82599 - perform pipeline reset
2188 *
2189 * @hw: pointer to hardware structure
2190 *
2191 * Reset pipeline by asserting Restart_AN together with LMS change to ensure
2192 * full pipeline reset. Note - We must hold the SW/FW semaphore before writing
2193 * to AUTOC, so this function assumes the semaphore is held.
2194 **/
2195 s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw)
2196 {
2197 s32 ret_val;
2198 u32 anlp1_reg = 0;
2199 u32 i, autoc_reg, autoc2_reg;
2200
2201 /* Enable link if disabled in NVM */
2202 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2203 if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
2204 autoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
2205 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
2206 IXGBE_WRITE_FLUSH(hw);
2207 }
2208
2209 autoc_reg = hw->mac.cached_autoc;
2210 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2211
2212 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
2213 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg ^ IXGBE_AUTOC_LMS_1G_AN);
2214
2215 /* Wait for AN to leave state 0 */
2216 for (i = 0; i < 10; i++) {
2217 usleep_range(4000, 8000);
2218 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2219 if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)
2220 break;
2221 }
2222
2223 if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) {
2224 hw_dbg(hw, "auto negotiation not completed\n");
2225 ret_val = IXGBE_ERR_RESET_FAILED;
2226 goto reset_pipeline_out;
2227 }
2228
2229 ret_val = 0;
2230
2231 reset_pipeline_out:
2232 /* Write AUTOC register with original LMS field and Restart_AN */
2233 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2234 IXGBE_WRITE_FLUSH(hw);
2235
2236 return ret_val;
2237 }
2238
2239 static struct ixgbe_mac_operations mac_ops_82599 = {
2240 .init_hw = &ixgbe_init_hw_generic,
2241 .reset_hw = &ixgbe_reset_hw_82599,
2242 .start_hw = &ixgbe_start_hw_82599,
2243 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
2244 .get_media_type = &ixgbe_get_media_type_82599,
2245 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
2246 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
2247 .disable_rx_buff = &ixgbe_disable_rx_buff_generic,
2248 .enable_rx_buff = &ixgbe_enable_rx_buff_generic,
2249 .get_mac_addr = &ixgbe_get_mac_addr_generic,
2250 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
2251 .get_device_caps = &ixgbe_get_device_caps_generic,
2252 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
2253 .stop_adapter = &ixgbe_stop_adapter_generic,
2254 .get_bus_info = &ixgbe_get_bus_info_generic,
2255 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
2256 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2257 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
2258 .setup_link = &ixgbe_setup_mac_link_82599,
2259 .set_rxpba = &ixgbe_set_rxpba_generic,
2260 .check_link = &ixgbe_check_mac_link_generic,
2261 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2262 .led_on = &ixgbe_led_on_generic,
2263 .led_off = &ixgbe_led_off_generic,
2264 .blink_led_start = &ixgbe_blink_led_start_generic,
2265 .blink_led_stop = &ixgbe_blink_led_stop_generic,
2266 .set_rar = &ixgbe_set_rar_generic,
2267 .clear_rar = &ixgbe_clear_rar_generic,
2268 .set_vmdq = &ixgbe_set_vmdq_generic,
2269 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic,
2270 .clear_vmdq = &ixgbe_clear_vmdq_generic,
2271 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
2272 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2273 .enable_mc = &ixgbe_enable_mc_generic,
2274 .disable_mc = &ixgbe_disable_mc_generic,
2275 .clear_vfta = &ixgbe_clear_vfta_generic,
2276 .set_vfta = &ixgbe_set_vfta_generic,
2277 .fc_enable = &ixgbe_fc_enable_generic,
2278 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic,
2279 .init_uta_tables = &ixgbe_init_uta_tables_generic,
2280 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
2281 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing,
2282 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
2283 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync,
2284 .release_swfw_sync = &ixgbe_release_swfw_sync,
2285 .get_thermal_sensor_data = &ixgbe_get_thermal_sensor_data_generic,
2286 .init_thermal_sensor_thresh = &ixgbe_init_thermal_sensor_thresh_generic,
2287 .mng_fw_enabled = &ixgbe_mng_enabled,
2288 };
2289
2290 static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2291 .init_params = &ixgbe_init_eeprom_params_generic,
2292 .read = &ixgbe_read_eeprom_82599,
2293 .read_buffer = &ixgbe_read_eeprom_buffer_82599,
2294 .write = &ixgbe_write_eeprom_generic,
2295 .write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic,
2296 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic,
2297 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2298 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
2299 };
2300
2301 static struct ixgbe_phy_operations phy_ops_82599 = {
2302 .identify = &ixgbe_identify_phy_82599,
2303 .identify_sfp = &ixgbe_identify_sfp_module_generic,
2304 .init = &ixgbe_init_phy_ops_82599,
2305 .reset = &ixgbe_reset_phy_generic,
2306 .read_reg = &ixgbe_read_phy_reg_generic,
2307 .write_reg = &ixgbe_write_phy_reg_generic,
2308 .setup_link = &ixgbe_setup_phy_link_generic,
2309 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2310 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2311 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
2312 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic,
2313 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2314 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
2315 .check_overtemp = &ixgbe_tn_check_overtemp,
2316 };
2317
2318 struct ixgbe_info ixgbe_82599_info = {
2319 .mac = ixgbe_mac_82599EB,
2320 .get_invariants = &ixgbe_get_invariants_82599,
2321 .mac_ops = &mac_ops_82599,
2322 .eeprom_ops = &eeprom_ops_82599,
2323 .phy_ops = &phy_ops_82599,
2324 .mbx_ops = &mbx_ops_generic,
2325 };
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