?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux 3.11-rc3
[cris-mirror.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_ethtool.c
blob24e2e7aafda2d42201541ef9ee855ee26e1661cb
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 /* ethtool support for ixgbe */
29
30 #include <linux/interrupt.h>
31 #include <linux/types.h>
32 #include <linux/module.h>
33 #include <linux/slab.h>
34 #include <linux/pci.h>
35 #include <linux/netdevice.h>
36 #include <linux/ethtool.h>
37 #include <linux/vmalloc.h>
38 #include <linux/highmem.h>
39 #include <linux/uaccess.h>
40
41 #include "ixgbe.h"
42 #include "ixgbe_phy.h"
43
44
45 #define IXGBE_ALL_RAR_ENTRIES 16
46
47 enum {NETDEV_STATS, IXGBE_STATS};
48
49 struct ixgbe_stats {
50 char stat_string[ETH_GSTRING_LEN];
51 int type;
52 int sizeof_stat;
53 int stat_offset;
54 };
55
56 #define IXGBE_STAT(m) IXGBE_STATS, \
57 sizeof(((struct ixgbe_adapter *)0)->m), \
58 offsetof(struct ixgbe_adapter, m)
59 #define IXGBE_NETDEV_STAT(m) NETDEV_STATS, \
60 sizeof(((struct rtnl_link_stats64 *)0)->m), \
61 offsetof(struct rtnl_link_stats64, m)
62
63 static const struct ixgbe_stats ixgbe_gstrings_stats[] = {
64 {"rx_packets", IXGBE_NETDEV_STAT(rx_packets)},
65 {"tx_packets", IXGBE_NETDEV_STAT(tx_packets)},
66 {"rx_bytes", IXGBE_NETDEV_STAT(rx_bytes)},
67 {"tx_bytes", IXGBE_NETDEV_STAT(tx_bytes)},
68 {"rx_pkts_nic", IXGBE_STAT(stats.gprc)},
69 {"tx_pkts_nic", IXGBE_STAT(stats.gptc)},
70 {"rx_bytes_nic", IXGBE_STAT(stats.gorc)},
71 {"tx_bytes_nic", IXGBE_STAT(stats.gotc)},
72 {"lsc_int", IXGBE_STAT(lsc_int)},
73 {"tx_busy", IXGBE_STAT(tx_busy)},
74 {"non_eop_descs", IXGBE_STAT(non_eop_descs)},
75 {"rx_errors", IXGBE_NETDEV_STAT(rx_errors)},
76 {"tx_errors", IXGBE_NETDEV_STAT(tx_errors)},
77 {"rx_dropped", IXGBE_NETDEV_STAT(rx_dropped)},
78 {"tx_dropped", IXGBE_NETDEV_STAT(tx_dropped)},
79 {"multicast", IXGBE_NETDEV_STAT(multicast)},
80 {"broadcast", IXGBE_STAT(stats.bprc)},
81 {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
82 {"collisions", IXGBE_NETDEV_STAT(collisions)},
83 {"rx_over_errors", IXGBE_NETDEV_STAT(rx_over_errors)},
84 {"rx_crc_errors", IXGBE_NETDEV_STAT(rx_crc_errors)},
85 {"rx_frame_errors", IXGBE_NETDEV_STAT(rx_frame_errors)},
86 {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)},
87 {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)},
88 {"fdir_match", IXGBE_STAT(stats.fdirmatch)},
89 {"fdir_miss", IXGBE_STAT(stats.fdirmiss)},
90 {"fdir_overflow", IXGBE_STAT(fdir_overflow)},
91 {"rx_fifo_errors", IXGBE_NETDEV_STAT(rx_fifo_errors)},
92 {"rx_missed_errors", IXGBE_NETDEV_STAT(rx_missed_errors)},
93 {"tx_aborted_errors", IXGBE_NETDEV_STAT(tx_aborted_errors)},
94 {"tx_carrier_errors", IXGBE_NETDEV_STAT(tx_carrier_errors)},
95 {"tx_fifo_errors", IXGBE_NETDEV_STAT(tx_fifo_errors)},
96 {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(tx_heartbeat_errors)},
97 {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
98 {"tx_restart_queue", IXGBE_STAT(restart_queue)},
99 {"rx_long_length_errors", IXGBE_STAT(stats.roc)},
100 {"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
101 {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
102 {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
103 {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
104 {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
105 {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
106 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
107 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
108 {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)},
109 {"os2bmc_rx_by_bmc", IXGBE_STAT(stats.o2bgptc)},
110 {"os2bmc_tx_by_bmc", IXGBE_STAT(stats.b2ospc)},
111 {"os2bmc_tx_by_host", IXGBE_STAT(stats.o2bspc)},
112 {"os2bmc_rx_by_host", IXGBE_STAT(stats.b2ogprc)},
113 #ifdef IXGBE_FCOE
114 {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)},
115 {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)},
116 {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)},
117 {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)},
118 {"fcoe_noddp", IXGBE_STAT(stats.fcoe_noddp)},
119 {"fcoe_noddp_ext_buff", IXGBE_STAT(stats.fcoe_noddp_ext_buff)},
120 {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)},
121 {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)},
122 #endif /* IXGBE_FCOE */
123 };
124
125 /* ixgbe allocates num_tx_queues and num_rx_queues symmetrically so
126 * we set the num_rx_queues to evaluate to num_tx_queues. This is
127 * used because we do not have a good way to get the max number of
128 * rx queues with CONFIG_RPS disabled.
129 */
130 #define IXGBE_NUM_RX_QUEUES netdev->num_tx_queues
131
132 #define IXGBE_QUEUE_STATS_LEN ( \
133 (netdev->num_tx_queues + IXGBE_NUM_RX_QUEUES) * \
134 (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
135 #define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
136 #define IXGBE_PB_STATS_LEN ( \
137 (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
138 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
139 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
140 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
141 / sizeof(u64))
142 #define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
143 IXGBE_PB_STATS_LEN + \
144 IXGBE_QUEUE_STATS_LEN)
145
146 static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
147 "Register test (offline)", "Eeprom test (offline)",
148 "Interrupt test (offline)", "Loopback test (offline)",
149 "Link test (on/offline)"
150 };
151 #define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
152
153 static int ixgbe_get_settings(struct net_device *netdev,
154 struct ethtool_cmd *ecmd)
155 {
156 struct ixgbe_adapter *adapter = netdev_priv(netdev);
157 struct ixgbe_hw *hw = &adapter->hw;
158 ixgbe_link_speed supported_link;
159 u32 link_speed = 0;
160 bool autoneg = false;
161 bool link_up;
162
163 hw->mac.ops.get_link_capabilities(hw, &supported_link, &autoneg);
164
165 /* set the supported link speeds */
166 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL)
167 ecmd->supported |= SUPPORTED_10000baseT_Full;
168 if (supported_link & IXGBE_LINK_SPEED_1GB_FULL)
169 ecmd->supported |= SUPPORTED_1000baseT_Full;
170 if (supported_link & IXGBE_LINK_SPEED_100_FULL)
171 ecmd->supported |= SUPPORTED_100baseT_Full;
172
173 /* set the advertised speeds */
174 if (hw->phy.autoneg_advertised) {
175 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
176 ecmd->advertising |= ADVERTISED_100baseT_Full;
177 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
178 ecmd->advertising |= ADVERTISED_10000baseT_Full;
179 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
180 ecmd->advertising |= ADVERTISED_1000baseT_Full;
181 } else {
182 /* default modes in case phy.autoneg_advertised isn't set */
183 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL)
184 ecmd->advertising |= ADVERTISED_10000baseT_Full;
185 if (supported_link & IXGBE_LINK_SPEED_1GB_FULL)
186 ecmd->advertising |= ADVERTISED_1000baseT_Full;
187 if (supported_link & IXGBE_LINK_SPEED_100_FULL)
188 ecmd->advertising |= ADVERTISED_100baseT_Full;
189 }
190
191 if (autoneg) {
192 ecmd->supported |= SUPPORTED_Autoneg;
193 ecmd->advertising |= ADVERTISED_Autoneg;
194 ecmd->autoneg = AUTONEG_ENABLE;
195 } else
196 ecmd->autoneg = AUTONEG_DISABLE;
197
198 ecmd->transceiver = XCVR_EXTERNAL;
199
200 /* Determine the remaining settings based on the PHY type. */
201 switch (adapter->hw.phy.type) {
202 case ixgbe_phy_tn:
203 case ixgbe_phy_aq:
204 case ixgbe_phy_cu_unknown:
205 ecmd->supported |= SUPPORTED_TP;
206 ecmd->advertising |= ADVERTISED_TP;
207 ecmd->port = PORT_TP;
208 break;
209 case ixgbe_phy_qt:
210 ecmd->supported |= SUPPORTED_FIBRE;
211 ecmd->advertising |= ADVERTISED_FIBRE;
212 ecmd->port = PORT_FIBRE;
213 break;
214 case ixgbe_phy_nl:
215 case ixgbe_phy_sfp_passive_tyco:
216 case ixgbe_phy_sfp_passive_unknown:
217 case ixgbe_phy_sfp_ftl:
218 case ixgbe_phy_sfp_avago:
219 case ixgbe_phy_sfp_intel:
220 case ixgbe_phy_sfp_unknown:
221 /* SFP+ devices, further checking needed */
222 switch (adapter->hw.phy.sfp_type) {
223 case ixgbe_sfp_type_da_cu:
224 case ixgbe_sfp_type_da_cu_core0:
225 case ixgbe_sfp_type_da_cu_core1:
226 ecmd->supported |= SUPPORTED_FIBRE;
227 ecmd->advertising |= ADVERTISED_FIBRE;
228 ecmd->port = PORT_DA;
229 break;
230 case ixgbe_sfp_type_sr:
231 case ixgbe_sfp_type_lr:
232 case ixgbe_sfp_type_srlr_core0:
233 case ixgbe_sfp_type_srlr_core1:
234 case ixgbe_sfp_type_1g_sx_core0:
235 case ixgbe_sfp_type_1g_sx_core1:
236 case ixgbe_sfp_type_1g_lx_core0:
237 case ixgbe_sfp_type_1g_lx_core1:
238 ecmd->supported |= SUPPORTED_FIBRE;
239 ecmd->advertising |= ADVERTISED_FIBRE;
240 ecmd->port = PORT_FIBRE;
241 break;
242 case ixgbe_sfp_type_not_present:
243 ecmd->supported |= SUPPORTED_FIBRE;
244 ecmd->advertising |= ADVERTISED_FIBRE;
245 ecmd->port = PORT_NONE;
246 break;
247 case ixgbe_sfp_type_1g_cu_core0:
248 case ixgbe_sfp_type_1g_cu_core1:
249 ecmd->supported |= SUPPORTED_TP;
250 ecmd->advertising |= ADVERTISED_TP;
251 ecmd->port = PORT_TP;
252 break;
253 case ixgbe_sfp_type_unknown:
254 default:
255 ecmd->supported |= SUPPORTED_FIBRE;
256 ecmd->advertising |= ADVERTISED_FIBRE;
257 ecmd->port = PORT_OTHER;
258 break;
259 }
260 break;
261 case ixgbe_phy_xaui:
262 ecmd->supported |= SUPPORTED_FIBRE;
263 ecmd->advertising |= ADVERTISED_FIBRE;
264 ecmd->port = PORT_NONE;
265 break;
266 case ixgbe_phy_unknown:
267 case ixgbe_phy_generic:
268 case ixgbe_phy_sfp_unsupported:
269 default:
270 ecmd->supported |= SUPPORTED_FIBRE;
271 ecmd->advertising |= ADVERTISED_FIBRE;
272 ecmd->port = PORT_OTHER;
273 break;
274 }
275
276 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
277 if (link_up) {
278 switch (link_speed) {
279 case IXGBE_LINK_SPEED_10GB_FULL:
280 ethtool_cmd_speed_set(ecmd, SPEED_10000);
281 break;
282 case IXGBE_LINK_SPEED_1GB_FULL:
283 ethtool_cmd_speed_set(ecmd, SPEED_1000);
284 break;
285 case IXGBE_LINK_SPEED_100_FULL:
286 ethtool_cmd_speed_set(ecmd, SPEED_100);
287 break;
288 default:
289 break;
290 }
291 ecmd->duplex = DUPLEX_FULL;
292 } else {
293 ethtool_cmd_speed_set(ecmd, -1);
294 ecmd->duplex = -1;
295 }
296
297 return 0;
298 }
299
300 static int ixgbe_set_settings(struct net_device *netdev,
301 struct ethtool_cmd *ecmd)
302 {
303 struct ixgbe_adapter *adapter = netdev_priv(netdev);
304 struct ixgbe_hw *hw = &adapter->hw;
305 u32 advertised, old;
306 s32 err = 0;
307
308 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
309 (hw->phy.multispeed_fiber)) {
310 /*
311 * this function does not support duplex forcing, but can
312 * limit the advertising of the adapter to the specified speed
313 */
314 if (ecmd->autoneg == AUTONEG_DISABLE)
315 return -EINVAL;
316
317 if (ecmd->advertising & ~ecmd->supported)
318 return -EINVAL;
319
320 old = hw->phy.autoneg_advertised;
321 advertised = 0;
322 if (ecmd->advertising & ADVERTISED_10000baseT_Full)
323 advertised |= IXGBE_LINK_SPEED_10GB_FULL;
324
325 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
326 advertised |= IXGBE_LINK_SPEED_1GB_FULL;
327
328 if (ecmd->advertising & ADVERTISED_100baseT_Full)
329 advertised |= IXGBE_LINK_SPEED_100_FULL;
330
331 if (old == advertised)
332 return err;
333 /* this sets the link speed and restarts auto-neg */
334 hw->mac.autotry_restart = true;
335 err = hw->mac.ops.setup_link(hw, advertised, true);
336 if (err) {
337 e_info(probe, "setup link failed with code %d\n", err);
338 hw->mac.ops.setup_link(hw, old, true);
339 }
340 } else {
341 /* in this case we currently only support 10Gb/FULL */
342 u32 speed = ethtool_cmd_speed(ecmd);
343 if ((ecmd->autoneg == AUTONEG_ENABLE) ||
344 (ecmd->advertising != ADVERTISED_10000baseT_Full) ||
345 (speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL))
346 return -EINVAL;
347 }
348
349 return err;
350 }
351
352 static void ixgbe_get_pauseparam(struct net_device *netdev,
353 struct ethtool_pauseparam *pause)
354 {
355 struct ixgbe_adapter *adapter = netdev_priv(netdev);
356 struct ixgbe_hw *hw = &adapter->hw;
357
358 if (hw->fc.disable_fc_autoneg)
359 pause->autoneg = 0;
360 else
361 pause->autoneg = 1;
362
363 if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
364 pause->rx_pause = 1;
365 } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
366 pause->tx_pause = 1;
367 } else if (hw->fc.current_mode == ixgbe_fc_full) {
368 pause->rx_pause = 1;
369 pause->tx_pause = 1;
370 }
371 }
372
373 static int ixgbe_set_pauseparam(struct net_device *netdev,
374 struct ethtool_pauseparam *pause)
375 {
376 struct ixgbe_adapter *adapter = netdev_priv(netdev);
377 struct ixgbe_hw *hw = &adapter->hw;
378 struct ixgbe_fc_info fc = hw->fc;
379
380 /* 82598 does no support link flow control with DCB enabled */
381 if ((hw->mac.type == ixgbe_mac_82598EB) &&
382 (adapter->flags & IXGBE_FLAG_DCB_ENABLED))
383 return -EINVAL;
384
385 /* some devices do not support autoneg of link flow control */
386 if ((pause->autoneg == AUTONEG_ENABLE) &&
387 (ixgbe_device_supports_autoneg_fc(hw) != 0))
388 return -EINVAL;
389
390 fc.disable_fc_autoneg = (pause->autoneg != AUTONEG_ENABLE);
391
392 if ((pause->rx_pause && pause->tx_pause) || pause->autoneg)
393 fc.requested_mode = ixgbe_fc_full;
394 else if (pause->rx_pause && !pause->tx_pause)
395 fc.requested_mode = ixgbe_fc_rx_pause;
396 else if (!pause->rx_pause && pause->tx_pause)
397 fc.requested_mode = ixgbe_fc_tx_pause;
398 else
399 fc.requested_mode = ixgbe_fc_none;
400
401 /* if the thing changed then we'll update and use new autoneg */
402 if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) {
403 hw->fc = fc;
404 if (netif_running(netdev))
405 ixgbe_reinit_locked(adapter);
406 else
407 ixgbe_reset(adapter);
408 }
409
410 return 0;
411 }
412
413 static u32 ixgbe_get_msglevel(struct net_device *netdev)
414 {
415 struct ixgbe_adapter *adapter = netdev_priv(netdev);
416 return adapter->msg_enable;
417 }
418
419 static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
420 {
421 struct ixgbe_adapter *adapter = netdev_priv(netdev);
422 adapter->msg_enable = data;
423 }
424
425 static int ixgbe_get_regs_len(struct net_device *netdev)
426 {
427 #define IXGBE_REGS_LEN 1129
428 return IXGBE_REGS_LEN * sizeof(u32);
429 }
430
431 #define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
432
433 static void ixgbe_get_regs(struct net_device *netdev,
434 struct ethtool_regs *regs, void *p)
435 {
436 struct ixgbe_adapter *adapter = netdev_priv(netdev);
437 struct ixgbe_hw *hw = &adapter->hw;
438 u32 *regs_buff = p;
439 u8 i;
440
441 memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
442
443 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
444 hw->device_id;
445
446 /* General Registers */
447 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
448 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
449 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
450 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
451 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
452 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
453 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
454 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
455
456 /* NVM Register */
457 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC);
458 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
459 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA);
460 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
461 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
462 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
463 regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
464 regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
465 regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
466 regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC);
467
468 /* Interrupt */
469 /* don't read EICR because it can clear interrupt causes, instead
470 * read EICS which is a shadow but doesn't clear EICR */
471 regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
472 regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
473 regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
474 regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
475 regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
476 regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
477 regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
478 regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
479 regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
480 regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
481 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
482 regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
483
484 /* Flow Control */
485 regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
486 regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0));
487 regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1));
488 regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2));
489 regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3));
490 for (i = 0; i < 8; i++) {
491 switch (hw->mac.type) {
492 case ixgbe_mac_82598EB:
493 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
494 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
495 break;
496 case ixgbe_mac_82599EB:
497 case ixgbe_mac_X540:
498 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i));
499 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
500 break;
501 default:
502 break;
503 }
504 }
505 regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
506 regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
507
508 /* Receive DMA */
509 for (i = 0; i < 64; i++)
510 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
511 for (i = 0; i < 64; i++)
512 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
513 for (i = 0; i < 64; i++)
514 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
515 for (i = 0; i < 64; i++)
516 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
517 for (i = 0; i < 64; i++)
518 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
519 for (i = 0; i < 64; i++)
520 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
521 for (i = 0; i < 16; i++)
522 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
523 for (i = 0; i < 16; i++)
524 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
525 regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
526 for (i = 0; i < 8; i++)
527 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
528 regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
529 regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
530
531 /* Receive */
532 regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
533 regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
534 for (i = 0; i < 16; i++)
535 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
536 for (i = 0; i < 16; i++)
537 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
538 regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
539 regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
540 regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
541 regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
542 regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
543 regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
544 for (i = 0; i < 8; i++)
545 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
546 for (i = 0; i < 8; i++)
547 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
548 regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
549
550 /* Transmit */
551 for (i = 0; i < 32; i++)
552 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
553 for (i = 0; i < 32; i++)
554 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
555 for (i = 0; i < 32; i++)
556 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
557 for (i = 0; i < 32; i++)
558 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
559 for (i = 0; i < 32; i++)
560 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
561 for (i = 0; i < 32; i++)
562 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
563 for (i = 0; i < 32; i++)
564 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
565 for (i = 0; i < 32; i++)
566 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
567 regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
568 for (i = 0; i < 16; i++)
569 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
570 regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
571 for (i = 0; i < 8; i++)
572 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
573 regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
574
575 /* Wake Up */
576 regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
577 regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
578 regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
579 regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
580 regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
581 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
582 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
583 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
584 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
585
586 /* DCB */
587 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS);
588 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
589 regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
590 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
591 for (i = 0; i < 8; i++)
592 regs_buff[833 + i] = IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
593 for (i = 0; i < 8; i++)
594 regs_buff[841 + i] = IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
595 for (i = 0; i < 8; i++)
596 regs_buff[849 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
597 for (i = 0; i < 8; i++)
598 regs_buff[857 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
599 for (i = 0; i < 8; i++)
600 regs_buff[865 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i));
601 for (i = 0; i < 8; i++)
602 regs_buff[873 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i));
603
604 /* Statistics */
605 regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
606 regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
607 regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
608 regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
609 for (i = 0; i < 8; i++)
610 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
611 regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
612 regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
613 regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
614 regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
615 regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
616 regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
617 regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
618 for (i = 0; i < 8; i++)
619 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
620 for (i = 0; i < 8; i++)
621 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
622 for (i = 0; i < 8; i++)
623 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
624 for (i = 0; i < 8; i++)
625 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
626 regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
627 regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
628 regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
629 regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
630 regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
631 regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
632 regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
633 regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
634 regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
635 regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
636 regs_buff[942] = IXGBE_GET_STAT(adapter, gorc);
637 regs_buff[944] = IXGBE_GET_STAT(adapter, gotc);
638 for (i = 0; i < 8; i++)
639 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
640 regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
641 regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
642 regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
643 regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
644 regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
645 regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
646 regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
647 regs_buff[961] = IXGBE_GET_STAT(adapter, tor);
648 regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
649 regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
650 regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
651 regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
652 regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
653 regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
654 regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
655 regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
656 regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
657 regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
658 regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
659 for (i = 0; i < 16; i++)
660 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
661 for (i = 0; i < 16; i++)
662 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
663 for (i = 0; i < 16; i++)
664 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
665 for (i = 0; i < 16; i++)
666 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
667
668 /* MAC */
669 regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
670 regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
671 regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
672 regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
673 regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
674 regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
675 regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
676 regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
677 regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
678 regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
679 regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
680 regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
681 regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
682 regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
683 regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
684 regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
685 regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
686 regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
687 regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
688 regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
689 regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
690 regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
691 regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
692 regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
693 regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
694 regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
695 regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
696 regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
697 regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
698 regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
699 regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
700 regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
701 regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
702
703 /* Diagnostic */
704 regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
705 for (i = 0; i < 8; i++)
706 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
707 regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
708 for (i = 0; i < 4; i++)
709 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
710 regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
711 regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
712 for (i = 0; i < 8; i++)
713 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
714 regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
715 for (i = 0; i < 4; i++)
716 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
717 regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
718 regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
719 regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0);
720 regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1);
721 regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2);
722 regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3);
723 regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
724 regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0);
725 regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1);
726 regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2);
727 regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3);
728 for (i = 0; i < 8; i++)
729 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
730 regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
731 regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
732 regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
733 regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
734 regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
735 regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
736 regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
737 regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
738 regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
739
740 /* 82599 X540 specific registers */
741 regs_buff[1128] = IXGBE_READ_REG(hw, IXGBE_MFLCN);
742 }
743
744 static int ixgbe_get_eeprom_len(struct net_device *netdev)
745 {
746 struct ixgbe_adapter *adapter = netdev_priv(netdev);
747 return adapter->hw.eeprom.word_size * 2;
748 }
749
750 static int ixgbe_get_eeprom(struct net_device *netdev,
751 struct ethtool_eeprom *eeprom, u8 *bytes)
752 {
753 struct ixgbe_adapter *adapter = netdev_priv(netdev);
754 struct ixgbe_hw *hw = &adapter->hw;
755 u16 *eeprom_buff;
756 int first_word, last_word, eeprom_len;
757 int ret_val = 0;
758 u16 i;
759
760 if (eeprom->len == 0)
761 return -EINVAL;
762
763 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
764
765 first_word = eeprom->offset >> 1;
766 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
767 eeprom_len = last_word - first_word + 1;
768
769 eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL);
770 if (!eeprom_buff)
771 return -ENOMEM;
772
773 ret_val = hw->eeprom.ops.read_buffer(hw, first_word, eeprom_len,
774 eeprom_buff);
775
776 /* Device's eeprom is always little-endian, word addressable */
777 for (i = 0; i < eeprom_len; i++)
778 le16_to_cpus(&eeprom_buff[i]);
779
780 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
781 kfree(eeprom_buff);
782
783 return ret_val;
784 }
785
786 static int ixgbe_set_eeprom(struct net_device *netdev,
787 struct ethtool_eeprom *eeprom, u8 *bytes)
788 {
789 struct ixgbe_adapter *adapter = netdev_priv(netdev);
790 struct ixgbe_hw *hw = &adapter->hw;
791 u16 *eeprom_buff;
792 void *ptr;
793 int max_len, first_word, last_word, ret_val = 0;
794 u16 i;
795
796 if (eeprom->len == 0)
797 return -EINVAL;
798
799 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
800 return -EINVAL;
801
802 max_len = hw->eeprom.word_size * 2;
803
804 first_word = eeprom->offset >> 1;
805 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
806 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
807 if (!eeprom_buff)
808 return -ENOMEM;
809
810 ptr = eeprom_buff;
811
812 if (eeprom->offset & 1) {
813 /*
814 * need read/modify/write of first changed EEPROM word
815 * only the second byte of the word is being modified
816 */
817 ret_val = hw->eeprom.ops.read(hw, first_word, &eeprom_buff[0]);
818 if (ret_val)
819 goto err;
820
821 ptr++;
822 }
823 if ((eeprom->offset + eeprom->len) & 1) {
824 /*
825 * need read/modify/write of last changed EEPROM word
826 * only the first byte of the word is being modified
827 */
828 ret_val = hw->eeprom.ops.read(hw, last_word,
829 &eeprom_buff[last_word - first_word]);
830 if (ret_val)
831 goto err;
832 }
833
834 /* Device's eeprom is always little-endian, word addressable */
835 for (i = 0; i < last_word - first_word + 1; i++)
836 le16_to_cpus(&eeprom_buff[i]);
837
838 memcpy(ptr, bytes, eeprom->len);
839
840 for (i = 0; i < last_word - first_word + 1; i++)
841 cpu_to_le16s(&eeprom_buff[i]);
842
843 ret_val = hw->eeprom.ops.write_buffer(hw, first_word,
844 last_word - first_word + 1,
845 eeprom_buff);
846
847 /* Update the checksum */
848 if (ret_val == 0)
849 hw->eeprom.ops.update_checksum(hw);
850
851 err:
852 kfree(eeprom_buff);
853 return ret_val;
854 }
855
856 static void ixgbe_get_drvinfo(struct net_device *netdev,
857 struct ethtool_drvinfo *drvinfo)
858 {
859 struct ixgbe_adapter *adapter = netdev_priv(netdev);
860 u32 nvm_track_id;
861
862 strlcpy(drvinfo->driver, ixgbe_driver_name, sizeof(drvinfo->driver));
863 strlcpy(drvinfo->version, ixgbe_driver_version,
864 sizeof(drvinfo->version));
865
866 nvm_track_id = (adapter->eeprom_verh << 16) |
867 adapter->eeprom_verl;
868 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), "0x%08x",
869 nvm_track_id);
870
871 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
872 sizeof(drvinfo->bus_info));
873 drvinfo->n_stats = IXGBE_STATS_LEN;
874 drvinfo->testinfo_len = IXGBE_TEST_LEN;
875 drvinfo->regdump_len = ixgbe_get_regs_len(netdev);
876 }
877
878 static void ixgbe_get_ringparam(struct net_device *netdev,
879 struct ethtool_ringparam *ring)
880 {
881 struct ixgbe_adapter *adapter = netdev_priv(netdev);
882 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
883 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
884
885 ring->rx_max_pending = IXGBE_MAX_RXD;
886 ring->tx_max_pending = IXGBE_MAX_TXD;
887 ring->rx_pending = rx_ring->count;
888 ring->tx_pending = tx_ring->count;
889 }
890
891 static int ixgbe_set_ringparam(struct net_device *netdev,
892 struct ethtool_ringparam *ring)
893 {
894 struct ixgbe_adapter *adapter = netdev_priv(netdev);
895 struct ixgbe_ring *temp_ring;
896 int i, err = 0;
897 u32 new_rx_count, new_tx_count;
898
899 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
900 return -EINVAL;
901
902 new_tx_count = clamp_t(u32, ring->tx_pending,
903 IXGBE_MIN_TXD, IXGBE_MAX_TXD);
904 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
905
906 new_rx_count = clamp_t(u32, ring->rx_pending,
907 IXGBE_MIN_RXD, IXGBE_MAX_RXD);
908 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
909
910 if ((new_tx_count == adapter->tx_ring_count) &&
911 (new_rx_count == adapter->rx_ring_count)) {
912 /* nothing to do */
913 return 0;
914 }
915
916 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
917 usleep_range(1000, 2000);
918
919 if (!netif_running(adapter->netdev)) {
920 for (i = 0; i < adapter->num_tx_queues; i++)
921 adapter->tx_ring[i]->count = new_tx_count;
922 for (i = 0; i < adapter->num_rx_queues; i++)
923 adapter->rx_ring[i]->count = new_rx_count;
924 adapter->tx_ring_count = new_tx_count;
925 adapter->rx_ring_count = new_rx_count;
926 goto clear_reset;
927 }
928
929 /* allocate temporary buffer to store rings in */
930 i = max_t(int, adapter->num_tx_queues, adapter->num_rx_queues);
931 temp_ring = vmalloc(i * sizeof(struct ixgbe_ring));
932
933 if (!temp_ring) {
934 err = -ENOMEM;
935 goto clear_reset;
936 }
937
938 ixgbe_down(adapter);
939
940 /*
941 * Setup new Tx resources and free the old Tx resources in that order.
942 * We can then assign the new resources to the rings via a memcpy.
943 * The advantage to this approach is that we are guaranteed to still
944 * have resources even in the case of an allocation failure.
945 */
946 if (new_tx_count != adapter->tx_ring_count) {
947 for (i = 0; i < adapter->num_tx_queues; i++) {
948 memcpy(&temp_ring[i], adapter->tx_ring[i],
949 sizeof(struct ixgbe_ring));
950
951 temp_ring[i].count = new_tx_count;
952 err = ixgbe_setup_tx_resources(&temp_ring[i]);
953 if (err) {
954 while (i) {
955 i--;
956 ixgbe_free_tx_resources(&temp_ring[i]);
957 }
958 goto err_setup;
959 }
960 }
961
962 for (i = 0; i < adapter->num_tx_queues; i++) {
963 ixgbe_free_tx_resources(adapter->tx_ring[i]);
964
965 memcpy(adapter->tx_ring[i], &temp_ring[i],
966 sizeof(struct ixgbe_ring));
967 }
968
969 adapter->tx_ring_count = new_tx_count;
970 }
971
972 /* Repeat the process for the Rx rings if needed */
973 if (new_rx_count != adapter->rx_ring_count) {
974 for (i = 0; i < adapter->num_rx_queues; i++) {
975 memcpy(&temp_ring[i], adapter->rx_ring[i],
976 sizeof(struct ixgbe_ring));
977
978 temp_ring[i].count = new_rx_count;
979 err = ixgbe_setup_rx_resources(&temp_ring[i]);
980 if (err) {
981 while (i) {
982 i--;
983 ixgbe_free_rx_resources(&temp_ring[i]);
984 }
985 goto err_setup;
986 }
987
988 }
989
990 for (i = 0; i < adapter->num_rx_queues; i++) {
991 ixgbe_free_rx_resources(adapter->rx_ring[i]);
992
993 memcpy(adapter->rx_ring[i], &temp_ring[i],
994 sizeof(struct ixgbe_ring));
995 }
996
997 adapter->rx_ring_count = new_rx_count;
998 }
999
1000 err_setup:
1001 ixgbe_up(adapter);
1002 vfree(temp_ring);
1003 clear_reset:
1004 clear_bit(__IXGBE_RESETTING, &adapter->state);
1005 return err;
1006 }
1007
1008 static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
1009 {
1010 switch (sset) {
1011 case ETH_SS_TEST:
1012 return IXGBE_TEST_LEN;
1013 case ETH_SS_STATS:
1014 return IXGBE_STATS_LEN;
1015 default:
1016 return -EOPNOTSUPP;
1017 }
1018 }
1019
1020 static void ixgbe_get_ethtool_stats(struct net_device *netdev,
1021 struct ethtool_stats *stats, u64 *data)
1022 {
1023 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1024 struct rtnl_link_stats64 temp;
1025 const struct rtnl_link_stats64 *net_stats;
1026 unsigned int start;
1027 struct ixgbe_ring *ring;
1028 int i, j;
1029 char *p = NULL;
1030
1031 ixgbe_update_stats(adapter);
1032 net_stats = dev_get_stats(netdev, &temp);
1033 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1034 switch (ixgbe_gstrings_stats[i].type) {
1035 case NETDEV_STATS:
1036 p = (char *) net_stats +
1037 ixgbe_gstrings_stats[i].stat_offset;
1038 break;
1039 case IXGBE_STATS:
1040 p = (char *) adapter +
1041 ixgbe_gstrings_stats[i].stat_offset;
1042 break;
1043 default:
1044 data[i] = 0;
1045 continue;
1046 }
1047
1048 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
1049 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
1050 }
1051 for (j = 0; j < IXGBE_NUM_RX_QUEUES; j++) {
1052 ring = adapter->tx_ring[j];
1053 if (!ring) {
1054 data[i] = 0;
1055 data[i+1] = 0;
1056 i += 2;
1057 #ifdef LL_EXTENDED_STATS
1058 data[i] = 0;
1059 data[i+1] = 0;
1060 data[i+2] = 0;
1061 i += 3;
1062 #endif
1063 continue;
1064 }
1065
1066 do {
1067 start = u64_stats_fetch_begin_bh(&ring->syncp);
1068 data[i] = ring->stats.packets;
1069 data[i+1] = ring->stats.bytes;
1070 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
1071 i += 2;
1072 #ifdef LL_EXTENDED_STATS
1073 data[i] = ring->stats.yields;
1074 data[i+1] = ring->stats.misses;
1075 data[i+2] = ring->stats.cleaned;
1076 i += 3;
1077 #endif
1078 }
1079 for (j = 0; j < IXGBE_NUM_RX_QUEUES; j++) {
1080 ring = adapter->rx_ring[j];
1081 if (!ring) {
1082 data[i] = 0;
1083 data[i+1] = 0;
1084 i += 2;
1085 #ifdef LL_EXTENDED_STATS
1086 data[i] = 0;
1087 data[i+1] = 0;
1088 data[i+2] = 0;
1089 i += 3;
1090 #endif
1091 continue;
1092 }
1093
1094 do {
1095 start = u64_stats_fetch_begin_bh(&ring->syncp);
1096 data[i] = ring->stats.packets;
1097 data[i+1] = ring->stats.bytes;
1098 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
1099 i += 2;
1100 #ifdef LL_EXTENDED_STATS
1101 data[i] = ring->stats.yields;
1102 data[i+1] = ring->stats.misses;
1103 data[i+2] = ring->stats.cleaned;
1104 i += 3;
1105 #endif
1106 }
1107
1108 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) {
1109 data[i++] = adapter->stats.pxontxc[j];
1110 data[i++] = adapter->stats.pxofftxc[j];
1111 }
1112 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) {
1113 data[i++] = adapter->stats.pxonrxc[j];
1114 data[i++] = adapter->stats.pxoffrxc[j];
1115 }
1116 }
1117
1118 static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
1119 u8 *data)
1120 {
1121 char *p = (char *)data;
1122 int i;
1123
1124 switch (stringset) {
1125 case ETH_SS_TEST:
1126 for (i = 0; i < IXGBE_TEST_LEN; i++) {
1127 memcpy(data, ixgbe_gstrings_test[i], ETH_GSTRING_LEN);
1128 data += ETH_GSTRING_LEN;
1129 }
1130 break;
1131 case ETH_SS_STATS:
1132 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1133 memcpy(p, ixgbe_gstrings_stats[i].stat_string,
1134 ETH_GSTRING_LEN);
1135 p += ETH_GSTRING_LEN;
1136 }
1137 for (i = 0; i < netdev->num_tx_queues; i++) {
1138 sprintf(p, "tx_queue_%u_packets", i);
1139 p += ETH_GSTRING_LEN;
1140 sprintf(p, "tx_queue_%u_bytes", i);
1141 p += ETH_GSTRING_LEN;
1142 #ifdef LL_EXTENDED_STATS
1143 sprintf(p, "tx_q_%u_napi_yield", i);
1144 p += ETH_GSTRING_LEN;
1145 sprintf(p, "tx_q_%u_misses", i);
1146 p += ETH_GSTRING_LEN;
1147 sprintf(p, "tx_q_%u_cleaned", i);
1148 p += ETH_GSTRING_LEN;
1149 #endif /* LL_EXTENDED_STATS */
1150 }
1151 for (i = 0; i < IXGBE_NUM_RX_QUEUES; i++) {
1152 sprintf(p, "rx_queue_%u_packets", i);
1153 p += ETH_GSTRING_LEN;
1154 sprintf(p, "rx_queue_%u_bytes", i);
1155 p += ETH_GSTRING_LEN;
1156 #ifdef LL_EXTENDED_STATS
1157 sprintf(p, "rx_q_%u_ll_poll_yield", i);
1158 p += ETH_GSTRING_LEN;
1159 sprintf(p, "rx_q_%u_misses", i);
1160 p += ETH_GSTRING_LEN;
1161 sprintf(p, "rx_q_%u_cleaned", i);
1162 p += ETH_GSTRING_LEN;
1163 #endif /* LL_EXTENDED_STATS */
1164 }
1165 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
1166 sprintf(p, "tx_pb_%u_pxon", i);
1167 p += ETH_GSTRING_LEN;
1168 sprintf(p, "tx_pb_%u_pxoff", i);
1169 p += ETH_GSTRING_LEN;
1170 }
1171 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
1172 sprintf(p, "rx_pb_%u_pxon", i);
1173 p += ETH_GSTRING_LEN;
1174 sprintf(p, "rx_pb_%u_pxoff", i);
1175 p += ETH_GSTRING_LEN;
1176 }
1177 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
1178 break;
1179 }
1180 }
1181
1182 static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
1183 {
1184 struct ixgbe_hw *hw = &adapter->hw;
1185 bool link_up;
1186 u32 link_speed = 0;
1187 *data = 0;
1188
1189 hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
1190 if (link_up)
1191 return *data;
1192 else
1193 *data = 1;
1194 return *data;
1195 }
1196
1197 /* ethtool register test data */
1198 struct ixgbe_reg_test {
1199 u16 reg;
1200 u8 array_len;
1201 u8 test_type;
1202 u32 mask;
1203 u32 write;
1204 };
1205
1206 /* In the hardware, registers are laid out either singly, in arrays
1207 * spaced 0x40 bytes apart, or in contiguous tables. We assume
1208 * most tests take place on arrays or single registers (handled
1209 * as a single-element array) and special-case the tables.
1210 * Table tests are always pattern tests.
1211 *
1212 * We also make provision for some required setup steps by specifying
1213 * registers to be written without any read-back testing.
1214 */
1215
1216 #define PATTERN_TEST 1
1217 #define SET_READ_TEST 2
1218 #define WRITE_NO_TEST 3
1219 #define TABLE32_TEST 4
1220 #define TABLE64_TEST_LO 5
1221 #define TABLE64_TEST_HI 6
1222
1223 /* default 82599 register test */
1224 static const struct ixgbe_reg_test reg_test_82599[] = {
1225 { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1226 { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1227 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1228 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1229 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
1230 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1231 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1232 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1233 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1234 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1235 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1236 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1237 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1238 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1239 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
1240 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
1241 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1242 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
1243 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1244 { 0, 0, 0, 0 }
1245 };
1246
1247 /* default 82598 register test */
1248 static const struct ixgbe_reg_test reg_test_82598[] = {
1249 { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1250 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1251 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1252 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1253 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1254 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1255 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1256 /* Enable all four RX queues before testing. */
1257 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1258 /* RDH is read-only for 82598, only test RDT. */
1259 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1260 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1261 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1262 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1263 { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
1264 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1265 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1266 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1267 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
1268 { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
1269 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1270 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
1271 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1272 { 0, 0, 0, 0 }
1273 };
1274
1275 static bool reg_pattern_test(struct ixgbe_adapter *adapter, u64 *data, int reg,
1276 u32 mask, u32 write)
1277 {
1278 u32 pat, val, before;
1279 static const u32 test_pattern[] = {
1280 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1281
1282 for (pat = 0; pat < ARRAY_SIZE(test_pattern); pat++) {
1283 before = readl(adapter->hw.hw_addr + reg);
1284 writel((test_pattern[pat] & write),
1285 (adapter->hw.hw_addr + reg));
1286 val = readl(adapter->hw.hw_addr + reg);
1287 if (val != (test_pattern[pat] & write & mask)) {
1288 e_err(drv, "pattern test reg %04X failed: got "
1289 "0x%08X expected 0x%08X\n",
1290 reg, val, (test_pattern[pat] & write & mask));
1291 *data = reg;
1292 writel(before, adapter->hw.hw_addr + reg);
1293 return 1;
1294 }
1295 writel(before, adapter->hw.hw_addr + reg);
1296 }
1297 return 0;
1298 }
1299
1300 static bool reg_set_and_check(struct ixgbe_adapter *adapter, u64 *data, int reg,
1301 u32 mask, u32 write)
1302 {
1303 u32 val, before;
1304 before = readl(adapter->hw.hw_addr + reg);
1305 writel((write & mask), (adapter->hw.hw_addr + reg));
1306 val = readl(adapter->hw.hw_addr + reg);
1307 if ((write & mask) != (val & mask)) {
1308 e_err(drv, "set/check reg %04X test failed: got 0x%08X "
1309 "expected 0x%08X\n", reg, (val & mask), (write & mask));
1310 *data = reg;
1311 writel(before, (adapter->hw.hw_addr + reg));
1312 return 1;
1313 }
1314 writel(before, (adapter->hw.hw_addr + reg));
1315 return 0;
1316 }
1317
1318 #define REG_PATTERN_TEST(reg, mask, write) \
1319 do { \
1320 if (reg_pattern_test(adapter, data, reg, mask, write)) \
1321 return 1; \
1322 } while (0) \
1323
1324
1325 #define REG_SET_AND_CHECK(reg, mask, write) \
1326 do { \
1327 if (reg_set_and_check(adapter, data, reg, mask, write)) \
1328 return 1; \
1329 } while (0) \
1330
1331 static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1332 {
1333 const struct ixgbe_reg_test *test;
1334 u32 value, before, after;
1335 u32 i, toggle;
1336
1337 switch (adapter->hw.mac.type) {
1338 case ixgbe_mac_82598EB:
1339 toggle = 0x7FFFF3FF;
1340 test = reg_test_82598;
1341 break;
1342 case ixgbe_mac_82599EB:
1343 case ixgbe_mac_X540:
1344 toggle = 0x7FFFF30F;
1345 test = reg_test_82599;
1346 break;
1347 default:
1348 *data = 1;
1349 return 1;
1350 break;
1351 }
1352
1353 /*
1354 * Because the status register is such a special case,
1355 * we handle it separately from the rest of the register
1356 * tests. Some bits are read-only, some toggle, and some
1357 * are writeable on newer MACs.
1358 */
1359 before = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS);
1360 value = (IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle);
1361 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, toggle);
1362 after = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle;
1363 if (value != after) {
1364 e_err(drv, "failed STATUS register test got: 0x%08X "
1365 "expected: 0x%08X\n", after, value);
1366 *data = 1;
1367 return 1;
1368 }
1369 /* restore previous status */
1370 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, before);
1371
1372 /*
1373 * Perform the remainder of the register test, looping through
1374 * the test table until we either fail or reach the null entry.
1375 */
1376 while (test->reg) {
1377 for (i = 0; i < test->array_len; i++) {
1378 switch (test->test_type) {
1379 case PATTERN_TEST:
1380 REG_PATTERN_TEST(test->reg + (i * 0x40),
1381 test->mask,
1382 test->write);
1383 break;
1384 case SET_READ_TEST:
1385 REG_SET_AND_CHECK(test->reg + (i * 0x40),
1386 test->mask,
1387 test->write);
1388 break;
1389 case WRITE_NO_TEST:
1390 writel(test->write,
1391 (adapter->hw.hw_addr + test->reg)
1392 + (i * 0x40));
1393 break;
1394 case TABLE32_TEST:
1395 REG_PATTERN_TEST(test->reg + (i * 4),
1396 test->mask,
1397 test->write);
1398 break;
1399 case TABLE64_TEST_LO:
1400 REG_PATTERN_TEST(test->reg + (i * 8),
1401 test->mask,
1402 test->write);
1403 break;
1404 case TABLE64_TEST_HI:
1405 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1406 test->mask,
1407 test->write);
1408 break;
1409 }
1410 }
1411 test++;
1412 }
1413
1414 *data = 0;
1415 return 0;
1416 }
1417
1418 static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
1419 {
1420 struct ixgbe_hw *hw = &adapter->hw;
1421 if (hw->eeprom.ops.validate_checksum(hw, NULL))
1422 *data = 1;
1423 else
1424 *data = 0;
1425 return *data;
1426 }
1427
1428 static irqreturn_t ixgbe_test_intr(int irq, void *data)
1429 {
1430 struct net_device *netdev = (struct net_device *) data;
1431 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1432
1433 adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
1434
1435 return IRQ_HANDLED;
1436 }
1437
1438 static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
1439 {
1440 struct net_device *netdev = adapter->netdev;
1441 u32 mask, i = 0, shared_int = true;
1442 u32 irq = adapter->pdev->irq;
1443
1444 *data = 0;
1445
1446 /* Hook up test interrupt handler just for this test */
1447 if (adapter->msix_entries) {
1448 /* NOTE: we don't test MSI-X interrupts here, yet */
1449 return 0;
1450 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1451 shared_int = false;
1452 if (request_irq(irq, ixgbe_test_intr, 0, netdev->name,
1453 netdev)) {
1454 *data = 1;
1455 return -1;
1456 }
1457 } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED,
1458 netdev->name, netdev)) {
1459 shared_int = false;
1460 } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED,
1461 netdev->name, netdev)) {
1462 *data = 1;
1463 return -1;
1464 }
1465 e_info(hw, "testing %s interrupt\n", shared_int ?
1466 "shared" : "unshared");
1467
1468 /* Disable all the interrupts */
1469 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1470 IXGBE_WRITE_FLUSH(&adapter->hw);
1471 usleep_range(10000, 20000);
1472
1473 /* Test each interrupt */
1474 for (; i < 10; i++) {
1475 /* Interrupt to test */
1476 mask = 1 << i;
1477
1478 if (!shared_int) {
1479 /*
1480 * Disable the interrupts to be reported in
1481 * the cause register and then force the same
1482 * interrupt and see if one gets posted. If
1483 * an interrupt was posted to the bus, the
1484 * test failed.
1485 */
1486 adapter->test_icr = 0;
1487 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1488 ~mask & 0x00007FFF);
1489 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1490 ~mask & 0x00007FFF);
1491 IXGBE_WRITE_FLUSH(&adapter->hw);
1492 usleep_range(10000, 20000);
1493
1494 if (adapter->test_icr & mask) {
1495 *data = 3;
1496 break;
1497 }
1498 }
1499
1500 /*
1501 * Enable the interrupt to be reported in the cause
1502 * register and then force the same interrupt and see
1503 * if one gets posted. If an interrupt was not posted
1504 * to the bus, the test failed.
1505 */
1506 adapter->test_icr = 0;
1507 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1508 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
1509 IXGBE_WRITE_FLUSH(&adapter->hw);
1510 usleep_range(10000, 20000);
1511
1512 if (!(adapter->test_icr &mask)) {
1513 *data = 4;
1514 break;
1515 }
1516
1517 if (!shared_int) {
1518 /*
1519 * Disable the other interrupts to be reported in
1520 * the cause register and then force the other
1521 * interrupts and see if any get posted. If
1522 * an interrupt was posted to the bus, the
1523 * test failed.
1524 */
1525 adapter->test_icr = 0;
1526 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1527 ~mask & 0x00007FFF);
1528 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1529 ~mask & 0x00007FFF);
1530 IXGBE_WRITE_FLUSH(&adapter->hw);
1531 usleep_range(10000, 20000);
1532
1533 if (adapter->test_icr) {
1534 *data = 5;
1535 break;
1536 }
1537 }
1538 }
1539
1540 /* Disable all the interrupts */
1541 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1542 IXGBE_WRITE_FLUSH(&adapter->hw);
1543 usleep_range(10000, 20000);
1544
1545 /* Unhook test interrupt handler */
1546 free_irq(irq, netdev);
1547
1548 return *data;
1549 }
1550
1551 static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
1552 {
1553 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1554 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1555 struct ixgbe_hw *hw = &adapter->hw;
1556 u32 reg_ctl;
1557
1558 /* shut down the DMA engines now so they can be reinitialized later */
1559
1560 /* first Rx */
1561 reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1562 reg_ctl &= ~IXGBE_RXCTRL_RXEN;
1563 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_ctl);
1564 ixgbe_disable_rx_queue(adapter, rx_ring);
1565
1566 /* now Tx */
1567 reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx));
1568 reg_ctl &= ~IXGBE_TXDCTL_ENABLE;
1569 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx), reg_ctl);
1570
1571 switch (hw->mac.type) {
1572 case ixgbe_mac_82599EB:
1573 case ixgbe_mac_X540:
1574 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1575 reg_ctl &= ~IXGBE_DMATXCTL_TE;
1576 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl);
1577 break;
1578 default:
1579 break;
1580 }
1581
1582 ixgbe_reset(adapter);
1583
1584 ixgbe_free_tx_resources(&adapter->test_tx_ring);
1585 ixgbe_free_rx_resources(&adapter->test_rx_ring);
1586 }
1587
1588 static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
1589 {
1590 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1591 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1592 u32 rctl, reg_data;
1593 int ret_val;
1594 int err;
1595
1596 /* Setup Tx descriptor ring and Tx buffers */
1597 tx_ring->count = IXGBE_DEFAULT_TXD;
1598 tx_ring->queue_index = 0;
1599 tx_ring->dev = &adapter->pdev->dev;
1600 tx_ring->netdev = adapter->netdev;
1601 tx_ring->reg_idx = adapter->tx_ring[0]->reg_idx;
1602
1603 err = ixgbe_setup_tx_resources(tx_ring);
1604 if (err)
1605 return 1;
1606
1607 switch (adapter->hw.mac.type) {
1608 case ixgbe_mac_82599EB:
1609 case ixgbe_mac_X540:
1610 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
1611 reg_data |= IXGBE_DMATXCTL_TE;
1612 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
1613 break;
1614 default:
1615 break;
1616 }
1617
1618 ixgbe_configure_tx_ring(adapter, tx_ring);
1619
1620 /* Setup Rx Descriptor ring and Rx buffers */
1621 rx_ring->count = IXGBE_DEFAULT_RXD;
1622 rx_ring->queue_index = 0;
1623 rx_ring->dev = &adapter->pdev->dev;
1624 rx_ring->netdev = adapter->netdev;
1625 rx_ring->reg_idx = adapter->rx_ring[0]->reg_idx;
1626
1627 err = ixgbe_setup_rx_resources(rx_ring);
1628 if (err) {
1629 ret_val = 4;
1630 goto err_nomem;
1631 }
1632
1633 rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1634 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl & ~IXGBE_RXCTRL_RXEN);
1635
1636 ixgbe_configure_rx_ring(adapter, rx_ring);
1637
1638 rctl |= IXGBE_RXCTRL_RXEN | IXGBE_RXCTRL_DMBYPS;
1639 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl);
1640
1641 return 0;
1642
1643 err_nomem:
1644 ixgbe_free_desc_rings(adapter);
1645 return ret_val;
1646 }
1647
1648 static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
1649 {
1650 struct ixgbe_hw *hw = &adapter->hw;
1651 u32 reg_data;
1652
1653
1654 /* Setup MAC loopback */
1655 reg_data = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1656 reg_data |= IXGBE_HLREG0_LPBK;
1657 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_data);
1658
1659 reg_data = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1660 reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
1661 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg_data);
1662
1663 /* X540 needs to set the MACC.FLU bit to force link up */
1664 if (adapter->hw.mac.type == ixgbe_mac_X540) {
1665 reg_data = IXGBE_READ_REG(hw, IXGBE_MACC);
1666 reg_data |= IXGBE_MACC_FLU;
1667 IXGBE_WRITE_REG(hw, IXGBE_MACC, reg_data);
1668 } else {
1669 if (hw->mac.orig_autoc) {
1670 reg_data = hw->mac.orig_autoc | IXGBE_AUTOC_FLU;
1671 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_data);
1672 } else {
1673 return 10;
1674 }
1675 }
1676 IXGBE_WRITE_FLUSH(hw);
1677 usleep_range(10000, 20000);
1678
1679 /* Disable Atlas Tx lanes; re-enabled in reset path */
1680 if (hw->mac.type == ixgbe_mac_82598EB) {
1681 u8 atlas;
1682
1683 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);
1684 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
1685 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);
1686
1687 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);
1688 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
1689 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);
1690
1691 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);
1692 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
1693 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);
1694
1695 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);
1696 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
1697 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);
1698 }
1699
1700 return 0;
1701 }
1702
1703 static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
1704 {
1705 u32 reg_data;
1706
1707 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1708 reg_data &= ~IXGBE_HLREG0_LPBK;
1709 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1710 }
1711
1712 static void ixgbe_create_lbtest_frame(struct sk_buff *skb,
1713 unsigned int frame_size)
1714 {
1715 memset(skb->data, 0xFF, frame_size);
1716 frame_size >>= 1;
1717 memset(&skb->data[frame_size], 0xAA, frame_size / 2 - 1);
1718 memset(&skb->data[frame_size + 10], 0xBE, 1);
1719 memset(&skb->data[frame_size + 12], 0xAF, 1);
1720 }
1721
1722 static bool ixgbe_check_lbtest_frame(struct ixgbe_rx_buffer *rx_buffer,
1723 unsigned int frame_size)
1724 {
1725 unsigned char *data;
1726 bool match = true;
1727
1728 frame_size >>= 1;
1729
1730 data = kmap(rx_buffer->page) + rx_buffer->page_offset;
1731
1732 if (data[3] != 0xFF ||
1733 data[frame_size + 10] != 0xBE ||
1734 data[frame_size + 12] != 0xAF)
1735 match = false;
1736
1737 kunmap(rx_buffer->page);
1738
1739 return match;
1740 }
1741
1742 static u16 ixgbe_clean_test_rings(struct ixgbe_ring *rx_ring,
1743 struct ixgbe_ring *tx_ring,
1744 unsigned int size)
1745 {
1746 union ixgbe_adv_rx_desc *rx_desc;
1747 struct ixgbe_rx_buffer *rx_buffer;
1748 struct ixgbe_tx_buffer *tx_buffer;
1749 u16 rx_ntc, tx_ntc, count = 0;
1750
1751 /* initialize next to clean and descriptor values */
1752 rx_ntc = rx_ring->next_to_clean;
1753 tx_ntc = tx_ring->next_to_clean;
1754 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc);
1755
1756 while (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD)) {
1757 /* check Rx buffer */
1758 rx_buffer = &rx_ring->rx_buffer_info[rx_ntc];
1759
1760 /* sync Rx buffer for CPU read */
1761 dma_sync_single_for_cpu(rx_ring->dev,
1762 rx_buffer->dma,
1763 ixgbe_rx_bufsz(rx_ring),
1764 DMA_FROM_DEVICE);
1765
1766 /* verify contents of skb */
1767 if (ixgbe_check_lbtest_frame(rx_buffer, size))
1768 count++;
1769
1770 /* sync Rx buffer for device write */
1771 dma_sync_single_for_device(rx_ring->dev,
1772 rx_buffer->dma,
1773 ixgbe_rx_bufsz(rx_ring),
1774 DMA_FROM_DEVICE);
1775
1776 /* unmap buffer on Tx side */
1777 tx_buffer = &tx_ring->tx_buffer_info[tx_ntc];
1778 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
1779
1780 /* increment Rx/Tx next to clean counters */
1781 rx_ntc++;
1782 if (rx_ntc == rx_ring->count)
1783 rx_ntc = 0;
1784 tx_ntc++;
1785 if (tx_ntc == tx_ring->count)
1786 tx_ntc = 0;
1787
1788 /* fetch next descriptor */
1789 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc);
1790 }
1791
1792 netdev_tx_reset_queue(txring_txq(tx_ring));
1793
1794 /* re-map buffers to ring, store next to clean values */
1795 ixgbe_alloc_rx_buffers(rx_ring, count);
1796 rx_ring->next_to_clean = rx_ntc;
1797 tx_ring->next_to_clean = tx_ntc;
1798
1799 return count;
1800 }
1801
1802 static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
1803 {
1804 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1805 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1806 int i, j, lc, good_cnt, ret_val = 0;
1807 unsigned int size = 1024;
1808 netdev_tx_t tx_ret_val;
1809 struct sk_buff *skb;
1810
1811 /* allocate test skb */
1812 skb = alloc_skb(size, GFP_KERNEL);
1813 if (!skb)
1814 return 11;
1815
1816 /* place data into test skb */
1817 ixgbe_create_lbtest_frame(skb, size);
1818 skb_put(skb, size);
1819
1820 /*
1821 * Calculate the loop count based on the largest descriptor ring
1822 * The idea is to wrap the largest ring a number of times using 64
1823 * send/receive pairs during each loop
1824 */
1825
1826 if (rx_ring->count <= tx_ring->count)
1827 lc = ((tx_ring->count / 64) * 2) + 1;
1828 else
1829 lc = ((rx_ring->count / 64) * 2) + 1;
1830
1831 for (j = 0; j <= lc; j++) {
1832 /* reset count of good packets */
1833 good_cnt = 0;
1834
1835 /* place 64 packets on the transmit queue*/
1836 for (i = 0; i < 64; i++) {
1837 skb_get(skb);
1838 tx_ret_val = ixgbe_xmit_frame_ring(skb,
1839 adapter,
1840 tx_ring);
1841 if (tx_ret_val == NETDEV_TX_OK)
1842 good_cnt++;
1843 }
1844
1845 if (good_cnt != 64) {
1846 ret_val = 12;
1847 break;
1848 }
1849
1850 /* allow 200 milliseconds for packets to go from Tx to Rx */
1851 msleep(200);
1852
1853 good_cnt = ixgbe_clean_test_rings(rx_ring, tx_ring, size);
1854 if (good_cnt != 64) {
1855 ret_val = 13;
1856 break;
1857 }
1858 }
1859
1860 /* free the original skb */
1861 kfree_skb(skb);
1862
1863 return ret_val;
1864 }
1865
1866 static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
1867 {
1868 *data = ixgbe_setup_desc_rings(adapter);
1869 if (*data)
1870 goto out;
1871 *data = ixgbe_setup_loopback_test(adapter);
1872 if (*data)
1873 goto err_loopback;
1874 *data = ixgbe_run_loopback_test(adapter);
1875 ixgbe_loopback_cleanup(adapter);
1876
1877 err_loopback:
1878 ixgbe_free_desc_rings(adapter);
1879 out:
1880 return *data;
1881 }
1882
1883 static void ixgbe_diag_test(struct net_device *netdev,
1884 struct ethtool_test *eth_test, u64 *data)
1885 {
1886 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1887 struct ixgbe_hw *hw = &adapter->hw;
1888 bool if_running = netif_running(netdev);
1889
1890 set_bit(__IXGBE_TESTING, &adapter->state);
1891 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1892 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
1893 int i;
1894 for (i = 0; i < adapter->num_vfs; i++) {
1895 if (adapter->vfinfo[i].clear_to_send) {
1896 netdev_warn(netdev, "%s",
1897 "offline diagnostic is not "
1898 "supported when VFs are "
1899 "present\n");
1900 data[0] = 1;
1901 data[1] = 1;
1902 data[2] = 1;
1903 data[3] = 1;
1904 eth_test->flags |= ETH_TEST_FL_FAILED;
1905 clear_bit(__IXGBE_TESTING,
1906 &adapter->state);
1907 goto skip_ol_tests;
1908 }
1909 }
1910 }
1911
1912 /* Offline tests */
1913 e_info(hw, "offline testing starting\n");
1914
1915 if (if_running)
1916 /* indicate we're in test mode */
1917 dev_close(netdev);
1918
1919 /* bringing adapter down disables SFP+ optics */
1920 if (hw->mac.ops.enable_tx_laser)
1921 hw->mac.ops.enable_tx_laser(hw);
1922
1923 /* Link test performed before hardware reset so autoneg doesn't
1924 * interfere with test result
1925 */
1926 if (ixgbe_link_test(adapter, &data[4]))
1927 eth_test->flags |= ETH_TEST_FL_FAILED;
1928
1929 ixgbe_reset(adapter);
1930 e_info(hw, "register testing starting\n");
1931 if (ixgbe_reg_test(adapter, &data[0]))
1932 eth_test->flags |= ETH_TEST_FL_FAILED;
1933
1934 ixgbe_reset(adapter);
1935 e_info(hw, "eeprom testing starting\n");
1936 if (ixgbe_eeprom_test(adapter, &data[1]))
1937 eth_test->flags |= ETH_TEST_FL_FAILED;
1938
1939 ixgbe_reset(adapter);
1940 e_info(hw, "interrupt testing starting\n");
1941 if (ixgbe_intr_test(adapter, &data[2]))
1942 eth_test->flags |= ETH_TEST_FL_FAILED;
1943
1944 /* If SRIOV or VMDq is enabled then skip MAC
1945 * loopback diagnostic. */
1946 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
1947 IXGBE_FLAG_VMDQ_ENABLED)) {
1948 e_info(hw, "Skip MAC loopback diagnostic in VT "
1949 "mode\n");
1950 data[3] = 0;
1951 goto skip_loopback;
1952 }
1953
1954 ixgbe_reset(adapter);
1955 e_info(hw, "loopback testing starting\n");
1956 if (ixgbe_loopback_test(adapter, &data[3]))
1957 eth_test->flags |= ETH_TEST_FL_FAILED;
1958
1959 skip_loopback:
1960 ixgbe_reset(adapter);
1961
1962 /* clear testing bit and return adapter to previous state */
1963 clear_bit(__IXGBE_TESTING, &adapter->state);
1964 if (if_running)
1965 dev_open(netdev);
1966 } else {
1967 e_info(hw, "online testing starting\n");
1968
1969 /* if adapter is down, SFP+ optics will be disabled */
1970 if (!if_running && hw->mac.ops.enable_tx_laser)
1971 hw->mac.ops.enable_tx_laser(hw);
1972
1973 /* Online tests */
1974 if (ixgbe_link_test(adapter, &data[4]))
1975 eth_test->flags |= ETH_TEST_FL_FAILED;
1976
1977 /* Offline tests aren't run; pass by default */
1978 data[0] = 0;
1979 data[1] = 0;
1980 data[2] = 0;
1981 data[3] = 0;
1982
1983 clear_bit(__IXGBE_TESTING, &adapter->state);
1984 }
1985
1986 /* if adapter was down, ensure SFP+ optics are disabled again */
1987 if (!if_running && hw->mac.ops.disable_tx_laser)
1988 hw->mac.ops.disable_tx_laser(hw);
1989 skip_ol_tests:
1990 msleep_interruptible(4 * 1000);
1991 }
1992
1993 static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
1994 struct ethtool_wolinfo *wol)
1995 {
1996 struct ixgbe_hw *hw = &adapter->hw;
1997 int retval = 0;
1998
1999 /* WOL not supported for all devices */
2000 if (!ixgbe_wol_supported(adapter, hw->device_id,
2001 hw->subsystem_device_id)) {
2002 retval = 1;
2003 wol->supported = 0;
2004 }
2005
2006 return retval;
2007 }
2008
2009 static void ixgbe_get_wol(struct net_device *netdev,
2010 struct ethtool_wolinfo *wol)
2011 {
2012 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2013
2014 wol->supported = WAKE_UCAST | WAKE_MCAST |
2015 WAKE_BCAST | WAKE_MAGIC;
2016 wol->wolopts = 0;
2017
2018 if (ixgbe_wol_exclusion(adapter, wol) ||
2019 !device_can_wakeup(&adapter->pdev->dev))
2020 return;
2021
2022 if (adapter->wol & IXGBE_WUFC_EX)
2023 wol->wolopts |= WAKE_UCAST;
2024 if (adapter->wol & IXGBE_WUFC_MC)
2025 wol->wolopts |= WAKE_MCAST;
2026 if (adapter->wol & IXGBE_WUFC_BC)
2027 wol->wolopts |= WAKE_BCAST;
2028 if (adapter->wol & IXGBE_WUFC_MAG)
2029 wol->wolopts |= WAKE_MAGIC;
2030 }
2031
2032 static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2033 {
2034 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2035
2036 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
2037 return -EOPNOTSUPP;
2038
2039 if (ixgbe_wol_exclusion(adapter, wol))
2040 return wol->wolopts ? -EOPNOTSUPP : 0;
2041
2042 adapter->wol = 0;
2043
2044 if (wol->wolopts & WAKE_UCAST)
2045 adapter->wol |= IXGBE_WUFC_EX;
2046 if (wol->wolopts & WAKE_MCAST)
2047 adapter->wol |= IXGBE_WUFC_MC;
2048 if (wol->wolopts & WAKE_BCAST)
2049 adapter->wol |= IXGBE_WUFC_BC;
2050 if (wol->wolopts & WAKE_MAGIC)
2051 adapter->wol |= IXGBE_WUFC_MAG;
2052
2053 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2054
2055 return 0;
2056 }
2057
2058 static int ixgbe_nway_reset(struct net_device *netdev)
2059 {
2060 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2061
2062 if (netif_running(netdev))
2063 ixgbe_reinit_locked(adapter);
2064
2065 return 0;
2066 }
2067
2068 static int ixgbe_set_phys_id(struct net_device *netdev,
2069 enum ethtool_phys_id_state state)
2070 {
2071 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2072 struct ixgbe_hw *hw = &adapter->hw;
2073
2074 switch (state) {
2075 case ETHTOOL_ID_ACTIVE:
2076 adapter->led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2077 return 2;
2078
2079 case ETHTOOL_ID_ON:
2080 hw->mac.ops.led_on(hw, IXGBE_LED_ON);
2081 break;
2082
2083 case ETHTOOL_ID_OFF:
2084 hw->mac.ops.led_off(hw, IXGBE_LED_ON);
2085 break;
2086
2087 case ETHTOOL_ID_INACTIVE:
2088 /* Restore LED settings */
2089 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, adapter->led_reg);
2090 break;
2091 }
2092
2093 return 0;
2094 }
2095
2096 static int ixgbe_get_coalesce(struct net_device *netdev,
2097 struct ethtool_coalesce *ec)
2098 {
2099 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2100
2101 /* only valid if in constant ITR mode */
2102 if (adapter->rx_itr_setting <= 1)
2103 ec->rx_coalesce_usecs = adapter->rx_itr_setting;
2104 else
2105 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
2106
2107 /* if in mixed tx/rx queues per vector mode, report only rx settings */
2108 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count)
2109 return 0;
2110
2111 /* only valid if in constant ITR mode */
2112 if (adapter->tx_itr_setting <= 1)
2113 ec->tx_coalesce_usecs = adapter->tx_itr_setting;
2114 else
2115 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
2116
2117 return 0;
2118 }
2119
2120 /*
2121 * this function must be called before setting the new value of
2122 * rx_itr_setting
2123 */
2124 static bool ixgbe_update_rsc(struct ixgbe_adapter *adapter)
2125 {
2126 struct net_device *netdev = adapter->netdev;
2127
2128 /* nothing to do if LRO or RSC are not enabled */
2129 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) ||
2130 !(netdev->features & NETIF_F_LRO))
2131 return false;
2132
2133 /* check the feature flag value and enable RSC if necessary */
2134 if (adapter->rx_itr_setting == 1 ||
2135 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
2136 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
2137 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
2138 e_info(probe, "rx-usecs value high enough "
2139 "to re-enable RSC\n");
2140 return true;
2141 }
2142 /* if interrupt rate is too high then disable RSC */
2143 } else if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2144 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
2145 e_info(probe, "rx-usecs set too low, disabling RSC\n");
2146 return true;
2147 }
2148 return false;
2149 }
2150
2151 static int ixgbe_set_coalesce(struct net_device *netdev,
2152 struct ethtool_coalesce *ec)
2153 {
2154 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2155 struct ixgbe_q_vector *q_vector;
2156 int i;
2157 u16 tx_itr_param, rx_itr_param, tx_itr_prev;
2158 bool need_reset = false;
2159
2160 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) {
2161 /* reject Tx specific changes in case of mixed RxTx vectors */
2162 if (ec->tx_coalesce_usecs)
2163 return -EINVAL;
2164 tx_itr_prev = adapter->rx_itr_setting;
2165 } else {
2166 tx_itr_prev = adapter->tx_itr_setting;
2167 }
2168
2169 if ((ec->rx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)) ||
2170 (ec->tx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)))
2171 return -EINVAL;
2172
2173 if (ec->rx_coalesce_usecs > 1)
2174 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
2175 else
2176 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
2177
2178 if (adapter->rx_itr_setting == 1)
2179 rx_itr_param = IXGBE_20K_ITR;
2180 else
2181 rx_itr_param = adapter->rx_itr_setting;
2182
2183 if (ec->tx_coalesce_usecs > 1)
2184 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
2185 else
2186 adapter->tx_itr_setting = ec->tx_coalesce_usecs;
2187
2188 if (adapter->tx_itr_setting == 1)
2189 tx_itr_param = IXGBE_10K_ITR;
2190 else
2191 tx_itr_param = adapter->tx_itr_setting;
2192
2193 /* mixed Rx/Tx */
2194 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count)
2195 adapter->tx_itr_setting = adapter->rx_itr_setting;
2196
2197 #if IS_ENABLED(CONFIG_BQL)
2198 /* detect ITR changes that require update of TXDCTL.WTHRESH */
2199 if ((adapter->tx_itr_setting > 1) &&
2200 (adapter->tx_itr_setting < IXGBE_100K_ITR)) {
2201 if ((tx_itr_prev == 1) ||
2202 (tx_itr_prev > IXGBE_100K_ITR))
2203 need_reset = true;
2204 } else {
2205 if ((tx_itr_prev > 1) &&
2206 (tx_itr_prev < IXGBE_100K_ITR))
2207 need_reset = true;
2208 }
2209 #endif
2210 /* check the old value and enable RSC if necessary */
2211 need_reset |= ixgbe_update_rsc(adapter);
2212
2213 for (i = 0; i < adapter->num_q_vectors; i++) {
2214 q_vector = adapter->q_vector[i];
2215 if (q_vector->tx.count && !q_vector->rx.count)
2216 /* tx only */
2217 q_vector->itr = tx_itr_param;
2218 else
2219 /* rx only or mixed */
2220 q_vector->itr = rx_itr_param;
2221 ixgbe_write_eitr(q_vector);
2222 }
2223
2224 /*
2225 * do reset here at the end to make sure EITR==0 case is handled
2226 * correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings
2227 * also locks in RSC enable/disable which requires reset
2228 */
2229 if (need_reset)
2230 ixgbe_do_reset(netdev);
2231
2232 return 0;
2233 }
2234
2235 static int ixgbe_get_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2236 struct ethtool_rxnfc *cmd)
2237 {
2238 union ixgbe_atr_input *mask = &adapter->fdir_mask;
2239 struct ethtool_rx_flow_spec *fsp =
2240 (struct ethtool_rx_flow_spec *)&cmd->fs;
2241 struct hlist_node *node2;
2242 struct ixgbe_fdir_filter *rule = NULL;
2243
2244 /* report total rule count */
2245 cmd->data = (1024 << adapter->fdir_pballoc) - 2;
2246
2247 hlist_for_each_entry_safe(rule, node2,
2248 &adapter->fdir_filter_list, fdir_node) {
2249 if (fsp->location <= rule->sw_idx)
2250 break;
2251 }
2252
2253 if (!rule || fsp->location != rule->sw_idx)
2254 return -EINVAL;
2255
2256 /* fill out the flow spec entry */
2257
2258 /* set flow type field */
2259 switch (rule->filter.formatted.flow_type) {
2260 case IXGBE_ATR_FLOW_TYPE_TCPV4:
2261 fsp->flow_type = TCP_V4_FLOW;
2262 break;
2263 case IXGBE_ATR_FLOW_TYPE_UDPV4:
2264 fsp->flow_type = UDP_V4_FLOW;
2265 break;
2266 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
2267 fsp->flow_type = SCTP_V4_FLOW;
2268 break;
2269 case IXGBE_ATR_FLOW_TYPE_IPV4:
2270 fsp->flow_type = IP_USER_FLOW;
2271 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
2272 fsp->h_u.usr_ip4_spec.proto = 0;
2273 fsp->m_u.usr_ip4_spec.proto = 0;
2274 break;
2275 default:
2276 return -EINVAL;
2277 }
2278
2279 fsp->h_u.tcp_ip4_spec.psrc = rule->filter.formatted.src_port;
2280 fsp->m_u.tcp_ip4_spec.psrc = mask->formatted.src_port;
2281 fsp->h_u.tcp_ip4_spec.pdst = rule->filter.formatted.dst_port;
2282 fsp->m_u.tcp_ip4_spec.pdst = mask->formatted.dst_port;
2283 fsp->h_u.tcp_ip4_spec.ip4src = rule->filter.formatted.src_ip[0];
2284 fsp->m_u.tcp_ip4_spec.ip4src = mask->formatted.src_ip[0];
2285 fsp->h_u.tcp_ip4_spec.ip4dst = rule->filter.formatted.dst_ip[0];
2286 fsp->m_u.tcp_ip4_spec.ip4dst = mask->formatted.dst_ip[0];
2287 fsp->h_ext.vlan_tci = rule->filter.formatted.vlan_id;
2288 fsp->m_ext.vlan_tci = mask->formatted.vlan_id;
2289 fsp->h_ext.vlan_etype = rule->filter.formatted.flex_bytes;
2290 fsp->m_ext.vlan_etype = mask->formatted.flex_bytes;
2291 fsp->h_ext.data[1] = htonl(rule->filter.formatted.vm_pool);
2292 fsp->m_ext.data[1] = htonl(mask->formatted.vm_pool);
2293 fsp->flow_type |= FLOW_EXT;
2294
2295 /* record action */
2296 if (rule->action == IXGBE_FDIR_DROP_QUEUE)
2297 fsp->ring_cookie = RX_CLS_FLOW_DISC;
2298 else
2299 fsp->ring_cookie = rule->action;
2300
2301 return 0;
2302 }
2303
2304 static int ixgbe_get_ethtool_fdir_all(struct ixgbe_adapter *adapter,
2305 struct ethtool_rxnfc *cmd,
2306 u32 *rule_locs)
2307 {
2308 struct hlist_node *node2;
2309 struct ixgbe_fdir_filter *rule;
2310 int cnt = 0;
2311
2312 /* report total rule count */
2313 cmd->data = (1024 << adapter->fdir_pballoc) - 2;
2314
2315 hlist_for_each_entry_safe(rule, node2,
2316 &adapter->fdir_filter_list, fdir_node) {
2317 if (cnt == cmd->rule_cnt)
2318 return -EMSGSIZE;
2319 rule_locs[cnt] = rule->sw_idx;
2320 cnt++;
2321 }
2322
2323 cmd->rule_cnt = cnt;
2324
2325 return 0;
2326 }
2327
2328 static int ixgbe_get_rss_hash_opts(struct ixgbe_adapter *adapter,
2329 struct ethtool_rxnfc *cmd)
2330 {
2331 cmd->data = 0;
2332
2333 /* Report default options for RSS on ixgbe */
2334 switch (cmd->flow_type) {
2335 case TCP_V4_FLOW:
2336 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2337 case UDP_V4_FLOW:
2338 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2339 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2340 case SCTP_V4_FLOW:
2341 case AH_ESP_V4_FLOW:
2342 case AH_V4_FLOW:
2343 case ESP_V4_FLOW:
2344 case IPV4_FLOW:
2345 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2346 break;
2347 case TCP_V6_FLOW:
2348 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2349 case UDP_V6_FLOW:
2350 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2351 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2352 case SCTP_V6_FLOW:
2353 case AH_ESP_V6_FLOW:
2354 case AH_V6_FLOW:
2355 case ESP_V6_FLOW:
2356 case IPV6_FLOW:
2357 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2358 break;
2359 default:
2360 return -EINVAL;
2361 }
2362
2363 return 0;
2364 }
2365
2366 static int ixgbe_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2367 u32 *rule_locs)
2368 {
2369 struct ixgbe_adapter *adapter = netdev_priv(dev);
2370 int ret = -EOPNOTSUPP;
2371
2372 switch (cmd->cmd) {
2373 case ETHTOOL_GRXRINGS:
2374 cmd->data = adapter->num_rx_queues;
2375 ret = 0;
2376 break;
2377 case ETHTOOL_GRXCLSRLCNT:
2378 cmd->rule_cnt = adapter->fdir_filter_count;
2379 ret = 0;
2380 break;
2381 case ETHTOOL_GRXCLSRULE:
2382 ret = ixgbe_get_ethtool_fdir_entry(adapter, cmd);
2383 break;
2384 case ETHTOOL_GRXCLSRLALL:
2385 ret = ixgbe_get_ethtool_fdir_all(adapter, cmd, rule_locs);
2386 break;
2387 case ETHTOOL_GRXFH:
2388 ret = ixgbe_get_rss_hash_opts(adapter, cmd);
2389 break;
2390 default:
2391 break;
2392 }
2393
2394 return ret;
2395 }
2396
2397 static int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2398 struct ixgbe_fdir_filter *input,
2399 u16 sw_idx)
2400 {
2401 struct ixgbe_hw *hw = &adapter->hw;
2402 struct hlist_node *node2;
2403 struct ixgbe_fdir_filter *rule, *parent;
2404 int err = -EINVAL;
2405
2406 parent = NULL;
2407 rule = NULL;
2408
2409 hlist_for_each_entry_safe(rule, node2,
2410 &adapter->fdir_filter_list, fdir_node) {
2411 /* hash found, or no matching entry */
2412 if (rule->sw_idx >= sw_idx)
2413 break;
2414 parent = rule;
2415 }
2416
2417 /* if there is an old rule occupying our place remove it */
2418 if (rule && (rule->sw_idx == sw_idx)) {
2419 if (!input || (rule->filter.formatted.bkt_hash !=
2420 input->filter.formatted.bkt_hash)) {
2421 err = ixgbe_fdir_erase_perfect_filter_82599(hw,
2422 &rule->filter,
2423 sw_idx);
2424 }
2425
2426 hlist_del(&rule->fdir_node);
2427 kfree(rule);
2428 adapter->fdir_filter_count--;
2429 }
2430
2431 /*
2432 * If no input this was a delete, err should be 0 if a rule was
2433 * successfully found and removed from the list else -EINVAL
2434 */
2435 if (!input)
2436 return err;
2437
2438 /* initialize node and set software index */
2439 INIT_HLIST_NODE(&input->fdir_node);
2440
2441 /* add filter to the list */
2442 if (parent)
2443 hlist_add_after(&parent->fdir_node, &input->fdir_node);
2444 else
2445 hlist_add_head(&input->fdir_node,
2446 &adapter->fdir_filter_list);
2447
2448 /* update counts */
2449 adapter->fdir_filter_count++;
2450
2451 return 0;
2452 }
2453
2454 static int ixgbe_flowspec_to_flow_type(struct ethtool_rx_flow_spec *fsp,
2455 u8 *flow_type)
2456 {
2457 switch (fsp->flow_type & ~FLOW_EXT) {
2458 case TCP_V4_FLOW:
2459 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
2460 break;
2461 case UDP_V4_FLOW:
2462 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
2463 break;
2464 case SCTP_V4_FLOW:
2465 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
2466 break;
2467 case IP_USER_FLOW:
2468 switch (fsp->h_u.usr_ip4_spec.proto) {
2469 case IPPROTO_TCP:
2470 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
2471 break;
2472 case IPPROTO_UDP:
2473 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
2474 break;
2475 case IPPROTO_SCTP:
2476 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
2477 break;
2478 case 0:
2479 if (!fsp->m_u.usr_ip4_spec.proto) {
2480 *flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;
2481 break;
2482 }
2483 default:
2484 return 0;
2485 }
2486 break;
2487 default:
2488 return 0;
2489 }
2490
2491 return 1;
2492 }
2493
2494 static int ixgbe_add_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2495 struct ethtool_rxnfc *cmd)
2496 {
2497 struct ethtool_rx_flow_spec *fsp =
2498 (struct ethtool_rx_flow_spec *)&cmd->fs;
2499 struct ixgbe_hw *hw = &adapter->hw;
2500 struct ixgbe_fdir_filter *input;
2501 union ixgbe_atr_input mask;
2502 int err;
2503
2504 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
2505 return -EOPNOTSUPP;
2506
2507 /*
2508 * Don't allow programming if the action is a queue greater than
2509 * the number of online Rx queues.
2510 */
2511 if ((fsp->ring_cookie != RX_CLS_FLOW_DISC) &&
2512 (fsp->ring_cookie >= adapter->num_rx_queues))
2513 return -EINVAL;
2514
2515 /* Don't allow indexes to exist outside of available space */
2516 if (fsp->location >= ((1024 << adapter->fdir_pballoc) - 2)) {
2517 e_err(drv, "Location out of range\n");
2518 return -EINVAL;
2519 }
2520
2521 input = kzalloc(sizeof(*input), GFP_ATOMIC);
2522 if (!input)
2523 return -ENOMEM;
2524
2525 memset(&mask, 0, sizeof(union ixgbe_atr_input));
2526
2527 /* set SW index */
2528 input->sw_idx = fsp->location;
2529
2530 /* record flow type */
2531 if (!ixgbe_flowspec_to_flow_type(fsp,
2532 &input->filter.formatted.flow_type)) {
2533 e_err(drv, "Unrecognized flow type\n");
2534 goto err_out;
2535 }
2536
2537 mask.formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
2538 IXGBE_ATR_L4TYPE_MASK;
2539
2540 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4)
2541 mask.formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK;
2542
2543 /* Copy input into formatted structures */
2544 input->filter.formatted.src_ip[0] = fsp->h_u.tcp_ip4_spec.ip4src;
2545 mask.formatted.src_ip[0] = fsp->m_u.tcp_ip4_spec.ip4src;
2546 input->filter.formatted.dst_ip[0] = fsp->h_u.tcp_ip4_spec.ip4dst;
2547 mask.formatted.dst_ip[0] = fsp->m_u.tcp_ip4_spec.ip4dst;
2548 input->filter.formatted.src_port = fsp->h_u.tcp_ip4_spec.psrc;
2549 mask.formatted.src_port = fsp->m_u.tcp_ip4_spec.psrc;
2550 input->filter.formatted.dst_port = fsp->h_u.tcp_ip4_spec.pdst;
2551 mask.formatted.dst_port = fsp->m_u.tcp_ip4_spec.pdst;
2552
2553 if (fsp->flow_type & FLOW_EXT) {
2554 input->filter.formatted.vm_pool =
2555 (unsigned char)ntohl(fsp->h_ext.data[1]);
2556 mask.formatted.vm_pool =
2557 (unsigned char)ntohl(fsp->m_ext.data[1]);
2558 input->filter.formatted.vlan_id = fsp->h_ext.vlan_tci;
2559 mask.formatted.vlan_id = fsp->m_ext.vlan_tci;
2560 input->filter.formatted.flex_bytes =
2561 fsp->h_ext.vlan_etype;
2562 mask.formatted.flex_bytes = fsp->m_ext.vlan_etype;
2563 }
2564
2565 /* determine if we need to drop or route the packet */
2566 if (fsp->ring_cookie == RX_CLS_FLOW_DISC)
2567 input->action = IXGBE_FDIR_DROP_QUEUE;
2568 else
2569 input->action = fsp->ring_cookie;
2570
2571 spin_lock(&adapter->fdir_perfect_lock);
2572
2573 if (hlist_empty(&adapter->fdir_filter_list)) {
2574 /* save mask and program input mask into HW */
2575 memcpy(&adapter->fdir_mask, &mask, sizeof(mask));
2576 err = ixgbe_fdir_set_input_mask_82599(hw, &mask);
2577 if (err) {
2578 e_err(drv, "Error writing mask\n");
2579 goto err_out_w_lock;
2580 }
2581 } else if (memcmp(&adapter->fdir_mask, &mask, sizeof(mask))) {
2582 e_err(drv, "Only one mask supported per port\n");
2583 goto err_out_w_lock;
2584 }
2585
2586 /* apply mask and compute/store hash */
2587 ixgbe_atr_compute_perfect_hash_82599(&input->filter, &mask);
2588
2589 /* program filters to filter memory */
2590 err = ixgbe_fdir_write_perfect_filter_82599(hw,
2591 &input->filter, input->sw_idx,
2592 (input->action == IXGBE_FDIR_DROP_QUEUE) ?
2593 IXGBE_FDIR_DROP_QUEUE :
2594 adapter->rx_ring[input->action]->reg_idx);
2595 if (err)
2596 goto err_out_w_lock;
2597
2598 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx);
2599
2600 spin_unlock(&adapter->fdir_perfect_lock);
2601
2602 return err;
2603 err_out_w_lock:
2604 spin_unlock(&adapter->fdir_perfect_lock);
2605 err_out:
2606 kfree(input);
2607 return -EINVAL;
2608 }
2609
2610 static int ixgbe_del_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2611 struct ethtool_rxnfc *cmd)
2612 {
2613 struct ethtool_rx_flow_spec *fsp =
2614 (struct ethtool_rx_flow_spec *)&cmd->fs;
2615 int err;
2616
2617 spin_lock(&adapter->fdir_perfect_lock);
2618 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, fsp->location);
2619 spin_unlock(&adapter->fdir_perfect_lock);
2620
2621 return err;
2622 }
2623
2624 #define UDP_RSS_FLAGS (IXGBE_FLAG2_RSS_FIELD_IPV4_UDP | \
2625 IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2626 static int ixgbe_set_rss_hash_opt(struct ixgbe_adapter *adapter,
2627 struct ethtool_rxnfc *nfc)
2628 {
2629 u32 flags2 = adapter->flags2;
2630
2631 /*
2632 * RSS does not support anything other than hashing
2633 * to queues on src and dst IPs and ports
2634 */
2635 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
2636 RXH_L4_B_0_1 | RXH_L4_B_2_3))
2637 return -EINVAL;
2638
2639 switch (nfc->flow_type) {
2640 case TCP_V4_FLOW:
2641 case TCP_V6_FLOW:
2642 if (!(nfc->data & RXH_IP_SRC) ||
2643 !(nfc->data & RXH_IP_DST) ||
2644 !(nfc->data & RXH_L4_B_0_1) ||
2645 !(nfc->data & RXH_L4_B_2_3))
2646 return -EINVAL;
2647 break;
2648 case UDP_V4_FLOW:
2649 if (!(nfc->data & RXH_IP_SRC) ||
2650 !(nfc->data & RXH_IP_DST))
2651 return -EINVAL;
2652 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2653 case 0:
2654 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV4_UDP;
2655 break;
2656 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2657 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV4_UDP;
2658 break;
2659 default:
2660 return -EINVAL;
2661 }
2662 break;
2663 case UDP_V6_FLOW:
2664 if (!(nfc->data & RXH_IP_SRC) ||
2665 !(nfc->data & RXH_IP_DST))
2666 return -EINVAL;
2667 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2668 case 0:
2669 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV6_UDP;
2670 break;
2671 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2672 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV6_UDP;
2673 break;
2674 default:
2675 return -EINVAL;
2676 }
2677 break;
2678 case AH_ESP_V4_FLOW:
2679 case AH_V4_FLOW:
2680 case ESP_V4_FLOW:
2681 case SCTP_V4_FLOW:
2682 case AH_ESP_V6_FLOW:
2683 case AH_V6_FLOW:
2684 case ESP_V6_FLOW:
2685 case SCTP_V6_FLOW:
2686 if (!(nfc->data & RXH_IP_SRC) ||
2687 !(nfc->data & RXH_IP_DST) ||
2688 (nfc->data & RXH_L4_B_0_1) ||
2689 (nfc->data & RXH_L4_B_2_3))
2690 return -EINVAL;
2691 break;
2692 default:
2693 return -EINVAL;
2694 }
2695
2696 /* if we changed something we need to update flags */
2697 if (flags2 != adapter->flags2) {
2698 struct ixgbe_hw *hw = &adapter->hw;
2699 u32 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2700
2701 if ((flags2 & UDP_RSS_FLAGS) &&
2702 !(adapter->flags2 & UDP_RSS_FLAGS))
2703 e_warn(drv, "enabling UDP RSS: fragmented packets"
2704 " may arrive out of order to the stack above\n");
2705
2706 adapter->flags2 = flags2;
2707
2708 /* Perform hash on these packet types */
2709 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2710 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2711 | IXGBE_MRQC_RSS_FIELD_IPV6
2712 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2713
2714 mrqc &= ~(IXGBE_MRQC_RSS_FIELD_IPV4_UDP |
2715 IXGBE_MRQC_RSS_FIELD_IPV6_UDP);
2716
2717 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2718 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2719
2720 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2721 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2722
2723 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2724 }
2725
2726 return 0;
2727 }
2728
2729 static int ixgbe_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2730 {
2731 struct ixgbe_adapter *adapter = netdev_priv(dev);
2732 int ret = -EOPNOTSUPP;
2733
2734 switch (cmd->cmd) {
2735 case ETHTOOL_SRXCLSRLINS:
2736 ret = ixgbe_add_ethtool_fdir_entry(adapter, cmd);
2737 break;
2738 case ETHTOOL_SRXCLSRLDEL:
2739 ret = ixgbe_del_ethtool_fdir_entry(adapter, cmd);
2740 break;
2741 case ETHTOOL_SRXFH:
2742 ret = ixgbe_set_rss_hash_opt(adapter, cmd);
2743 break;
2744 default:
2745 break;
2746 }
2747
2748 return ret;
2749 }
2750
2751 static int ixgbe_get_ts_info(struct net_device *dev,
2752 struct ethtool_ts_info *info)
2753 {
2754 struct ixgbe_adapter *adapter = netdev_priv(dev);
2755
2756 switch (adapter->hw.mac.type) {
2757 case ixgbe_mac_X540:
2758 case ixgbe_mac_82599EB:
2759 info->so_timestamping =
2760 SOF_TIMESTAMPING_TX_SOFTWARE |
2761 SOF_TIMESTAMPING_RX_SOFTWARE |
2762 SOF_TIMESTAMPING_SOFTWARE |
2763 SOF_TIMESTAMPING_TX_HARDWARE |
2764 SOF_TIMESTAMPING_RX_HARDWARE |
2765 SOF_TIMESTAMPING_RAW_HARDWARE;
2766
2767 if (adapter->ptp_clock)
2768 info->phc_index = ptp_clock_index(adapter->ptp_clock);
2769 else
2770 info->phc_index = -1;
2771
2772 info->tx_types =
2773 (1 << HWTSTAMP_TX_OFF) |
2774 (1 << HWTSTAMP_TX_ON);
2775
2776 info->rx_filters =
2777 (1 << HWTSTAMP_FILTER_NONE) |
2778 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
2779 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
2780 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
2781 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
2782 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) |
2783 (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
2784 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
2785 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) |
2786 (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
2787 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
2788 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2789 break;
2790 default:
2791 return ethtool_op_get_ts_info(dev, info);
2792 break;
2793 }
2794 return 0;
2795 }
2796
2797 static unsigned int ixgbe_max_channels(struct ixgbe_adapter *adapter)
2798 {
2799 unsigned int max_combined;
2800 u8 tcs = netdev_get_num_tc(adapter->netdev);
2801
2802 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2803 /* We only support one q_vector without MSI-X */
2804 max_combined = 1;
2805 } else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2806 /* SR-IOV currently only allows one queue on the PF */
2807 max_combined = 1;
2808 } else if (tcs > 1) {
2809 /* For DCB report channels per traffic class */
2810 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2811 /* 8 TC w/ 4 queues per TC */
2812 max_combined = 4;
2813 } else if (tcs > 4) {
2814 /* 8 TC w/ 8 queues per TC */
2815 max_combined = 8;
2816 } else {
2817 /* 4 TC w/ 16 queues per TC */
2818 max_combined = 16;
2819 }
2820 } else if (adapter->atr_sample_rate) {
2821 /* support up to 64 queues with ATR */
2822 max_combined = IXGBE_MAX_FDIR_INDICES;
2823 } else {
2824 /* support up to 16 queues with RSS */
2825 max_combined = IXGBE_MAX_RSS_INDICES;
2826 }
2827
2828 return max_combined;
2829 }
2830
2831 static void ixgbe_get_channels(struct net_device *dev,
2832 struct ethtool_channels *ch)
2833 {
2834 struct ixgbe_adapter *adapter = netdev_priv(dev);
2835
2836 /* report maximum channels */
2837 ch->max_combined = ixgbe_max_channels(adapter);
2838
2839 /* report info for other vector */
2840 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2841 ch->max_other = NON_Q_VECTORS;
2842 ch->other_count = NON_Q_VECTORS;
2843 }
2844
2845 /* record RSS queues */
2846 ch->combined_count = adapter->ring_feature[RING_F_RSS].indices;
2847
2848 /* nothing else to report if RSS is disabled */
2849 if (ch->combined_count == 1)
2850 return;
2851
2852 /* we do not support ATR queueing if SR-IOV is enabled */
2853 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
2854 return;
2855
2856 /* same thing goes for being DCB enabled */
2857 if (netdev_get_num_tc(dev) > 1)
2858 return;
2859
2860 /* if ATR is disabled we can exit */
2861 if (!adapter->atr_sample_rate)
2862 return;
2863
2864 /* report flow director queues as maximum channels */
2865 ch->combined_count = adapter->ring_feature[RING_F_FDIR].indices;
2866 }
2867
2868 static int ixgbe_set_channels(struct net_device *dev,
2869 struct ethtool_channels *ch)
2870 {
2871 struct ixgbe_adapter *adapter = netdev_priv(dev);
2872 unsigned int count = ch->combined_count;
2873
2874 /* verify they are not requesting separate vectors */
2875 if (!count || ch->rx_count || ch->tx_count)
2876 return -EINVAL;
2877
2878 /* verify other_count has not changed */
2879 if (ch->other_count != NON_Q_VECTORS)
2880 return -EINVAL;
2881
2882 /* verify the number of channels does not exceed hardware limits */
2883 if (count > ixgbe_max_channels(adapter))
2884 return -EINVAL;
2885
2886 /* update feature limits from largest to smallest supported values */
2887 adapter->ring_feature[RING_F_FDIR].limit = count;
2888
2889 /* cap RSS limit at 16 */
2890 if (count > IXGBE_MAX_RSS_INDICES)
2891 count = IXGBE_MAX_RSS_INDICES;
2892 adapter->ring_feature[RING_F_RSS].limit = count;
2893
2894 #ifdef IXGBE_FCOE
2895 /* cap FCoE limit at 8 */
2896 if (count > IXGBE_FCRETA_SIZE)
2897 count = IXGBE_FCRETA_SIZE;
2898 adapter->ring_feature[RING_F_FCOE].limit = count;
2899
2900 #endif
2901 /* use setup TC to update any traffic class queue mapping */
2902 return ixgbe_setup_tc(dev, netdev_get_num_tc(dev));
2903 }
2904
2905 static int ixgbe_get_module_info(struct net_device *dev,
2906 struct ethtool_modinfo *modinfo)
2907 {
2908 struct ixgbe_adapter *adapter = netdev_priv(dev);
2909 struct ixgbe_hw *hw = &adapter->hw;
2910 u32 status;
2911 u8 sff8472_rev, addr_mode;
2912 int ret_val = 0;
2913 bool page_swap = false;
2914
2915 /* avoid concurent i2c reads */
2916 while (test_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
2917 msleep(100);
2918
2919 /* used by the service task */
2920 set_bit(__IXGBE_READ_I2C, &adapter->state);
2921
2922 /* Check whether we support SFF-8472 or not */
2923 status = hw->phy.ops.read_i2c_eeprom(hw,
2924 IXGBE_SFF_SFF_8472_COMP,
2925 &sff8472_rev);
2926 if (status != 0) {
2927 ret_val = -EIO;
2928 goto err_out;
2929 }
2930
2931 /* addressing mode is not supported */
2932 status = hw->phy.ops.read_i2c_eeprom(hw,
2933 IXGBE_SFF_SFF_8472_SWAP,
2934 &addr_mode);
2935 if (status != 0) {
2936 ret_val = -EIO;
2937 goto err_out;
2938 }
2939
2940 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
2941 e_err(drv, "Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n");
2942 page_swap = true;
2943 }
2944
2945 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
2946 /* We have a SFP, but it does not support SFF-8472 */
2947 modinfo->type = ETH_MODULE_SFF_8079;
2948 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
2949 } else {
2950 /* We have a SFP which supports a revision of SFF-8472. */
2951 modinfo->type = ETH_MODULE_SFF_8472;
2952 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2953 }
2954
2955 err_out:
2956 clear_bit(__IXGBE_READ_I2C, &adapter->state);
2957 return ret_val;
2958 }
2959
2960 static int ixgbe_get_module_eeprom(struct net_device *dev,
2961 struct ethtool_eeprom *ee,
2962 u8 *data)
2963 {
2964 struct ixgbe_adapter *adapter = netdev_priv(dev);
2965 struct ixgbe_hw *hw = &adapter->hw;
2966 u32 status = IXGBE_ERR_PHY_ADDR_INVALID;
2967 u8 databyte = 0xFF;
2968 int i = 0;
2969 int ret_val = 0;
2970
2971 /* ixgbe_get_module_info is called before this function in all
2972 * cases, so we do not need any checks we already do above,
2973 * and can trust ee->len to be a known value.
2974 */
2975
2976 while (test_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
2977 msleep(100);
2978 set_bit(__IXGBE_READ_I2C, &adapter->state);
2979
2980 /* Read the first block, SFF-8079 */
2981 for (i = 0; i < ETH_MODULE_SFF_8079_LEN; i++) {
2982 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
2983 if (status != 0) {
2984 /* Error occured while reading module */
2985 ret_val = -EIO;
2986 goto err_out;
2987 }
2988 data[i] = databyte;
2989 }
2990
2991 /* If the second block is requested, check if SFF-8472 is supported. */
2992 if (ee->len == ETH_MODULE_SFF_8472_LEN) {
2993 if (data[IXGBE_SFF_SFF_8472_COMP] == IXGBE_SFF_SFF_8472_UNSUP)
2994 return -EOPNOTSUPP;
2995
2996 /* Read the second block, SFF-8472 */
2997 for (i = ETH_MODULE_SFF_8079_LEN;
2998 i < ETH_MODULE_SFF_8472_LEN; i++) {
2999 status = hw->phy.ops.read_i2c_sff8472(hw,
3000 i - ETH_MODULE_SFF_8079_LEN, &databyte);
3001 if (status != 0) {
3002 /* Error occured while reading module */
3003 ret_val = -EIO;
3004 goto err_out;
3005 }
3006 data[i] = databyte;
3007 }
3008 }
3009
3010 err_out:
3011 clear_bit(__IXGBE_READ_I2C, &adapter->state);
3012
3013 return ret_val;
3014 }
3015
3016 static const struct ethtool_ops ixgbe_ethtool_ops = {
3017 .get_settings = ixgbe_get_settings,
3018 .set_settings = ixgbe_set_settings,
3019 .get_drvinfo = ixgbe_get_drvinfo,
3020 .get_regs_len = ixgbe_get_regs_len,
3021 .get_regs = ixgbe_get_regs,
3022 .get_wol = ixgbe_get_wol,
3023 .set_wol = ixgbe_set_wol,
3024 .nway_reset = ixgbe_nway_reset,
3025 .get_link = ethtool_op_get_link,
3026 .get_eeprom_len = ixgbe_get_eeprom_len,
3027 .get_eeprom = ixgbe_get_eeprom,
3028 .set_eeprom = ixgbe_set_eeprom,
3029 .get_ringparam = ixgbe_get_ringparam,
3030 .set_ringparam = ixgbe_set_ringparam,
3031 .get_pauseparam = ixgbe_get_pauseparam,
3032 .set_pauseparam = ixgbe_set_pauseparam,
3033 .get_msglevel = ixgbe_get_msglevel,
3034 .set_msglevel = ixgbe_set_msglevel,
3035 .self_test = ixgbe_diag_test,
3036 .get_strings = ixgbe_get_strings,
3037 .set_phys_id = ixgbe_set_phys_id,
3038 .get_sset_count = ixgbe_get_sset_count,
3039 .get_ethtool_stats = ixgbe_get_ethtool_stats,
3040 .get_coalesce = ixgbe_get_coalesce,
3041 .set_coalesce = ixgbe_set_coalesce,
3042 .get_rxnfc = ixgbe_get_rxnfc,
3043 .set_rxnfc = ixgbe_set_rxnfc,
3044 .get_channels = ixgbe_get_channels,
3045 .set_channels = ixgbe_set_channels,
3046 .get_ts_info = ixgbe_get_ts_info,
3047 .get_module_info = ixgbe_get_module_info,
3048 .get_module_eeprom = ixgbe_get_module_eeprom,
3049 };
3050
3051 void ixgbe_set_ethtool_ops(struct net_device *netdev)
3052 {
3053 SET_ETHTOOL_OPS(netdev, &ixgbe_ethtool_ops);
3054 }
CRIS linux kernel tree