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Linux 3.11-rc3
[cris-mirror.git] / drivers / net / wireless / ath / ath9k / ar9003_phy.c
blob1f694ab3cc78ba2ede3f7ca4b192c2e7dded96ab
1 /*
2 * Copyright (c) 2010-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/export.h>
18 #include "hw.h"
19 #include "ar9003_phy.h"
20
21 static const int firstep_table[] =
22 /* level: 0 1 2 3 4 5 6 7 8 */
23 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
24
25 static const int cycpwrThr1_table[] =
26 /* level: 0 1 2 3 4 5 6 7 8 */
27 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
28
29 /*
30 * register values to turn OFDM weak signal detection OFF
31 */
32 static const int m1ThreshLow_off = 127;
33 static const int m2ThreshLow_off = 127;
34 static const int m1Thresh_off = 127;
35 static const int m2Thresh_off = 127;
36 static const int m2CountThr_off = 31;
37 static const int m2CountThrLow_off = 63;
38 static const int m1ThreshLowExt_off = 127;
39 static const int m2ThreshLowExt_off = 127;
40 static const int m1ThreshExt_off = 127;
41 static const int m2ThreshExt_off = 127;
42
43 /**
44 * ar9003_hw_set_channel - set channel on single-chip device
45 * @ah: atheros hardware structure
46 * @chan:
47 *
48 * This is the function to change channel on single-chip devices, that is
49 * for AR9300 family of chipsets.
50 *
51 * This function takes the channel value in MHz and sets
52 * hardware channel value. Assumes writes have been enabled to analog bus.
53 *
54 * Actual Expression,
55 *
56 * For 2GHz channel,
57 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
58 * (freq_ref = 40MHz)
59 *
60 * For 5GHz channel,
61 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
62 * (freq_ref = 40MHz/(24>>amodeRefSel))
63 *
64 * For 5GHz channels which are 5MHz spaced,
65 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
66 * (freq_ref = 40MHz)
67 */
68 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
69 {
70 u16 bMode, fracMode = 0, aModeRefSel = 0;
71 u32 freq, chan_frac, div, channelSel = 0, reg32 = 0;
72 struct chan_centers centers;
73 int loadSynthChannel;
74
75 ath9k_hw_get_channel_centers(ah, chan, &centers);
76 freq = centers.synth_center;
77
78 if (freq < 4800) { /* 2 GHz, fractional mode */
79 if (AR_SREV_9330(ah)) {
80 if (ah->is_clk_25mhz)
81 div = 75;
82 else
83 div = 120;
84
85 channelSel = (freq * 4) / div;
86 chan_frac = (((freq * 4) % div) * 0x20000) / div;
87 channelSel = (channelSel << 17) | chan_frac;
88 } else if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
89 /*
90 * freq_ref = 40 / (refdiva >> amoderefsel);
91 * where refdiva=1 and amoderefsel=0
92 * ndiv = ((chan_mhz * 4) / 3) / freq_ref;
93 * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000
94 */
95 channelSel = (freq * 4) / 120;
96 chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
97 channelSel = (channelSel << 17) | chan_frac;
98 } else if (AR_SREV_9340(ah)) {
99 if (ah->is_clk_25mhz) {
100 channelSel = (freq * 2) / 75;
101 chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
102 channelSel = (channelSel << 17) | chan_frac;
103 } else {
104 channelSel = CHANSEL_2G(freq) >> 1;
105 }
106 } else if (AR_SREV_9550(ah)) {
107 if (ah->is_clk_25mhz)
108 div = 75;
109 else
110 div = 120;
111
112 channelSel = (freq * 4) / div;
113 chan_frac = (((freq * 4) % div) * 0x20000) / div;
114 channelSel = (channelSel << 17) | chan_frac;
115 } else {
116 channelSel = CHANSEL_2G(freq);
117 }
118 /* Set to 2G mode */
119 bMode = 1;
120 } else {
121 if ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) &&
122 ah->is_clk_25mhz) {
123 channelSel = freq / 75;
124 chan_frac = ((freq % 75) * 0x20000) / 75;
125 channelSel = (channelSel << 17) | chan_frac;
126 } else {
127 channelSel = CHANSEL_5G(freq);
128 /* Doubler is ON, so, divide channelSel by 2. */
129 channelSel >>= 1;
130 }
131 /* Set to 5G mode */
132 bMode = 0;
133 }
134
135 /* Enable fractional mode for all channels */
136 fracMode = 1;
137 aModeRefSel = 0;
138 loadSynthChannel = 0;
139
140 reg32 = (bMode << 29);
141 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
142
143 /* Enable Long shift Select for Synthesizer */
144 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
145 AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
146
147 /* Program Synth. setting */
148 reg32 = (channelSel << 2) | (fracMode << 30) |
149 (aModeRefSel << 28) | (loadSynthChannel << 31);
150 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
151
152 /* Toggle Load Synth channel bit */
153 loadSynthChannel = 1;
154 reg32 = (channelSel << 2) | (fracMode << 30) |
155 (aModeRefSel << 28) | (loadSynthChannel << 31);
156 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
157
158 ah->curchan = chan;
159
160 return 0;
161 }
162
163 /**
164 * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
165 * @ah: atheros hardware structure
166 * @chan:
167 *
168 * For single-chip solutions. Converts to baseband spur frequency given the
169 * input channel frequency and compute register settings below.
170 *
171 * Spur mitigation for MRC CCK
172 */
173 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
174 struct ath9k_channel *chan)
175 {
176 static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
177 int cur_bb_spur, negative = 0, cck_spur_freq;
178 int i;
179 int range, max_spur_cnts, synth_freq;
180 u8 *spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, IS_CHAN_2GHZ(chan));
181
182 /*
183 * Need to verify range +/- 10 MHz in control channel, otherwise spur
184 * is out-of-band and can be ignored.
185 */
186
187 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
188 AR_SREV_9550(ah)) {
189 if (spur_fbin_ptr[0] == 0) /* No spur */
190 return;
191 max_spur_cnts = 5;
192 if (IS_CHAN_HT40(chan)) {
193 range = 19;
194 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
195 AR_PHY_GC_DYN2040_PRI_CH) == 0)
196 synth_freq = chan->channel + 10;
197 else
198 synth_freq = chan->channel - 10;
199 } else {
200 range = 10;
201 synth_freq = chan->channel;
202 }
203 } else {
204 range = AR_SREV_9462(ah) ? 5 : 10;
205 max_spur_cnts = 4;
206 synth_freq = chan->channel;
207 }
208
209 for (i = 0; i < max_spur_cnts; i++) {
210 if (AR_SREV_9462(ah) && (i == 0 || i == 3))
211 continue;
212
213 negative = 0;
214 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
215 AR_SREV_9550(ah))
216 cur_bb_spur = ath9k_hw_fbin2freq(spur_fbin_ptr[i],
217 IS_CHAN_2GHZ(chan));
218 else
219 cur_bb_spur = spur_freq[i];
220
221 cur_bb_spur -= synth_freq;
222 if (cur_bb_spur < 0) {
223 negative = 1;
224 cur_bb_spur = -cur_bb_spur;
225 }
226 if (cur_bb_spur < range) {
227 cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
228
229 if (negative == 1)
230 cck_spur_freq = -cck_spur_freq;
231
232 cck_spur_freq = cck_spur_freq & 0xfffff;
233
234 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
235 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
236 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
237 AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
238 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
239 AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
240 0x2);
241 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
242 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
243 0x1);
244 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
245 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
246 cck_spur_freq);
247
248 return;
249 }
250 }
251
252 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
253 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
254 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
255 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
256 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
257 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
258 }
259
260 /* Clean all spur register fields */
261 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
262 {
263 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
264 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
265 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
266 AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
267 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
268 AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
269 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
270 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
271 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
272 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
273 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
274 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
275 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
276 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
277 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
278 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
279 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
280 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
281
282 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
283 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
284 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
285 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
286 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
287 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
288 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
289 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
290 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
291 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
292 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
293 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
294 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
295 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
296 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
297 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
298 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
299 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
300 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
301 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
302 }
303
304 static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
305 int freq_offset,
306 int spur_freq_sd,
307 int spur_delta_phase,
308 int spur_subchannel_sd,
309 int range,
310 int synth_freq)
311 {
312 int mask_index = 0;
313
314 /* OFDM Spur mitigation */
315 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
316 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
317 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
318 AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
319 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
320 AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
321 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
322 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
323 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
324 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
325
326 if (!(AR_SREV_9565(ah) && range == 10 && synth_freq == 2437))
327 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
328 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
329
330 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
331 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
332 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
333 AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
334 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
335 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
336
337 if (!AR_SREV_9340(ah) &&
338 REG_READ_FIELD(ah, AR_PHY_MODE,
339 AR_PHY_MODE_DYNAMIC) == 0x1)
340 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
341 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
342
343 mask_index = (freq_offset << 4) / 5;
344 if (mask_index < 0)
345 mask_index = mask_index - 1;
346
347 mask_index = mask_index & 0x7f;
348
349 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
350 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
351 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
352 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
353 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
354 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
355 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
356 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
357 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
358 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
359 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
360 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
361 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
362 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
363 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
364 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
365 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
366 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
367 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
368 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
369 }
370
371 static void ar9003_hw_spur_ofdm_9565(struct ath_hw *ah,
372 int freq_offset)
373 {
374 int mask_index = 0;
375
376 mask_index = (freq_offset << 4) / 5;
377 if (mask_index < 0)
378 mask_index = mask_index - 1;
379
380 mask_index = mask_index & 0x7f;
381
382 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
383 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B,
384 mask_index);
385
386 /* A == B */
387 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
388 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A,
389 mask_index);
390
391 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
392 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B,
393 mask_index);
394 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
395 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_B, 0xe);
396 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
397 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_B, 0xe);
398
399 /* A == B */
400 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
401 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
402 }
403
404 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
405 struct ath9k_channel *chan,
406 int freq_offset,
407 int range,
408 int synth_freq)
409 {
410 int spur_freq_sd = 0;
411 int spur_subchannel_sd = 0;
412 int spur_delta_phase = 0;
413
414 if (IS_CHAN_HT40(chan)) {
415 if (freq_offset < 0) {
416 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
417 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
418 spur_subchannel_sd = 1;
419 else
420 spur_subchannel_sd = 0;
421
422 spur_freq_sd = ((freq_offset + 10) << 9) / 11;
423
424 } else {
425 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
426 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
427 spur_subchannel_sd = 0;
428 else
429 spur_subchannel_sd = 1;
430
431 spur_freq_sd = ((freq_offset - 10) << 9) / 11;
432
433 }
434
435 spur_delta_phase = (freq_offset << 17) / 5;
436
437 } else {
438 spur_subchannel_sd = 0;
439 spur_freq_sd = (freq_offset << 9) /11;
440 spur_delta_phase = (freq_offset << 18) / 5;
441 }
442
443 spur_freq_sd = spur_freq_sd & 0x3ff;
444 spur_delta_phase = spur_delta_phase & 0xfffff;
445
446 ar9003_hw_spur_ofdm(ah,
447 freq_offset,
448 spur_freq_sd,
449 spur_delta_phase,
450 spur_subchannel_sd,
451 range, synth_freq);
452 }
453
454 /* Spur mitigation for OFDM */
455 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
456 struct ath9k_channel *chan)
457 {
458 int synth_freq;
459 int range = 10;
460 int freq_offset = 0;
461 int mode;
462 u8* spurChansPtr;
463 unsigned int i;
464 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
465
466 if (IS_CHAN_5GHZ(chan)) {
467 spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
468 mode = 0;
469 }
470 else {
471 spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
472 mode = 1;
473 }
474
475 if (spurChansPtr[0] == 0)
476 return; /* No spur in the mode */
477
478 if (IS_CHAN_HT40(chan)) {
479 range = 19;
480 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
481 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
482 synth_freq = chan->channel - 10;
483 else
484 synth_freq = chan->channel + 10;
485 } else {
486 range = 10;
487 synth_freq = chan->channel;
488 }
489
490 ar9003_hw_spur_ofdm_clear(ah);
491
492 for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) {
493 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i], mode);
494 freq_offset -= synth_freq;
495 if (abs(freq_offset) < range) {
496 ar9003_hw_spur_ofdm_work(ah, chan, freq_offset,
497 range, synth_freq);
498
499 if (AR_SREV_9565(ah) && (i < 4)) {
500 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i + 1],
501 mode);
502 freq_offset -= synth_freq;
503 if (abs(freq_offset) < range)
504 ar9003_hw_spur_ofdm_9565(ah, freq_offset);
505 }
506
507 break;
508 }
509 }
510 }
511
512 static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
513 struct ath9k_channel *chan)
514 {
515 if (!AR_SREV_9565(ah))
516 ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
517 ar9003_hw_spur_mitigate_ofdm(ah, chan);
518 }
519
520 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
521 struct ath9k_channel *chan)
522 {
523 u32 pll;
524
525 pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
526
527 if (chan && IS_CHAN_HALF_RATE(chan))
528 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
529 else if (chan && IS_CHAN_QUARTER_RATE(chan))
530 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
531
532 pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
533
534 return pll;
535 }
536
537 static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
538 struct ath9k_channel *chan)
539 {
540 u32 phymode;
541 u32 enableDacFifo = 0;
542
543 enableDacFifo =
544 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
545
546 /* Enable 11n HT, 20 MHz */
547 phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 |
548 AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
549
550 /* Configure baseband for dynamic 20/40 operation */
551 if (IS_CHAN_HT40(chan)) {
552 phymode |= AR_PHY_GC_DYN2040_EN;
553 /* Configure control (primary) channel at +-10MHz */
554 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
555 (chan->chanmode == CHANNEL_G_HT40PLUS))
556 phymode |= AR_PHY_GC_DYN2040_PRI_CH;
557
558 }
559
560 /* make sure we preserve INI settings */
561 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
562 /* turn off Green Field detection for STA for now */
563 phymode &= ~AR_PHY_GC_GF_DETECT_EN;
564
565 REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
566
567 /* Configure MAC for 20/40 operation */
568 ath9k_hw_set11nmac2040(ah);
569
570 /* global transmit timeout (25 TUs default)*/
571 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
572 /* carrier sense timeout */
573 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
574 }
575
576 static void ar9003_hw_init_bb(struct ath_hw *ah,
577 struct ath9k_channel *chan)
578 {
579 u32 synthDelay;
580
581 /*
582 * Wait for the frequency synth to settle (synth goes on
583 * via AR_PHY_ACTIVE_EN). Read the phy active delay register.
584 * Value is in 100ns increments.
585 */
586 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
587
588 /* Activate the PHY (includes baseband activate + synthesizer on) */
589 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
590 ath9k_hw_synth_delay(ah, chan, synthDelay);
591 }
592
593 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
594 {
595 if (ah->caps.tx_chainmask == 5 || ah->caps.rx_chainmask == 5)
596 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
597 AR_PHY_SWAP_ALT_CHAIN);
598
599 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
600 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
601
602 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
603 tx = 3;
604
605 REG_WRITE(ah, AR_SELFGEN_MASK, tx);
606 }
607
608 /*
609 * Override INI values with chip specific configuration.
610 */
611 static void ar9003_hw_override_ini(struct ath_hw *ah)
612 {
613 u32 val;
614
615 /*
616 * Set the RX_ABORT and RX_DIS and clear it only after
617 * RXE is set for MAC. This prevents frames with
618 * corrupted descriptor status.
619 */
620 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
621
622 /*
623 * For AR9280 and above, there is a new feature that allows
624 * Multicast search based on both MAC Address and Key ID. By default,
625 * this feature is enabled. But since the driver is not using this
626 * feature, we switch it off; otherwise multicast search based on
627 * MAC addr only will fail.
628 */
629 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
630 REG_WRITE(ah, AR_PCU_MISC_MODE2,
631 val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE);
632
633 REG_SET_BIT(ah, AR_PHY_CCK_DETECT,
634 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
635 }
636
637 static void ar9003_hw_prog_ini(struct ath_hw *ah,
638 struct ar5416IniArray *iniArr,
639 int column)
640 {
641 unsigned int i, regWrites = 0;
642
643 /* New INI format: Array may be undefined (pre, core, post arrays) */
644 if (!iniArr->ia_array)
645 return;
646
647 /*
648 * New INI format: Pre, core, and post arrays for a given subsystem
649 * may be modal (> 2 columns) or non-modal (2 columns). Determine if
650 * the array is non-modal and force the column to 1.
651 */
652 if (column >= iniArr->ia_columns)
653 column = 1;
654
655 for (i = 0; i < iniArr->ia_rows; i++) {
656 u32 reg = INI_RA(iniArr, i, 0);
657 u32 val = INI_RA(iniArr, i, column);
658
659 REG_WRITE(ah, reg, val);
660
661 DO_DELAY(regWrites);
662 }
663 }
664
665 static int ar9550_hw_get_modes_txgain_index(struct ath_hw *ah,
666 struct ath9k_channel *chan)
667 {
668 int ret;
669
670 switch (chan->chanmode) {
671 case CHANNEL_A:
672 case CHANNEL_A_HT20:
673 if (chan->channel <= 5350)
674 ret = 1;
675 else if ((chan->channel > 5350) && (chan->channel <= 5600))
676 ret = 3;
677 else
678 ret = 5;
679 break;
680
681 case CHANNEL_A_HT40PLUS:
682 case CHANNEL_A_HT40MINUS:
683 if (chan->channel <= 5350)
684 ret = 2;
685 else if ((chan->channel > 5350) && (chan->channel <= 5600))
686 ret = 4;
687 else
688 ret = 6;
689 break;
690
691 case CHANNEL_G:
692 case CHANNEL_G_HT20:
693 case CHANNEL_B:
694 ret = 8;
695 break;
696
697 case CHANNEL_G_HT40PLUS:
698 case CHANNEL_G_HT40MINUS:
699 ret = 7;
700 break;
701
702 default:
703 ret = -EINVAL;
704 }
705
706 return ret;
707 }
708
709 static int ar9003_hw_process_ini(struct ath_hw *ah,
710 struct ath9k_channel *chan)
711 {
712 unsigned int regWrites = 0, i;
713 u32 modesIndex;
714
715 switch (chan->chanmode) {
716 case CHANNEL_A:
717 case CHANNEL_A_HT20:
718 modesIndex = 1;
719 break;
720 case CHANNEL_A_HT40PLUS:
721 case CHANNEL_A_HT40MINUS:
722 modesIndex = 2;
723 break;
724 case CHANNEL_G:
725 case CHANNEL_G_HT20:
726 case CHANNEL_B:
727 modesIndex = 4;
728 break;
729 case CHANNEL_G_HT40PLUS:
730 case CHANNEL_G_HT40MINUS:
731 modesIndex = 3;
732 break;
733
734 default:
735 return -EINVAL;
736 }
737
738 /*
739 * SOC, MAC, BB, RADIO initvals.
740 */
741 for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
742 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
743 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
744 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
745 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
746 if (i == ATH_INI_POST && AR_SREV_9462_20_OR_LATER(ah))
747 ar9003_hw_prog_ini(ah,
748 &ah->ini_radio_post_sys2ant,
749 modesIndex);
750 }
751
752 /*
753 * RXGAIN initvals.
754 */
755 REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
756
757 if (AR_SREV_9462_20_OR_LATER(ah)) {
758 /*
759 * CUS217 mix LNA mode.
760 */
761 if (ar9003_hw_get_rx_gain_idx(ah) == 2) {
762 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core,
763 1, regWrites);
764 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
765 modesIndex, regWrites);
766 }
767
768 /*
769 * 5G-XLNA
770 */
771 if ((ar9003_hw_get_rx_gain_idx(ah) == 2) ||
772 (ar9003_hw_get_rx_gain_idx(ah) == 3)) {
773 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
774 modesIndex, regWrites);
775 }
776 }
777
778 if (AR_SREV_9550(ah))
779 REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex,
780 regWrites);
781
782 /*
783 * TXGAIN initvals.
784 */
785 if (AR_SREV_9550(ah)) {
786 int modes_txgain_index;
787
788 modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan);
789 if (modes_txgain_index < 0)
790 return -EINVAL;
791
792 REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index,
793 regWrites);
794 } else {
795 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
796 }
797
798 /*
799 * For 5GHz channels requiring Fast Clock, apply
800 * different modal values.
801 */
802 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
803 REG_WRITE_ARRAY(&ah->iniModesFastClock,
804 modesIndex, regWrites);
805
806 /*
807 * Clock frequency initvals.
808 */
809 REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
810
811 /*
812 * JAPAN regulatory.
813 */
814 if (chan->channel == 2484)
815 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
816
817 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
818 REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE,
819 AR_GLB_SWREG_DISCONT_EN_BT_WLAN);
820
821 ah->modes_index = modesIndex;
822 ar9003_hw_override_ini(ah);
823 ar9003_hw_set_channel_regs(ah, chan);
824 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
825 ath9k_hw_apply_txpower(ah, chan, false);
826
827 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
828 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
829 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))
830 ah->enabled_cals |= TX_IQ_CAL;
831 else
832 ah->enabled_cals &= ~TX_IQ_CAL;
833
834 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
835 ah->enabled_cals |= TX_CL_CAL;
836 else
837 ah->enabled_cals &= ~TX_CL_CAL;
838 }
839
840 return 0;
841 }
842
843 static void ar9003_hw_set_rfmode(struct ath_hw *ah,
844 struct ath9k_channel *chan)
845 {
846 u32 rfMode = 0;
847
848 if (chan == NULL)
849 return;
850
851 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
852 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
853
854 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
855 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
856 if (IS_CHAN_QUARTER_RATE(chan))
857 rfMode |= AR_PHY_MODE_QUARTER;
858 if (IS_CHAN_HALF_RATE(chan))
859 rfMode |= AR_PHY_MODE_HALF;
860
861 if (rfMode & (AR_PHY_MODE_QUARTER | AR_PHY_MODE_HALF))
862 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
863 AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW, 3);
864
865 REG_WRITE(ah, AR_PHY_MODE, rfMode);
866 }
867
868 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
869 {
870 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
871 }
872
873 static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
874 struct ath9k_channel *chan)
875 {
876 u32 coef_scaled, ds_coef_exp, ds_coef_man;
877 u32 clockMhzScaled = 0x64000000;
878 struct chan_centers centers;
879
880 /*
881 * half and quarter rate can divide the scaled clock by 2 or 4
882 * scale for selected channel bandwidth
883 */
884 if (IS_CHAN_HALF_RATE(chan))
885 clockMhzScaled = clockMhzScaled >> 1;
886 else if (IS_CHAN_QUARTER_RATE(chan))
887 clockMhzScaled = clockMhzScaled >> 2;
888
889 /*
890 * ALGO -> coef = 1e8/fcarrier*fclock/40;
891 * scaled coef to provide precision for this floating calculation
892 */
893 ath9k_hw_get_channel_centers(ah, chan, &centers);
894 coef_scaled = clockMhzScaled / centers.synth_center;
895
896 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
897 &ds_coef_exp);
898
899 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
900 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
901 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
902 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
903
904 /*
905 * For Short GI,
906 * scaled coeff is 9/10 that of normal coeff
907 */
908 coef_scaled = (9 * coef_scaled) / 10;
909
910 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
911 &ds_coef_exp);
912
913 /* for short gi */
914 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
915 AR_PHY_SGI_DSC_MAN, ds_coef_man);
916 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
917 AR_PHY_SGI_DSC_EXP, ds_coef_exp);
918 }
919
920 static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
921 {
922 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
923 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
924 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
925 }
926
927 /*
928 * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
929 * Read the phy active delay register. Value is in 100ns increments.
930 */
931 static void ar9003_hw_rfbus_done(struct ath_hw *ah)
932 {
933 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
934
935 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay);
936
937 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
938 }
939
940 static bool ar9003_hw_ani_control(struct ath_hw *ah,
941 enum ath9k_ani_cmd cmd, int param)
942 {
943 struct ath_common *common = ath9k_hw_common(ah);
944 struct ath9k_channel *chan = ah->curchan;
945 struct ar5416AniState *aniState = &ah->ani;
946 int m1ThreshLow, m2ThreshLow;
947 int m1Thresh, m2Thresh;
948 int m2CountThr, m2CountThrLow;
949 int m1ThreshLowExt, m2ThreshLowExt;
950 int m1ThreshExt, m2ThreshExt;
951 s32 value, value2;
952
953 switch (cmd & ah->ani_function) {
954 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
955 /*
956 * on == 1 means ofdm weak signal detection is ON
957 * on == 1 is the default, for less noise immunity
958 *
959 * on == 0 means ofdm weak signal detection is OFF
960 * on == 0 means more noise imm
961 */
962 u32 on = param ? 1 : 0;
963
964 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
965 goto skip_ws_det;
966
967 m1ThreshLow = on ?
968 aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
969 m2ThreshLow = on ?
970 aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
971 m1Thresh = on ?
972 aniState->iniDef.m1Thresh : m1Thresh_off;
973 m2Thresh = on ?
974 aniState->iniDef.m2Thresh : m2Thresh_off;
975 m2CountThr = on ?
976 aniState->iniDef.m2CountThr : m2CountThr_off;
977 m2CountThrLow = on ?
978 aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
979 m1ThreshLowExt = on ?
980 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
981 m2ThreshLowExt = on ?
982 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
983 m1ThreshExt = on ?
984 aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
985 m2ThreshExt = on ?
986 aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
987
988 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
989 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
990 m1ThreshLow);
991 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
992 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
993 m2ThreshLow);
994 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
995 AR_PHY_SFCORR_M1_THRESH,
996 m1Thresh);
997 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
998 AR_PHY_SFCORR_M2_THRESH,
999 m2Thresh);
1000 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1001 AR_PHY_SFCORR_M2COUNT_THR,
1002 m2CountThr);
1003 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1004 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
1005 m2CountThrLow);
1006 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1007 AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
1008 m1ThreshLowExt);
1009 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1010 AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
1011 m2ThreshLowExt);
1012 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1013 AR_PHY_SFCORR_EXT_M1_THRESH,
1014 m1ThreshExt);
1015 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1016 AR_PHY_SFCORR_EXT_M2_THRESH,
1017 m2ThreshExt);
1018 skip_ws_det:
1019 if (on)
1020 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1021 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1022 else
1023 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1024 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1025
1026 if (on != aniState->ofdmWeakSigDetect) {
1027 ath_dbg(common, ANI,
1028 "** ch %d: ofdm weak signal: %s=>%s\n",
1029 chan->channel,
1030 aniState->ofdmWeakSigDetect ?
1031 "on" : "off",
1032 on ? "on" : "off");
1033 if (on)
1034 ah->stats.ast_ani_ofdmon++;
1035 else
1036 ah->stats.ast_ani_ofdmoff++;
1037 aniState->ofdmWeakSigDetect = on;
1038 }
1039 break;
1040 }
1041 case ATH9K_ANI_FIRSTEP_LEVEL:{
1042 u32 level = param;
1043
1044 if (level >= ARRAY_SIZE(firstep_table)) {
1045 ath_dbg(common, ANI,
1046 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
1047 level, ARRAY_SIZE(firstep_table));
1048 return false;
1049 }
1050
1051 /*
1052 * make register setting relative to default
1053 * from INI file & cap value
1054 */
1055 value = firstep_table[level] -
1056 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
1057 aniState->iniDef.firstep;
1058 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1059 value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1060 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1061 value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1062 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1063 AR_PHY_FIND_SIG_FIRSTEP,
1064 value);
1065 /*
1066 * we need to set first step low register too
1067 * make register setting relative to default
1068 * from INI file & cap value
1069 */
1070 value2 = firstep_table[level] -
1071 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
1072 aniState->iniDef.firstepLow;
1073 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1074 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1075 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1076 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1077
1078 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
1079 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
1080
1081 if (level != aniState->firstepLevel) {
1082 ath_dbg(common, ANI,
1083 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
1084 chan->channel,
1085 aniState->firstepLevel,
1086 level,
1087 ATH9K_ANI_FIRSTEP_LVL,
1088 value,
1089 aniState->iniDef.firstep);
1090 ath_dbg(common, ANI,
1091 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
1092 chan->channel,
1093 aniState->firstepLevel,
1094 level,
1095 ATH9K_ANI_FIRSTEP_LVL,
1096 value2,
1097 aniState->iniDef.firstepLow);
1098 if (level > aniState->firstepLevel)
1099 ah->stats.ast_ani_stepup++;
1100 else if (level < aniState->firstepLevel)
1101 ah->stats.ast_ani_stepdown++;
1102 aniState->firstepLevel = level;
1103 }
1104 break;
1105 }
1106 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1107 u32 level = param;
1108
1109 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
1110 ath_dbg(common, ANI,
1111 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
1112 level, ARRAY_SIZE(cycpwrThr1_table));
1113 return false;
1114 }
1115 /*
1116 * make register setting relative to default
1117 * from INI file & cap value
1118 */
1119 value = cycpwrThr1_table[level] -
1120 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
1121 aniState->iniDef.cycpwrThr1;
1122 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1123 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1124 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1125 value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1126 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1127 AR_PHY_TIMING5_CYCPWR_THR1,
1128 value);
1129
1130 /*
1131 * set AR_PHY_EXT_CCA for extension channel
1132 * make register setting relative to default
1133 * from INI file & cap value
1134 */
1135 value2 = cycpwrThr1_table[level] -
1136 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
1137 aniState->iniDef.cycpwrThr1Ext;
1138 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1139 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1140 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1141 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1142 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1143 AR_PHY_EXT_CYCPWR_THR1, value2);
1144
1145 if (level != aniState->spurImmunityLevel) {
1146 ath_dbg(common, ANI,
1147 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
1148 chan->channel,
1149 aniState->spurImmunityLevel,
1150 level,
1151 ATH9K_ANI_SPUR_IMMUNE_LVL,
1152 value,
1153 aniState->iniDef.cycpwrThr1);
1154 ath_dbg(common, ANI,
1155 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1156 chan->channel,
1157 aniState->spurImmunityLevel,
1158 level,
1159 ATH9K_ANI_SPUR_IMMUNE_LVL,
1160 value2,
1161 aniState->iniDef.cycpwrThr1Ext);
1162 if (level > aniState->spurImmunityLevel)
1163 ah->stats.ast_ani_spurup++;
1164 else if (level < aniState->spurImmunityLevel)
1165 ah->stats.ast_ani_spurdown++;
1166 aniState->spurImmunityLevel = level;
1167 }
1168 break;
1169 }
1170 case ATH9K_ANI_MRC_CCK:{
1171 /*
1172 * is_on == 1 means MRC CCK ON (default, less noise imm)
1173 * is_on == 0 means MRC CCK is OFF (more noise imm)
1174 */
1175 bool is_on = param ? 1 : 0;
1176 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1177 AR_PHY_MRC_CCK_ENABLE, is_on);
1178 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1179 AR_PHY_MRC_CCK_MUX_REG, is_on);
1180 if (is_on != aniState->mrcCCK) {
1181 ath_dbg(common, ANI, "** ch %d: MRC CCK: %s=>%s\n",
1182 chan->channel,
1183 aniState->mrcCCK ? "on" : "off",
1184 is_on ? "on" : "off");
1185 if (is_on)
1186 ah->stats.ast_ani_ccklow++;
1187 else
1188 ah->stats.ast_ani_cckhigh++;
1189 aniState->mrcCCK = is_on;
1190 }
1191 break;
1192 }
1193 case ATH9K_ANI_PRESENT:
1194 break;
1195 default:
1196 ath_dbg(common, ANI, "invalid cmd %u\n", cmd);
1197 return false;
1198 }
1199
1200 ath_dbg(common, ANI,
1201 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1202 aniState->spurImmunityLevel,
1203 aniState->ofdmWeakSigDetect ? "on" : "off",
1204 aniState->firstepLevel,
1205 aniState->mrcCCK ? "on" : "off",
1206 aniState->listenTime,
1207 aniState->ofdmPhyErrCount,
1208 aniState->cckPhyErrCount);
1209 return true;
1210 }
1211
1212 static void ar9003_hw_do_getnf(struct ath_hw *ah,
1213 int16_t nfarray[NUM_NF_READINGS])
1214 {
1215 #define AR_PHY_CH_MINCCA_PWR 0x1FF00000
1216 #define AR_PHY_CH_MINCCA_PWR_S 20
1217 #define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
1218 #define AR_PHY_CH_EXT_MINCCA_PWR_S 16
1219
1220 int16_t nf;
1221 int i;
1222
1223 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1224 if (ah->rxchainmask & BIT(i)) {
1225 nf = MS(REG_READ(ah, ah->nf_regs[i]),
1226 AR_PHY_CH_MINCCA_PWR);
1227 nfarray[i] = sign_extend32(nf, 8);
1228
1229 if (IS_CHAN_HT40(ah->curchan)) {
1230 u8 ext_idx = AR9300_MAX_CHAINS + i;
1231
1232 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
1233 AR_PHY_CH_EXT_MINCCA_PWR);
1234 nfarray[ext_idx] = sign_extend32(nf, 8);
1235 }
1236 }
1237 }
1238 }
1239
1240 static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
1241 {
1242 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1243 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
1244 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
1245 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1246 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1247 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
1248
1249 if (AR_SREV_9330(ah))
1250 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ;
1251
1252 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
1253 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ;
1254 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ;
1255 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ;
1256 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9462_5GHZ;
1257 }
1258 }
1259
1260 /*
1261 * Initialize the ANI register values with default (ini) values.
1262 * This routine is called during a (full) hardware reset after
1263 * all the registers are initialised from the INI.
1264 */
1265 static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1266 {
1267 struct ar5416AniState *aniState;
1268 struct ath_common *common = ath9k_hw_common(ah);
1269 struct ath9k_channel *chan = ah->curchan;
1270 struct ath9k_ani_default *iniDef;
1271 u32 val;
1272
1273 aniState = &ah->ani;
1274 iniDef = &aniState->iniDef;
1275
1276 ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
1277 ah->hw_version.macVersion,
1278 ah->hw_version.macRev,
1279 ah->opmode,
1280 chan->channel,
1281 chan->channelFlags);
1282
1283 val = REG_READ(ah, AR_PHY_SFCORR);
1284 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1285 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1286 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1287
1288 val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1289 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1290 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1291 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1292
1293 val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1294 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1295 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1296 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1297 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1298 iniDef->firstep = REG_READ_FIELD(ah,
1299 AR_PHY_FIND_SIG,
1300 AR_PHY_FIND_SIG_FIRSTEP);
1301 iniDef->firstepLow = REG_READ_FIELD(ah,
1302 AR_PHY_FIND_SIG_LOW,
1303 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
1304 iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1305 AR_PHY_TIMING5,
1306 AR_PHY_TIMING5_CYCPWR_THR1);
1307 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1308 AR_PHY_EXT_CCA,
1309 AR_PHY_EXT_CYCPWR_THR1);
1310
1311 /* these levels just got reset to defaults by the INI */
1312 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
1313 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
1314 aniState->ofdmWeakSigDetect = true;
1315 aniState->mrcCCK = true;
1316 }
1317
1318 static void ar9003_hw_set_radar_params(struct ath_hw *ah,
1319 struct ath_hw_radar_conf *conf)
1320 {
1321 u32 radar_0 = 0, radar_1 = 0;
1322
1323 if (!conf) {
1324 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1325 return;
1326 }
1327
1328 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1329 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1330 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1331 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1332 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1333 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1334
1335 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1336 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1337 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1338 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1339 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1340
1341 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1342 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1343 if (conf->ext_channel)
1344 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1345 else
1346 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1347 }
1348
1349 static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
1350 {
1351 struct ath_hw_radar_conf *conf = &ah->radar_conf;
1352
1353 conf->fir_power = -28;
1354 conf->radar_rssi = 0;
1355 conf->pulse_height = 10;
1356 conf->pulse_rssi = 24;
1357 conf->pulse_inband = 8;
1358 conf->pulse_maxlen = 255;
1359 conf->pulse_inband_step = 12;
1360 conf->radar_inband = 8;
1361 }
1362
1363 static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
1364 struct ath_hw_antcomb_conf *antconf)
1365 {
1366 u32 regval;
1367
1368 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1369 antconf->main_lna_conf = (regval & AR_PHY_ANT_DIV_MAIN_LNACONF) >>
1370 AR_PHY_ANT_DIV_MAIN_LNACONF_S;
1371 antconf->alt_lna_conf = (regval & AR_PHY_ANT_DIV_ALT_LNACONF) >>
1372 AR_PHY_ANT_DIV_ALT_LNACONF_S;
1373 antconf->fast_div_bias = (regval & AR_PHY_ANT_FAST_DIV_BIAS) >>
1374 AR_PHY_ANT_FAST_DIV_BIAS_S;
1375
1376 if (AR_SREV_9330_11(ah)) {
1377 antconf->lna1_lna2_delta = -9;
1378 antconf->div_group = 1;
1379 } else if (AR_SREV_9485(ah)) {
1380 antconf->lna1_lna2_delta = -9;
1381 antconf->div_group = 2;
1382 } else if (AR_SREV_9565(ah)) {
1383 antconf->lna1_lna2_delta = -3;
1384 antconf->div_group = 3;
1385 } else {
1386 antconf->lna1_lna2_delta = -3;
1387 antconf->div_group = 0;
1388 }
1389 }
1390
1391 static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
1392 struct ath_hw_antcomb_conf *antconf)
1393 {
1394 u32 regval;
1395
1396 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1397 regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1398 AR_PHY_ANT_DIV_ALT_LNACONF |
1399 AR_PHY_ANT_FAST_DIV_BIAS |
1400 AR_PHY_ANT_DIV_MAIN_GAINTB |
1401 AR_PHY_ANT_DIV_ALT_GAINTB);
1402 regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S)
1403 & AR_PHY_ANT_DIV_MAIN_LNACONF);
1404 regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S)
1405 & AR_PHY_ANT_DIV_ALT_LNACONF);
1406 regval |= ((antconf->fast_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S)
1407 & AR_PHY_ANT_FAST_DIV_BIAS);
1408 regval |= ((antconf->main_gaintb << AR_PHY_ANT_DIV_MAIN_GAINTB_S)
1409 & AR_PHY_ANT_DIV_MAIN_GAINTB);
1410 regval |= ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S)
1411 & AR_PHY_ANT_DIV_ALT_GAINTB);
1412
1413 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1414 }
1415
1416 static void ar9003_hw_antctrl_shared_chain_lnadiv(struct ath_hw *ah,
1417 bool enable)
1418 {
1419 u8 ant_div_ctl1;
1420 u32 regval;
1421
1422 if (!AR_SREV_9565(ah))
1423 return;
1424
1425 ah->shared_chain_lnadiv = enable;
1426 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
1427
1428 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1429 regval &= (~AR_ANT_DIV_CTRL_ALL);
1430 regval |= (ant_div_ctl1 & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
1431 regval &= ~AR_PHY_ANT_DIV_LNADIV;
1432 regval |= ((ant_div_ctl1 >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;
1433
1434 if (enable)
1435 regval |= AR_ANT_DIV_ENABLE;
1436
1437 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1438
1439 regval = REG_READ(ah, AR_PHY_CCK_DETECT);
1440 regval &= ~AR_FAST_DIV_ENABLE;
1441 regval |= ((ant_div_ctl1 >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;
1442
1443 if (enable)
1444 regval |= AR_FAST_DIV_ENABLE;
1445
1446 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
1447
1448 if (enable) {
1449 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1450 (1 << AR_PHY_ANT_SW_RX_PROT_S));
1451 if (ah->curchan && IS_CHAN_2GHZ(ah->curchan))
1452 REG_SET_BIT(ah, AR_PHY_RESTART,
1453 AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
1454 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV,
1455 AR_BTCOEX_WL_LNADIV_FORCE_ON);
1456 } else {
1457 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, AR_ANT_DIV_ENABLE);
1458 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1459 (1 << AR_PHY_ANT_SW_RX_PROT_S));
1460 REG_CLR_BIT(ah, AR_PHY_CCK_DETECT, AR_FAST_DIV_ENABLE);
1461 REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV,
1462 AR_BTCOEX_WL_LNADIV_FORCE_ON);
1463
1464 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1465 regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1466 AR_PHY_ANT_DIV_ALT_LNACONF |
1467 AR_PHY_ANT_DIV_MAIN_GAINTB |
1468 AR_PHY_ANT_DIV_ALT_GAINTB);
1469 regval |= (AR_PHY_ANT_DIV_LNA1 << AR_PHY_ANT_DIV_MAIN_LNACONF_S);
1470 regval |= (AR_PHY_ANT_DIV_LNA2 << AR_PHY_ANT_DIV_ALT_LNACONF_S);
1471 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1472 }
1473 }
1474
1475 static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
1476 struct ath9k_channel *chan,
1477 u8 *ini_reloaded)
1478 {
1479 unsigned int regWrites = 0;
1480 u32 modesIndex;
1481
1482 switch (chan->chanmode) {
1483 case CHANNEL_A:
1484 case CHANNEL_A_HT20:
1485 modesIndex = 1;
1486 break;
1487 case CHANNEL_A_HT40PLUS:
1488 case CHANNEL_A_HT40MINUS:
1489 modesIndex = 2;
1490 break;
1491 case CHANNEL_G:
1492 case CHANNEL_G_HT20:
1493 case CHANNEL_B:
1494 modesIndex = 4;
1495 break;
1496 case CHANNEL_G_HT40PLUS:
1497 case CHANNEL_G_HT40MINUS:
1498 modesIndex = 3;
1499 break;
1500
1501 default:
1502 return -EINVAL;
1503 }
1504
1505 if (modesIndex == ah->modes_index) {
1506 *ini_reloaded = false;
1507 goto set_rfmode;
1508 }
1509
1510 ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex);
1511 ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex);
1512 ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex);
1513 ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex);
1514
1515 if (AR_SREV_9462_20_OR_LATER(ah))
1516 ar9003_hw_prog_ini(ah, &ah->ini_radio_post_sys2ant,
1517 modesIndex);
1518
1519 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1520
1521 /*
1522 * For 5GHz channels requiring Fast Clock, apply
1523 * different modal values.
1524 */
1525 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1526 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites);
1527
1528 if (AR_SREV_9565(ah))
1529 REG_WRITE_ARRAY(&ah->iniModesFastClock, 1, regWrites);
1530
1531 REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
1532
1533 ah->modes_index = modesIndex;
1534 *ini_reloaded = true;
1535
1536 set_rfmode:
1537 ar9003_hw_set_rfmode(ah, chan);
1538 return 0;
1539 }
1540
1541 static void ar9003_hw_spectral_scan_config(struct ath_hw *ah,
1542 struct ath_spec_scan *param)
1543 {
1544 u8 count;
1545
1546 if (!param->enabled) {
1547 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1548 AR_PHY_SPECTRAL_SCAN_ENABLE);
1549 return;
1550 }
1551
1552 REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA);
1553 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE);
1554
1555 /* on AR93xx and newer, count = 0 will make the the chip send
1556 * spectral samples endlessly. Check if this really was intended,
1557 * and fix otherwise.
1558 */
1559 count = param->count;
1560 if (param->endless)
1561 count = 0;
1562 else if (param->count == 0)
1563 count = 1;
1564
1565 if (param->short_repeat)
1566 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1567 AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT);
1568 else
1569 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1570 AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT);
1571
1572 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1573 AR_PHY_SPECTRAL_SCAN_COUNT, count);
1574 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1575 AR_PHY_SPECTRAL_SCAN_PERIOD, param->period);
1576 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1577 AR_PHY_SPECTRAL_SCAN_FFT_PERIOD, param->fft_period);
1578
1579 return;
1580 }
1581
1582 static void ar9003_hw_spectral_scan_trigger(struct ath_hw *ah)
1583 {
1584 /* Activate spectral scan */
1585 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1586 AR_PHY_SPECTRAL_SCAN_ACTIVE);
1587 }
1588
1589 static void ar9003_hw_spectral_scan_wait(struct ath_hw *ah)
1590 {
1591 struct ath_common *common = ath9k_hw_common(ah);
1592
1593 /* Poll for spectral scan complete */
1594 if (!ath9k_hw_wait(ah, AR_PHY_SPECTRAL_SCAN,
1595 AR_PHY_SPECTRAL_SCAN_ACTIVE,
1596 0, AH_WAIT_TIMEOUT)) {
1597 ath_err(common, "spectral scan wait failed\n");
1598 return;
1599 }
1600 }
1601
1602 void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1603 {
1604 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1605 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1606 static const u32 ar9300_cca_regs[6] = {
1607 AR_PHY_CCA_0,
1608 AR_PHY_CCA_1,
1609 AR_PHY_CCA_2,
1610 AR_PHY_EXT_CCA,
1611 AR_PHY_EXT_CCA_1,
1612 AR_PHY_EXT_CCA_2,
1613 };
1614
1615 priv_ops->rf_set_freq = ar9003_hw_set_channel;
1616 priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
1617 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
1618 priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
1619 priv_ops->init_bb = ar9003_hw_init_bb;
1620 priv_ops->process_ini = ar9003_hw_process_ini;
1621 priv_ops->set_rfmode = ar9003_hw_set_rfmode;
1622 priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
1623 priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
1624 priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1625 priv_ops->rfbus_done = ar9003_hw_rfbus_done;
1626 priv_ops->ani_control = ar9003_hw_ani_control;
1627 priv_ops->do_getnf = ar9003_hw_do_getnf;
1628 priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
1629 priv_ops->set_radar_params = ar9003_hw_set_radar_params;
1630 priv_ops->fast_chan_change = ar9003_hw_fast_chan_change;
1631
1632 ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
1633 ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
1634 ops->antctrl_shared_chain_lnadiv = ar9003_hw_antctrl_shared_chain_lnadiv;
1635 ops->spectral_scan_config = ar9003_hw_spectral_scan_config;
1636 ops->spectral_scan_trigger = ar9003_hw_spectral_scan_trigger;
1637 ops->spectral_scan_wait = ar9003_hw_spectral_scan_wait;
1638
1639 ar9003_hw_set_nf_limits(ah);
1640 ar9003_hw_set_radar_conf(ah);
1641 memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
1642 }
1643
1644 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
1645 {
1646 struct ath_common *common = ath9k_hw_common(ah);
1647 u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms;
1648 u32 val, idle_count;
1649
1650 if (!idle_tmo_ms) {
1651 /* disable IRQ, disable chip-reset for BB panic */
1652 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1653 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) &
1654 ~(AR_PHY_WATCHDOG_RST_ENABLE |
1655 AR_PHY_WATCHDOG_IRQ_ENABLE));
1656
1657 /* disable watchdog in non-IDLE mode, disable in IDLE mode */
1658 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1659 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) &
1660 ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1661 AR_PHY_WATCHDOG_IDLE_ENABLE));
1662
1663 ath_dbg(common, RESET, "Disabled BB Watchdog\n");
1664 return;
1665 }
1666
1667 /* enable IRQ, disable chip-reset for BB watchdog */
1668 val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK;
1669 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1670 (val | AR_PHY_WATCHDOG_IRQ_ENABLE) &
1671 ~AR_PHY_WATCHDOG_RST_ENABLE);
1672
1673 /* bound limit to 10 secs */
1674 if (idle_tmo_ms > 10000)
1675 idle_tmo_ms = 10000;
1676
1677 /*
1678 * The time unit for watchdog event is 2^15 44/88MHz cycles.
1679 *
1680 * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick
1681 * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick
1682 *
1683 * Given we use fast clock now in 5 GHz, these time units should
1684 * be common for both 2 GHz and 5 GHz.
1685 */
1686 idle_count = (100 * idle_tmo_ms) / 74;
1687 if (ah->curchan && IS_CHAN_HT40(ah->curchan))
1688 idle_count = (100 * idle_tmo_ms) / 37;
1689
1690 /*
1691 * enable watchdog in non-IDLE mode, disable in IDLE mode,
1692 * set idle time-out.
1693 */
1694 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1695 AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1696 AR_PHY_WATCHDOG_IDLE_MASK |
1697 (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
1698
1699 ath_dbg(common, RESET, "Enabled BB Watchdog timeout (%u ms)\n",
1700 idle_tmo_ms);
1701 }
1702
1703 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
1704 {
1705 /*
1706 * we want to avoid printing in ISR context so we save the
1707 * watchdog status to be printed later in bottom half context.
1708 */
1709 ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS);
1710
1711 /*
1712 * the watchdog timer should reset on status read but to be sure
1713 * sure we write 0 to the watchdog status bit.
1714 */
1715 REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,
1716 ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR);
1717 }
1718
1719 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
1720 {
1721 struct ath_common *common = ath9k_hw_common(ah);
1722 u32 status;
1723
1724 if (likely(!(common->debug_mask & ATH_DBG_RESET)))
1725 return;
1726
1727 status = ah->bb_watchdog_last_status;
1728 ath_dbg(common, RESET,
1729 "\n==== BB update: BB status=0x%08x ====\n", status);
1730 ath_dbg(common, RESET,
1731 "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
1732 MS(status, AR_PHY_WATCHDOG_INFO),
1733 MS(status, AR_PHY_WATCHDOG_DET_HANG),
1734 MS(status, AR_PHY_WATCHDOG_RADAR_SM),
1735 MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
1736 MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
1737 MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
1738 MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
1739 MS(status, AR_PHY_WATCHDOG_AGC_SM),
1740 MS(status, AR_PHY_WATCHDOG_SRCH_SM));
1741
1742 ath_dbg(common, RESET, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
1743 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
1744 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
1745 ath_dbg(common, RESET, "** BB mode: BB_gen_controls=0x%08x **\n",
1746 REG_READ(ah, AR_PHY_GEN_CTRL));
1747
1748 #define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles)
1749 if (common->cc_survey.cycles)
1750 ath_dbg(common, RESET,
1751 "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n",
1752 PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
1753
1754 ath_dbg(common, RESET, "==== BB update: done ====\n\n");
1755 }
1756 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);
1757
1758 void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
1759 {
1760 u32 val;
1761
1762 /* While receiving unsupported rate frame rx state machine
1763 * gets into a state 0xb and if phy_restart happens in that
1764 * state, BB would go hang. If RXSM is in 0xb state after
1765 * first bb panic, ensure to disable the phy_restart.
1766 */
1767 if (!((MS(ah->bb_watchdog_last_status,
1768 AR_PHY_WATCHDOG_RX_OFDM_SM) == 0xb) ||
1769 ah->bb_hang_rx_ofdm))
1770 return;
1771
1772 ah->bb_hang_rx_ofdm = true;
1773 val = REG_READ(ah, AR_PHY_RESTART);
1774 val &= ~AR_PHY_RESTART_ENA;
1775
1776 REG_WRITE(ah, AR_PHY_RESTART, val);
1777 }
1778 EXPORT_SYMBOL(ar9003_hw_disable_phy_restart);
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