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Linux 3.11-rc3
[cris-mirror.git] / drivers / net / wireless / iwlwifi / pcie / trans.c
blob826c15602c469a524b857c135f7b38cb4e5782a1
1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2007 - 2013 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called COPYING.
26 *
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 *****************************************************************************/
63 #include <linux/pci.h>
64 #include <linux/pci-aspm.h>
65 #include <linux/interrupt.h>
66 #include <linux/debugfs.h>
67 #include <linux/sched.h>
68 #include <linux/bitops.h>
69 #include <linux/gfp.h>
70
71 #include "iwl-drv.h"
72 #include "iwl-trans.h"
73 #include "iwl-csr.h"
74 #include "iwl-prph.h"
75 #include "iwl-agn-hw.h"
76 #include "internal.h"
77
78 static void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans,
79 u32 reg, u32 mask, u32 value)
80 {
81 u32 v;
82
83 #ifdef CONFIG_IWLWIFI_DEBUG
84 WARN_ON_ONCE(value & ~mask);
85 #endif
86
87 v = iwl_read32(trans, reg);
88 v &= ~mask;
89 v |= value;
90 iwl_write32(trans, reg, v);
91 }
92
93 static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans,
94 u32 reg, u32 mask)
95 {
96 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0);
97 }
98
99 static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans,
100 u32 reg, u32 mask)
101 {
102 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask);
103 }
104
105 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
106 {
107 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
108 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
109 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
110 ~APMG_PS_CTRL_MSK_PWR_SRC);
111 else
112 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
113 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
114 ~APMG_PS_CTRL_MSK_PWR_SRC);
115 }
116
117 /* PCI registers */
118 #define PCI_CFG_RETRY_TIMEOUT 0x041
119
120 static void iwl_pcie_apm_config(struct iwl_trans *trans)
121 {
122 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
123 u16 lctl;
124
125 /*
126 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
127 * Check if BIOS (or OS) enabled L1-ASPM on this device.
128 * If so (likely), disable L0S, so device moves directly L0->L1;
129 * costs negligible amount of power savings.
130 * If not (unlikely), enable L0S, so there is at least some
131 * power savings, even without L1.
132 */
133 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
134 if (lctl & PCI_EXP_LNKCTL_ASPM_L1) {
135 /* L1-ASPM enabled; disable(!) L0S */
136 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
137 dev_info(trans->dev, "L1 Enabled; Disabling L0S\n");
138 } else {
139 /* L1-ASPM disabled; enable(!) L0S */
140 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
141 dev_info(trans->dev, "L1 Disabled; Enabling L0S\n");
142 }
143 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
144 }
145
146 /*
147 * Start up NIC's basic functionality after it has been reset
148 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
149 * NOTE: This does not load uCode nor start the embedded processor
150 */
151 static int iwl_pcie_apm_init(struct iwl_trans *trans)
152 {
153 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
154 int ret = 0;
155 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
156
157 /*
158 * Use "set_bit" below rather than "write", to preserve any hardware
159 * bits already set by default after reset.
160 */
161
162 /* Disable L0S exit timer (platform NMI Work/Around) */
163 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
164 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
165
166 /*
167 * Disable L0s without affecting L1;
168 * don't wait for ICH L0s (ICH bug W/A)
169 */
170 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
171 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
172
173 /* Set FH wait threshold to maximum (HW error during stress W/A) */
174 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
175
176 /*
177 * Enable HAP INTA (interrupt from management bus) to
178 * wake device's PCI Express link L1a -> L0s
179 */
180 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
181 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
182
183 iwl_pcie_apm_config(trans);
184
185 /* Configure analog phase-lock-loop before activating to D0A */
186 if (trans->cfg->base_params->pll_cfg_val)
187 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
188 trans->cfg->base_params->pll_cfg_val);
189
190 /*
191 * Set "initialization complete" bit to move adapter from
192 * D0U* --> D0A* (powered-up active) state.
193 */
194 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
195
196 /*
197 * Wait for clock stabilization; once stabilized, access to
198 * device-internal resources is supported, e.g. iwl_write_prph()
199 * and accesses to uCode SRAM.
200 */
201 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
202 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
203 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
204 if (ret < 0) {
205 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
206 goto out;
207 }
208
209 /*
210 * Enable DMA clock and wait for it to stabilize.
211 *
212 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
213 * do not disable clocks. This preserves any hardware bits already
214 * set by default in "CLK_CTRL_REG" after reset.
215 */
216 iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
217 udelay(20);
218
219 /* Disable L1-Active */
220 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
221 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
222
223 set_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
224
225 out:
226 return ret;
227 }
228
229 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
230 {
231 int ret = 0;
232
233 /* stop device's busmaster DMA activity */
234 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
235
236 ret = iwl_poll_bit(trans, CSR_RESET,
237 CSR_RESET_REG_FLAG_MASTER_DISABLED,
238 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
239 if (ret)
240 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
241
242 IWL_DEBUG_INFO(trans, "stop master\n");
243
244 return ret;
245 }
246
247 static void iwl_pcie_apm_stop(struct iwl_trans *trans)
248 {
249 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
250 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
251
252 clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
253
254 /* Stop device's DMA activity */
255 iwl_pcie_apm_stop_master(trans);
256
257 /* Reset the entire device */
258 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
259
260 udelay(10);
261
262 /*
263 * Clear "initialization complete" bit to move adapter from
264 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
265 */
266 iwl_clear_bit(trans, CSR_GP_CNTRL,
267 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
268 }
269
270 static int iwl_pcie_nic_init(struct iwl_trans *trans)
271 {
272 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
273 unsigned long flags;
274
275 /* nic_init */
276 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
277 iwl_pcie_apm_init(trans);
278
279 /* Set interrupt coalescing calibration timer to default (512 usecs) */
280 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
281
282 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
283
284 iwl_pcie_set_pwr(trans, false);
285
286 iwl_op_mode_nic_config(trans->op_mode);
287
288 /* Allocate the RX queue, or reset if it is already allocated */
289 iwl_pcie_rx_init(trans);
290
291 /* Allocate or reset and init all Tx and Command queues */
292 if (iwl_pcie_tx_init(trans))
293 return -ENOMEM;
294
295 if (trans->cfg->base_params->shadow_reg_enable) {
296 /* enable shadow regs in HW */
297 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
298 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
299 }
300
301 return 0;
302 }
303
304 #define HW_READY_TIMEOUT (50)
305
306 /* Note: returns poll_bit return value, which is >= 0 if success */
307 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
308 {
309 int ret;
310
311 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
312 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
313
314 /* See if we got it */
315 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
316 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
317 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
318 HW_READY_TIMEOUT);
319
320 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
321 return ret;
322 }
323
324 /* Note: returns standard 0/-ERROR code */
325 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
326 {
327 int ret;
328 int t = 0;
329
330 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
331
332 ret = iwl_pcie_set_hw_ready(trans);
333 /* If the card is ready, exit 0 */
334 if (ret >= 0)
335 return 0;
336
337 /* If HW is not ready, prepare the conditions to check again */
338 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
339 CSR_HW_IF_CONFIG_REG_PREPARE);
340
341 do {
342 ret = iwl_pcie_set_hw_ready(trans);
343 if (ret >= 0)
344 return 0;
345
346 usleep_range(200, 1000);
347 t += 200;
348 } while (t < 150000);
349
350 return ret;
351 }
352
353 /*
354 * ucode
355 */
356 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
357 dma_addr_t phy_addr, u32 byte_cnt)
358 {
359 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
360 int ret;
361
362 trans_pcie->ucode_write_complete = false;
363
364 iwl_write_direct32(trans,
365 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
366 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
367
368 iwl_write_direct32(trans,
369 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
370 dst_addr);
371
372 iwl_write_direct32(trans,
373 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
374 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
375
376 iwl_write_direct32(trans,
377 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
378 (iwl_get_dma_hi_addr(phy_addr)
379 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
380
381 iwl_write_direct32(trans,
382 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
383 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
384 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
385 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
386
387 iwl_write_direct32(trans,
388 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
389 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
390 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
391 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
392
393 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
394 trans_pcie->ucode_write_complete, 5 * HZ);
395 if (!ret) {
396 IWL_ERR(trans, "Failed to load firmware chunk!\n");
397 return -ETIMEDOUT;
398 }
399
400 return 0;
401 }
402
403 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
404 const struct fw_desc *section)
405 {
406 u8 *v_addr;
407 dma_addr_t p_addr;
408 u32 offset, chunk_sz = section->len;
409 int ret = 0;
410
411 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
412 section_num);
413
414 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
415 GFP_KERNEL | __GFP_NOWARN);
416 if (!v_addr) {
417 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
418 chunk_sz = PAGE_SIZE;
419 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
420 &p_addr, GFP_KERNEL);
421 if (!v_addr)
422 return -ENOMEM;
423 }
424
425 for (offset = 0; offset < section->len; offset += chunk_sz) {
426 u32 copy_size;
427
428 copy_size = min_t(u32, chunk_sz, section->len - offset);
429
430 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
431 ret = iwl_pcie_load_firmware_chunk(trans,
432 section->offset + offset,
433 p_addr, copy_size);
434 if (ret) {
435 IWL_ERR(trans,
436 "Could not load the [%d] uCode section\n",
437 section_num);
438 break;
439 }
440 }
441
442 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
443 return ret;
444 }
445
446 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
447 const struct fw_img *image)
448 {
449 int i, ret = 0;
450
451 for (i = 0; i < IWL_UCODE_SECTION_MAX; i++) {
452 if (!image->sec[i].data)
453 break;
454
455 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
456 if (ret)
457 return ret;
458 }
459
460 /* Remove all resets to allow NIC to operate */
461 iwl_write32(trans, CSR_RESET, 0);
462
463 return 0;
464 }
465
466 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
467 const struct fw_img *fw, bool run_in_rfkill)
468 {
469 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
470 int ret;
471 bool hw_rfkill;
472
473 /* This may fail if AMT took ownership of the device */
474 if (iwl_pcie_prepare_card_hw(trans)) {
475 IWL_WARN(trans, "Exit HW not ready\n");
476 return -EIO;
477 }
478
479 clear_bit(STATUS_FW_ERROR, &trans_pcie->status);
480
481 iwl_enable_rfkill_int(trans);
482
483 /* If platform's RF_KILL switch is NOT set to KILL */
484 hw_rfkill = iwl_is_rfkill_set(trans);
485 if (hw_rfkill)
486 set_bit(STATUS_RFKILL, &trans_pcie->status);
487 else
488 clear_bit(STATUS_RFKILL, &trans_pcie->status);
489 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
490 if (hw_rfkill && !run_in_rfkill)
491 return -ERFKILL;
492
493 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
494
495 ret = iwl_pcie_nic_init(trans);
496 if (ret) {
497 IWL_ERR(trans, "Unable to init nic\n");
498 return ret;
499 }
500
501 /* make sure rfkill handshake bits are cleared */
502 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
503 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
504 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
505
506 /* clear (again), then enable host interrupts */
507 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
508 iwl_enable_interrupts(trans);
509
510 /* really make sure rfkill handshake bits are cleared */
511 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
512 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
513
514 /* Load the given image to the HW */
515 return iwl_pcie_load_given_ucode(trans, fw);
516 }
517
518 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
519 {
520 iwl_pcie_reset_ict(trans);
521 iwl_pcie_tx_start(trans, scd_addr);
522 }
523
524 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
525 {
526 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
527 unsigned long flags;
528
529 /* tell the device to stop sending interrupts */
530 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
531 iwl_disable_interrupts(trans);
532 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
533
534 /* device going down, Stop using ICT table */
535 iwl_pcie_disable_ict(trans);
536
537 /*
538 * If a HW restart happens during firmware loading,
539 * then the firmware loading might call this function
540 * and later it might be called again due to the
541 * restart. So don't process again if the device is
542 * already dead.
543 */
544 if (test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status)) {
545 iwl_pcie_tx_stop(trans);
546 iwl_pcie_rx_stop(trans);
547
548 /* Power-down device's busmaster DMA clocks */
549 iwl_write_prph(trans, APMG_CLK_DIS_REG,
550 APMG_CLK_VAL_DMA_CLK_RQT);
551 udelay(5);
552 }
553
554 /* Make sure (redundant) we've released our request to stay awake */
555 iwl_clear_bit(trans, CSR_GP_CNTRL,
556 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
557
558 /* Stop the device, and put it in low power state */
559 iwl_pcie_apm_stop(trans);
560
561 /* Upon stop, the APM issues an interrupt if HW RF kill is set.
562 * Clean again the interrupt here
563 */
564 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
565 iwl_disable_interrupts(trans);
566 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
567
568 iwl_enable_rfkill_int(trans);
569
570 /* stop and reset the on-board processor */
571 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
572
573 /* clear all status bits */
574 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
575 clear_bit(STATUS_INT_ENABLED, &trans_pcie->status);
576 clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
577 clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
578 clear_bit(STATUS_RFKILL, &trans_pcie->status);
579 }
580
581 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
582 {
583 iwl_disable_interrupts(trans);
584
585 /*
586 * in testing mode, the host stays awake and the
587 * hardware won't be reset (not even partially)
588 */
589 if (test)
590 return;
591
592 iwl_pcie_disable_ict(trans);
593
594 iwl_clear_bit(trans, CSR_GP_CNTRL,
595 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
596 iwl_clear_bit(trans, CSR_GP_CNTRL,
597 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
598
599 /*
600 * reset TX queues -- some of their registers reset during S3
601 * so if we don't reset everything here the D3 image would try
602 * to execute some invalid memory upon resume
603 */
604 iwl_trans_pcie_tx_reset(trans);
605
606 iwl_pcie_set_pwr(trans, true);
607 }
608
609 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
610 enum iwl_d3_status *status,
611 bool test)
612 {
613 u32 val;
614 int ret;
615
616 if (test) {
617 iwl_enable_interrupts(trans);
618 *status = IWL_D3_STATUS_ALIVE;
619 return 0;
620 }
621
622 iwl_pcie_set_pwr(trans, false);
623
624 val = iwl_read32(trans, CSR_RESET);
625 if (val & CSR_RESET_REG_FLAG_NEVO_RESET) {
626 *status = IWL_D3_STATUS_RESET;
627 return 0;
628 }
629
630 /*
631 * Also enables interrupts - none will happen as the device doesn't
632 * know we're waking it up, only when the opmode actually tells it
633 * after this call.
634 */
635 iwl_pcie_reset_ict(trans);
636
637 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
638 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
639
640 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
641 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
642 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
643 25000);
644 if (ret) {
645 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
646 return ret;
647 }
648
649 iwl_trans_pcie_tx_reset(trans);
650
651 ret = iwl_pcie_rx_init(trans);
652 if (ret) {
653 IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
654 return ret;
655 }
656
657 *status = IWL_D3_STATUS_ALIVE;
658 return 0;
659 }
660
661 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
662 {
663 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
664 bool hw_rfkill;
665 int err;
666
667 err = iwl_pcie_prepare_card_hw(trans);
668 if (err) {
669 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
670 return err;
671 }
672
673 iwl_pcie_apm_init(trans);
674
675 /* From now on, the op_mode will be kept updated about RF kill state */
676 iwl_enable_rfkill_int(trans);
677
678 hw_rfkill = iwl_is_rfkill_set(trans);
679 if (hw_rfkill)
680 set_bit(STATUS_RFKILL, &trans_pcie->status);
681 else
682 clear_bit(STATUS_RFKILL, &trans_pcie->status);
683 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
684
685 return 0;
686 }
687
688 static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans,
689 bool op_mode_leaving)
690 {
691 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
692 bool hw_rfkill;
693 unsigned long flags;
694
695 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
696 iwl_disable_interrupts(trans);
697 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
698
699 iwl_pcie_apm_stop(trans);
700
701 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
702 iwl_disable_interrupts(trans);
703 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
704
705 iwl_pcie_disable_ict(trans);
706
707 if (!op_mode_leaving) {
708 /*
709 * Even if we stop the HW, we still want the RF kill
710 * interrupt
711 */
712 iwl_enable_rfkill_int(trans);
713
714 /*
715 * Check again since the RF kill state may have changed while
716 * all the interrupts were disabled, in this case we couldn't
717 * receive the RF kill interrupt and update the state in the
718 * op_mode.
719 */
720 hw_rfkill = iwl_is_rfkill_set(trans);
721 if (hw_rfkill)
722 set_bit(STATUS_RFKILL, &trans_pcie->status);
723 else
724 clear_bit(STATUS_RFKILL, &trans_pcie->status);
725 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
726 }
727 }
728
729 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
730 {
731 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
732 }
733
734 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
735 {
736 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
737 }
738
739 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
740 {
741 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
742 }
743
744 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
745 {
746 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
747 ((reg & 0x000FFFFF) | (3 << 24)));
748 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
749 }
750
751 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
752 u32 val)
753 {
754 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
755 ((addr & 0x000FFFFF) | (3 << 24)));
756 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
757 }
758
759 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
760 const struct iwl_trans_config *trans_cfg)
761 {
762 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
763
764 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
765 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
766 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
767 trans_pcie->n_no_reclaim_cmds = 0;
768 else
769 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
770 if (trans_pcie->n_no_reclaim_cmds)
771 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
772 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
773
774 trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
775 if (trans_pcie->rx_buf_size_8k)
776 trans_pcie->rx_page_order = get_order(8 * 1024);
777 else
778 trans_pcie->rx_page_order = get_order(4 * 1024);
779
780 trans_pcie->wd_timeout =
781 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
782
783 trans_pcie->command_names = trans_cfg->command_names;
784 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
785 }
786
787 void iwl_trans_pcie_free(struct iwl_trans *trans)
788 {
789 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
790
791 synchronize_irq(trans_pcie->pci_dev->irq);
792
793 iwl_pcie_tx_free(trans);
794 iwl_pcie_rx_free(trans);
795
796 free_irq(trans_pcie->pci_dev->irq, trans);
797 iwl_pcie_free_ict(trans);
798
799 pci_disable_msi(trans_pcie->pci_dev);
800 iounmap(trans_pcie->hw_base);
801 pci_release_regions(trans_pcie->pci_dev);
802 pci_disable_device(trans_pcie->pci_dev);
803 kmem_cache_destroy(trans->dev_cmd_pool);
804
805 kfree(trans);
806 }
807
808 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
809 {
810 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
811
812 if (state)
813 set_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
814 else
815 clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
816 }
817
818 #ifdef CONFIG_PM_SLEEP
819 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
820 {
821 return 0;
822 }
823
824 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
825 {
826 bool hw_rfkill;
827
828 iwl_enable_rfkill_int(trans);
829
830 hw_rfkill = iwl_is_rfkill_set(trans);
831 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
832
833 return 0;
834 }
835 #endif /* CONFIG_PM_SLEEP */
836
837 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
838 unsigned long *flags)
839 {
840 int ret;
841 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
842
843 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
844
845 /* this bit wakes up the NIC */
846 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
847 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
848
849 /*
850 * These bits say the device is running, and should keep running for
851 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
852 * but they do not indicate that embedded SRAM is restored yet;
853 * 3945 and 4965 have volatile SRAM, and must save/restore contents
854 * to/from host DRAM when sleeping/waking for power-saving.
855 * Each direction takes approximately 1/4 millisecond; with this
856 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
857 * series of register accesses are expected (e.g. reading Event Log),
858 * to keep device from sleeping.
859 *
860 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
861 * SRAM is okay/restored. We don't check that here because this call
862 * is just for hardware register access; but GP1 MAC_SLEEP check is a
863 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
864 *
865 * 5000 series and later (including 1000 series) have non-volatile SRAM,
866 * and do not save/restore SRAM when power cycling.
867 */
868 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
869 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
870 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
871 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
872 if (unlikely(ret < 0)) {
873 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
874 if (!silent) {
875 u32 val = iwl_read32(trans, CSR_GP_CNTRL);
876 WARN_ONCE(1,
877 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
878 val);
879 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
880 return false;
881 }
882 }
883
884 /*
885 * Fool sparse by faking we release the lock - sparse will
886 * track nic_access anyway.
887 */
888 __release(&trans_pcie->reg_lock);
889 return true;
890 }
891
892 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
893 unsigned long *flags)
894 {
895 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
896
897 lockdep_assert_held(&trans_pcie->reg_lock);
898
899 /*
900 * Fool sparse by faking we acquiring the lock - sparse will
901 * track nic_access anyway.
902 */
903 __acquire(&trans_pcie->reg_lock);
904
905 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
906 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
907 /*
908 * Above we read the CSR_GP_CNTRL register, which will flush
909 * any previous writes, but we need the write that clears the
910 * MAC_ACCESS_REQ bit to be performed before any other writes
911 * scheduled on different CPUs (after we drop reg_lock).
912 */
913 mmiowb();
914 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
915 }
916
917 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
918 void *buf, int dwords)
919 {
920 unsigned long flags;
921 int offs, ret = 0;
922 u32 *vals = buf;
923
924 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
925 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
926 for (offs = 0; offs < dwords; offs++)
927 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
928 iwl_trans_release_nic_access(trans, &flags);
929 } else {
930 ret = -EBUSY;
931 }
932 return ret;
933 }
934
935 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
936 const void *buf, int dwords)
937 {
938 unsigned long flags;
939 int offs, ret = 0;
940 const u32 *vals = buf;
941
942 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
943 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
944 for (offs = 0; offs < dwords; offs++)
945 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
946 vals ? vals[offs] : 0);
947 iwl_trans_release_nic_access(trans, &flags);
948 } else {
949 ret = -EBUSY;
950 }
951 return ret;
952 }
953
954 #define IWL_FLUSH_WAIT_MS 2000
955
956 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans)
957 {
958 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
959 struct iwl_txq *txq;
960 struct iwl_queue *q;
961 int cnt;
962 unsigned long now = jiffies;
963 u32 scd_sram_addr;
964 u8 buf[16];
965 int ret = 0;
966
967 /* waiting for all the tx frames complete might take a while */
968 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
969 if (cnt == trans_pcie->cmd_queue)
970 continue;
971 txq = &trans_pcie->txq[cnt];
972 q = &txq->q;
973 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
974 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
975 msleep(1);
976
977 if (q->read_ptr != q->write_ptr) {
978 IWL_ERR(trans,
979 "fail to flush all tx fifo queues Q %d\n", cnt);
980 ret = -ETIMEDOUT;
981 break;
982 }
983 }
984
985 if (!ret)
986 return 0;
987
988 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
989 txq->q.read_ptr, txq->q.write_ptr);
990
991 scd_sram_addr = trans_pcie->scd_base_addr +
992 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
993 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
994
995 iwl_print_hex_error(trans, buf, sizeof(buf));
996
997 for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
998 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
999 iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1000
1001 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1002 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1003 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1004 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1005 u32 tbl_dw =
1006 iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1007 SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1008
1009 if (cnt & 0x1)
1010 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1011 else
1012 tbl_dw = tbl_dw & 0x0000FFFF;
1013
1014 IWL_ERR(trans,
1015 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1016 cnt, active ? "" : "in", fifo, tbl_dw,
1017 iwl_read_prph(trans,
1018 SCD_QUEUE_RDPTR(cnt)) & (txq->q.n_bd - 1),
1019 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1020 }
1021
1022 return ret;
1023 }
1024
1025 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1026 u32 mask, u32 value)
1027 {
1028 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1029 unsigned long flags;
1030
1031 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1032 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
1033 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1034 }
1035
1036 static const char *get_fh_string(int cmd)
1037 {
1038 #define IWL_CMD(x) case x: return #x
1039 switch (cmd) {
1040 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1041 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1042 IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1043 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1044 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1045 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1046 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1047 IWL_CMD(FH_TSSR_TX_STATUS_REG);
1048 IWL_CMD(FH_TSSR_TX_ERROR_REG);
1049 default:
1050 return "UNKNOWN";
1051 }
1052 #undef IWL_CMD
1053 }
1054
1055 int iwl_pcie_dump_fh(struct iwl_trans *trans, char **buf)
1056 {
1057 int i;
1058 static const u32 fh_tbl[] = {
1059 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1060 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1061 FH_RSCSR_CHNL0_WPTR,
1062 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1063 FH_MEM_RSSR_SHARED_CTRL_REG,
1064 FH_MEM_RSSR_RX_STATUS_REG,
1065 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1066 FH_TSSR_TX_STATUS_REG,
1067 FH_TSSR_TX_ERROR_REG
1068 };
1069
1070 #ifdef CONFIG_IWLWIFI_DEBUGFS
1071 if (buf) {
1072 int pos = 0;
1073 size_t bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1074
1075 *buf = kmalloc(bufsz, GFP_KERNEL);
1076 if (!*buf)
1077 return -ENOMEM;
1078
1079 pos += scnprintf(*buf + pos, bufsz - pos,
1080 "FH register values:\n");
1081
1082 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++)
1083 pos += scnprintf(*buf + pos, bufsz - pos,
1084 " %34s: 0X%08x\n",
1085 get_fh_string(fh_tbl[i]),
1086 iwl_read_direct32(trans, fh_tbl[i]));
1087
1088 return pos;
1089 }
1090 #endif
1091
1092 IWL_ERR(trans, "FH register values:\n");
1093 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++)
1094 IWL_ERR(trans, " %34s: 0X%08x\n",
1095 get_fh_string(fh_tbl[i]),
1096 iwl_read_direct32(trans, fh_tbl[i]));
1097
1098 return 0;
1099 }
1100
1101 static const char *get_csr_string(int cmd)
1102 {
1103 #define IWL_CMD(x) case x: return #x
1104 switch (cmd) {
1105 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1106 IWL_CMD(CSR_INT_COALESCING);
1107 IWL_CMD(CSR_INT);
1108 IWL_CMD(CSR_INT_MASK);
1109 IWL_CMD(CSR_FH_INT_STATUS);
1110 IWL_CMD(CSR_GPIO_IN);
1111 IWL_CMD(CSR_RESET);
1112 IWL_CMD(CSR_GP_CNTRL);
1113 IWL_CMD(CSR_HW_REV);
1114 IWL_CMD(CSR_EEPROM_REG);
1115 IWL_CMD(CSR_EEPROM_GP);
1116 IWL_CMD(CSR_OTP_GP_REG);
1117 IWL_CMD(CSR_GIO_REG);
1118 IWL_CMD(CSR_GP_UCODE_REG);
1119 IWL_CMD(CSR_GP_DRIVER_REG);
1120 IWL_CMD(CSR_UCODE_DRV_GP1);
1121 IWL_CMD(CSR_UCODE_DRV_GP2);
1122 IWL_CMD(CSR_LED_REG);
1123 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1124 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1125 IWL_CMD(CSR_ANA_PLL_CFG);
1126 IWL_CMD(CSR_HW_REV_WA_REG);
1127 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1128 default:
1129 return "UNKNOWN";
1130 }
1131 #undef IWL_CMD
1132 }
1133
1134 void iwl_pcie_dump_csr(struct iwl_trans *trans)
1135 {
1136 int i;
1137 static const u32 csr_tbl[] = {
1138 CSR_HW_IF_CONFIG_REG,
1139 CSR_INT_COALESCING,
1140 CSR_INT,
1141 CSR_INT_MASK,
1142 CSR_FH_INT_STATUS,
1143 CSR_GPIO_IN,
1144 CSR_RESET,
1145 CSR_GP_CNTRL,
1146 CSR_HW_REV,
1147 CSR_EEPROM_REG,
1148 CSR_EEPROM_GP,
1149 CSR_OTP_GP_REG,
1150 CSR_GIO_REG,
1151 CSR_GP_UCODE_REG,
1152 CSR_GP_DRIVER_REG,
1153 CSR_UCODE_DRV_GP1,
1154 CSR_UCODE_DRV_GP2,
1155 CSR_LED_REG,
1156 CSR_DRAM_INT_TBL_REG,
1157 CSR_GIO_CHICKEN_BITS,
1158 CSR_ANA_PLL_CFG,
1159 CSR_HW_REV_WA_REG,
1160 CSR_DBG_HPET_MEM_REG
1161 };
1162 IWL_ERR(trans, "CSR values:\n");
1163 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1164 "CSR_INT_PERIODIC_REG)\n");
1165 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1166 IWL_ERR(trans, " %25s: 0X%08x\n",
1167 get_csr_string(csr_tbl[i]),
1168 iwl_read32(trans, csr_tbl[i]));
1169 }
1170 }
1171
1172 #ifdef CONFIG_IWLWIFI_DEBUGFS
1173 /* create and remove of files */
1174 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1175 if (!debugfs_create_file(#name, mode, parent, trans, \
1176 &iwl_dbgfs_##name##_ops)) \
1177 goto err; \
1178 } while (0)
1179
1180 /* file operation */
1181 #define DEBUGFS_READ_FUNC(name) \
1182 static ssize_t iwl_dbgfs_##name##_read(struct file *file, \
1183 char __user *user_buf, \
1184 size_t count, loff_t *ppos);
1185
1186 #define DEBUGFS_WRITE_FUNC(name) \
1187 static ssize_t iwl_dbgfs_##name##_write(struct file *file, \
1188 const char __user *user_buf, \
1189 size_t count, loff_t *ppos);
1190
1191 #define DEBUGFS_READ_FILE_OPS(name) \
1192 DEBUGFS_READ_FUNC(name); \
1193 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1194 .read = iwl_dbgfs_##name##_read, \
1195 .open = simple_open, \
1196 .llseek = generic_file_llseek, \
1197 };
1198
1199 #define DEBUGFS_WRITE_FILE_OPS(name) \
1200 DEBUGFS_WRITE_FUNC(name); \
1201 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1202 .write = iwl_dbgfs_##name##_write, \
1203 .open = simple_open, \
1204 .llseek = generic_file_llseek, \
1205 };
1206
1207 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1208 DEBUGFS_READ_FUNC(name); \
1209 DEBUGFS_WRITE_FUNC(name); \
1210 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1211 .write = iwl_dbgfs_##name##_write, \
1212 .read = iwl_dbgfs_##name##_read, \
1213 .open = simple_open, \
1214 .llseek = generic_file_llseek, \
1215 };
1216
1217 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1218 char __user *user_buf,
1219 size_t count, loff_t *ppos)
1220 {
1221 struct iwl_trans *trans = file->private_data;
1222 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1223 struct iwl_txq *txq;
1224 struct iwl_queue *q;
1225 char *buf;
1226 int pos = 0;
1227 int cnt;
1228 int ret;
1229 size_t bufsz;
1230
1231 bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
1232
1233 if (!trans_pcie->txq)
1234 return -EAGAIN;
1235
1236 buf = kzalloc(bufsz, GFP_KERNEL);
1237 if (!buf)
1238 return -ENOMEM;
1239
1240 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1241 txq = &trans_pcie->txq[cnt];
1242 q = &txq->q;
1243 pos += scnprintf(buf + pos, bufsz - pos,
1244 "hwq %.2d: read=%u write=%u use=%d stop=%d\n",
1245 cnt, q->read_ptr, q->write_ptr,
1246 !!test_bit(cnt, trans_pcie->queue_used),
1247 !!test_bit(cnt, trans_pcie->queue_stopped));
1248 }
1249 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1250 kfree(buf);
1251 return ret;
1252 }
1253
1254 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1255 char __user *user_buf,
1256 size_t count, loff_t *ppos)
1257 {
1258 struct iwl_trans *trans = file->private_data;
1259 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1260 struct iwl_rxq *rxq = &trans_pcie->rxq;
1261 char buf[256];
1262 int pos = 0;
1263 const size_t bufsz = sizeof(buf);
1264
1265 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1266 rxq->read);
1267 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1268 rxq->write);
1269 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1270 rxq->free_count);
1271 if (rxq->rb_stts) {
1272 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1273 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1274 } else {
1275 pos += scnprintf(buf + pos, bufsz - pos,
1276 "closed_rb_num: Not Allocated\n");
1277 }
1278 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1279 }
1280
1281 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1282 char __user *user_buf,
1283 size_t count, loff_t *ppos)
1284 {
1285 struct iwl_trans *trans = file->private_data;
1286 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1287 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1288
1289 int pos = 0;
1290 char *buf;
1291 int bufsz = 24 * 64; /* 24 items * 64 char per item */
1292 ssize_t ret;
1293
1294 buf = kzalloc(bufsz, GFP_KERNEL);
1295 if (!buf)
1296 return -ENOMEM;
1297
1298 pos += scnprintf(buf + pos, bufsz - pos,
1299 "Interrupt Statistics Report:\n");
1300
1301 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1302 isr_stats->hw);
1303 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1304 isr_stats->sw);
1305 if (isr_stats->sw || isr_stats->hw) {
1306 pos += scnprintf(buf + pos, bufsz - pos,
1307 "\tLast Restarting Code: 0x%X\n",
1308 isr_stats->err_code);
1309 }
1310 #ifdef CONFIG_IWLWIFI_DEBUG
1311 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1312 isr_stats->sch);
1313 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1314 isr_stats->alive);
1315 #endif
1316 pos += scnprintf(buf + pos, bufsz - pos,
1317 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1318
1319 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1320 isr_stats->ctkill);
1321
1322 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1323 isr_stats->wakeup);
1324
1325 pos += scnprintf(buf + pos, bufsz - pos,
1326 "Rx command responses:\t\t %u\n", isr_stats->rx);
1327
1328 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1329 isr_stats->tx);
1330
1331 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1332 isr_stats->unhandled);
1333
1334 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1335 kfree(buf);
1336 return ret;
1337 }
1338
1339 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1340 const char __user *user_buf,
1341 size_t count, loff_t *ppos)
1342 {
1343 struct iwl_trans *trans = file->private_data;
1344 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1345 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1346
1347 char buf[8];
1348 int buf_size;
1349 u32 reset_flag;
1350
1351 memset(buf, 0, sizeof(buf));
1352 buf_size = min(count, sizeof(buf) - 1);
1353 if (copy_from_user(buf, user_buf, buf_size))
1354 return -EFAULT;
1355 if (sscanf(buf, "%x", &reset_flag) != 1)
1356 return -EFAULT;
1357 if (reset_flag == 0)
1358 memset(isr_stats, 0, sizeof(*isr_stats));
1359
1360 return count;
1361 }
1362
1363 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1364 const char __user *user_buf,
1365 size_t count, loff_t *ppos)
1366 {
1367 struct iwl_trans *trans = file->private_data;
1368 char buf[8];
1369 int buf_size;
1370 int csr;
1371
1372 memset(buf, 0, sizeof(buf));
1373 buf_size = min(count, sizeof(buf) - 1);
1374 if (copy_from_user(buf, user_buf, buf_size))
1375 return -EFAULT;
1376 if (sscanf(buf, "%d", &csr) != 1)
1377 return -EFAULT;
1378
1379 iwl_pcie_dump_csr(trans);
1380
1381 return count;
1382 }
1383
1384 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1385 char __user *user_buf,
1386 size_t count, loff_t *ppos)
1387 {
1388 struct iwl_trans *trans = file->private_data;
1389 char *buf = NULL;
1390 int pos = 0;
1391 ssize_t ret = -EFAULT;
1392
1393 ret = pos = iwl_pcie_dump_fh(trans, &buf);
1394 if (buf) {
1395 ret = simple_read_from_buffer(user_buf,
1396 count, ppos, buf, pos);
1397 kfree(buf);
1398 }
1399
1400 return ret;
1401 }
1402
1403 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1404 DEBUGFS_READ_FILE_OPS(fh_reg);
1405 DEBUGFS_READ_FILE_OPS(rx_queue);
1406 DEBUGFS_READ_FILE_OPS(tx_queue);
1407 DEBUGFS_WRITE_FILE_OPS(csr);
1408
1409 /*
1410 * Create the debugfs files and directories
1411 *
1412 */
1413 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1414 struct dentry *dir)
1415 {
1416 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1417 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1418 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1419 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1420 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1421 return 0;
1422
1423 err:
1424 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
1425 return -ENOMEM;
1426 }
1427 #else
1428 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1429 struct dentry *dir)
1430 {
1431 return 0;
1432 }
1433 #endif /*CONFIG_IWLWIFI_DEBUGFS */
1434
1435 static const struct iwl_trans_ops trans_ops_pcie = {
1436 .start_hw = iwl_trans_pcie_start_hw,
1437 .stop_hw = iwl_trans_pcie_stop_hw,
1438 .fw_alive = iwl_trans_pcie_fw_alive,
1439 .start_fw = iwl_trans_pcie_start_fw,
1440 .stop_device = iwl_trans_pcie_stop_device,
1441
1442 .d3_suspend = iwl_trans_pcie_d3_suspend,
1443 .d3_resume = iwl_trans_pcie_d3_resume,
1444
1445 .send_cmd = iwl_trans_pcie_send_hcmd,
1446
1447 .tx = iwl_trans_pcie_tx,
1448 .reclaim = iwl_trans_pcie_reclaim,
1449
1450 .txq_disable = iwl_trans_pcie_txq_disable,
1451 .txq_enable = iwl_trans_pcie_txq_enable,
1452
1453 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
1454
1455 .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
1456
1457 #ifdef CONFIG_PM_SLEEP
1458 .suspend = iwl_trans_pcie_suspend,
1459 .resume = iwl_trans_pcie_resume,
1460 #endif
1461 .write8 = iwl_trans_pcie_write8,
1462 .write32 = iwl_trans_pcie_write32,
1463 .read32 = iwl_trans_pcie_read32,
1464 .read_prph = iwl_trans_pcie_read_prph,
1465 .write_prph = iwl_trans_pcie_write_prph,
1466 .read_mem = iwl_trans_pcie_read_mem,
1467 .write_mem = iwl_trans_pcie_write_mem,
1468 .configure = iwl_trans_pcie_configure,
1469 .set_pmi = iwl_trans_pcie_set_pmi,
1470 .grab_nic_access = iwl_trans_pcie_grab_nic_access,
1471 .release_nic_access = iwl_trans_pcie_release_nic_access,
1472 .set_bits_mask = iwl_trans_pcie_set_bits_mask,
1473 };
1474
1475 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
1476 const struct pci_device_id *ent,
1477 const struct iwl_cfg *cfg)
1478 {
1479 struct iwl_trans_pcie *trans_pcie;
1480 struct iwl_trans *trans;
1481 u16 pci_cmd;
1482 int err;
1483
1484 trans = kzalloc(sizeof(struct iwl_trans) +
1485 sizeof(struct iwl_trans_pcie), GFP_KERNEL);
1486
1487 if (!trans)
1488 return NULL;
1489
1490 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1491
1492 trans->ops = &trans_ops_pcie;
1493 trans->cfg = cfg;
1494 trans_lockdep_init(trans);
1495 trans_pcie->trans = trans;
1496 spin_lock_init(&trans_pcie->irq_lock);
1497 spin_lock_init(&trans_pcie->reg_lock);
1498 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
1499
1500 /* W/A - seems to solve weird behavior. We need to remove this if we
1501 * don't want to stay in L1 all the time. This wastes a lot of power */
1502 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
1503 PCIE_LINK_STATE_CLKPM);
1504
1505 if (pci_enable_device(pdev)) {
1506 err = -ENODEV;
1507 goto out_no_pci;
1508 }
1509
1510 pci_set_master(pdev);
1511
1512 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
1513 if (!err)
1514 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
1515 if (err) {
1516 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1517 if (!err)
1518 err = pci_set_consistent_dma_mask(pdev,
1519 DMA_BIT_MASK(32));
1520 /* both attempts failed: */
1521 if (err) {
1522 dev_err(&pdev->dev, "No suitable DMA available\n");
1523 goto out_pci_disable_device;
1524 }
1525 }
1526
1527 err = pci_request_regions(pdev, DRV_NAME);
1528 if (err) {
1529 dev_err(&pdev->dev, "pci_request_regions failed\n");
1530 goto out_pci_disable_device;
1531 }
1532
1533 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
1534 if (!trans_pcie->hw_base) {
1535 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
1536 err = -ENODEV;
1537 goto out_pci_release_regions;
1538 }
1539
1540 /* We disable the RETRY_TIMEOUT register (0x41) to keep
1541 * PCI Tx retries from interfering with C3 CPU state */
1542 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
1543
1544 err = pci_enable_msi(pdev);
1545 if (err) {
1546 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
1547 /* enable rfkill interrupt: hw bug w/a */
1548 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1549 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1550 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1551 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1552 }
1553 }
1554
1555 trans->dev = &pdev->dev;
1556 trans_pcie->pci_dev = pdev;
1557 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
1558 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
1559 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
1560 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
1561
1562 /* Initialize the wait queue for commands */
1563 init_waitqueue_head(&trans_pcie->wait_command_queue);
1564
1565 snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
1566 "iwl_cmd_pool:%s", dev_name(trans->dev));
1567
1568 trans->dev_cmd_headroom = 0;
1569 trans->dev_cmd_pool =
1570 kmem_cache_create(trans->dev_cmd_pool_name,
1571 sizeof(struct iwl_device_cmd)
1572 + trans->dev_cmd_headroom,
1573 sizeof(void *),
1574 SLAB_HWCACHE_ALIGN,
1575 NULL);
1576
1577 if (!trans->dev_cmd_pool)
1578 goto out_pci_disable_msi;
1579
1580 trans_pcie->inta_mask = CSR_INI_SET_MASK;
1581
1582 if (iwl_pcie_alloc_ict(trans))
1583 goto out_free_cmd_pool;
1584
1585 if (request_threaded_irq(pdev->irq, iwl_pcie_isr_ict,
1586 iwl_pcie_irq_handler,
1587 IRQF_SHARED, DRV_NAME, trans)) {
1588 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
1589 goto out_free_ict;
1590 }
1591
1592 return trans;
1593
1594 out_free_ict:
1595 iwl_pcie_free_ict(trans);
1596 out_free_cmd_pool:
1597 kmem_cache_destroy(trans->dev_cmd_pool);
1598 out_pci_disable_msi:
1599 pci_disable_msi(pdev);
1600 out_pci_release_regions:
1601 pci_release_regions(pdev);
1602 out_pci_disable_device:
1603 pci_disable_device(pdev);
1604 out_no_pci:
1605 kfree(trans);
1606 return NULL;
1607 }
CRIS linux kernel tree