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Linux 3.11-rc3
[cris-mirror.git] / drivers / net / wireless / iwlwifi / pcie / tx.c
blobc47c92165aba91d2e97631f1953bd4e480cabad7
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2013 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29 #include <linux/etherdevice.h>
30 #include <linux/slab.h>
31 #include <linux/sched.h>
32
33 #include "iwl-debug.h"
34 #include "iwl-csr.h"
35 #include "iwl-prph.h"
36 #include "iwl-io.h"
37 #include "iwl-op-mode.h"
38 #include "internal.h"
39 /* FIXME: need to abstract out TX command (once we know what it looks like) */
40 #include "dvm/commands.h"
41
42 #define IWL_TX_CRC_SIZE 4
43 #define IWL_TX_DELIMITER_SIZE 4
44
45 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
46 * DMA services
47 *
48 * Theory of operation
49 *
50 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
51 * of buffer descriptors, each of which points to one or more data buffers for
52 * the device to read from or fill. Driver and device exchange status of each
53 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
54 * entries in each circular buffer, to protect against confusing empty and full
55 * queue states.
56 *
57 * The device reads or writes the data in the queues via the device's several
58 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
59 *
60 * For Tx queue, there are low mark and high mark limits. If, after queuing
61 * the packet for Tx, free space become < low mark, Tx queue stopped. When
62 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
63 * Tx queue resumed.
64 *
65 ***************************************************/
66 static int iwl_queue_space(const struct iwl_queue *q)
67 {
68 int s = q->read_ptr - q->write_ptr;
69
70 if (q->read_ptr > q->write_ptr)
71 s -= q->n_bd;
72
73 if (s <= 0)
74 s += q->n_window;
75 /* keep some reserve to not confuse empty and full situations */
76 s -= 2;
77 if (s < 0)
78 s = 0;
79 return s;
80 }
81
82 /*
83 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
84 */
85 static int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id)
86 {
87 q->n_bd = count;
88 q->n_window = slots_num;
89 q->id = id;
90
91 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
92 * and iwl_queue_dec_wrap are broken. */
93 if (WARN_ON(!is_power_of_2(count)))
94 return -EINVAL;
95
96 /* slots_num must be power-of-two size, otherwise
97 * get_cmd_index is broken. */
98 if (WARN_ON(!is_power_of_2(slots_num)))
99 return -EINVAL;
100
101 q->low_mark = q->n_window / 4;
102 if (q->low_mark < 4)
103 q->low_mark = 4;
104
105 q->high_mark = q->n_window / 8;
106 if (q->high_mark < 2)
107 q->high_mark = 2;
108
109 q->write_ptr = 0;
110 q->read_ptr = 0;
111
112 return 0;
113 }
114
115 static int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
116 struct iwl_dma_ptr *ptr, size_t size)
117 {
118 if (WARN_ON(ptr->addr))
119 return -EINVAL;
120
121 ptr->addr = dma_alloc_coherent(trans->dev, size,
122 &ptr->dma, GFP_KERNEL);
123 if (!ptr->addr)
124 return -ENOMEM;
125 ptr->size = size;
126 return 0;
127 }
128
129 static void iwl_pcie_free_dma_ptr(struct iwl_trans *trans,
130 struct iwl_dma_ptr *ptr)
131 {
132 if (unlikely(!ptr->addr))
133 return;
134
135 dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
136 memset(ptr, 0, sizeof(*ptr));
137 }
138
139 static void iwl_pcie_txq_stuck_timer(unsigned long data)
140 {
141 struct iwl_txq *txq = (void *)data;
142 struct iwl_queue *q = &txq->q;
143 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
144 struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
145 u32 scd_sram_addr = trans_pcie->scd_base_addr +
146 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
147 u8 buf[16];
148 int i;
149
150 spin_lock(&txq->lock);
151 /* check if triggered erroneously */
152 if (txq->q.read_ptr == txq->q.write_ptr) {
153 spin_unlock(&txq->lock);
154 return;
155 }
156 spin_unlock(&txq->lock);
157
158 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id,
159 jiffies_to_msecs(trans_pcie->wd_timeout));
160 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
161 txq->q.read_ptr, txq->q.write_ptr);
162
163 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
164
165 iwl_print_hex_error(trans, buf, sizeof(buf));
166
167 for (i = 0; i < FH_TCSR_CHNL_NUM; i++)
168 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", i,
169 iwl_read_direct32(trans, FH_TX_TRB_REG(i)));
170
171 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
172 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(i));
173 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
174 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
175 u32 tbl_dw =
176 iwl_trans_read_mem32(trans,
177 trans_pcie->scd_base_addr +
178 SCD_TRANS_TBL_OFFSET_QUEUE(i));
179
180 if (i & 0x1)
181 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
182 else
183 tbl_dw = tbl_dw & 0x0000FFFF;
184
185 IWL_ERR(trans,
186 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
187 i, active ? "" : "in", fifo, tbl_dw,
188 iwl_read_prph(trans,
189 SCD_QUEUE_RDPTR(i)) & (txq->q.n_bd - 1),
190 iwl_read_prph(trans, SCD_QUEUE_WRPTR(i)));
191 }
192
193 for (i = q->read_ptr; i != q->write_ptr;
194 i = iwl_queue_inc_wrap(i, q->n_bd))
195 IWL_ERR(trans, "scratch %d = 0x%08x\n", i,
196 le32_to_cpu(txq->scratchbufs[i].scratch));
197
198 iwl_op_mode_nic_error(trans->op_mode);
199 }
200
201 /*
202 * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
203 */
204 static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
205 struct iwl_txq *txq, u16 byte_cnt)
206 {
207 struct iwlagn_scd_bc_tbl *scd_bc_tbl;
208 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
209 int write_ptr = txq->q.write_ptr;
210 int txq_id = txq->q.id;
211 u8 sec_ctl = 0;
212 u8 sta_id = 0;
213 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
214 __le16 bc_ent;
215 struct iwl_tx_cmd *tx_cmd =
216 (void *) txq->entries[txq->q.write_ptr].cmd->payload;
217
218 scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
219
220 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
221
222 sta_id = tx_cmd->sta_id;
223 sec_ctl = tx_cmd->sec_ctl;
224
225 switch (sec_ctl & TX_CMD_SEC_MSK) {
226 case TX_CMD_SEC_CCM:
227 len += IEEE80211_CCMP_MIC_LEN;
228 break;
229 case TX_CMD_SEC_TKIP:
230 len += IEEE80211_TKIP_ICV_LEN;
231 break;
232 case TX_CMD_SEC_WEP:
233 len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN;
234 break;
235 }
236
237 if (trans_pcie->bc_table_dword)
238 len = DIV_ROUND_UP(len, 4);
239
240 bc_ent = cpu_to_le16(len | (sta_id << 12));
241
242 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
243
244 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
245 scd_bc_tbl[txq_id].
246 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
247 }
248
249 static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
250 struct iwl_txq *txq)
251 {
252 struct iwl_trans_pcie *trans_pcie =
253 IWL_TRANS_GET_PCIE_TRANS(trans);
254 struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
255 int txq_id = txq->q.id;
256 int read_ptr = txq->q.read_ptr;
257 u8 sta_id = 0;
258 __le16 bc_ent;
259 struct iwl_tx_cmd *tx_cmd =
260 (void *)txq->entries[txq->q.read_ptr].cmd->payload;
261
262 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
263
264 if (txq_id != trans_pcie->cmd_queue)
265 sta_id = tx_cmd->sta_id;
266
267 bc_ent = cpu_to_le16(1 | (sta_id << 12));
268 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
269
270 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
271 scd_bc_tbl[txq_id].
272 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
273 }
274
275 /*
276 * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware
277 */
278 void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans, struct iwl_txq *txq)
279 {
280 u32 reg = 0;
281 int txq_id = txq->q.id;
282
283 if (txq->need_update == 0)
284 return;
285
286 if (trans->cfg->base_params->shadow_reg_enable) {
287 /* shadow register enabled */
288 iwl_write32(trans, HBUS_TARG_WRPTR,
289 txq->q.write_ptr | (txq_id << 8));
290 } else {
291 struct iwl_trans_pcie *trans_pcie =
292 IWL_TRANS_GET_PCIE_TRANS(trans);
293 /* if we're trying to save power */
294 if (test_bit(STATUS_TPOWER_PMI, &trans_pcie->status)) {
295 /* wake up nic if it's powered down ...
296 * uCode will wake up, and interrupt us again, so next
297 * time we'll skip this part. */
298 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
299
300 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
301 IWL_DEBUG_INFO(trans,
302 "Tx queue %d requesting wakeup,"
303 " GP1 = 0x%x\n", txq_id, reg);
304 iwl_set_bit(trans, CSR_GP_CNTRL,
305 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
306 return;
307 }
308
309 IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id,
310 txq->q.write_ptr);
311
312 iwl_write_direct32(trans, HBUS_TARG_WRPTR,
313 txq->q.write_ptr | (txq_id << 8));
314
315 /*
316 * else not in power-save mode,
317 * uCode will never sleep when we're
318 * trying to tx (during RFKILL, we're not trying to tx).
319 */
320 } else
321 iwl_write32(trans, HBUS_TARG_WRPTR,
322 txq->q.write_ptr | (txq_id << 8));
323 }
324 txq->need_update = 0;
325 }
326
327 static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
328 {
329 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
330
331 dma_addr_t addr = get_unaligned_le32(&tb->lo);
332 if (sizeof(dma_addr_t) > sizeof(u32))
333 addr |=
334 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
335
336 return addr;
337 }
338
339 static inline u16 iwl_pcie_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
340 {
341 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
342
343 return le16_to_cpu(tb->hi_n_len) >> 4;
344 }
345
346 static inline void iwl_pcie_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
347 dma_addr_t addr, u16 len)
348 {
349 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
350 u16 hi_n_len = len << 4;
351
352 put_unaligned_le32(addr, &tb->lo);
353 if (sizeof(dma_addr_t) > sizeof(u32))
354 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
355
356 tb->hi_n_len = cpu_to_le16(hi_n_len);
357
358 tfd->num_tbs = idx + 1;
359 }
360
361 static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_tfd *tfd)
362 {
363 return tfd->num_tbs & 0x1f;
364 }
365
366 static void iwl_pcie_tfd_unmap(struct iwl_trans *trans,
367 struct iwl_cmd_meta *meta,
368 struct iwl_tfd *tfd)
369 {
370 int i;
371 int num_tbs;
372
373 /* Sanity check on number of chunks */
374 num_tbs = iwl_pcie_tfd_get_num_tbs(tfd);
375
376 if (num_tbs >= IWL_NUM_OF_TBS) {
377 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
378 /* @todo issue fatal error, it is quite serious situation */
379 return;
380 }
381
382 /* first TB is never freed - it's the scratchbuf data */
383
384 for (i = 1; i < num_tbs; i++)
385 dma_unmap_single(trans->dev, iwl_pcie_tfd_tb_get_addr(tfd, i),
386 iwl_pcie_tfd_tb_get_len(tfd, i),
387 DMA_TO_DEVICE);
388
389 tfd->num_tbs = 0;
390 }
391
392 /*
393 * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
394 * @trans - transport private data
395 * @txq - tx queue
396 * @dma_dir - the direction of the DMA mapping
397 *
398 * Does NOT advance any TFD circular buffer read/write indexes
399 * Does NOT free the TFD itself (which is within circular buffer)
400 */
401 static void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq)
402 {
403 struct iwl_tfd *tfd_tmp = txq->tfds;
404
405 /* rd_ptr is bounded by n_bd and idx is bounded by n_window */
406 int rd_ptr = txq->q.read_ptr;
407 int idx = get_cmd_index(&txq->q, rd_ptr);
408
409 lockdep_assert_held(&txq->lock);
410
411 /* We have only q->n_window txq->entries, but we use q->n_bd tfds */
412 iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, &tfd_tmp[rd_ptr]);
413
414 /* free SKB */
415 if (txq->entries) {
416 struct sk_buff *skb;
417
418 skb = txq->entries[idx].skb;
419
420 /* Can be called from irqs-disabled context
421 * If skb is not NULL, it means that the whole queue is being
422 * freed and that the queue is not empty - free the skb
423 */
424 if (skb) {
425 iwl_op_mode_free_skb(trans->op_mode, skb);
426 txq->entries[idx].skb = NULL;
427 }
428 }
429 }
430
431 static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq,
432 dma_addr_t addr, u16 len, u8 reset)
433 {
434 struct iwl_queue *q;
435 struct iwl_tfd *tfd, *tfd_tmp;
436 u32 num_tbs;
437
438 q = &txq->q;
439 tfd_tmp = txq->tfds;
440 tfd = &tfd_tmp[q->write_ptr];
441
442 if (reset)
443 memset(tfd, 0, sizeof(*tfd));
444
445 num_tbs = iwl_pcie_tfd_get_num_tbs(tfd);
446
447 /* Each TFD can point to a maximum 20 Tx buffers */
448 if (num_tbs >= IWL_NUM_OF_TBS) {
449 IWL_ERR(trans, "Error can not send more than %d chunks\n",
450 IWL_NUM_OF_TBS);
451 return -EINVAL;
452 }
453
454 if (WARN_ON(addr & ~DMA_BIT_MASK(36)))
455 return -EINVAL;
456
457 if (unlikely(addr & ~IWL_TX_DMA_MASK))
458 IWL_ERR(trans, "Unaligned address = %llx\n",
459 (unsigned long long)addr);
460
461 iwl_pcie_tfd_set_tb(tfd, num_tbs, addr, len);
462
463 return 0;
464 }
465
466 static int iwl_pcie_txq_alloc(struct iwl_trans *trans,
467 struct iwl_txq *txq, int slots_num,
468 u32 txq_id)
469 {
470 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
471 size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
472 size_t scratchbuf_sz;
473 int i;
474
475 if (WARN_ON(txq->entries || txq->tfds))
476 return -EINVAL;
477
478 setup_timer(&txq->stuck_timer, iwl_pcie_txq_stuck_timer,
479 (unsigned long)txq);
480 txq->trans_pcie = trans_pcie;
481
482 txq->q.n_window = slots_num;
483
484 txq->entries = kcalloc(slots_num,
485 sizeof(struct iwl_pcie_txq_entry),
486 GFP_KERNEL);
487
488 if (!txq->entries)
489 goto error;
490
491 if (txq_id == trans_pcie->cmd_queue)
492 for (i = 0; i < slots_num; i++) {
493 txq->entries[i].cmd =
494 kmalloc(sizeof(struct iwl_device_cmd),
495 GFP_KERNEL);
496 if (!txq->entries[i].cmd)
497 goto error;
498 }
499
500 /* Circular buffer of transmit frame descriptors (TFDs),
501 * shared with device */
502 txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
503 &txq->q.dma_addr, GFP_KERNEL);
504 if (!txq->tfds)
505 goto error;
506
507 BUILD_BUG_ON(IWL_HCMD_SCRATCHBUF_SIZE != sizeof(*txq->scratchbufs));
508 BUILD_BUG_ON(offsetof(struct iwl_pcie_txq_scratch_buf, scratch) !=
509 sizeof(struct iwl_cmd_header) +
510 offsetof(struct iwl_tx_cmd, scratch));
511
512 scratchbuf_sz = sizeof(*txq->scratchbufs) * slots_num;
513
514 txq->scratchbufs = dma_alloc_coherent(trans->dev, scratchbuf_sz,
515 &txq->scratchbufs_dma,
516 GFP_KERNEL);
517 if (!txq->scratchbufs)
518 goto err_free_tfds;
519
520 txq->q.id = txq_id;
521
522 return 0;
523 err_free_tfds:
524 dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->q.dma_addr);
525 error:
526 if (txq->entries && txq_id == trans_pcie->cmd_queue)
527 for (i = 0; i < slots_num; i++)
528 kfree(txq->entries[i].cmd);
529 kfree(txq->entries);
530 txq->entries = NULL;
531
532 return -ENOMEM;
533
534 }
535
536 static int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq,
537 int slots_num, u32 txq_id)
538 {
539 int ret;
540
541 txq->need_update = 0;
542
543 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
544 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
545 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
546
547 /* Initialize queue's high/low-water marks, and head/tail indexes */
548 ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
549 txq_id);
550 if (ret)
551 return ret;
552
553 spin_lock_init(&txq->lock);
554
555 /*
556 * Tell nic where to find circular buffer of Tx Frame Descriptors for
557 * given Tx queue, and enable the DMA channel used for that queue.
558 * Circular buffer (TFD queue in DRAM) physical base address */
559 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
560 txq->q.dma_addr >> 8);
561
562 return 0;
563 }
564
565 /*
566 * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's
567 */
568 static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id)
569 {
570 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
571 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
572 struct iwl_queue *q = &txq->q;
573
574 if (!q->n_bd)
575 return;
576
577 spin_lock_bh(&txq->lock);
578 while (q->write_ptr != q->read_ptr) {
579 IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n",
580 txq_id, q->read_ptr);
581 iwl_pcie_txq_free_tfd(trans, txq);
582 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
583 }
584 txq->active = false;
585 spin_unlock_bh(&txq->lock);
586
587 /* just in case - this queue may have been stopped */
588 iwl_wake_queue(trans, txq);
589 }
590
591 /*
592 * iwl_pcie_txq_free - Deallocate DMA queue.
593 * @txq: Transmit queue to deallocate.
594 *
595 * Empty queue by removing and destroying all BD's.
596 * Free all buffers.
597 * 0-fill, but do not free "txq" descriptor structure.
598 */
599 static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id)
600 {
601 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
602 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
603 struct device *dev = trans->dev;
604 int i;
605
606 if (WARN_ON(!txq))
607 return;
608
609 iwl_pcie_txq_unmap(trans, txq_id);
610
611 /* De-alloc array of command/tx buffers */
612 if (txq_id == trans_pcie->cmd_queue)
613 for (i = 0; i < txq->q.n_window; i++) {
614 kfree(txq->entries[i].cmd);
615 kfree(txq->entries[i].free_buf);
616 }
617
618 /* De-alloc circular buffer of TFDs */
619 if (txq->q.n_bd) {
620 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
621 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
622 txq->q.dma_addr = 0;
623
624 dma_free_coherent(dev,
625 sizeof(*txq->scratchbufs) * txq->q.n_window,
626 txq->scratchbufs, txq->scratchbufs_dma);
627 }
628
629 kfree(txq->entries);
630 txq->entries = NULL;
631
632 del_timer_sync(&txq->stuck_timer);
633
634 /* 0-fill queue descriptor structure */
635 memset(txq, 0, sizeof(*txq));
636 }
637
638 /*
639 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
640 */
641 static void iwl_pcie_txq_set_sched(struct iwl_trans *trans, u32 mask)
642 {
643 struct iwl_trans_pcie __maybe_unused *trans_pcie =
644 IWL_TRANS_GET_PCIE_TRANS(trans);
645
646 iwl_write_prph(trans, SCD_TXFACT, mask);
647 }
648
649 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
650 {
651 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
652 int nq = trans->cfg->base_params->num_of_queues;
653 int chan;
654 u32 reg_val;
655 int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) -
656 SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32);
657
658 /* make sure all queue are not stopped/used */
659 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
660 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
661
662 trans_pcie->scd_base_addr =
663 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
664
665 WARN_ON(scd_base_addr != 0 &&
666 scd_base_addr != trans_pcie->scd_base_addr);
667
668 /* reset context data, TX status and translation data */
669 iwl_trans_write_mem(trans, trans_pcie->scd_base_addr +
670 SCD_CONTEXT_MEM_LOWER_BOUND,
671 NULL, clear_dwords);
672
673 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
674 trans_pcie->scd_bc_tbls.dma >> 10);
675
676 /* The chain extension of the SCD doesn't work well. This feature is
677 * enabled by default by the HW, so we need to disable it manually.
678 */
679 iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
680
681 iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue,
682 trans_pcie->cmd_fifo);
683
684 /* Activate all Tx DMA/FIFO channels */
685 iwl_pcie_txq_set_sched(trans, IWL_MASK(0, 7));
686
687 /* Enable DMA channel */
688 for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++)
689 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
690 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
691 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
692
693 /* Update FH chicken bits */
694 reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
695 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
696 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
697
698 /* Enable L1-Active */
699 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
700 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
701 }
702
703 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans)
704 {
705 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
706 int txq_id;
707
708 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
709 txq_id++) {
710 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
711
712 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
713 txq->q.dma_addr >> 8);
714 iwl_pcie_txq_unmap(trans, txq_id);
715 txq->q.read_ptr = 0;
716 txq->q.write_ptr = 0;
717 }
718
719 /* Tell NIC where to find the "keep warm" buffer */
720 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
721 trans_pcie->kw.dma >> 4);
722
723 iwl_pcie_tx_start(trans, trans_pcie->scd_base_addr);
724 }
725
726 /*
727 * iwl_pcie_tx_stop - Stop all Tx DMA channels
728 */
729 int iwl_pcie_tx_stop(struct iwl_trans *trans)
730 {
731 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
732 int ch, txq_id, ret;
733 unsigned long flags;
734
735 /* Turn off all Tx DMA fifos */
736 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
737
738 iwl_pcie_txq_set_sched(trans, 0);
739
740 /* Stop each Tx DMA channel, and wait for it to be idle */
741 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
742 iwl_write_direct32(trans,
743 FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
744 ret = iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG,
745 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 1000);
746 if (ret < 0)
747 IWL_ERR(trans,
748 "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
749 ch,
750 iwl_read_direct32(trans,
751 FH_TSSR_TX_STATUS_REG));
752 }
753 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
754
755 if (!trans_pcie->txq) {
756 IWL_WARN(trans,
757 "Stopping tx queues that aren't allocated...\n");
758 return 0;
759 }
760
761 /* Unmap DMA from host system and free skb's */
762 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
763 txq_id++)
764 iwl_pcie_txq_unmap(trans, txq_id);
765
766 return 0;
767 }
768
769 /*
770 * iwl_trans_tx_free - Free TXQ Context
771 *
772 * Destroy all TX DMA queues and structures
773 */
774 void iwl_pcie_tx_free(struct iwl_trans *trans)
775 {
776 int txq_id;
777 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
778
779 /* Tx queues */
780 if (trans_pcie->txq) {
781 for (txq_id = 0;
782 txq_id < trans->cfg->base_params->num_of_queues; txq_id++)
783 iwl_pcie_txq_free(trans, txq_id);
784 }
785
786 kfree(trans_pcie->txq);
787 trans_pcie->txq = NULL;
788
789 iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw);
790
791 iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
792 }
793
794 /*
795 * iwl_pcie_tx_alloc - allocate TX context
796 * Allocate all Tx DMA structures and initialize them
797 */
798 static int iwl_pcie_tx_alloc(struct iwl_trans *trans)
799 {
800 int ret;
801 int txq_id, slots_num;
802 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
803
804 u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues *
805 sizeof(struct iwlagn_scd_bc_tbl);
806
807 /*It is not allowed to alloc twice, so warn when this happens.
808 * We cannot rely on the previous allocation, so free and fail */
809 if (WARN_ON(trans_pcie->txq)) {
810 ret = -EINVAL;
811 goto error;
812 }
813
814 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
815 scd_bc_tbls_size);
816 if (ret) {
817 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
818 goto error;
819 }
820
821 /* Alloc keep-warm buffer */
822 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
823 if (ret) {
824 IWL_ERR(trans, "Keep Warm allocation failed\n");
825 goto error;
826 }
827
828 trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues,
829 sizeof(struct iwl_txq), GFP_KERNEL);
830 if (!trans_pcie->txq) {
831 IWL_ERR(trans, "Not enough memory for txq\n");
832 ret = ENOMEM;
833 goto error;
834 }
835
836 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
837 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
838 txq_id++) {
839 slots_num = (txq_id == trans_pcie->cmd_queue) ?
840 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
841 ret = iwl_pcie_txq_alloc(trans, &trans_pcie->txq[txq_id],
842 slots_num, txq_id);
843 if (ret) {
844 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
845 goto error;
846 }
847 }
848
849 return 0;
850
851 error:
852 iwl_pcie_tx_free(trans);
853
854 return ret;
855 }
856 int iwl_pcie_tx_init(struct iwl_trans *trans)
857 {
858 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
859 int ret;
860 int txq_id, slots_num;
861 unsigned long flags;
862 bool alloc = false;
863
864 if (!trans_pcie->txq) {
865 ret = iwl_pcie_tx_alloc(trans);
866 if (ret)
867 goto error;
868 alloc = true;
869 }
870
871 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
872
873 /* Turn off all Tx DMA fifos */
874 iwl_write_prph(trans, SCD_TXFACT, 0);
875
876 /* Tell NIC where to find the "keep warm" buffer */
877 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
878 trans_pcie->kw.dma >> 4);
879
880 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
881
882 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
883 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
884 txq_id++) {
885 slots_num = (txq_id == trans_pcie->cmd_queue) ?
886 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
887 ret = iwl_pcie_txq_init(trans, &trans_pcie->txq[txq_id],
888 slots_num, txq_id);
889 if (ret) {
890 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
891 goto error;
892 }
893 }
894
895 return 0;
896 error:
897 /*Upon error, free only if we allocated something */
898 if (alloc)
899 iwl_pcie_tx_free(trans);
900 return ret;
901 }
902
903 static inline void iwl_pcie_txq_progress(struct iwl_trans_pcie *trans_pcie,
904 struct iwl_txq *txq)
905 {
906 if (!trans_pcie->wd_timeout)
907 return;
908
909 /*
910 * if empty delete timer, otherwise move timer forward
911 * since we're making progress on this queue
912 */
913 if (txq->q.read_ptr == txq->q.write_ptr)
914 del_timer(&txq->stuck_timer);
915 else
916 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
917 }
918
919 /* Frees buffers until index _not_ inclusive */
920 void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
921 struct sk_buff_head *skbs)
922 {
923 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
924 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
925 /* n_bd is usually 256 => n_bd - 1 = 0xff */
926 int tfd_num = ssn & (txq->q.n_bd - 1);
927 struct iwl_queue *q = &txq->q;
928 int last_to_free;
929
930 /* This function is not meant to release cmd queue*/
931 if (WARN_ON(txq_id == trans_pcie->cmd_queue))
932 return;
933
934 spin_lock_bh(&txq->lock);
935
936 if (!txq->active) {
937 IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n",
938 txq_id, ssn);
939 goto out;
940 }
941
942 if (txq->q.read_ptr == tfd_num)
943 goto out;
944
945 IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
946 txq_id, txq->q.read_ptr, tfd_num, ssn);
947
948 /*Since we free until index _not_ inclusive, the one before index is
949 * the last we will free. This one must be used */
950 last_to_free = iwl_queue_dec_wrap(tfd_num, q->n_bd);
951
952 if (!iwl_queue_used(q, last_to_free)) {
953 IWL_ERR(trans,
954 "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",
955 __func__, txq_id, last_to_free, q->n_bd,
956 q->write_ptr, q->read_ptr);
957 goto out;
958 }
959
960 if (WARN_ON(!skb_queue_empty(skbs)))
961 goto out;
962
963 for (;
964 q->read_ptr != tfd_num;
965 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
966
967 if (WARN_ON_ONCE(txq->entries[txq->q.read_ptr].skb == NULL))
968 continue;
969
970 __skb_queue_tail(skbs, txq->entries[txq->q.read_ptr].skb);
971
972 txq->entries[txq->q.read_ptr].skb = NULL;
973
974 iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq);
975
976 iwl_pcie_txq_free_tfd(trans, txq);
977 }
978
979 iwl_pcie_txq_progress(trans_pcie, txq);
980
981 if (iwl_queue_space(&txq->q) > txq->q.low_mark)
982 iwl_wake_queue(trans, txq);
983 out:
984 spin_unlock_bh(&txq->lock);
985 }
986
987 /*
988 * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd
989 *
990 * When FW advances 'R' index, all entries between old and new 'R' index
991 * need to be reclaimed. As result, some free space forms. If there is
992 * enough free space (> low mark), wake the stack that feeds us.
993 */
994 static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx)
995 {
996 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
997 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
998 struct iwl_queue *q = &txq->q;
999 int nfreed = 0;
1000
1001 lockdep_assert_held(&txq->lock);
1002
1003 if ((idx >= q->n_bd) || (!iwl_queue_used(q, idx))) {
1004 IWL_ERR(trans,
1005 "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
1006 __func__, txq_id, idx, q->n_bd,
1007 q->write_ptr, q->read_ptr);
1008 return;
1009 }
1010
1011 for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
1012 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1013
1014 if (nfreed++ > 0) {
1015 IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n",
1016 idx, q->write_ptr, q->read_ptr);
1017 iwl_op_mode_nic_error(trans->op_mode);
1018 }
1019 }
1020
1021 iwl_pcie_txq_progress(trans_pcie, txq);
1022 }
1023
1024 static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid,
1025 u16 txq_id)
1026 {
1027 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1028 u32 tbl_dw_addr;
1029 u32 tbl_dw;
1030 u16 scd_q2ratid;
1031
1032 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
1033
1034 tbl_dw_addr = trans_pcie->scd_base_addr +
1035 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
1036
1037 tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr);
1038
1039 if (txq_id & 0x1)
1040 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1041 else
1042 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1043
1044 iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw);
1045
1046 return 0;
1047 }
1048
1049 static inline void iwl_pcie_txq_set_inactive(struct iwl_trans *trans,
1050 u16 txq_id)
1051 {
1052 /* Simply stop the queue, but don't change any configuration;
1053 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
1054 iwl_write_prph(trans,
1055 SCD_QUEUE_STATUS_BITS(txq_id),
1056 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
1057 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
1058 }
1059
1060 /* Receiver address (actually, Rx station's index into station table),
1061 * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */
1062 #define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid))
1063
1064 void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, int fifo,
1065 int sta_id, int tid, int frame_limit, u16 ssn)
1066 {
1067 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1068
1069 if (test_and_set_bit(txq_id, trans_pcie->queue_used))
1070 WARN_ONCE(1, "queue %d already used - expect issues", txq_id);
1071
1072 /* Stop this Tx queue before configuring it */
1073 iwl_pcie_txq_set_inactive(trans, txq_id);
1074
1075 /* Set this queue as a chain-building queue unless it is CMD queue */
1076 if (txq_id != trans_pcie->cmd_queue)
1077 iwl_set_bits_prph(trans, SCD_QUEUECHAIN_SEL, BIT(txq_id));
1078
1079 /* If this queue is mapped to a certain station: it is an AGG queue */
1080 if (sta_id >= 0) {
1081 u16 ra_tid = BUILD_RAxTID(sta_id, tid);
1082
1083 /* Map receiver-address / traffic-ID to this queue */
1084 iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id);
1085
1086 /* enable aggregations for the queue */
1087 iwl_set_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id));
1088 trans_pcie->txq[txq_id].ampdu = true;
1089 } else {
1090 /*
1091 * disable aggregations for the queue, this will also make the
1092 * ra_tid mapping configuration irrelevant since it is now a
1093 * non-AGG queue.
1094 */
1095 iwl_clear_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id));
1096 }
1097
1098 /* Place first TFD at index corresponding to start sequence number.
1099 * Assumes that ssn_idx is valid (!= 0xFFF) */
1100 trans_pcie->txq[txq_id].q.read_ptr = (ssn & 0xff);
1101 trans_pcie->txq[txq_id].q.write_ptr = (ssn & 0xff);
1102
1103 iwl_write_direct32(trans, HBUS_TARG_WRPTR,
1104 (ssn & 0xff) | (txq_id << 8));
1105 iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);
1106
1107 /* Set up Tx window size and frame limit for this queue */
1108 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
1109 SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0);
1110 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
1111 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1112 ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1113 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1114 ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1115 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1116
1117 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1118 iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
1119 (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1120 (fifo << SCD_QUEUE_STTS_REG_POS_TXF) |
1121 (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
1122 SCD_QUEUE_STTS_REG_MSK);
1123 trans_pcie->txq[txq_id].active = true;
1124 IWL_DEBUG_TX_QUEUES(trans, "Activate queue %d on FIFO %d WrPtr: %d\n",
1125 txq_id, fifo, ssn & 0xff);
1126 }
1127
1128 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id)
1129 {
1130 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1131 u32 stts_addr = trans_pcie->scd_base_addr +
1132 SCD_TX_STTS_QUEUE_OFFSET(txq_id);
1133 static const u32 zero_val[4] = {};
1134
1135 if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) {
1136 WARN_ONCE(1, "queue %d not used", txq_id);
1137 return;
1138 }
1139
1140 iwl_pcie_txq_set_inactive(trans, txq_id);
1141
1142 iwl_trans_write_mem(trans, stts_addr, (void *)zero_val,
1143 ARRAY_SIZE(zero_val));
1144
1145 iwl_pcie_txq_unmap(trans, txq_id);
1146 trans_pcie->txq[txq_id].ampdu = false;
1147
1148 IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id);
1149 }
1150
1151 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
1152
1153 /*
1154 * iwl_pcie_enqueue_hcmd - enqueue a uCode command
1155 * @priv: device private data point
1156 * @cmd: a point to the ucode command structure
1157 *
1158 * The function returns < 0 values to indicate the operation is
1159 * failed. On success, it turns the index (> 0) of command in the
1160 * command queue.
1161 */
1162 static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
1163 struct iwl_host_cmd *cmd)
1164 {
1165 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1166 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1167 struct iwl_queue *q = &txq->q;
1168 struct iwl_device_cmd *out_cmd;
1169 struct iwl_cmd_meta *out_meta;
1170 void *dup_buf = NULL;
1171 dma_addr_t phys_addr;
1172 int idx;
1173 u16 copy_size, cmd_size, scratch_size;
1174 bool had_nocopy = false;
1175 int i;
1176 u32 cmd_pos;
1177 const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD];
1178 u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD];
1179
1180 copy_size = sizeof(out_cmd->hdr);
1181 cmd_size = sizeof(out_cmd->hdr);
1182
1183 /* need one for the header if the first is NOCOPY */
1184 BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1);
1185
1186 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1187 cmddata[i] = cmd->data[i];
1188 cmdlen[i] = cmd->len[i];
1189
1190 if (!cmd->len[i])
1191 continue;
1192
1193 /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */
1194 if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) {
1195 int copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size;
1196
1197 if (copy > cmdlen[i])
1198 copy = cmdlen[i];
1199 cmdlen[i] -= copy;
1200 cmddata[i] += copy;
1201 copy_size += copy;
1202 }
1203
1204 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
1205 had_nocopy = true;
1206 if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) {
1207 idx = -EINVAL;
1208 goto free_dup_buf;
1209 }
1210 } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) {
1211 /*
1212 * This is also a chunk that isn't copied
1213 * to the static buffer so set had_nocopy.
1214 */
1215 had_nocopy = true;
1216
1217 /* only allowed once */
1218 if (WARN_ON(dup_buf)) {
1219 idx = -EINVAL;
1220 goto free_dup_buf;
1221 }
1222
1223 dup_buf = kmemdup(cmddata[i], cmdlen[i],
1224 GFP_ATOMIC);
1225 if (!dup_buf)
1226 return -ENOMEM;
1227 } else {
1228 /* NOCOPY must not be followed by normal! */
1229 if (WARN_ON(had_nocopy)) {
1230 idx = -EINVAL;
1231 goto free_dup_buf;
1232 }
1233 copy_size += cmdlen[i];
1234 }
1235 cmd_size += cmd->len[i];
1236 }
1237
1238 /*
1239 * If any of the command structures end up being larger than
1240 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
1241 * allocated into separate TFDs, then we will need to
1242 * increase the size of the buffers.
1243 */
1244 if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE,
1245 "Command %s (%#x) is too large (%d bytes)\n",
1246 get_cmd_string(trans_pcie, cmd->id), cmd->id, copy_size)) {
1247 idx = -EINVAL;
1248 goto free_dup_buf;
1249 }
1250
1251 spin_lock_bh(&txq->lock);
1252
1253 if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
1254 spin_unlock_bh(&txq->lock);
1255
1256 IWL_ERR(trans, "No space in command queue\n");
1257 iwl_op_mode_cmd_queue_full(trans->op_mode);
1258 idx = -ENOSPC;
1259 goto free_dup_buf;
1260 }
1261
1262 idx = get_cmd_index(q, q->write_ptr);
1263 out_cmd = txq->entries[idx].cmd;
1264 out_meta = &txq->entries[idx].meta;
1265
1266 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
1267 if (cmd->flags & CMD_WANT_SKB)
1268 out_meta->source = cmd;
1269
1270 /* set up the header */
1271
1272 out_cmd->hdr.cmd = cmd->id;
1273 out_cmd->hdr.flags = 0;
1274 out_cmd->hdr.sequence =
1275 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1276 INDEX_TO_SEQ(q->write_ptr));
1277
1278 /* and copy the data that needs to be copied */
1279 cmd_pos = offsetof(struct iwl_device_cmd, payload);
1280 copy_size = sizeof(out_cmd->hdr);
1281 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1282 int copy = 0;
1283
1284 if (!cmd->len[i])
1285 continue;
1286
1287 /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */
1288 if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) {
1289 copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size;
1290
1291 if (copy > cmd->len[i])
1292 copy = cmd->len[i];
1293 }
1294
1295 /* copy everything if not nocopy/dup */
1296 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1297 IWL_HCMD_DFL_DUP)))
1298 copy = cmd->len[i];
1299
1300 if (copy) {
1301 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1302 cmd_pos += copy;
1303 copy_size += copy;
1304 }
1305 }
1306
1307 IWL_DEBUG_HC(trans,
1308 "Sending command %s (#%x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
1309 get_cmd_string(trans_pcie, out_cmd->hdr.cmd),
1310 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
1311 cmd_size, q->write_ptr, idx, trans_pcie->cmd_queue);
1312
1313 /* start the TFD with the scratchbuf */
1314 scratch_size = min_t(int, copy_size, IWL_HCMD_SCRATCHBUF_SIZE);
1315 memcpy(&txq->scratchbufs[q->write_ptr], &out_cmd->hdr, scratch_size);
1316 iwl_pcie_txq_build_tfd(trans, txq,
1317 iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr),
1318 scratch_size, 1);
1319
1320 /* map first command fragment, if any remains */
1321 if (copy_size > scratch_size) {
1322 phys_addr = dma_map_single(trans->dev,
1323 ((u8 *)&out_cmd->hdr) + scratch_size,
1324 copy_size - scratch_size,
1325 DMA_TO_DEVICE);
1326 if (dma_mapping_error(trans->dev, phys_addr)) {
1327 iwl_pcie_tfd_unmap(trans, out_meta,
1328 &txq->tfds[q->write_ptr]);
1329 idx = -ENOMEM;
1330 goto out;
1331 }
1332
1333 iwl_pcie_txq_build_tfd(trans, txq, phys_addr,
1334 copy_size - scratch_size, 0);
1335 }
1336
1337 /* map the remaining (adjusted) nocopy/dup fragments */
1338 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1339 const void *data = cmddata[i];
1340
1341 if (!cmdlen[i])
1342 continue;
1343 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1344 IWL_HCMD_DFL_DUP)))
1345 continue;
1346 if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP)
1347 data = dup_buf;
1348 phys_addr = dma_map_single(trans->dev, (void *)data,
1349 cmdlen[i], DMA_TO_DEVICE);
1350 if (dma_mapping_error(trans->dev, phys_addr)) {
1351 iwl_pcie_tfd_unmap(trans, out_meta,
1352 &txq->tfds[q->write_ptr]);
1353 idx = -ENOMEM;
1354 goto out;
1355 }
1356
1357 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], 0);
1358 }
1359
1360 out_meta->flags = cmd->flags;
1361 if (WARN_ON_ONCE(txq->entries[idx].free_buf))
1362 kfree(txq->entries[idx].free_buf);
1363 txq->entries[idx].free_buf = dup_buf;
1364
1365 txq->need_update = 1;
1366
1367 trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr);
1368
1369 /* start timer if queue currently empty */
1370 if (q->read_ptr == q->write_ptr && trans_pcie->wd_timeout)
1371 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
1372
1373 /* Increment and update queue's write index */
1374 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1375 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1376
1377 out:
1378 spin_unlock_bh(&txq->lock);
1379 free_dup_buf:
1380 if (idx < 0)
1381 kfree(dup_buf);
1382 return idx;
1383 }
1384
1385 /*
1386 * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them
1387 * @rxb: Rx buffer to reclaim
1388 * @handler_status: return value of the handler of the command
1389 * (put in setup_rx_handlers)
1390 *
1391 * If an Rx buffer has an async callback associated with it the callback
1392 * will be executed. The attached skb (if present) will only be freed
1393 * if the callback returns 1
1394 */
1395 void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
1396 struct iwl_rx_cmd_buffer *rxb, int handler_status)
1397 {
1398 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1399 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1400 int txq_id = SEQ_TO_QUEUE(sequence);
1401 int index = SEQ_TO_INDEX(sequence);
1402 int cmd_index;
1403 struct iwl_device_cmd *cmd;
1404 struct iwl_cmd_meta *meta;
1405 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1406 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1407
1408 /* If a Tx command is being handled and it isn't in the actual
1409 * command queue then there a command routing bug has been introduced
1410 * in the queue management code. */
1411 if (WARN(txq_id != trans_pcie->cmd_queue,
1412 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
1413 txq_id, trans_pcie->cmd_queue, sequence,
1414 trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr,
1415 trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) {
1416 iwl_print_hex_error(trans, pkt, 32);
1417 return;
1418 }
1419
1420 spin_lock_bh(&txq->lock);
1421
1422 cmd_index = get_cmd_index(&txq->q, index);
1423 cmd = txq->entries[cmd_index].cmd;
1424 meta = &txq->entries[cmd_index].meta;
1425
1426 iwl_pcie_tfd_unmap(trans, meta, &txq->tfds[index]);
1427
1428 /* Input error checking is done when commands are added to queue. */
1429 if (meta->flags & CMD_WANT_SKB) {
1430 struct page *p = rxb_steal_page(rxb);
1431
1432 meta->source->resp_pkt = pkt;
1433 meta->source->_rx_page_addr = (unsigned long)page_address(p);
1434 meta->source->_rx_page_order = trans_pcie->rx_page_order;
1435 meta->source->handler_status = handler_status;
1436 }
1437
1438 iwl_pcie_cmdq_reclaim(trans, txq_id, index);
1439
1440 if (!(meta->flags & CMD_ASYNC)) {
1441 if (!test_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status)) {
1442 IWL_WARN(trans,
1443 "HCMD_ACTIVE already clear for command %s\n",
1444 get_cmd_string(trans_pcie, cmd->hdr.cmd));
1445 }
1446 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
1447 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1448 get_cmd_string(trans_pcie, cmd->hdr.cmd));
1449 wake_up(&trans_pcie->wait_command_queue);
1450 }
1451
1452 meta->flags = 0;
1453
1454 spin_unlock_bh(&txq->lock);
1455 }
1456
1457 #define HOST_COMPLETE_TIMEOUT (2 * HZ)
1458
1459 static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans,
1460 struct iwl_host_cmd *cmd)
1461 {
1462 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1463 int ret;
1464
1465 /* An asynchronous command can not expect an SKB to be set. */
1466 if (WARN_ON(cmd->flags & CMD_WANT_SKB))
1467 return -EINVAL;
1468
1469 ret = iwl_pcie_enqueue_hcmd(trans, cmd);
1470 if (ret < 0) {
1471 IWL_ERR(trans,
1472 "Error sending %s: enqueue_hcmd failed: %d\n",
1473 get_cmd_string(trans_pcie, cmd->id), ret);
1474 return ret;
1475 }
1476 return 0;
1477 }
1478
1479 static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans,
1480 struct iwl_host_cmd *cmd)
1481 {
1482 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1483 int cmd_idx;
1484 int ret;
1485
1486 IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n",
1487 get_cmd_string(trans_pcie, cmd->id));
1488
1489 if (WARN_ON(test_and_set_bit(STATUS_HCMD_ACTIVE,
1490 &trans_pcie->status))) {
1491 IWL_ERR(trans, "Command %s: a command is already active!\n",
1492 get_cmd_string(trans_pcie, cmd->id));
1493 return -EIO;
1494 }
1495
1496 IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n",
1497 get_cmd_string(trans_pcie, cmd->id));
1498
1499 cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd);
1500 if (cmd_idx < 0) {
1501 ret = cmd_idx;
1502 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
1503 IWL_ERR(trans,
1504 "Error sending %s: enqueue_hcmd failed: %d\n",
1505 get_cmd_string(trans_pcie, cmd->id), ret);
1506 return ret;
1507 }
1508
1509 ret = wait_event_timeout(trans_pcie->wait_command_queue,
1510 !test_bit(STATUS_HCMD_ACTIVE,
1511 &trans_pcie->status),
1512 HOST_COMPLETE_TIMEOUT);
1513 if (!ret) {
1514 if (test_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status)) {
1515 struct iwl_txq *txq =
1516 &trans_pcie->txq[trans_pcie->cmd_queue];
1517 struct iwl_queue *q = &txq->q;
1518
1519 IWL_ERR(trans,
1520 "Error sending %s: time out after %dms.\n",
1521 get_cmd_string(trans_pcie, cmd->id),
1522 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
1523
1524 IWL_ERR(trans,
1525 "Current CMD queue read_ptr %d write_ptr %d\n",
1526 q->read_ptr, q->write_ptr);
1527
1528 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
1529 IWL_DEBUG_INFO(trans,
1530 "Clearing HCMD_ACTIVE for command %s\n",
1531 get_cmd_string(trans_pcie, cmd->id));
1532 ret = -ETIMEDOUT;
1533 goto cancel;
1534 }
1535 }
1536
1537 if (test_bit(STATUS_FW_ERROR, &trans_pcie->status)) {
1538 IWL_ERR(trans, "FW error in SYNC CMD %s\n",
1539 get_cmd_string(trans_pcie, cmd->id));
1540 dump_stack();
1541 ret = -EIO;
1542 goto cancel;
1543 }
1544
1545 if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1546 test_bit(STATUS_RFKILL, &trans_pcie->status)) {
1547 IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n");
1548 ret = -ERFKILL;
1549 goto cancel;
1550 }
1551
1552 if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) {
1553 IWL_ERR(trans, "Error: Response NULL in '%s'\n",
1554 get_cmd_string(trans_pcie, cmd->id));
1555 ret = -EIO;
1556 goto cancel;
1557 }
1558
1559 return 0;
1560
1561 cancel:
1562 if (cmd->flags & CMD_WANT_SKB) {
1563 /*
1564 * Cancel the CMD_WANT_SKB flag for the cmd in the
1565 * TX cmd queue. Otherwise in case the cmd comes
1566 * in later, it will possibly set an invalid
1567 * address (cmd->meta.source).
1568 */
1569 trans_pcie->txq[trans_pcie->cmd_queue].
1570 entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB;
1571 }
1572
1573 if (cmd->resp_pkt) {
1574 iwl_free_resp(cmd);
1575 cmd->resp_pkt = NULL;
1576 }
1577
1578 return ret;
1579 }
1580
1581 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
1582 {
1583 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1584
1585 if (test_bit(STATUS_FW_ERROR, &trans_pcie->status))
1586 return -EIO;
1587
1588 if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1589 test_bit(STATUS_RFKILL, &trans_pcie->status)) {
1590 IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n",
1591 cmd->id);
1592 return -ERFKILL;
1593 }
1594
1595 if (cmd->flags & CMD_ASYNC)
1596 return iwl_pcie_send_hcmd_async(trans, cmd);
1597
1598 /* We still can fail on RFKILL that can be asserted while we wait */
1599 return iwl_pcie_send_hcmd_sync(trans, cmd);
1600 }
1601
1602 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1603 struct iwl_device_cmd *dev_cmd, int txq_id)
1604 {
1605 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1606 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1607 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload;
1608 struct iwl_cmd_meta *out_meta;
1609 struct iwl_txq *txq;
1610 struct iwl_queue *q;
1611 dma_addr_t tb0_phys, tb1_phys, scratch_phys;
1612 void *tb1_addr;
1613 u16 len, tb1_len, tb2_len;
1614 u8 wait_write_ptr = 0;
1615 __le16 fc = hdr->frame_control;
1616 u8 hdr_len = ieee80211_hdrlen(fc);
1617 u16 wifi_seq;
1618
1619 txq = &trans_pcie->txq[txq_id];
1620 q = &txq->q;
1621
1622 if (unlikely(!test_bit(txq_id, trans_pcie->queue_used))) {
1623 WARN_ON_ONCE(1);
1624 return -EINVAL;
1625 }
1626
1627 spin_lock(&txq->lock);
1628
1629 /* In AGG mode, the index in the ring must correspond to the WiFi
1630 * sequence number. This is a HW requirements to help the SCD to parse
1631 * the BA.
1632 * Check here that the packets are in the right place on the ring.
1633 */
1634 wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
1635 WARN_ONCE(trans_pcie->txq[txq_id].ampdu &&
1636 (wifi_seq & 0xff) != q->write_ptr,
1637 "Q: %d WiFi Seq %d tfdNum %d",
1638 txq_id, wifi_seq, q->write_ptr);
1639
1640 /* Set up driver data for this TFD */
1641 txq->entries[q->write_ptr].skb = skb;
1642 txq->entries[q->write_ptr].cmd = dev_cmd;
1643
1644 dev_cmd->hdr.cmd = REPLY_TX;
1645 dev_cmd->hdr.sequence =
1646 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1647 INDEX_TO_SEQ(q->write_ptr)));
1648
1649 tb0_phys = iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr);
1650 scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) +
1651 offsetof(struct iwl_tx_cmd, scratch);
1652
1653 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1654 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1655
1656 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1657 out_meta = &txq->entries[q->write_ptr].meta;
1658
1659 /*
1660 * The second TB (tb1) points to the remainder of the TX command
1661 * and the 802.11 header - dword aligned size
1662 * (This calculation modifies the TX command, so do it before the
1663 * setup of the first TB)
1664 */
1665 len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) +
1666 hdr_len - IWL_HCMD_SCRATCHBUF_SIZE;
1667 tb1_len = (len + 3) & ~3;
1668
1669 /* Tell NIC about any 2-byte padding after MAC header */
1670 if (tb1_len != len)
1671 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1672
1673 /* The first TB points to the scratchbuf data - min_copy bytes */
1674 memcpy(&txq->scratchbufs[q->write_ptr], &dev_cmd->hdr,
1675 IWL_HCMD_SCRATCHBUF_SIZE);
1676 iwl_pcie_txq_build_tfd(trans, txq, tb0_phys,
1677 IWL_HCMD_SCRATCHBUF_SIZE, 1);
1678
1679 /* there must be data left over for TB1 or this code must be changed */
1680 BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_HCMD_SCRATCHBUF_SIZE);
1681
1682 /* map the data for TB1 */
1683 tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_HCMD_SCRATCHBUF_SIZE;
1684 tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE);
1685 if (unlikely(dma_mapping_error(trans->dev, tb1_phys)))
1686 goto out_err;
1687 iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, 0);
1688
1689 /*
1690 * Set up TFD's third entry to point directly to remainder
1691 * of skb, if any (802.11 null frames have no payload).
1692 */
1693 tb2_len = skb->len - hdr_len;
1694 if (tb2_len > 0) {
1695 dma_addr_t tb2_phys = dma_map_single(trans->dev,
1696 skb->data + hdr_len,
1697 tb2_len, DMA_TO_DEVICE);
1698 if (unlikely(dma_mapping_error(trans->dev, tb2_phys))) {
1699 iwl_pcie_tfd_unmap(trans, out_meta,
1700 &txq->tfds[q->write_ptr]);
1701 goto out_err;
1702 }
1703 iwl_pcie_txq_build_tfd(trans, txq, tb2_phys, tb2_len, 0);
1704 }
1705
1706 /* Set up entry for this TFD in Tx byte-count array */
1707 iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1708
1709 trace_iwlwifi_dev_tx(trans->dev, skb,
1710 &txq->tfds[txq->q.write_ptr],
1711 sizeof(struct iwl_tfd),
1712 &dev_cmd->hdr, IWL_HCMD_SCRATCHBUF_SIZE + tb1_len,
1713 skb->data + hdr_len, tb2_len);
1714 trace_iwlwifi_dev_tx_data(trans->dev, skb,
1715 skb->data + hdr_len, tb2_len);
1716
1717 if (!ieee80211_has_morefrags(fc)) {
1718 txq->need_update = 1;
1719 } else {
1720 wait_write_ptr = 1;
1721 txq->need_update = 0;
1722 }
1723
1724 /* start timer if queue currently empty */
1725 if (txq->need_update && q->read_ptr == q->write_ptr &&
1726 trans_pcie->wd_timeout)
1727 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
1728
1729 /* Tell device the write index *just past* this latest filled TFD */
1730 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1731 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1732
1733 /*
1734 * At this point the frame is "transmitted" successfully
1735 * and we will get a TX status notification eventually,
1736 * regardless of the value of ret. "ret" only indicates
1737 * whether or not we should update the write pointer.
1738 */
1739 if (iwl_queue_space(q) < q->high_mark) {
1740 if (wait_write_ptr) {
1741 txq->need_update = 1;
1742 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1743 } else {
1744 iwl_stop_queue(trans, txq);
1745 }
1746 }
1747 spin_unlock(&txq->lock);
1748 return 0;
1749 out_err:
1750 spin_unlock(&txq->lock);
1751 return -1;
1752 }
CRIS linux kernel tree