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Linux 3.11-rc3
[cris-mirror.git] / drivers / net / wireless / rt2x00 / rt2800pci.c
blob00055627eb8de41282a8248f0ad855a87fe00c86
1 /*
2 Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
6 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
7 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
8 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
9 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
10 <http://rt2x00.serialmonkey.com>
11
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
16
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the
24 Free Software Foundation, Inc.,
25 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 */
27
28 /*
29 Module: rt2800pci
30 Abstract: rt2800pci device specific routines.
31 Supported chipsets: RT2800E & RT2800ED.
32 */
33
34 #include <linux/delay.h>
35 #include <linux/etherdevice.h>
36 #include <linux/init.h>
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/platform_device.h>
41 #include <linux/eeprom_93cx6.h>
42
43 #include "rt2x00.h"
44 #include "rt2x00mmio.h"
45 #include "rt2x00pci.h"
46 #include "rt2x00soc.h"
47 #include "rt2800lib.h"
48 #include "rt2800.h"
49 #include "rt2800pci.h"
50
51 /*
52 * Allow hardware encryption to be disabled.
53 */
54 static bool modparam_nohwcrypt = false;
55 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
56 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
57
58 static bool rt2800pci_hwcrypt_disabled(struct rt2x00_dev *rt2x00dev)
59 {
60 return modparam_nohwcrypt;
61 }
62
63 static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
64 {
65 unsigned int i;
66 u32 reg;
67
68 /*
69 * SOC devices don't support MCU requests.
70 */
71 if (rt2x00_is_soc(rt2x00dev))
72 return;
73
74 for (i = 0; i < 200; i++) {
75 rt2x00mmio_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
76
77 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
78 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
79 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
80 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
81 break;
82
83 udelay(REGISTER_BUSY_DELAY);
84 }
85
86 if (i == 200)
87 rt2x00_err(rt2x00dev, "MCU request failed, no response from hardware\n");
88
89 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
90 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
91 }
92
93 #if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
94 static int rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
95 {
96 void __iomem *base_addr = ioremap(0x1F040000, EEPROM_SIZE);
97
98 if (!base_addr)
99 return -ENOMEM;
100
101 memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
102
103 iounmap(base_addr);
104 return 0;
105 }
106 #else
107 static inline int rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
108 {
109 return -ENOMEM;
110 }
111 #endif /* CONFIG_SOC_RT288X || CONFIG_SOC_RT305X */
112
113 #ifdef CONFIG_PCI
114 static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
115 {
116 struct rt2x00_dev *rt2x00dev = eeprom->data;
117 u32 reg;
118
119 rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, &reg);
120
121 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
122 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
123 eeprom->reg_data_clock =
124 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
125 eeprom->reg_chip_select =
126 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
127 }
128
129 static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
130 {
131 struct rt2x00_dev *rt2x00dev = eeprom->data;
132 u32 reg = 0;
133
134 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
135 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
136 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
137 !!eeprom->reg_data_clock);
138 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
139 !!eeprom->reg_chip_select);
140
141 rt2x00mmio_register_write(rt2x00dev, E2PROM_CSR, reg);
142 }
143
144 static int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
145 {
146 struct eeprom_93cx6 eeprom;
147 u32 reg;
148
149 rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, &reg);
150
151 eeprom.data = rt2x00dev;
152 eeprom.register_read = rt2800pci_eepromregister_read;
153 eeprom.register_write = rt2800pci_eepromregister_write;
154 switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
155 {
156 case 0:
157 eeprom.width = PCI_EEPROM_WIDTH_93C46;
158 break;
159 case 1:
160 eeprom.width = PCI_EEPROM_WIDTH_93C66;
161 break;
162 default:
163 eeprom.width = PCI_EEPROM_WIDTH_93C86;
164 break;
165 }
166 eeprom.reg_data_in = 0;
167 eeprom.reg_data_out = 0;
168 eeprom.reg_data_clock = 0;
169 eeprom.reg_chip_select = 0;
170
171 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
172 EEPROM_SIZE / sizeof(u16));
173
174 return 0;
175 }
176
177 static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
178 {
179 return rt2800_efuse_detect(rt2x00dev);
180 }
181
182 static inline int rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
183 {
184 return rt2800_read_eeprom_efuse(rt2x00dev);
185 }
186 #else
187 static inline int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
188 {
189 return -EOPNOTSUPP;
190 }
191
192 static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
193 {
194 return 0;
195 }
196
197 static inline int rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
198 {
199 return -EOPNOTSUPP;
200 }
201 #endif /* CONFIG_PCI */
202
203 /*
204 * Queue handlers.
205 */
206 static void rt2800pci_start_queue(struct data_queue *queue)
207 {
208 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
209 u32 reg;
210
211 switch (queue->qid) {
212 case QID_RX:
213 rt2x00mmio_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
214 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
215 rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
216 break;
217 case QID_BEACON:
218 rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
219 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
220 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
221 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
222 rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);
223
224 rt2x00mmio_register_read(rt2x00dev, INT_TIMER_EN, &reg);
225 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 1);
226 rt2x00mmio_register_write(rt2x00dev, INT_TIMER_EN, reg);
227 break;
228 default:
229 break;
230 }
231 }
232
233 static void rt2800pci_kick_queue(struct data_queue *queue)
234 {
235 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
236 struct queue_entry *entry;
237
238 switch (queue->qid) {
239 case QID_AC_VO:
240 case QID_AC_VI:
241 case QID_AC_BE:
242 case QID_AC_BK:
243 entry = rt2x00queue_get_entry(queue, Q_INDEX);
244 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX(queue->qid),
245 entry->entry_idx);
246 break;
247 case QID_MGMT:
248 entry = rt2x00queue_get_entry(queue, Q_INDEX);
249 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX(5),
250 entry->entry_idx);
251 break;
252 default:
253 break;
254 }
255 }
256
257 static void rt2800pci_stop_queue(struct data_queue *queue)
258 {
259 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
260 u32 reg;
261
262 switch (queue->qid) {
263 case QID_RX:
264 rt2x00mmio_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
265 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
266 rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
267 break;
268 case QID_BEACON:
269 rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
270 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
271 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
272 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
273 rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);
274
275 rt2x00mmio_register_read(rt2x00dev, INT_TIMER_EN, &reg);
276 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 0);
277 rt2x00mmio_register_write(rt2x00dev, INT_TIMER_EN, reg);
278
279 /*
280 * Wait for current invocation to finish. The tasklet
281 * won't be scheduled anymore afterwards since we disabled
282 * the TBTT and PRE TBTT timer.
283 */
284 tasklet_kill(&rt2x00dev->tbtt_tasklet);
285 tasklet_kill(&rt2x00dev->pretbtt_tasklet);
286
287 break;
288 default:
289 break;
290 }
291 }
292
293 /*
294 * Firmware functions
295 */
296 static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
297 {
298 /*
299 * Chip rt3290 use specific 4KB firmware named rt3290.bin.
300 */
301 if (rt2x00_rt(rt2x00dev, RT3290))
302 return FIRMWARE_RT3290;
303 else
304 return FIRMWARE_RT2860;
305 }
306
307 static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
308 const u8 *data, const size_t len)
309 {
310 u32 reg;
311
312 /*
313 * enable Host program ram write selection
314 */
315 reg = 0;
316 rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
317 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
318
319 /*
320 * Write firmware to device.
321 */
322 rt2x00mmio_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
323 data, len);
324
325 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
326 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
327
328 rt2x00mmio_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
329 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
330
331 return 0;
332 }
333
334 /*
335 * Initialization functions.
336 */
337 static bool rt2800pci_get_entry_state(struct queue_entry *entry)
338 {
339 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
340 u32 word;
341
342 if (entry->queue->qid == QID_RX) {
343 rt2x00_desc_read(entry_priv->desc, 1, &word);
344
345 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
346 } else {
347 rt2x00_desc_read(entry_priv->desc, 1, &word);
348
349 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
350 }
351 }
352
353 static void rt2800pci_clear_entry(struct queue_entry *entry)
354 {
355 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
356 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
357 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
358 u32 word;
359
360 if (entry->queue->qid == QID_RX) {
361 rt2x00_desc_read(entry_priv->desc, 0, &word);
362 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
363 rt2x00_desc_write(entry_priv->desc, 0, word);
364
365 rt2x00_desc_read(entry_priv->desc, 1, &word);
366 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
367 rt2x00_desc_write(entry_priv->desc, 1, word);
368
369 /*
370 * Set RX IDX in register to inform hardware that we have
371 * handled this entry and it is available for reuse again.
372 */
373 rt2x00mmio_register_write(rt2x00dev, RX_CRX_IDX,
374 entry->entry_idx);
375 } else {
376 rt2x00_desc_read(entry_priv->desc, 1, &word);
377 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
378 rt2x00_desc_write(entry_priv->desc, 1, word);
379 }
380 }
381
382 static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
383 {
384 struct queue_entry_priv_mmio *entry_priv;
385
386 /*
387 * Initialize registers.
388 */
389 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
390 rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR0,
391 entry_priv->desc_dma);
392 rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT0,
393 rt2x00dev->tx[0].limit);
394 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX0, 0);
395 rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX0, 0);
396
397 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
398 rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR1,
399 entry_priv->desc_dma);
400 rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT1,
401 rt2x00dev->tx[1].limit);
402 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX1, 0);
403 rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX1, 0);
404
405 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
406 rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR2,
407 entry_priv->desc_dma);
408 rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT2,
409 rt2x00dev->tx[2].limit);
410 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX2, 0);
411 rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX2, 0);
412
413 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
414 rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR3,
415 entry_priv->desc_dma);
416 rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT3,
417 rt2x00dev->tx[3].limit);
418 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX3, 0);
419 rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX3, 0);
420
421 rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR4, 0);
422 rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT4, 0);
423 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX4, 0);
424 rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX4, 0);
425
426 rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR5, 0);
427 rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT5, 0);
428 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX5, 0);
429 rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX5, 0);
430
431 entry_priv = rt2x00dev->rx->entries[0].priv_data;
432 rt2x00mmio_register_write(rt2x00dev, RX_BASE_PTR,
433 entry_priv->desc_dma);
434 rt2x00mmio_register_write(rt2x00dev, RX_MAX_CNT,
435 rt2x00dev->rx[0].limit);
436 rt2x00mmio_register_write(rt2x00dev, RX_CRX_IDX,
437 rt2x00dev->rx[0].limit - 1);
438 rt2x00mmio_register_write(rt2x00dev, RX_DRX_IDX, 0);
439
440 rt2800_disable_wpdma(rt2x00dev);
441
442 rt2x00mmio_register_write(rt2x00dev, DELAY_INT_CFG, 0);
443
444 return 0;
445 }
446
447 /*
448 * Device state switch handlers.
449 */
450 static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
451 enum dev_state state)
452 {
453 u32 reg;
454 unsigned long flags;
455
456 /*
457 * When interrupts are being enabled, the interrupt registers
458 * should clear the register to assure a clean state.
459 */
460 if (state == STATE_RADIO_IRQ_ON) {
461 rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
462 rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
463 }
464
465 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
466 reg = 0;
467 if (state == STATE_RADIO_IRQ_ON) {
468 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, 1);
469 rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, 1);
470 rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, 1);
471 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, 1);
472 rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, 1);
473 }
474 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
475 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
476
477 if (state == STATE_RADIO_IRQ_OFF) {
478 /*
479 * Wait for possibly running tasklets to finish.
480 */
481 tasklet_kill(&rt2x00dev->txstatus_tasklet);
482 tasklet_kill(&rt2x00dev->rxdone_tasklet);
483 tasklet_kill(&rt2x00dev->autowake_tasklet);
484 tasklet_kill(&rt2x00dev->tbtt_tasklet);
485 tasklet_kill(&rt2x00dev->pretbtt_tasklet);
486 }
487 }
488
489 static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
490 {
491 u32 reg;
492
493 /*
494 * Reset DMA indexes
495 */
496 rt2x00mmio_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
497 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
498 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
499 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
500 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
501 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
502 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
503 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
504 rt2x00mmio_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
505
506 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
507 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
508
509 if (rt2x00_is_pcie(rt2x00dev) &&
510 (rt2x00_rt(rt2x00dev, RT3572) ||
511 rt2x00_rt(rt2x00dev, RT5390) ||
512 rt2x00_rt(rt2x00dev, RT5392))) {
513 rt2x00mmio_register_read(rt2x00dev, AUX_CTRL, &reg);
514 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
515 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
516 rt2x00mmio_register_write(rt2x00dev, AUX_CTRL, reg);
517 }
518
519 rt2x00mmio_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
520
521 reg = 0;
522 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
523 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
524 rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
525
526 rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
527
528 return 0;
529 }
530
531 static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
532 {
533 int retval;
534
535 /* Wait for DMA, ignore error until we initialize queues. */
536 rt2800_wait_wpdma_ready(rt2x00dev);
537
538 if (unlikely(rt2800pci_init_queues(rt2x00dev)))
539 return -EIO;
540
541 retval = rt2800_enable_radio(rt2x00dev);
542 if (retval)
543 return retval;
544
545 /* After resume MCU_BOOT_SIGNAL will trash these. */
546 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
547 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
548
549 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_RADIO_OFF, 0xff, 0x02);
550 rt2800pci_mcu_status(rt2x00dev, TOKEN_RADIO_OFF);
551
552 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP, 0, 0);
553 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
554
555 return retval;
556 }
557
558 static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
559 {
560 if (rt2x00_is_soc(rt2x00dev)) {
561 rt2800_disable_radio(rt2x00dev);
562 rt2x00mmio_register_write(rt2x00dev, PWR_PIN_CFG, 0);
563 rt2x00mmio_register_write(rt2x00dev, TX_PIN_CFG, 0);
564 }
565 }
566
567 static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
568 enum dev_state state)
569 {
570 if (state == STATE_AWAKE) {
571 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP,
572 0, 0x02);
573 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
574 } else if (state == STATE_SLEEP) {
575 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS,
576 0xffffffff);
577 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID,
578 0xffffffff);
579 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_SLEEP,
580 0xff, 0x01);
581 }
582
583 return 0;
584 }
585
586 static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
587 enum dev_state state)
588 {
589 int retval = 0;
590
591 switch (state) {
592 case STATE_RADIO_ON:
593 retval = rt2800pci_enable_radio(rt2x00dev);
594 break;
595 case STATE_RADIO_OFF:
596 /*
597 * After the radio has been disabled, the device should
598 * be put to sleep for powersaving.
599 */
600 rt2800pci_disable_radio(rt2x00dev);
601 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
602 break;
603 case STATE_RADIO_IRQ_ON:
604 case STATE_RADIO_IRQ_OFF:
605 rt2800pci_toggle_irq(rt2x00dev, state);
606 break;
607 case STATE_DEEP_SLEEP:
608 case STATE_SLEEP:
609 case STATE_STANDBY:
610 case STATE_AWAKE:
611 retval = rt2800pci_set_state(rt2x00dev, state);
612 break;
613 default:
614 retval = -ENOTSUPP;
615 break;
616 }
617
618 if (unlikely(retval))
619 rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
620 state, retval);
621
622 return retval;
623 }
624
625 /*
626 * TX descriptor initialization
627 */
628 static __le32 *rt2800pci_get_txwi(struct queue_entry *entry)
629 {
630 return (__le32 *) entry->skb->data;
631 }
632
633 static void rt2800pci_write_tx_desc(struct queue_entry *entry,
634 struct txentry_desc *txdesc)
635 {
636 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
637 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
638 __le32 *txd = entry_priv->desc;
639 u32 word;
640 const unsigned int txwi_size = entry->queue->winfo_size;
641
642 /*
643 * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
644 * must contains a TXWI structure + 802.11 header + padding + 802.11
645 * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
646 * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
647 * data. It means that LAST_SEC0 is always 0.
648 */
649
650 /*
651 * Initialize TX descriptor
652 */
653 word = 0;
654 rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
655 rt2x00_desc_write(txd, 0, word);
656
657 word = 0;
658 rt2x00_set_field32(&word, TXD_W1_SD_LEN1, entry->skb->len);
659 rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
660 !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
661 rt2x00_set_field32(&word, TXD_W1_BURST,
662 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
663 rt2x00_set_field32(&word, TXD_W1_SD_LEN0, txwi_size);
664 rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
665 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
666 rt2x00_desc_write(txd, 1, word);
667
668 word = 0;
669 rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
670 skbdesc->skb_dma + txwi_size);
671 rt2x00_desc_write(txd, 2, word);
672
673 word = 0;
674 rt2x00_set_field32(&word, TXD_W3_WIV,
675 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
676 rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
677 rt2x00_desc_write(txd, 3, word);
678
679 /*
680 * Register descriptor details in skb frame descriptor.
681 */
682 skbdesc->desc = txd;
683 skbdesc->desc_len = TXD_DESC_SIZE;
684 }
685
686 /*
687 * RX control handlers
688 */
689 static void rt2800pci_fill_rxdone(struct queue_entry *entry,
690 struct rxdone_entry_desc *rxdesc)
691 {
692 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
693 __le32 *rxd = entry_priv->desc;
694 u32 word;
695
696 rt2x00_desc_read(rxd, 3, &word);
697
698 if (rt2x00_get_field32(word, RXD_W3_CRC_ERROR))
699 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
700
701 /*
702 * Unfortunately we don't know the cipher type used during
703 * decryption. This prevents us from correct providing
704 * correct statistics through debugfs.
705 */
706 rxdesc->cipher_status = rt2x00_get_field32(word, RXD_W3_CIPHER_ERROR);
707
708 if (rt2x00_get_field32(word, RXD_W3_DECRYPTED)) {
709 /*
710 * Hardware has stripped IV/EIV data from 802.11 frame during
711 * decryption. Unfortunately the descriptor doesn't contain
712 * any fields with the EIV/IV data either, so they can't
713 * be restored by rt2x00lib.
714 */
715 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
716
717 /*
718 * The hardware has already checked the Michael Mic and has
719 * stripped it from the frame. Signal this to mac80211.
720 */
721 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
722
723 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
724 rxdesc->flags |= RX_FLAG_DECRYPTED;
725 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
726 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
727 }
728
729 if (rt2x00_get_field32(word, RXD_W3_MY_BSS))
730 rxdesc->dev_flags |= RXDONE_MY_BSS;
731
732 if (rt2x00_get_field32(word, RXD_W3_L2PAD))
733 rxdesc->dev_flags |= RXDONE_L2PAD;
734
735 /*
736 * Process the RXWI structure that is at the start of the buffer.
737 */
738 rt2800_process_rxwi(entry, rxdesc);
739 }
740
741 /*
742 * Interrupt functions.
743 */
744 static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
745 {
746 struct ieee80211_conf conf = { .flags = 0 };
747 struct rt2x00lib_conf libconf = { .conf = &conf };
748
749 rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
750 }
751
752 static bool rt2800pci_txdone_entry_check(struct queue_entry *entry, u32 status)
753 {
754 __le32 *txwi;
755 u32 word;
756 int wcid, tx_wcid;
757
758 wcid = rt2x00_get_field32(status, TX_STA_FIFO_WCID);
759
760 txwi = rt2800_drv_get_txwi(entry);
761 rt2x00_desc_read(txwi, 1, &word);
762 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
763
764 return (tx_wcid == wcid);
765 }
766
767 static bool rt2800pci_txdone_find_entry(struct queue_entry *entry, void *data)
768 {
769 u32 status = *(u32 *)data;
770
771 /*
772 * rt2800pci hardware might reorder frames when exchanging traffic
773 * with multiple BA enabled STAs.
774 *
775 * For example, a tx queue
776 * [ STA1 | STA2 | STA1 | STA2 ]
777 * can result in tx status reports
778 * [ STA1 | STA1 | STA2 | STA2 ]
779 * when the hw decides to aggregate the frames for STA1 into one AMPDU.
780 *
781 * To mitigate this effect, associate the tx status to the first frame
782 * in the tx queue with a matching wcid.
783 */
784 if (rt2800pci_txdone_entry_check(entry, status) &&
785 !test_bit(ENTRY_DATA_STATUS_SET, &entry->flags)) {
786 /*
787 * Got a matching frame, associate the tx status with
788 * the frame
789 */
790 entry->status = status;
791 set_bit(ENTRY_DATA_STATUS_SET, &entry->flags);
792 return true;
793 }
794
795 /* Check the next frame */
796 return false;
797 }
798
799 static bool rt2800pci_txdone_match_first(struct queue_entry *entry, void *data)
800 {
801 u32 status = *(u32 *)data;
802
803 /*
804 * Find the first frame without tx status and assign this status to it
805 * regardless if it matches or not.
806 */
807 if (!test_bit(ENTRY_DATA_STATUS_SET, &entry->flags)) {
808 /*
809 * Got a matching frame, associate the tx status with
810 * the frame
811 */
812 entry->status = status;
813 set_bit(ENTRY_DATA_STATUS_SET, &entry->flags);
814 return true;
815 }
816
817 /* Check the next frame */
818 return false;
819 }
820 static bool rt2800pci_txdone_release_entries(struct queue_entry *entry,
821 void *data)
822 {
823 if (test_bit(ENTRY_DATA_STATUS_SET, &entry->flags)) {
824 rt2800_txdone_entry(entry, entry->status,
825 rt2800pci_get_txwi(entry));
826 return false;
827 }
828
829 /* No more frames to release */
830 return true;
831 }
832
833 static bool rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
834 {
835 struct data_queue *queue;
836 u32 status;
837 u8 qid;
838 int max_tx_done = 16;
839
840 while (kfifo_get(&rt2x00dev->txstatus_fifo, &status)) {
841 qid = rt2x00_get_field32(status, TX_STA_FIFO_PID_QUEUE);
842 if (unlikely(qid >= QID_RX)) {
843 /*
844 * Unknown queue, this shouldn't happen. Just drop
845 * this tx status.
846 */
847 rt2x00_warn(rt2x00dev, "Got TX status report with unexpected pid %u, dropping\n",
848 qid);
849 break;
850 }
851
852 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
853 if (unlikely(queue == NULL)) {
854 /*
855 * The queue is NULL, this shouldn't happen. Stop
856 * processing here and drop the tx status
857 */
858 rt2x00_warn(rt2x00dev, "Got TX status for an unavailable queue %u, dropping\n",
859 qid);
860 break;
861 }
862
863 if (unlikely(rt2x00queue_empty(queue))) {
864 /*
865 * The queue is empty. Stop processing here
866 * and drop the tx status.
867 */
868 rt2x00_warn(rt2x00dev, "Got TX status for an empty queue %u, dropping\n",
869 qid);
870 break;
871 }
872
873 /*
874 * Let's associate this tx status with the first
875 * matching frame.
876 */
877 if (!rt2x00queue_for_each_entry(queue, Q_INDEX_DONE,
878 Q_INDEX, &status,
879 rt2800pci_txdone_find_entry)) {
880 /*
881 * We cannot match the tx status to any frame, so just
882 * use the first one.
883 */
884 if (!rt2x00queue_for_each_entry(queue, Q_INDEX_DONE,
885 Q_INDEX, &status,
886 rt2800pci_txdone_match_first)) {
887 rt2x00_warn(rt2x00dev, "No frame found for TX status on queue %u, dropping\n",
888 qid);
889 break;
890 }
891 }
892
893 /*
894 * Release all frames with a valid tx status.
895 */
896 rt2x00queue_for_each_entry(queue, Q_INDEX_DONE,
897 Q_INDEX, NULL,
898 rt2800pci_txdone_release_entries);
899
900 if (--max_tx_done == 0)
901 break;
902 }
903
904 return !max_tx_done;
905 }
906
907 static inline void rt2800pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
908 struct rt2x00_field32 irq_field)
909 {
910 u32 reg;
911
912 /*
913 * Enable a single interrupt. The interrupt mask register
914 * access needs locking.
915 */
916 spin_lock_irq(&rt2x00dev->irqmask_lock);
917 rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, &reg);
918 rt2x00_set_field32(&reg, irq_field, 1);
919 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
920 spin_unlock_irq(&rt2x00dev->irqmask_lock);
921 }
922
923 static void rt2800pci_txstatus_tasklet(unsigned long data)
924 {
925 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
926 if (rt2800pci_txdone(rt2x00dev))
927 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
928
929 /*
930 * No need to enable the tx status interrupt here as we always
931 * leave it enabled to minimize the possibility of a tx status
932 * register overflow. See comment in interrupt handler.
933 */
934 }
935
936 static void rt2800pci_pretbtt_tasklet(unsigned long data)
937 {
938 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
939 rt2x00lib_pretbtt(rt2x00dev);
940 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
941 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_PRE_TBTT);
942 }
943
944 static void rt2800pci_tbtt_tasklet(unsigned long data)
945 {
946 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
947 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
948 u32 reg;
949
950 rt2x00lib_beacondone(rt2x00dev);
951
952 if (rt2x00dev->intf_ap_count) {
953 /*
954 * The rt2800pci hardware tbtt timer is off by 1us per tbtt
955 * causing beacon skew and as a result causing problems with
956 * some powersaving clients over time. Shorten the beacon
957 * interval every 64 beacons by 64us to mitigate this effect.
958 */
959 if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 2)) {
960 rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
961 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
962 (rt2x00dev->beacon_int * 16) - 1);
963 rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);
964 } else if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 1)) {
965 rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
966 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
967 (rt2x00dev->beacon_int * 16));
968 rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);
969 }
970 drv_data->tbtt_tick++;
971 drv_data->tbtt_tick %= BCN_TBTT_OFFSET;
972 }
973
974 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
975 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_TBTT);
976 }
977
978 static void rt2800pci_rxdone_tasklet(unsigned long data)
979 {
980 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
981 if (rt2x00mmio_rxdone(rt2x00dev))
982 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
983 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
984 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RX_DONE);
985 }
986
987 static void rt2800pci_autowake_tasklet(unsigned long data)
988 {
989 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
990 rt2800pci_wakeup(rt2x00dev);
991 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
992 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_AUTO_WAKEUP);
993 }
994
995 static void rt2800pci_txstatus_interrupt(struct rt2x00_dev *rt2x00dev)
996 {
997 u32 status;
998 int i;
999
1000 /*
1001 * The TX_FIFO_STATUS interrupt needs special care. We should
1002 * read TX_STA_FIFO but we should do it immediately as otherwise
1003 * the register can overflow and we would lose status reports.
1004 *
1005 * Hence, read the TX_STA_FIFO register and copy all tx status
1006 * reports into a kernel FIFO which is handled in the txstatus
1007 * tasklet. We use a tasklet to process the tx status reports
1008 * because we can schedule the tasklet multiple times (when the
1009 * interrupt fires again during tx status processing).
1010 *
1011 * Furthermore we don't disable the TX_FIFO_STATUS
1012 * interrupt here but leave it enabled so that the TX_STA_FIFO
1013 * can also be read while the tx status tasklet gets executed.
1014 *
1015 * Since we have only one producer and one consumer we don't
1016 * need to lock the kfifo.
1017 */
1018 for (i = 0; i < rt2x00dev->tx->limit; i++) {
1019 rt2x00mmio_register_read(rt2x00dev, TX_STA_FIFO, &status);
1020
1021 if (!rt2x00_get_field32(status, TX_STA_FIFO_VALID))
1022 break;
1023
1024 if (!kfifo_put(&rt2x00dev->txstatus_fifo, &status)) {
1025 rt2x00_warn(rt2x00dev, "TX status FIFO overrun, drop tx status report\n");
1026 break;
1027 }
1028 }
1029
1030 /* Schedule the tasklet for processing the tx status. */
1031 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
1032 }
1033
1034 static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
1035 {
1036 struct rt2x00_dev *rt2x00dev = dev_instance;
1037 u32 reg, mask;
1038
1039 /* Read status and ACK all interrupts */
1040 rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1041 rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1042
1043 if (!reg)
1044 return IRQ_NONE;
1045
1046 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1047 return IRQ_HANDLED;
1048
1049 /*
1050 * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
1051 * for interrupts and interrupt masks we can just use the value of
1052 * INT_SOURCE_CSR to create the interrupt mask.
1053 */
1054 mask = ~reg;
1055
1056 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS)) {
1057 rt2800pci_txstatus_interrupt(rt2x00dev);
1058 /*
1059 * Never disable the TX_FIFO_STATUS interrupt.
1060 */
1061 rt2x00_set_field32(&mask, INT_MASK_CSR_TX_FIFO_STATUS, 1);
1062 }
1063
1064 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT))
1065 tasklet_hi_schedule(&rt2x00dev->pretbtt_tasklet);
1066
1067 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
1068 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
1069
1070 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
1071 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1072
1073 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
1074 tasklet_schedule(&rt2x00dev->autowake_tasklet);
1075
1076 /*
1077 * Disable all interrupts for which a tasklet was scheduled right now,
1078 * the tasklet will reenable the appropriate interrupts.
1079 */
1080 spin_lock(&rt2x00dev->irqmask_lock);
1081 rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1082 reg &= mask;
1083 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
1084 spin_unlock(&rt2x00dev->irqmask_lock);
1085
1086 return IRQ_HANDLED;
1087 }
1088
1089 /*
1090 * Device probe functions.
1091 */
1092 static int rt2800pci_read_eeprom(struct rt2x00_dev *rt2x00dev)
1093 {
1094 int retval;
1095
1096 if (rt2x00_is_soc(rt2x00dev))
1097 retval = rt2800pci_read_eeprom_soc(rt2x00dev);
1098 else if (rt2800pci_efuse_detect(rt2x00dev))
1099 retval = rt2800pci_read_eeprom_efuse(rt2x00dev);
1100 else
1101 retval = rt2800pci_read_eeprom_pci(rt2x00dev);
1102
1103 return retval;
1104 }
1105
1106 static const struct ieee80211_ops rt2800pci_mac80211_ops = {
1107 .tx = rt2x00mac_tx,
1108 .start = rt2x00mac_start,
1109 .stop = rt2x00mac_stop,
1110 .add_interface = rt2x00mac_add_interface,
1111 .remove_interface = rt2x00mac_remove_interface,
1112 .config = rt2x00mac_config,
1113 .configure_filter = rt2x00mac_configure_filter,
1114 .set_key = rt2x00mac_set_key,
1115 .sw_scan_start = rt2x00mac_sw_scan_start,
1116 .sw_scan_complete = rt2x00mac_sw_scan_complete,
1117 .get_stats = rt2x00mac_get_stats,
1118 .get_tkip_seq = rt2800_get_tkip_seq,
1119 .set_rts_threshold = rt2800_set_rts_threshold,
1120 .sta_add = rt2x00mac_sta_add,
1121 .sta_remove = rt2x00mac_sta_remove,
1122 .bss_info_changed = rt2x00mac_bss_info_changed,
1123 .conf_tx = rt2800_conf_tx,
1124 .get_tsf = rt2800_get_tsf,
1125 .rfkill_poll = rt2x00mac_rfkill_poll,
1126 .ampdu_action = rt2800_ampdu_action,
1127 .flush = rt2x00mac_flush,
1128 .get_survey = rt2800_get_survey,
1129 .get_ringparam = rt2x00mac_get_ringparam,
1130 .tx_frames_pending = rt2x00mac_tx_frames_pending,
1131 };
1132
1133 static const struct rt2800_ops rt2800pci_rt2800_ops = {
1134 .register_read = rt2x00mmio_register_read,
1135 .register_read_lock = rt2x00mmio_register_read, /* same for PCI */
1136 .register_write = rt2x00mmio_register_write,
1137 .register_write_lock = rt2x00mmio_register_write, /* same for PCI */
1138 .register_multiread = rt2x00mmio_register_multiread,
1139 .register_multiwrite = rt2x00mmio_register_multiwrite,
1140 .regbusy_read = rt2x00mmio_regbusy_read,
1141 .read_eeprom = rt2800pci_read_eeprom,
1142 .hwcrypt_disabled = rt2800pci_hwcrypt_disabled,
1143 .drv_write_firmware = rt2800pci_write_firmware,
1144 .drv_init_registers = rt2800pci_init_registers,
1145 .drv_get_txwi = rt2800pci_get_txwi,
1146 };
1147
1148 static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1149 .irq_handler = rt2800pci_interrupt,
1150 .txstatus_tasklet = rt2800pci_txstatus_tasklet,
1151 .pretbtt_tasklet = rt2800pci_pretbtt_tasklet,
1152 .tbtt_tasklet = rt2800pci_tbtt_tasklet,
1153 .rxdone_tasklet = rt2800pci_rxdone_tasklet,
1154 .autowake_tasklet = rt2800pci_autowake_tasklet,
1155 .probe_hw = rt2800_probe_hw,
1156 .get_firmware_name = rt2800pci_get_firmware_name,
1157 .check_firmware = rt2800_check_firmware,
1158 .load_firmware = rt2800_load_firmware,
1159 .initialize = rt2x00mmio_initialize,
1160 .uninitialize = rt2x00mmio_uninitialize,
1161 .get_entry_state = rt2800pci_get_entry_state,
1162 .clear_entry = rt2800pci_clear_entry,
1163 .set_device_state = rt2800pci_set_device_state,
1164 .rfkill_poll = rt2800_rfkill_poll,
1165 .link_stats = rt2800_link_stats,
1166 .reset_tuner = rt2800_reset_tuner,
1167 .link_tuner = rt2800_link_tuner,
1168 .gain_calibration = rt2800_gain_calibration,
1169 .vco_calibration = rt2800_vco_calibration,
1170 .start_queue = rt2800pci_start_queue,
1171 .kick_queue = rt2800pci_kick_queue,
1172 .stop_queue = rt2800pci_stop_queue,
1173 .flush_queue = rt2x00mmio_flush_queue,
1174 .write_tx_desc = rt2800pci_write_tx_desc,
1175 .write_tx_data = rt2800_write_tx_data,
1176 .write_beacon = rt2800_write_beacon,
1177 .clear_beacon = rt2800_clear_beacon,
1178 .fill_rxdone = rt2800pci_fill_rxdone,
1179 .config_shared_key = rt2800_config_shared_key,
1180 .config_pairwise_key = rt2800_config_pairwise_key,
1181 .config_filter = rt2800_config_filter,
1182 .config_intf = rt2800_config_intf,
1183 .config_erp = rt2800_config_erp,
1184 .config_ant = rt2800_config_ant,
1185 .config = rt2800_config,
1186 .sta_add = rt2800_sta_add,
1187 .sta_remove = rt2800_sta_remove,
1188 };
1189
1190 static void rt2800pci_queue_init(struct data_queue *queue)
1191 {
1192 switch (queue->qid) {
1193 case QID_RX:
1194 queue->limit = 128;
1195 queue->data_size = AGGREGATION_SIZE;
1196 queue->desc_size = RXD_DESC_SIZE;
1197 queue->winfo_size = RXWI_DESC_SIZE_4WORDS;
1198 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
1199 break;
1200
1201 case QID_AC_VO:
1202 case QID_AC_VI:
1203 case QID_AC_BE:
1204 case QID_AC_BK:
1205 queue->limit = 64;
1206 queue->data_size = AGGREGATION_SIZE;
1207 queue->desc_size = TXD_DESC_SIZE;
1208 queue->winfo_size = TXWI_DESC_SIZE_4WORDS;
1209 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
1210 break;
1211
1212 case QID_BEACON:
1213 queue->limit = 8;
1214 queue->data_size = 0; /* No DMA required for beacons */
1215 queue->desc_size = TXD_DESC_SIZE;
1216 queue->winfo_size = TXWI_DESC_SIZE_4WORDS;
1217 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
1218 break;
1219
1220 case QID_ATIM:
1221 /* fallthrough */
1222 default:
1223 BUG();
1224 break;
1225 }
1226 }
1227
1228 static const struct rt2x00_ops rt2800pci_ops = {
1229 .name = KBUILD_MODNAME,
1230 .drv_data_size = sizeof(struct rt2800_drv_data),
1231 .max_ap_intf = 8,
1232 .eeprom_size = EEPROM_SIZE,
1233 .rf_size = RF_SIZE,
1234 .tx_queues = NUM_TX_QUEUES,
1235 .queue_init = rt2800pci_queue_init,
1236 .lib = &rt2800pci_rt2x00_ops,
1237 .drv = &rt2800pci_rt2800_ops,
1238 .hw = &rt2800pci_mac80211_ops,
1239 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1240 .debugfs = &rt2800_rt2x00debug,
1241 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1242 };
1243
1244 /*
1245 * RT2800pci module information.
1246 */
1247 #ifdef CONFIG_PCI
1248 static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
1249 { PCI_DEVICE(0x1814, 0x0601) },
1250 { PCI_DEVICE(0x1814, 0x0681) },
1251 { PCI_DEVICE(0x1814, 0x0701) },
1252 { PCI_DEVICE(0x1814, 0x0781) },
1253 { PCI_DEVICE(0x1814, 0x3090) },
1254 { PCI_DEVICE(0x1814, 0x3091) },
1255 { PCI_DEVICE(0x1814, 0x3092) },
1256 { PCI_DEVICE(0x1432, 0x7708) },
1257 { PCI_DEVICE(0x1432, 0x7727) },
1258 { PCI_DEVICE(0x1432, 0x7728) },
1259 { PCI_DEVICE(0x1432, 0x7738) },
1260 { PCI_DEVICE(0x1432, 0x7748) },
1261 { PCI_DEVICE(0x1432, 0x7758) },
1262 { PCI_DEVICE(0x1432, 0x7768) },
1263 { PCI_DEVICE(0x1462, 0x891a) },
1264 { PCI_DEVICE(0x1a3b, 0x1059) },
1265 #ifdef CONFIG_RT2800PCI_RT3290
1266 { PCI_DEVICE(0x1814, 0x3290) },
1267 #endif
1268 #ifdef CONFIG_RT2800PCI_RT33XX
1269 { PCI_DEVICE(0x1814, 0x3390) },
1270 #endif
1271 #ifdef CONFIG_RT2800PCI_RT35XX
1272 { PCI_DEVICE(0x1432, 0x7711) },
1273 { PCI_DEVICE(0x1432, 0x7722) },
1274 { PCI_DEVICE(0x1814, 0x3060) },
1275 { PCI_DEVICE(0x1814, 0x3062) },
1276 { PCI_DEVICE(0x1814, 0x3562) },
1277 { PCI_DEVICE(0x1814, 0x3592) },
1278 { PCI_DEVICE(0x1814, 0x3593) },
1279 { PCI_DEVICE(0x1814, 0x359f) },
1280 #endif
1281 #ifdef CONFIG_RT2800PCI_RT53XX
1282 { PCI_DEVICE(0x1814, 0x5360) },
1283 { PCI_DEVICE(0x1814, 0x5362) },
1284 { PCI_DEVICE(0x1814, 0x5390) },
1285 { PCI_DEVICE(0x1814, 0x5392) },
1286 { PCI_DEVICE(0x1814, 0x539a) },
1287 { PCI_DEVICE(0x1814, 0x539b) },
1288 { PCI_DEVICE(0x1814, 0x539f) },
1289 #endif
1290 { 0, }
1291 };
1292 #endif /* CONFIG_PCI */
1293
1294 MODULE_AUTHOR(DRV_PROJECT);
1295 MODULE_VERSION(DRV_VERSION);
1296 MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1297 MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1298 #ifdef CONFIG_PCI
1299 MODULE_FIRMWARE(FIRMWARE_RT2860);
1300 MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
1301 #endif /* CONFIG_PCI */
1302 MODULE_LICENSE("GPL");
1303
1304 #if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
1305 static int rt2800soc_probe(struct platform_device *pdev)
1306 {
1307 return rt2x00soc_probe(pdev, &rt2800pci_ops);
1308 }
1309
1310 static struct platform_driver rt2800soc_driver = {
1311 .driver = {
1312 .name = "rt2800_wmac",
1313 .owner = THIS_MODULE,
1314 .mod_name = KBUILD_MODNAME,
1315 },
1316 .probe = rt2800soc_probe,
1317 .remove = rt2x00soc_remove,
1318 .suspend = rt2x00soc_suspend,
1319 .resume = rt2x00soc_resume,
1320 };
1321 #endif /* CONFIG_SOC_RT288X || CONFIG_SOC_RT305X */
1322
1323 #ifdef CONFIG_PCI
1324 static int rt2800pci_probe(struct pci_dev *pci_dev,
1325 const struct pci_device_id *id)
1326 {
1327 return rt2x00pci_probe(pci_dev, &rt2800pci_ops);
1328 }
1329
1330 static struct pci_driver rt2800pci_driver = {
1331 .name = KBUILD_MODNAME,
1332 .id_table = rt2800pci_device_table,
1333 .probe = rt2800pci_probe,
1334 .remove = rt2x00pci_remove,
1335 .suspend = rt2x00pci_suspend,
1336 .resume = rt2x00pci_resume,
1337 };
1338 #endif /* CONFIG_PCI */
1339
1340 static int __init rt2800pci_init(void)
1341 {
1342 int ret = 0;
1343
1344 #if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
1345 ret = platform_driver_register(&rt2800soc_driver);
1346 if (ret)
1347 return ret;
1348 #endif
1349 #ifdef CONFIG_PCI
1350 ret = pci_register_driver(&rt2800pci_driver);
1351 if (ret) {
1352 #if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
1353 platform_driver_unregister(&rt2800soc_driver);
1354 #endif
1355 return ret;
1356 }
1357 #endif
1358
1359 return ret;
1360 }
1361
1362 static void __exit rt2800pci_exit(void)
1363 {
1364 #ifdef CONFIG_PCI
1365 pci_unregister_driver(&rt2800pci_driver);
1366 #endif
1367 #if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
1368 platform_driver_unregister(&rt2800soc_driver);
1369 #endif
1370 }
1371
1372 module_init(rt2800pci_init);
1373 module_exit(rt2800pci_exit);
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