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Linux 3.11-rc3
[cris-mirror.git] / drivers / pinctrl / sh-pfc / pfc-sh7372.c
blob6dfb18772574bba8d7c1da9bc4f5c8ecf950b72e
1 /*
2 * sh7372 processor support - PFC hardware block
3 *
4 * Copyright (C) 2010 Kuninori Morimoto <morimoto.kuninori@renesas.com>
5 *
6 * Based on
7 * sh7367 processor support - PFC hardware block
8 * Copyright (C) 2010 Magnus Damm
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23 #include <linux/io.h>
24 #include <linux/kernel.h>
25 #include <linux/pinctrl/pinconf-generic.h>
26
27 #include <mach/irqs.h>
28 #include <mach/sh7372.h>
29
30 #include "core.h"
31 #include "sh_pfc.h"
32
33 #define CPU_ALL_PORT(fn, pfx, sfx) \
34 PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \
35 PORT_10(fn, pfx##10, sfx), PORT_10(fn, pfx##11, sfx), \
36 PORT_10(fn, pfx##12, sfx), PORT_10(fn, pfx##13, sfx), \
37 PORT_10(fn, pfx##14, sfx), PORT_10(fn, pfx##15, sfx), \
38 PORT_10(fn, pfx##16, sfx), PORT_10(fn, pfx##17, sfx), \
39 PORT_10(fn, pfx##18, sfx), PORT_1(fn, pfx##190, sfx)
40
41 #undef _GPIO_PORT
42 #define _GPIO_PORT(gpio, sfx) \
43 [gpio] = { \
44 .name = __stringify(PORT##gpio), \
45 .enum_id = PORT##gpio##_DATA, \
46 }
47
48 #define IRQC_PIN_MUX(irq, pin) \
49 static const unsigned int intc_irq##irq##_pins[] = { \
50 pin, \
51 }; \
52 static const unsigned int intc_irq##irq##_mux[] = { \
53 IRQ##irq##_MARK, \
54 }
55
56 #define IRQC_PINS_MUX(irq, pin0, pin1) \
57 static const unsigned int intc_irq##irq##_0_pins[] = { \
58 pin0, \
59 }; \
60 static const unsigned int intc_irq##irq##_0_mux[] = { \
61 IRQ##irq##_##pin0##_MARK, \
62 }; \
63 static const unsigned int intc_irq##irq##_1_pins[] = { \
64 pin1, \
65 }; \
66 static const unsigned int intc_irq##irq##_1_mux[] = { \
67 IRQ##irq##_##pin1##_MARK, \
68 }
69
70 enum {
71 PINMUX_RESERVED = 0,
72
73 /* PORT0_DATA -> PORT190_DATA */
74 PINMUX_DATA_BEGIN,
75 PORT_ALL(DATA),
76 PINMUX_DATA_END,
77
78 /* PORT0_IN -> PORT190_IN */
79 PINMUX_INPUT_BEGIN,
80 PORT_ALL(IN),
81 PINMUX_INPUT_END,
82
83 /* PORT0_OUT -> PORT190_OUT */
84 PINMUX_OUTPUT_BEGIN,
85 PORT_ALL(OUT),
86 PINMUX_OUTPUT_END,
87
88 PINMUX_FUNCTION_BEGIN,
89 PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT190_FN_IN */
90 PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT190_FN_OUT */
91 PORT_ALL(FN0), /* PORT0_FN0 -> PORT190_FN0 */
92 PORT_ALL(FN1), /* PORT0_FN1 -> PORT190_FN1 */
93 PORT_ALL(FN2), /* PORT0_FN2 -> PORT190_FN2 */
94 PORT_ALL(FN3), /* PORT0_FN3 -> PORT190_FN3 */
95 PORT_ALL(FN4), /* PORT0_FN4 -> PORT190_FN4 */
96 PORT_ALL(FN5), /* PORT0_FN5 -> PORT190_FN5 */
97 PORT_ALL(FN6), /* PORT0_FN6 -> PORT190_FN6 */
98 PORT_ALL(FN7), /* PORT0_FN7 -> PORT190_FN7 */
99
100 MSEL1CR_31_0, MSEL1CR_31_1,
101 MSEL1CR_30_0, MSEL1CR_30_1,
102 MSEL1CR_29_0, MSEL1CR_29_1,
103 MSEL1CR_28_0, MSEL1CR_28_1,
104 MSEL1CR_27_0, MSEL1CR_27_1,
105 MSEL1CR_26_0, MSEL1CR_26_1,
106 MSEL1CR_16_0, MSEL1CR_16_1,
107 MSEL1CR_15_0, MSEL1CR_15_1,
108 MSEL1CR_14_0, MSEL1CR_14_1,
109 MSEL1CR_13_0, MSEL1CR_13_1,
110 MSEL1CR_12_0, MSEL1CR_12_1,
111 MSEL1CR_9_0, MSEL1CR_9_1,
112 MSEL1CR_8_0, MSEL1CR_8_1,
113 MSEL1CR_7_0, MSEL1CR_7_1,
114 MSEL1CR_6_0, MSEL1CR_6_1,
115 MSEL1CR_4_0, MSEL1CR_4_1,
116 MSEL1CR_3_0, MSEL1CR_3_1,
117 MSEL1CR_2_0, MSEL1CR_2_1,
118 MSEL1CR_0_0, MSEL1CR_0_1,
119
120 MSEL3CR_27_0, MSEL3CR_27_1,
121 MSEL3CR_26_0, MSEL3CR_26_1,
122 MSEL3CR_21_0, MSEL3CR_21_1,
123 MSEL3CR_20_0, MSEL3CR_20_1,
124 MSEL3CR_15_0, MSEL3CR_15_1,
125 MSEL3CR_9_0, MSEL3CR_9_1,
126 MSEL3CR_6_0, MSEL3CR_6_1,
127
128 MSEL4CR_19_0, MSEL4CR_19_1,
129 MSEL4CR_18_0, MSEL4CR_18_1,
130 MSEL4CR_17_0, MSEL4CR_17_1,
131 MSEL4CR_16_0, MSEL4CR_16_1,
132 MSEL4CR_15_0, MSEL4CR_15_1,
133 MSEL4CR_14_0, MSEL4CR_14_1,
134 MSEL4CR_10_0, MSEL4CR_10_1,
135 MSEL4CR_6_0, MSEL4CR_6_1,
136 MSEL4CR_4_0, MSEL4CR_4_1,
137 MSEL4CR_1_0, MSEL4CR_1_1,
138 PINMUX_FUNCTION_END,
139
140 PINMUX_MARK_BEGIN,
141
142 /* IRQ */
143 IRQ0_6_MARK, IRQ0_162_MARK, IRQ1_MARK, IRQ2_4_MARK,
144 IRQ2_5_MARK, IRQ3_8_MARK, IRQ3_16_MARK, IRQ4_17_MARK,
145 IRQ4_163_MARK, IRQ5_MARK, IRQ6_39_MARK, IRQ6_164_MARK,
146 IRQ7_40_MARK, IRQ7_167_MARK, IRQ8_41_MARK, IRQ8_168_MARK,
147 IRQ9_42_MARK, IRQ9_169_MARK, IRQ10_MARK, IRQ11_MARK,
148 IRQ12_80_MARK, IRQ12_137_MARK, IRQ13_81_MARK, IRQ13_145_MARK,
149 IRQ14_82_MARK, IRQ14_146_MARK, IRQ15_83_MARK, IRQ15_147_MARK,
150 IRQ16_84_MARK, IRQ16_170_MARK, IRQ17_MARK, IRQ18_MARK,
151 IRQ19_MARK, IRQ20_MARK, IRQ21_MARK, IRQ22_MARK,
152 IRQ23_MARK, IRQ24_MARK, IRQ25_MARK, IRQ26_121_MARK,
153 IRQ26_172_MARK, IRQ27_122_MARK, IRQ27_180_MARK, IRQ28_123_MARK,
154 IRQ28_181_MARK, IRQ29_129_MARK, IRQ29_182_MARK, IRQ30_130_MARK,
155 IRQ30_183_MARK, IRQ31_138_MARK, IRQ31_184_MARK,
156
157 /* MSIOF0 */
158 MSIOF0_TSYNC_MARK, MSIOF0_TSCK_MARK, MSIOF0_RXD_MARK,
159 MSIOF0_RSCK_MARK, MSIOF0_RSYNC_MARK, MSIOF0_MCK0_MARK,
160 MSIOF0_MCK1_MARK, MSIOF0_SS1_MARK, MSIOF0_SS2_MARK,
161 MSIOF0_TXD_MARK,
162
163 /* MSIOF1 */
164 MSIOF1_TSCK_39_MARK, MSIOF1_TSYNC_40_MARK,
165 MSIOF1_TSCK_88_MARK, MSIOF1_TSYNC_89_MARK,
166 MSIOF1_TXD_41_MARK, MSIOF1_RXD_42_MARK,
167 MSIOF1_TXD_90_MARK, MSIOF1_RXD_91_MARK,
168 MSIOF1_SS1_43_MARK, MSIOF1_SS2_44_MARK,
169 MSIOF1_SS1_92_MARK, MSIOF1_SS2_93_MARK,
170 MSIOF1_RSCK_MARK, MSIOF1_RSYNC_MARK,
171 MSIOF1_MCK0_MARK, MSIOF1_MCK1_MARK,
172
173 /* MSIOF2 */
174 MSIOF2_RSCK_MARK, MSIOF2_RSYNC_MARK, MSIOF2_MCK0_MARK,
175 MSIOF2_MCK1_MARK, MSIOF2_SS1_MARK, MSIOF2_SS2_MARK,
176 MSIOF2_TSYNC_MARK, MSIOF2_TSCK_MARK, MSIOF2_RXD_MARK,
177 MSIOF2_TXD_MARK,
178
179 /* BBIF1 */
180 BBIF1_RXD_MARK, BBIF1_TSYNC_MARK, BBIF1_TSCK_MARK,
181 BBIF1_TXD_MARK, BBIF1_RSCK_MARK, BBIF1_RSYNC_MARK,
182 BBIF1_FLOW_MARK, BB_RX_FLOW_N_MARK,
183
184 /* BBIF2 */
185 BBIF2_TSCK1_MARK, BBIF2_TSYNC1_MARK,
186 BBIF2_TXD1_MARK, BBIF2_RXD_MARK,
187
188 /* FSI */
189 FSIACK_MARK, FSIBCK_MARK, FSIAILR_MARK, FSIAIBT_MARK,
190 FSIAISLD_MARK, FSIAOMC_MARK, FSIAOLR_MARK, FSIAOBT_MARK,
191 FSIAOSLD_MARK, FSIASPDIF_11_MARK, FSIASPDIF_15_MARK,
192
193 /* FMSI */
194 FMSOCK_MARK, FMSOOLR_MARK, FMSIOLR_MARK, FMSOOBT_MARK,
195 FMSIOBT_MARK, FMSOSLD_MARK, FMSOILR_MARK, FMSIILR_MARK,
196 FMSOIBT_MARK, FMSIIBT_MARK, FMSISLD_MARK, FMSICK_MARK,
197
198 /* SCIFA0 */
199 SCIFA0_TXD_MARK, SCIFA0_RXD_MARK, SCIFA0_SCK_MARK,
200 SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
201
202 /* SCIFA1 */
203 SCIFA1_TXD_MARK, SCIFA1_RXD_MARK, SCIFA1_SCK_MARK,
204 SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
205
206 /* SCIFA2 */
207 SCIFA2_CTS1_MARK, SCIFA2_RTS1_MARK, SCIFA2_TXD1_MARK,
208 SCIFA2_RXD1_MARK, SCIFA2_SCK1_MARK,
209
210 /* SCIFA3 */
211 SCIFA3_CTS_43_MARK, SCIFA3_CTS_140_MARK, SCIFA3_RTS_44_MARK,
212 SCIFA3_RTS_141_MARK, SCIFA3_SCK_MARK, SCIFA3_TXD_MARK,
213 SCIFA3_RXD_MARK,
214
215 /* SCIFA4 */
216 SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
217
218 /* SCIFA5 */
219 SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
220
221 /* SCIFB */
222 SCIFB_SCK_MARK, SCIFB_RTS_MARK, SCIFB_CTS_MARK,
223 SCIFB_TXD_MARK, SCIFB_RXD_MARK,
224
225 /* CEU */
226 VIO_HD_MARK, VIO_CKO1_MARK, VIO_CKO2_MARK, VIO_VD_MARK,
227 VIO_CLK_MARK, VIO_FIELD_MARK, VIO_CKO_MARK,
228 VIO_D0_MARK, VIO_D1_MARK, VIO_D2_MARK, VIO_D3_MARK,
229 VIO_D4_MARK, VIO_D5_MARK, VIO_D6_MARK, VIO_D7_MARK,
230 VIO_D8_MARK, VIO_D9_MARK, VIO_D10_MARK, VIO_D11_MARK,
231 VIO_D12_MARK, VIO_D13_MARK, VIO_D14_MARK, VIO_D15_MARK,
232
233 /* USB0 */
234 IDIN_0_MARK, EXTLP_0_MARK, OVCN2_0_MARK, PWEN_0_MARK,
235 OVCN_0_MARK, VBUS0_0_MARK,
236
237 /* USB1 */
238 IDIN_1_18_MARK, IDIN_1_113_MARK,
239 PWEN_1_115_MARK, PWEN_1_138_MARK,
240 OVCN_1_114_MARK, OVCN_1_162_MARK,
241 EXTLP_1_MARK, OVCN2_1_MARK,
242 VBUS0_1_MARK,
243
244 /* GPIO */
245 GPI0_MARK, GPI1_MARK, GPO0_MARK, GPO1_MARK,
246
247 /* BSC */
248 BS_MARK, WE1_MARK,
249 CKO_MARK, WAIT_MARK, RDWR_MARK,
250
251 A0_MARK, A1_MARK, A2_MARK, A3_MARK,
252 A6_MARK, A7_MARK, A8_MARK, A9_MARK,
253 A10_MARK, A11_MARK, A12_MARK, A13_MARK,
254 A14_MARK, A15_MARK, A16_MARK, A17_MARK,
255 A18_MARK, A19_MARK, A20_MARK, A21_MARK,
256 A22_MARK, A23_MARK, A24_MARK, A25_MARK,
257 A26_MARK,
258
259 CS0_MARK, CS2_MARK, CS4_MARK,
260 CS5A_MARK, CS5B_MARK, CS6A_MARK,
261
262 /* BSC/FLCTL */
263 RD_FSC_MARK, WE0_FWE_MARK, A4_FOE_MARK, A5_FCDE_MARK,
264 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
265 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
266 D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
267 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
268
269 /* MMCIF(1) */
270 MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
271 MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
272 MMCCMD0_MARK, MMCCLK0_MARK,
273
274 /* MMCIF(2) */
275 MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
276 MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
277 MMCCLK1_MARK, MMCCMD1_MARK,
278
279 /* SPU2 */
280 VINT_I_MARK,
281
282 /* FLCTL */
283 FCE1_MARK, FCE0_MARK, FRB_MARK,
284
285 /* HSI */
286 GP_RX_FLAG_MARK, GP_RX_DATA_MARK, GP_TX_READY_MARK,
287 GP_RX_WAKE_MARK, MP_TX_FLAG_MARK, MP_TX_DATA_MARK,
288 MP_RX_READY_MARK, MP_TX_WAKE_MARK,
289
290 /* MFI */
291 MFIv6_MARK,
292 MFIv4_MARK,
293
294 MEMC_CS0_MARK, MEMC_BUSCLK_MEMC_A0_MARK,
295 MEMC_CS1_MEMC_A1_MARK, MEMC_ADV_MEMC_DREQ0_MARK,
296 MEMC_WAIT_MEMC_DREQ1_MARK, MEMC_NOE_MARK,
297 MEMC_NWE_MARK, MEMC_INT_MARK,
298
299 MEMC_AD0_MARK, MEMC_AD1_MARK, MEMC_AD2_MARK,
300 MEMC_AD3_MARK, MEMC_AD4_MARK, MEMC_AD5_MARK,
301 MEMC_AD6_MARK, MEMC_AD7_MARK, MEMC_AD8_MARK,
302 MEMC_AD9_MARK, MEMC_AD10_MARK, MEMC_AD11_MARK,
303 MEMC_AD12_MARK, MEMC_AD13_MARK, MEMC_AD14_MARK,
304 MEMC_AD15_MARK,
305
306 /* SIM */
307 SIM_RST_MARK, SIM_CLK_MARK, SIM_D_MARK,
308
309 /* TPU */
310 TPU0TO0_MARK, TPU0TO1_MARK,
311 TPU0TO2_93_MARK, TPU0TO2_99_MARK,
312 TPU0TO3_MARK,
313
314 /* I2C2 */
315 I2C_SCL2_MARK, I2C_SDA2_MARK,
316
317 /* I2C3(1) */
318 I2C_SCL3_MARK, I2C_SDA3_MARK,
319
320 /* I2C3(2) */
321 I2C_SCL3S_MARK, I2C_SDA3S_MARK,
322
323 /* I2C4(2) */
324 I2C_SCL4_MARK, I2C_SDA4_MARK,
325
326 /* I2C4(2) */
327 I2C_SCL4S_MARK, I2C_SDA4S_MARK,
328
329 /* KEYSC */
330 KEYOUT0_MARK, KEYIN0_121_MARK, KEYIN0_136_MARK,
331 KEYOUT1_MARK, KEYIN1_122_MARK, KEYIN1_135_MARK,
332 KEYOUT2_MARK, KEYIN2_123_MARK, KEYIN2_134_MARK,
333 KEYOUT3_MARK, KEYIN3_124_MARK, KEYIN3_133_MARK,
334 KEYOUT4_MARK, KEYIN4_MARK,
335 KEYOUT5_MARK, KEYIN5_MARK,
336 KEYOUT6_MARK, KEYIN6_MARK,
337 KEYOUT7_MARK, KEYIN7_MARK,
338
339 /* LCDC */
340 LCDC0_SELECT_MARK,
341 LCDC1_SELECT_MARK,
342 LCDHSYN_MARK, LCDCS_MARK, LCDVSYN_MARK, LCDDCK_MARK,
343 LCDWR_MARK, LCDRD_MARK, LCDDISP_MARK, LCDRS_MARK,
344 LCDLCLK_MARK, LCDDON_MARK,
345
346 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
347 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
348 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
349 LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
350 LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK,
351 LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK,
352
353 /* IRDA */
354 IRDA_OUT_MARK, IRDA_IN_MARK, IRDA_FIRSEL_MARK,
355 IROUT_139_MARK, IROUT_140_MARK,
356
357 /* TSIF1 */
358 TS0_1SELECT_MARK,
359 TS0_2SELECT_MARK,
360 TS1_1SELECT_MARK,
361 TS1_2SELECT_MARK,
362
363 TS_SPSYNC1_MARK, TS_SDAT1_MARK,
364 TS_SDEN1_MARK, TS_SCK1_MARK,
365
366 /* TSIF2 */
367 TS_SPSYNC2_MARK, TS_SDAT2_MARK,
368 TS_SDEN2_MARK, TS_SCK2_MARK,
369
370 /* HDMI */
371 HDMI_HPD_MARK, HDMI_CEC_MARK,
372
373 /* SDHI0 */
374 SDHICLK0_MARK, SDHICD0_MARK,
375 SDHICMD0_MARK, SDHIWP0_MARK,
376 SDHID0_0_MARK, SDHID0_1_MARK,
377 SDHID0_2_MARK, SDHID0_3_MARK,
378
379 /* SDHI1 */
380 SDHICLK1_MARK, SDHICMD1_MARK, SDHID1_0_MARK,
381 SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
382
383 /* SDHI2 */
384 SDHICLK2_MARK, SDHICMD2_MARK, SDHID2_0_MARK,
385 SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
386
387 /* SDENC */
388 SDENC_CPG_MARK,
389 SDENC_DV_CLKI_MARK,
390
391 PINMUX_MARK_END,
392 };
393
394 #define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx)
395 #define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
396
397 static const pinmux_enum_t pinmux_data[] = {
398 PINMUX_DATA_GP_ALL(),
399
400 /* IRQ */
401 PINMUX_DATA(IRQ0_6_MARK, PORT6_FN0, MSEL1CR_0_0),
402 PINMUX_DATA(IRQ0_162_MARK, PORT162_FN0, MSEL1CR_0_1),
403 PINMUX_DATA(IRQ1_MARK, PORT12_FN0),
404 PINMUX_DATA(IRQ2_4_MARK, PORT4_FN0, MSEL1CR_2_0),
405 PINMUX_DATA(IRQ2_5_MARK, PORT5_FN0, MSEL1CR_2_1),
406 PINMUX_DATA(IRQ3_8_MARK, PORT8_FN0, MSEL1CR_3_0),
407 PINMUX_DATA(IRQ3_16_MARK, PORT16_FN0, MSEL1CR_3_1),
408 PINMUX_DATA(IRQ4_17_MARK, PORT17_FN0, MSEL1CR_4_0),
409 PINMUX_DATA(IRQ4_163_MARK, PORT163_FN0, MSEL1CR_4_1),
410 PINMUX_DATA(IRQ5_MARK, PORT18_FN0),
411 PINMUX_DATA(IRQ6_39_MARK, PORT39_FN0, MSEL1CR_6_0),
412 PINMUX_DATA(IRQ6_164_MARK, PORT164_FN0, MSEL1CR_6_1),
413 PINMUX_DATA(IRQ7_40_MARK, PORT40_FN0, MSEL1CR_7_1),
414 PINMUX_DATA(IRQ7_167_MARK, PORT167_FN0, MSEL1CR_7_0),
415 PINMUX_DATA(IRQ8_41_MARK, PORT41_FN0, MSEL1CR_8_1),
416 PINMUX_DATA(IRQ8_168_MARK, PORT168_FN0, MSEL1CR_8_0),
417 PINMUX_DATA(IRQ9_42_MARK, PORT42_FN0, MSEL1CR_9_0),
418 PINMUX_DATA(IRQ9_169_MARK, PORT169_FN0, MSEL1CR_9_1),
419 PINMUX_DATA(IRQ10_MARK, PORT65_FN0, MSEL1CR_9_1),
420 PINMUX_DATA(IRQ11_MARK, PORT67_FN0),
421 PINMUX_DATA(IRQ12_80_MARK, PORT80_FN0, MSEL1CR_12_0),
422 PINMUX_DATA(IRQ12_137_MARK, PORT137_FN0, MSEL1CR_12_1),
423 PINMUX_DATA(IRQ13_81_MARK, PORT81_FN0, MSEL1CR_13_0),
424 PINMUX_DATA(IRQ13_145_MARK, PORT145_FN0, MSEL1CR_13_1),
425 PINMUX_DATA(IRQ14_82_MARK, PORT82_FN0, MSEL1CR_14_0),
426 PINMUX_DATA(IRQ14_146_MARK, PORT146_FN0, MSEL1CR_14_1),
427 PINMUX_DATA(IRQ15_83_MARK, PORT83_FN0, MSEL1CR_15_0),
428 PINMUX_DATA(IRQ15_147_MARK, PORT147_FN0, MSEL1CR_15_1),
429 PINMUX_DATA(IRQ16_84_MARK, PORT84_FN0, MSEL1CR_16_0),
430 PINMUX_DATA(IRQ16_170_MARK, PORT170_FN0, MSEL1CR_16_1),
431 PINMUX_DATA(IRQ17_MARK, PORT85_FN0),
432 PINMUX_DATA(IRQ18_MARK, PORT86_FN0),
433 PINMUX_DATA(IRQ19_MARK, PORT87_FN0),
434 PINMUX_DATA(IRQ20_MARK, PORT92_FN0),
435 PINMUX_DATA(IRQ21_MARK, PORT93_FN0),
436 PINMUX_DATA(IRQ22_MARK, PORT94_FN0),
437 PINMUX_DATA(IRQ23_MARK, PORT95_FN0),
438 PINMUX_DATA(IRQ24_MARK, PORT112_FN0),
439 PINMUX_DATA(IRQ25_MARK, PORT119_FN0),
440 PINMUX_DATA(IRQ26_121_MARK, PORT121_FN0, MSEL1CR_26_1),
441 PINMUX_DATA(IRQ26_172_MARK, PORT172_FN0, MSEL1CR_26_0),
442 PINMUX_DATA(IRQ27_122_MARK, PORT122_FN0, MSEL1CR_27_1),
443 PINMUX_DATA(IRQ27_180_MARK, PORT180_FN0, MSEL1CR_27_0),
444 PINMUX_DATA(IRQ28_123_MARK, PORT123_FN0, MSEL1CR_28_1),
445 PINMUX_DATA(IRQ28_181_MARK, PORT181_FN0, MSEL1CR_28_0),
446 PINMUX_DATA(IRQ29_129_MARK, PORT129_FN0, MSEL1CR_29_1),
447 PINMUX_DATA(IRQ29_182_MARK, PORT182_FN0, MSEL1CR_29_0),
448 PINMUX_DATA(IRQ30_130_MARK, PORT130_FN0, MSEL1CR_30_1),
449 PINMUX_DATA(IRQ30_183_MARK, PORT183_FN0, MSEL1CR_30_0),
450 PINMUX_DATA(IRQ31_138_MARK, PORT138_FN0, MSEL1CR_31_1),
451 PINMUX_DATA(IRQ31_184_MARK, PORT184_FN0, MSEL1CR_31_0),
452
453 /* Function 1 */
454 PINMUX_DATA(BBIF2_TSCK1_MARK, PORT0_FN1),
455 PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT1_FN1),
456 PINMUX_DATA(BBIF2_TXD1_MARK, PORT2_FN1),
457 PINMUX_DATA(BBIF2_RXD_MARK, PORT3_FN1),
458 PINMUX_DATA(FSIACK_MARK, PORT4_FN1),
459 PINMUX_DATA(FSIAILR_MARK, PORT5_FN1),
460 PINMUX_DATA(FSIAIBT_MARK, PORT6_FN1),
461 PINMUX_DATA(FSIAISLD_MARK, PORT7_FN1),
462 PINMUX_DATA(FSIAOMC_MARK, PORT8_FN1),
463 PINMUX_DATA(FSIAOLR_MARK, PORT9_FN1),
464 PINMUX_DATA(FSIAOBT_MARK, PORT10_FN1),
465 PINMUX_DATA(FSIAOSLD_MARK, PORT11_FN1),
466 PINMUX_DATA(FMSOCK_MARK, PORT12_FN1),
467 PINMUX_DATA(FMSOOLR_MARK, PORT13_FN1),
468 PINMUX_DATA(FMSOOBT_MARK, PORT14_FN1),
469 PINMUX_DATA(FMSOSLD_MARK, PORT15_FN1),
470 PINMUX_DATA(FMSOILR_MARK, PORT16_FN1),
471 PINMUX_DATA(FMSOIBT_MARK, PORT17_FN1),
472 PINMUX_DATA(FMSISLD_MARK, PORT18_FN1),
473 PINMUX_DATA(A0_MARK, PORT19_FN1),
474 PINMUX_DATA(A1_MARK, PORT20_FN1),
475 PINMUX_DATA(A2_MARK, PORT21_FN1),
476 PINMUX_DATA(A3_MARK, PORT22_FN1),
477 PINMUX_DATA(A4_FOE_MARK, PORT23_FN1),
478 PINMUX_DATA(A5_FCDE_MARK, PORT24_FN1),
479 PINMUX_DATA(A6_MARK, PORT25_FN1),
480 PINMUX_DATA(A7_MARK, PORT26_FN1),
481 PINMUX_DATA(A8_MARK, PORT27_FN1),
482 PINMUX_DATA(A9_MARK, PORT28_FN1),
483 PINMUX_DATA(A10_MARK, PORT29_FN1),
484 PINMUX_DATA(A11_MARK, PORT30_FN1),
485 PINMUX_DATA(A12_MARK, PORT31_FN1),
486 PINMUX_DATA(A13_MARK, PORT32_FN1),
487 PINMUX_DATA(A14_MARK, PORT33_FN1),
488 PINMUX_DATA(A15_MARK, PORT34_FN1),
489 PINMUX_DATA(A16_MARK, PORT35_FN1),
490 PINMUX_DATA(A17_MARK, PORT36_FN1),
491 PINMUX_DATA(A18_MARK, PORT37_FN1),
492 PINMUX_DATA(A19_MARK, PORT38_FN1),
493 PINMUX_DATA(A20_MARK, PORT39_FN1),
494 PINMUX_DATA(A21_MARK, PORT40_FN1),
495 PINMUX_DATA(A22_MARK, PORT41_FN1),
496 PINMUX_DATA(A23_MARK, PORT42_FN1),
497 PINMUX_DATA(A24_MARK, PORT43_FN1),
498 PINMUX_DATA(A25_MARK, PORT44_FN1),
499 PINMUX_DATA(A26_MARK, PORT45_FN1),
500 PINMUX_DATA(D0_NAF0_MARK, PORT46_FN1),
501 PINMUX_DATA(D1_NAF1_MARK, PORT47_FN1),
502 PINMUX_DATA(D2_NAF2_MARK, PORT48_FN1),
503 PINMUX_DATA(D3_NAF3_MARK, PORT49_FN1),
504 PINMUX_DATA(D4_NAF4_MARK, PORT50_FN1),
505 PINMUX_DATA(D5_NAF5_MARK, PORT51_FN1),
506 PINMUX_DATA(D6_NAF6_MARK, PORT52_FN1),
507 PINMUX_DATA(D7_NAF7_MARK, PORT53_FN1),
508 PINMUX_DATA(D8_NAF8_MARK, PORT54_FN1),
509 PINMUX_DATA(D9_NAF9_MARK, PORT55_FN1),
510 PINMUX_DATA(D10_NAF10_MARK, PORT56_FN1),
511 PINMUX_DATA(D11_NAF11_MARK, PORT57_FN1),
512 PINMUX_DATA(D12_NAF12_MARK, PORT58_FN1),
513 PINMUX_DATA(D13_NAF13_MARK, PORT59_FN1),
514 PINMUX_DATA(D14_NAF14_MARK, PORT60_FN1),
515 PINMUX_DATA(D15_NAF15_MARK, PORT61_FN1),
516 PINMUX_DATA(CS0_MARK, PORT62_FN1),
517 PINMUX_DATA(CS2_MARK, PORT63_FN1),
518 PINMUX_DATA(CS4_MARK, PORT64_FN1),
519 PINMUX_DATA(CS5A_MARK, PORT65_FN1),
520 PINMUX_DATA(CS5B_MARK, PORT66_FN1),
521 PINMUX_DATA(CS6A_MARK, PORT67_FN1),
522 PINMUX_DATA(FCE0_MARK, PORT68_FN1),
523 PINMUX_DATA(RD_FSC_MARK, PORT69_FN1),
524 PINMUX_DATA(WE0_FWE_MARK, PORT70_FN1),
525 PINMUX_DATA(WE1_MARK, PORT71_FN1),
526 PINMUX_DATA(CKO_MARK, PORT72_FN1),
527 PINMUX_DATA(FRB_MARK, PORT73_FN1),
528 PINMUX_DATA(WAIT_MARK, PORT74_FN1),
529 PINMUX_DATA(RDWR_MARK, PORT75_FN1),
530 PINMUX_DATA(MEMC_AD0_MARK, PORT76_FN1),
531 PINMUX_DATA(MEMC_AD1_MARK, PORT77_FN1),
532 PINMUX_DATA(MEMC_AD2_MARK, PORT78_FN1),
533 PINMUX_DATA(MEMC_AD3_MARK, PORT79_FN1),
534 PINMUX_DATA(MEMC_AD4_MARK, PORT80_FN1),
535 PINMUX_DATA(MEMC_AD5_MARK, PORT81_FN1),
536 PINMUX_DATA(MEMC_AD6_MARK, PORT82_FN1),
537 PINMUX_DATA(MEMC_AD7_MARK, PORT83_FN1),
538 PINMUX_DATA(MEMC_AD8_MARK, PORT84_FN1),
539 PINMUX_DATA(MEMC_AD9_MARK, PORT85_FN1),
540 PINMUX_DATA(MEMC_AD10_MARK, PORT86_FN1),
541 PINMUX_DATA(MEMC_AD11_MARK, PORT87_FN1),
542 PINMUX_DATA(MEMC_AD12_MARK, PORT88_FN1),
543 PINMUX_DATA(MEMC_AD13_MARK, PORT89_FN1),
544 PINMUX_DATA(MEMC_AD14_MARK, PORT90_FN1),
545 PINMUX_DATA(MEMC_AD15_MARK, PORT91_FN1),
546 PINMUX_DATA(MEMC_CS0_MARK, PORT92_FN1),
547 PINMUX_DATA(MEMC_BUSCLK_MEMC_A0_MARK, PORT93_FN1),
548 PINMUX_DATA(MEMC_CS1_MEMC_A1_MARK, PORT94_FN1),
549 PINMUX_DATA(MEMC_ADV_MEMC_DREQ0_MARK, PORT95_FN1),
550 PINMUX_DATA(MEMC_WAIT_MEMC_DREQ1_MARK, PORT96_FN1),
551 PINMUX_DATA(MEMC_NOE_MARK, PORT97_FN1),
552 PINMUX_DATA(MEMC_NWE_MARK, PORT98_FN1),
553 PINMUX_DATA(MEMC_INT_MARK, PORT99_FN1),
554 PINMUX_DATA(VIO_VD_MARK, PORT100_FN1),
555 PINMUX_DATA(VIO_HD_MARK, PORT101_FN1),
556 PINMUX_DATA(VIO_D0_MARK, PORT102_FN1),
557 PINMUX_DATA(VIO_D1_MARK, PORT103_FN1),
558 PINMUX_DATA(VIO_D2_MARK, PORT104_FN1),
559 PINMUX_DATA(VIO_D3_MARK, PORT105_FN1),
560 PINMUX_DATA(VIO_D4_MARK, PORT106_FN1),
561 PINMUX_DATA(VIO_D5_MARK, PORT107_FN1),
562 PINMUX_DATA(VIO_D6_MARK, PORT108_FN1),
563 PINMUX_DATA(VIO_D7_MARK, PORT109_FN1),
564 PINMUX_DATA(VIO_D8_MARK, PORT110_FN1),
565 PINMUX_DATA(VIO_D9_MARK, PORT111_FN1),
566 PINMUX_DATA(VIO_D10_MARK, PORT112_FN1),
567 PINMUX_DATA(VIO_D11_MARK, PORT113_FN1),
568 PINMUX_DATA(VIO_D12_MARK, PORT114_FN1),
569 PINMUX_DATA(VIO_D13_MARK, PORT115_FN1),
570 PINMUX_DATA(VIO_D14_MARK, PORT116_FN1),
571 PINMUX_DATA(VIO_D15_MARK, PORT117_FN1),
572 PINMUX_DATA(VIO_CLK_MARK, PORT118_FN1),
573 PINMUX_DATA(VIO_FIELD_MARK, PORT119_FN1),
574 PINMUX_DATA(VIO_CKO_MARK, PORT120_FN1),
575 PINMUX_DATA(LCDD0_MARK, PORT121_FN1),
576 PINMUX_DATA(LCDD1_MARK, PORT122_FN1),
577 PINMUX_DATA(LCDD2_MARK, PORT123_FN1),
578 PINMUX_DATA(LCDD3_MARK, PORT124_FN1),
579 PINMUX_DATA(LCDD4_MARK, PORT125_FN1),
580 PINMUX_DATA(LCDD5_MARK, PORT126_FN1),
581 PINMUX_DATA(LCDD6_MARK, PORT127_FN1),
582 PINMUX_DATA(LCDD7_MARK, PORT128_FN1),
583 PINMUX_DATA(LCDD8_MARK, PORT129_FN1),
584 PINMUX_DATA(LCDD9_MARK, PORT130_FN1),
585 PINMUX_DATA(LCDD10_MARK, PORT131_FN1),
586 PINMUX_DATA(LCDD11_MARK, PORT132_FN1),
587 PINMUX_DATA(LCDD12_MARK, PORT133_FN1),
588 PINMUX_DATA(LCDD13_MARK, PORT134_FN1),
589 PINMUX_DATA(LCDD14_MARK, PORT135_FN1),
590 PINMUX_DATA(LCDD15_MARK, PORT136_FN1),
591 PINMUX_DATA(LCDD16_MARK, PORT137_FN1),
592 PINMUX_DATA(LCDD17_MARK, PORT138_FN1),
593 PINMUX_DATA(LCDD18_MARK, PORT139_FN1),
594 PINMUX_DATA(LCDD19_MARK, PORT140_FN1),
595 PINMUX_DATA(LCDD20_MARK, PORT141_FN1),
596 PINMUX_DATA(LCDD21_MARK, PORT142_FN1),
597 PINMUX_DATA(LCDD22_MARK, PORT143_FN1),
598 PINMUX_DATA(LCDD23_MARK, PORT144_FN1),
599 PINMUX_DATA(LCDHSYN_MARK, PORT145_FN1),
600 PINMUX_DATA(LCDVSYN_MARK, PORT146_FN1),
601 PINMUX_DATA(LCDDCK_MARK, PORT147_FN1),
602 PINMUX_DATA(LCDRD_MARK, PORT148_FN1),
603 PINMUX_DATA(LCDDISP_MARK, PORT149_FN1),
604 PINMUX_DATA(LCDLCLK_MARK, PORT150_FN1),
605 PINMUX_DATA(LCDDON_MARK, PORT151_FN1),
606 PINMUX_DATA(SCIFA0_TXD_MARK, PORT152_FN1),
607 PINMUX_DATA(SCIFA0_RXD_MARK, PORT153_FN1),
608 PINMUX_DATA(SCIFA1_TXD_MARK, PORT154_FN1),
609 PINMUX_DATA(SCIFA1_RXD_MARK, PORT155_FN1),
610 PINMUX_DATA(TS_SPSYNC1_MARK, PORT156_FN1),
611 PINMUX_DATA(TS_SDAT1_MARK, PORT157_FN1),
612 PINMUX_DATA(TS_SDEN1_MARK, PORT158_FN1),
613 PINMUX_DATA(TS_SCK1_MARK, PORT159_FN1),
614 PINMUX_DATA(TPU0TO0_MARK, PORT160_FN1),
615 PINMUX_DATA(TPU0TO1_MARK, PORT161_FN1),
616 PINMUX_DATA(SCIFB_SCK_MARK, PORT162_FN1),
617 PINMUX_DATA(SCIFB_RTS_MARK, PORT163_FN1),
618 PINMUX_DATA(SCIFB_CTS_MARK, PORT164_FN1),
619 PINMUX_DATA(SCIFB_TXD_MARK, PORT165_FN1),
620 PINMUX_DATA(SCIFB_RXD_MARK, PORT166_FN1),
621 PINMUX_DATA(VBUS0_0_MARK, PORT167_FN1),
622 PINMUX_DATA(VBUS0_1_MARK, PORT168_FN1),
623 PINMUX_DATA(HDMI_HPD_MARK, PORT169_FN1),
624 PINMUX_DATA(HDMI_CEC_MARK, PORT170_FN1),
625 PINMUX_DATA(SDHICLK0_MARK, PORT171_FN1),
626 PINMUX_DATA(SDHICD0_MARK, PORT172_FN1),
627 PINMUX_DATA(SDHID0_0_MARK, PORT173_FN1),
628 PINMUX_DATA(SDHID0_1_MARK, PORT174_FN1),
629 PINMUX_DATA(SDHID0_2_MARK, PORT175_FN1),
630 PINMUX_DATA(SDHID0_3_MARK, PORT176_FN1),
631 PINMUX_DATA(SDHICMD0_MARK, PORT177_FN1),
632 PINMUX_DATA(SDHIWP0_MARK, PORT178_FN1),
633 PINMUX_DATA(SDHICLK1_MARK, PORT179_FN1),
634 PINMUX_DATA(SDHID1_0_MARK, PORT180_FN1),
635 PINMUX_DATA(SDHID1_1_MARK, PORT181_FN1),
636 PINMUX_DATA(SDHID1_2_MARK, PORT182_FN1),
637 PINMUX_DATA(SDHID1_3_MARK, PORT183_FN1),
638 PINMUX_DATA(SDHICMD1_MARK, PORT184_FN1),
639 PINMUX_DATA(SDHICLK2_MARK, PORT185_FN1),
640 PINMUX_DATA(SDHID2_0_MARK, PORT186_FN1),
641 PINMUX_DATA(SDHID2_1_MARK, PORT187_FN1),
642 PINMUX_DATA(SDHID2_2_MARK, PORT188_FN1),
643 PINMUX_DATA(SDHID2_3_MARK, PORT189_FN1),
644 PINMUX_DATA(SDHICMD2_MARK, PORT190_FN1),
645
646 /* Function 2 */
647 PINMUX_DATA(FSIBCK_MARK, PORT4_FN2),
648 PINMUX_DATA(SCIFA4_RXD_MARK, PORT5_FN2),
649 PINMUX_DATA(SCIFA4_TXD_MARK, PORT6_FN2),
650 PINMUX_DATA(SCIFA5_RXD_MARK, PORT8_FN2),
651 PINMUX_DATA(FSIASPDIF_11_MARK, PORT11_FN2),
652 PINMUX_DATA(SCIFA5_TXD_MARK, PORT12_FN2),
653 PINMUX_DATA(FMSIOLR_MARK, PORT13_FN2),
654 PINMUX_DATA(FMSIOBT_MARK, PORT14_FN2),
655 PINMUX_DATA(FSIASPDIF_15_MARK, PORT15_FN2),
656 PINMUX_DATA(FMSIILR_MARK, PORT16_FN2),
657 PINMUX_DATA(FMSIIBT_MARK, PORT17_FN2),
658 PINMUX_DATA(BS_MARK, PORT19_FN2),
659 PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT36_FN2),
660 PINMUX_DATA(MSIOF0_TSCK_MARK, PORT37_FN2),
661 PINMUX_DATA(MSIOF0_RXD_MARK, PORT38_FN2),
662 PINMUX_DATA(MSIOF0_RSCK_MARK, PORT39_FN2),
663 PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT40_FN2),
664 PINMUX_DATA(MSIOF0_MCK0_MARK, PORT41_FN2),
665 PINMUX_DATA(MSIOF0_MCK1_MARK, PORT42_FN2),
666 PINMUX_DATA(MSIOF0_SS1_MARK, PORT43_FN2),
667 PINMUX_DATA(MSIOF0_SS2_MARK, PORT44_FN2),
668 PINMUX_DATA(MSIOF0_TXD_MARK, PORT45_FN2),
669 PINMUX_DATA(FMSICK_MARK, PORT65_FN2),
670 PINMUX_DATA(FCE1_MARK, PORT66_FN2),
671 PINMUX_DATA(BBIF1_RXD_MARK, PORT76_FN2),
672 PINMUX_DATA(BBIF1_TSYNC_MARK, PORT77_FN2),
673 PINMUX_DATA(BBIF1_TSCK_MARK, PORT78_FN2),
674 PINMUX_DATA(BBIF1_TXD_MARK, PORT79_FN2),
675 PINMUX_DATA(BBIF1_RSCK_MARK, PORT80_FN2),
676 PINMUX_DATA(BBIF1_RSYNC_MARK, PORT81_FN2),
677 PINMUX_DATA(BBIF1_FLOW_MARK, PORT82_FN2),
678 PINMUX_DATA(BB_RX_FLOW_N_MARK, PORT83_FN2),
679 PINMUX_DATA(MSIOF1_RSCK_MARK, PORT84_FN2),
680 PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT85_FN2),
681 PINMUX_DATA(MSIOF1_MCK0_MARK, PORT86_FN2),
682 PINMUX_DATA(MSIOF1_MCK1_MARK, PORT87_FN2),
683 PINMUX_DATA(MSIOF1_TSCK_88_MARK, PORT88_FN2, MSEL4CR_10_1),
684 PINMUX_DATA(MSIOF1_TSYNC_89_MARK, PORT89_FN2, MSEL4CR_10_1),
685 PINMUX_DATA(MSIOF1_TXD_90_MARK, PORT90_FN2, MSEL4CR_10_1),
686 PINMUX_DATA(MSIOF1_RXD_91_MARK, PORT91_FN2, MSEL4CR_10_1),
687 PINMUX_DATA(MSIOF1_SS1_92_MARK, PORT92_FN2, MSEL4CR_10_1),
688 PINMUX_DATA(MSIOF1_SS2_93_MARK, PORT93_FN2, MSEL4CR_10_1),
689 PINMUX_DATA(SCIFA2_CTS1_MARK, PORT94_FN2),
690 PINMUX_DATA(SCIFA2_RTS1_MARK, PORT95_FN2),
691 PINMUX_DATA(SCIFA2_TXD1_MARK, PORT96_FN2),
692 PINMUX_DATA(SCIFA2_RXD1_MARK, PORT97_FN2),
693 PINMUX_DATA(SCIFA2_SCK1_MARK, PORT98_FN2),
694 PINMUX_DATA(I2C_SCL2_MARK, PORT110_FN2),
695 PINMUX_DATA(I2C_SDA2_MARK, PORT111_FN2),
696 PINMUX_DATA(I2C_SCL3_MARK, PORT114_FN2, MSEL4CR_16_1),
697 PINMUX_DATA(I2C_SDA3_MARK, PORT115_FN2, MSEL4CR_16_1),
698 PINMUX_DATA(I2C_SCL4_MARK, PORT116_FN2, MSEL4CR_17_1),
699 PINMUX_DATA(I2C_SDA4_MARK, PORT117_FN2, MSEL4CR_17_1),
700 PINMUX_DATA(MSIOF2_RSCK_MARK, PORT134_FN2),
701 PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT135_FN2),
702 PINMUX_DATA(MSIOF2_MCK0_MARK, PORT136_FN2),
703 PINMUX_DATA(MSIOF2_MCK1_MARK, PORT137_FN2),
704 PINMUX_DATA(MSIOF2_SS1_MARK, PORT138_FN2),
705 PINMUX_DATA(MSIOF2_SS2_MARK, PORT139_FN2),
706 PINMUX_DATA(SCIFA3_CTS_140_MARK, PORT140_FN2, MSEL3CR_9_1),
707 PINMUX_DATA(SCIFA3_RTS_141_MARK, PORT141_FN2),
708 PINMUX_DATA(SCIFA3_SCK_MARK, PORT142_FN2),
709 PINMUX_DATA(SCIFA3_TXD_MARK, PORT143_FN2),
710 PINMUX_DATA(SCIFA3_RXD_MARK, PORT144_FN2),
711 PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT148_FN2),
712 PINMUX_DATA(MSIOF2_TSCK_MARK, PORT149_FN2),
713 PINMUX_DATA(MSIOF2_RXD_MARK, PORT150_FN2),
714 PINMUX_DATA(MSIOF2_TXD_MARK, PORT151_FN2),
715 PINMUX_DATA(SCIFA0_SCK_MARK, PORT156_FN2),
716 PINMUX_DATA(SCIFA0_RTS_MARK, PORT157_FN2),
717 PINMUX_DATA(SCIFA0_CTS_MARK, PORT158_FN2),
718 PINMUX_DATA(SCIFA1_SCK_MARK, PORT159_FN2),
719 PINMUX_DATA(SCIFA1_RTS_MARK, PORT160_FN2),
720 PINMUX_DATA(SCIFA1_CTS_MARK, PORT161_FN2),
721
722 /* Function 3 */
723 PINMUX_DATA(VIO_CKO1_MARK, PORT16_FN3),
724 PINMUX_DATA(VIO_CKO2_MARK, PORT17_FN3),
725 PINMUX_DATA(IDIN_1_18_MARK, PORT18_FN3, MSEL4CR_14_1),
726 PINMUX_DATA(MSIOF1_TSCK_39_MARK, PORT39_FN3, MSEL4CR_10_0),
727 PINMUX_DATA(MSIOF1_TSYNC_40_MARK, PORT40_FN3, MSEL4CR_10_0),
728 PINMUX_DATA(MSIOF1_TXD_41_MARK, PORT41_FN3, MSEL4CR_10_0),
729 PINMUX_DATA(MSIOF1_RXD_42_MARK, PORT42_FN3, MSEL4CR_10_0),
730 PINMUX_DATA(MSIOF1_SS1_43_MARK, PORT43_FN3, MSEL4CR_10_0),
731 PINMUX_DATA(MSIOF1_SS2_44_MARK, PORT44_FN3, MSEL4CR_10_0),
732 PINMUX_DATA(MMCD1_0_MARK, PORT54_FN3, MSEL4CR_15_1),
733 PINMUX_DATA(MMCD1_1_MARK, PORT55_FN3, MSEL4CR_15_1),
734 PINMUX_DATA(MMCD1_2_MARK, PORT56_FN3, MSEL4CR_15_1),
735 PINMUX_DATA(MMCD1_3_MARK, PORT57_FN3, MSEL4CR_15_1),
736 PINMUX_DATA(MMCD1_4_MARK, PORT58_FN3, MSEL4CR_15_1),
737 PINMUX_DATA(MMCD1_5_MARK, PORT59_FN3, MSEL4CR_15_1),
738 PINMUX_DATA(MMCD1_6_MARK, PORT60_FN3, MSEL4CR_15_1),
739 PINMUX_DATA(MMCD1_7_MARK, PORT61_FN3, MSEL4CR_15_1),
740 PINMUX_DATA(VINT_I_MARK, PORT65_FN3),
741 PINMUX_DATA(MMCCLK1_MARK, PORT66_FN3, MSEL4CR_15_1),
742 PINMUX_DATA(MMCCMD1_MARK, PORT67_FN3, MSEL4CR_15_1),
743 PINMUX_DATA(TPU0TO2_93_MARK, PORT93_FN3),
744 PINMUX_DATA(TPU0TO2_99_MARK, PORT99_FN3),
745 PINMUX_DATA(TPU0TO3_MARK, PORT112_FN3),
746 PINMUX_DATA(IDIN_0_MARK, PORT113_FN3),
747 PINMUX_DATA(EXTLP_0_MARK, PORT114_FN3),
748 PINMUX_DATA(OVCN2_0_MARK, PORT115_FN3),
749 PINMUX_DATA(PWEN_0_MARK, PORT116_FN3),
750 PINMUX_DATA(OVCN_0_MARK, PORT117_FN3),
751 PINMUX_DATA(KEYOUT7_MARK, PORT121_FN3),
752 PINMUX_DATA(KEYOUT6_MARK, PORT122_FN3),
753 PINMUX_DATA(KEYOUT5_MARK, PORT123_FN3),
754 PINMUX_DATA(KEYOUT4_MARK, PORT124_FN3),
755 PINMUX_DATA(KEYOUT3_MARK, PORT125_FN3),
756 PINMUX_DATA(KEYOUT2_MARK, PORT126_FN3),
757 PINMUX_DATA(KEYOUT1_MARK, PORT127_FN3),
758 PINMUX_DATA(KEYOUT0_MARK, PORT128_FN3),
759 PINMUX_DATA(KEYIN7_MARK, PORT129_FN3),
760 PINMUX_DATA(KEYIN6_MARK, PORT130_FN3),
761 PINMUX_DATA(KEYIN5_MARK, PORT131_FN3),
762 PINMUX_DATA(KEYIN4_MARK, PORT132_FN3),
763 PINMUX_DATA(KEYIN3_133_MARK, PORT133_FN3, MSEL4CR_18_0),
764 PINMUX_DATA(KEYIN2_134_MARK, PORT134_FN3, MSEL4CR_18_0),
765 PINMUX_DATA(KEYIN1_135_MARK, PORT135_FN3, MSEL4CR_18_0),
766 PINMUX_DATA(KEYIN0_136_MARK, PORT136_FN3, MSEL4CR_18_0),
767 PINMUX_DATA(TS_SPSYNC2_MARK, PORT137_FN3),
768 PINMUX_DATA(IROUT_139_MARK, PORT139_FN3),
769 PINMUX_DATA(IRDA_OUT_MARK, PORT140_FN3),
770 PINMUX_DATA(IRDA_IN_MARK, PORT141_FN3),
771 PINMUX_DATA(IRDA_FIRSEL_MARK, PORT142_FN3),
772 PINMUX_DATA(TS_SDAT2_MARK, PORT145_FN3),
773 PINMUX_DATA(TS_SDEN2_MARK, PORT146_FN3),
774 PINMUX_DATA(TS_SCK2_MARK, PORT147_FN3),
775
776 /* Function 4 */
777 PINMUX_DATA(SCIFA3_CTS_43_MARK, PORT43_FN4, MSEL3CR_9_0),
778 PINMUX_DATA(SCIFA3_RTS_44_MARK, PORT44_FN4),
779 PINMUX_DATA(GP_RX_FLAG_MARK, PORT76_FN4),
780 PINMUX_DATA(GP_RX_DATA_MARK, PORT77_FN4),
781 PINMUX_DATA(GP_TX_READY_MARK, PORT78_FN4),
782 PINMUX_DATA(GP_RX_WAKE_MARK, PORT79_FN4),
783 PINMUX_DATA(MP_TX_FLAG_MARK, PORT80_FN4),
784 PINMUX_DATA(MP_TX_DATA_MARK, PORT81_FN4),
785 PINMUX_DATA(MP_RX_READY_MARK, PORT82_FN4),
786 PINMUX_DATA(MP_TX_WAKE_MARK, PORT83_FN4),
787 PINMUX_DATA(MMCD0_0_MARK, PORT84_FN4, MSEL4CR_15_0),
788 PINMUX_DATA(MMCD0_1_MARK, PORT85_FN4, MSEL4CR_15_0),
789 PINMUX_DATA(MMCD0_2_MARK, PORT86_FN4, MSEL4CR_15_0),
790 PINMUX_DATA(MMCD0_3_MARK, PORT87_FN4, MSEL4CR_15_0),
791 PINMUX_DATA(MMCD0_4_MARK, PORT88_FN4, MSEL4CR_15_0),
792 PINMUX_DATA(MMCD0_5_MARK, PORT89_FN4, MSEL4CR_15_0),
793 PINMUX_DATA(MMCD0_6_MARK, PORT90_FN4, MSEL4CR_15_0),
794 PINMUX_DATA(MMCD0_7_MARK, PORT91_FN4, MSEL4CR_15_0),
795 PINMUX_DATA(MMCCMD0_MARK, PORT92_FN4, MSEL4CR_15_0),
796 PINMUX_DATA(SIM_RST_MARK, PORT94_FN4),
797 PINMUX_DATA(SIM_CLK_MARK, PORT95_FN4),
798 PINMUX_DATA(SIM_D_MARK, PORT98_FN4),
799 PINMUX_DATA(MMCCLK0_MARK, PORT99_FN4, MSEL4CR_15_0),
800 PINMUX_DATA(IDIN_1_113_MARK, PORT113_FN4, MSEL4CR_14_0),
801 PINMUX_DATA(OVCN_1_114_MARK, PORT114_FN4, MSEL4CR_14_0),
802 PINMUX_DATA(PWEN_1_115_MARK, PORT115_FN4),
803 PINMUX_DATA(EXTLP_1_MARK, PORT116_FN4),
804 PINMUX_DATA(OVCN2_1_MARK, PORT117_FN4),
805 PINMUX_DATA(KEYIN0_121_MARK, PORT121_FN4, MSEL4CR_18_1),
806 PINMUX_DATA(KEYIN1_122_MARK, PORT122_FN4, MSEL4CR_18_1),
807 PINMUX_DATA(KEYIN2_123_MARK, PORT123_FN4, MSEL4CR_18_1),
808 PINMUX_DATA(KEYIN3_124_MARK, PORT124_FN4, MSEL4CR_18_1),
809 PINMUX_DATA(PWEN_1_138_MARK, PORT138_FN4),
810 PINMUX_DATA(IROUT_140_MARK, PORT140_FN4),
811 PINMUX_DATA(LCDCS_MARK, PORT145_FN4),
812 PINMUX_DATA(LCDWR_MARK, PORT147_FN4),
813 PINMUX_DATA(LCDRS_MARK, PORT149_FN4),
814 PINMUX_DATA(OVCN_1_162_MARK, PORT162_FN4, MSEL4CR_14_1),
815
816 /* Function 5 */
817 PINMUX_DATA(GPI0_MARK, PORT41_FN5),
818 PINMUX_DATA(GPI1_MARK, PORT42_FN5),
819 PINMUX_DATA(GPO0_MARK, PORT43_FN5),
820 PINMUX_DATA(GPO1_MARK, PORT44_FN5),
821 PINMUX_DATA(I2C_SCL3S_MARK, PORT137_FN5, MSEL4CR_16_0),
822 PINMUX_DATA(I2C_SDA3S_MARK, PORT145_FN5, MSEL4CR_16_0),
823 PINMUX_DATA(I2C_SCL4S_MARK, PORT146_FN5, MSEL4CR_17_0),
824 PINMUX_DATA(I2C_SDA4S_MARK, PORT147_FN5, MSEL4CR_17_0),
825
826 /* Function select */
827 PINMUX_DATA(LCDC0_SELECT_MARK, MSEL3CR_6_0),
828 PINMUX_DATA(LCDC1_SELECT_MARK, MSEL3CR_6_1),
829
830 PINMUX_DATA(TS0_1SELECT_MARK, MSEL3CR_21_0, MSEL3CR_20_0),
831 PINMUX_DATA(TS0_2SELECT_MARK, MSEL3CR_21_0, MSEL3CR_20_1),
832 PINMUX_DATA(TS1_1SELECT_MARK, MSEL3CR_27_0, MSEL3CR_26_0),
833 PINMUX_DATA(TS1_2SELECT_MARK, MSEL3CR_27_0, MSEL3CR_26_1),
834
835 PINMUX_DATA(SDENC_CPG_MARK, MSEL4CR_19_0),
836 PINMUX_DATA(SDENC_DV_CLKI_MARK, MSEL4CR_19_1),
837
838 PINMUX_DATA(MFIv6_MARK, MSEL4CR_6_0),
839 PINMUX_DATA(MFIv4_MARK, MSEL4CR_6_1),
840 };
841
842 #define SH7372_PIN(pin, cfgs) \
843 { \
844 .name = __stringify(PORT##pin), \
845 .enum_id = PORT##pin##_DATA, \
846 .configs = cfgs, \
847 }
848
849 #define __I (SH_PFC_PIN_CFG_INPUT)
850 #define __O (SH_PFC_PIN_CFG_OUTPUT)
851 #define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
852 #define __PD (SH_PFC_PIN_CFG_PULL_DOWN)
853 #define __PU (SH_PFC_PIN_CFG_PULL_UP)
854 #define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
855
856 #define SH7372_PIN_I_PD(pin) SH7372_PIN(pin, __I | __PD)
857 #define SH7372_PIN_I_PU(pin) SH7372_PIN(pin, __I | __PU)
858 #define SH7372_PIN_I_PU_PD(pin) SH7372_PIN(pin, __I | __PUD)
859 #define SH7372_PIN_IO(pin) SH7372_PIN(pin, __IO)
860 #define SH7372_PIN_IO_PD(pin) SH7372_PIN(pin, __IO | __PD)
861 #define SH7372_PIN_IO_PU(pin) SH7372_PIN(pin, __IO | __PU)
862 #define SH7372_PIN_IO_PU_PD(pin) SH7372_PIN(pin, __IO | __PUD)
863 #define SH7372_PIN_O(pin) SH7372_PIN(pin, __O)
864 #define SH7372_PIN_O_PU_PD(pin) SH7372_PIN(pin, __O | __PUD)
865
866 static struct sh_pfc_pin pinmux_pins[] = {
867 /* Table 57-1 (I/O and Pull U/D) */
868 SH7372_PIN_IO_PD(0), SH7372_PIN_IO_PD(1),
869 SH7372_PIN_O(2), SH7372_PIN_I_PD(3),
870 SH7372_PIN_I_PD(4), SH7372_PIN_I_PD(5),
871 SH7372_PIN_IO_PU_PD(6), SH7372_PIN_I_PD(7),
872 SH7372_PIN_IO_PD(8), SH7372_PIN_O(9),
873 SH7372_PIN_O(10), SH7372_PIN_O(11),
874 SH7372_PIN_IO_PU_PD(12), SH7372_PIN_IO_PD(13),
875 SH7372_PIN_IO_PD(14), SH7372_PIN_O(15),
876 SH7372_PIN_IO_PD(16), SH7372_PIN_IO_PD(17),
877 SH7372_PIN_I_PD(18), SH7372_PIN_IO(19),
878 SH7372_PIN_IO(20), SH7372_PIN_IO(21),
879 SH7372_PIN_IO(22), SH7372_PIN_IO(23),
880 SH7372_PIN_IO(24), SH7372_PIN_IO(25),
881 SH7372_PIN_IO(26), SH7372_PIN_IO(27),
882 SH7372_PIN_IO(28), SH7372_PIN_IO(29),
883 SH7372_PIN_IO(30), SH7372_PIN_IO(31),
884 SH7372_PIN_IO(32), SH7372_PIN_IO(33),
885 SH7372_PIN_IO(34), SH7372_PIN_IO(35),
886 SH7372_PIN_IO(36), SH7372_PIN_IO(37),
887 SH7372_PIN_IO(38), SH7372_PIN_IO(39),
888 SH7372_PIN_IO(40), SH7372_PIN_IO(41),
889 SH7372_PIN_IO(42), SH7372_PIN_IO(43),
890 SH7372_PIN_IO(44), SH7372_PIN_IO(45),
891 SH7372_PIN_IO_PU(46), SH7372_PIN_IO_PU(47),
892 SH7372_PIN_IO_PU(48), SH7372_PIN_IO_PU(49),
893 SH7372_PIN_IO_PU(50), SH7372_PIN_IO_PU(51),
894 SH7372_PIN_IO_PU(52), SH7372_PIN_IO_PU(53),
895 SH7372_PIN_IO_PU(54), SH7372_PIN_IO_PU(55),
896 SH7372_PIN_IO_PU(56), SH7372_PIN_IO_PU(57),
897 SH7372_PIN_IO_PU(58), SH7372_PIN_IO_PU(59),
898 SH7372_PIN_IO_PU(60), SH7372_PIN_IO_PU(61),
899 SH7372_PIN_IO(62), SH7372_PIN_O(63),
900 SH7372_PIN_O(64), SH7372_PIN_IO_PU(65),
901 SH7372_PIN_O_PU_PD(66), SH7372_PIN_IO_PU(67),
902 SH7372_PIN_O(68), SH7372_PIN_IO(69),
903 SH7372_PIN_IO(70), SH7372_PIN_IO(71),
904 SH7372_PIN_O(72), SH7372_PIN_I_PU(73),
905 SH7372_PIN_I_PU_PD(74), SH7372_PIN_IO_PU_PD(75),
906 SH7372_PIN_IO_PU_PD(76), SH7372_PIN_IO_PU_PD(77),
907 SH7372_PIN_IO_PU_PD(78), SH7372_PIN_IO_PU_PD(79),
908 SH7372_PIN_IO_PU_PD(80), SH7372_PIN_IO_PU_PD(81),
909 SH7372_PIN_IO_PU_PD(82), SH7372_PIN_IO_PU_PD(83),
910 SH7372_PIN_IO_PU_PD(84), SH7372_PIN_IO_PU_PD(85),
911 SH7372_PIN_IO_PU_PD(86), SH7372_PIN_IO_PU_PD(87),
912 SH7372_PIN_IO_PU_PD(88), SH7372_PIN_IO_PU_PD(89),
913 SH7372_PIN_IO_PU_PD(90), SH7372_PIN_IO_PU_PD(91),
914 SH7372_PIN_IO_PU_PD(92), SH7372_PIN_IO_PU_PD(93),
915 SH7372_PIN_IO_PU_PD(94), SH7372_PIN_IO_PU_PD(95),
916 SH7372_PIN_IO_PU(96), SH7372_PIN_IO_PU_PD(97),
917 SH7372_PIN_IO_PU_PD(98), SH7372_PIN_O_PU_PD(99),
918 SH7372_PIN_IO_PD(100), SH7372_PIN_IO_PD(101),
919 SH7372_PIN_IO_PD(102), SH7372_PIN_IO_PD(103),
920 SH7372_PIN_IO_PD(104), SH7372_PIN_IO_PD(105),
921 SH7372_PIN_IO_PU(106), SH7372_PIN_IO_PU(107),
922 SH7372_PIN_IO_PU(108), SH7372_PIN_IO_PU(109),
923 SH7372_PIN_IO_PU(110), SH7372_PIN_IO_PU(111),
924 SH7372_PIN_IO_PD(112), SH7372_PIN_IO_PD(113),
925 SH7372_PIN_IO_PU(114), SH7372_PIN_IO_PU(115),
926 SH7372_PIN_IO_PU(116), SH7372_PIN_IO_PU(117),
927 SH7372_PIN_IO_PU(118), SH7372_PIN_IO_PU(119),
928 SH7372_PIN_IO_PU(120), SH7372_PIN_IO_PD(121),
929 SH7372_PIN_IO_PD(122), SH7372_PIN_IO_PD(123),
930 SH7372_PIN_IO_PD(124), SH7372_PIN_IO_PD(125),
931 SH7372_PIN_IO_PD(126), SH7372_PIN_IO_PD(127),
932 SH7372_PIN_IO_PD(128), SH7372_PIN_IO_PU_PD(129),
933 SH7372_PIN_IO_PU_PD(130), SH7372_PIN_IO_PU_PD(131),
934 SH7372_PIN_IO_PU_PD(132), SH7372_PIN_IO_PU_PD(133),
935 SH7372_PIN_IO_PU_PD(134), SH7372_PIN_IO_PU_PD(135),
936 SH7372_PIN_IO_PD(136), SH7372_PIN_IO_PD(137),
937 SH7372_PIN_IO_PD(138), SH7372_PIN_IO_PD(139),
938 SH7372_PIN_IO_PD(140), SH7372_PIN_IO_PD(141),
939 SH7372_PIN_IO_PD(142), SH7372_PIN_IO_PU_PD(143),
940 SH7372_PIN_IO_PD(144), SH7372_PIN_IO_PD(145),
941 SH7372_PIN_IO_PD(146), SH7372_PIN_IO_PD(147),
942 SH7372_PIN_IO_PD(148), SH7372_PIN_IO_PD(149),
943 SH7372_PIN_IO_PD(150), SH7372_PIN_IO_PD(151),
944 SH7372_PIN_IO_PU_PD(152), SH7372_PIN_I_PD(153),
945 SH7372_PIN_IO_PU_PD(154), SH7372_PIN_I_PD(155),
946 SH7372_PIN_IO_PD(156), SH7372_PIN_IO_PD(157),
947 SH7372_PIN_I_PD(158), SH7372_PIN_IO_PD(159),
948 SH7372_PIN_O(160), SH7372_PIN_IO_PD(161),
949 SH7372_PIN_IO_PD(162), SH7372_PIN_IO_PD(163),
950 SH7372_PIN_I_PD(164), SH7372_PIN_IO_PD(165),
951 SH7372_PIN_I_PD(166), SH7372_PIN_I_PD(167),
952 SH7372_PIN_I_PD(168), SH7372_PIN_I_PD(169),
953 SH7372_PIN_I_PD(170), SH7372_PIN_O(171),
954 SH7372_PIN_IO_PU_PD(172), SH7372_PIN_IO_PU_PD(173),
955 SH7372_PIN_IO_PU_PD(174), SH7372_PIN_IO_PU_PD(175),
956 SH7372_PIN_IO_PU_PD(176), SH7372_PIN_IO_PU_PD(177),
957 SH7372_PIN_IO_PU_PD(178), SH7372_PIN_O(179),
958 SH7372_PIN_IO_PU_PD(180), SH7372_PIN_IO_PU_PD(181),
959 SH7372_PIN_IO_PU_PD(182), SH7372_PIN_IO_PU_PD(183),
960 SH7372_PIN_IO_PU_PD(184), SH7372_PIN_O(185),
961 SH7372_PIN_IO_PU_PD(186), SH7372_PIN_IO_PU_PD(187),
962 SH7372_PIN_IO_PU_PD(188), SH7372_PIN_IO_PU_PD(189),
963 SH7372_PIN_IO_PU_PD(190),
964 };
965
966 /* - BSC -------------------------------------------------------------------- */
967 static const unsigned int bsc_data8_pins[] = {
968 /* D[0:7] */
969 46, 47, 48, 49, 50, 51, 52, 53,
970 };
971 static const unsigned int bsc_data8_mux[] = {
972 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
973 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
974 };
975 static const unsigned int bsc_data16_pins[] = {
976 /* D[0:15] */
977 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
978 };
979 static const unsigned int bsc_data16_mux[] = {
980 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
981 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
982 D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
983 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
984 };
985 static const unsigned int bsc_cs0_pins[] = {
986 /* CS */
987 62,
988 };
989 static const unsigned int bsc_cs0_mux[] = {
990 CS0_MARK,
991 };
992 static const unsigned int bsc_cs2_pins[] = {
993 /* CS */
994 63,
995 };
996 static const unsigned int bsc_cs2_mux[] = {
997 CS2_MARK,
998 };
999 static const unsigned int bsc_cs4_pins[] = {
1000 /* CS */
1001 64,
1002 };
1003 static const unsigned int bsc_cs4_mux[] = {
1004 CS4_MARK,
1005 };
1006 static const unsigned int bsc_cs5a_pins[] = {
1007 /* CS */
1008 65,
1009 };
1010 static const unsigned int bsc_cs5a_mux[] = {
1011 CS5A_MARK,
1012 };
1013 static const unsigned int bsc_cs5b_pins[] = {
1014 /* CS */
1015 66,
1016 };
1017 static const unsigned int bsc_cs5b_mux[] = {
1018 CS5B_MARK,
1019 };
1020 static const unsigned int bsc_cs6a_pins[] = {
1021 /* CS */
1022 67,
1023 };
1024 static const unsigned int bsc_cs6a_mux[] = {
1025 CS6A_MARK,
1026 };
1027 static const unsigned int bsc_rd_we8_pins[] = {
1028 /* RD, WE[0] */
1029 69, 70,
1030 };
1031 static const unsigned int bsc_rd_we8_mux[] = {
1032 RD_FSC_MARK, WE0_FWE_MARK,
1033 };
1034 static const unsigned int bsc_rd_we16_pins[] = {
1035 /* RD, WE[0:1] */
1036 69, 70, 71,
1037 };
1038 static const unsigned int bsc_rd_we16_mux[] = {
1039 RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK,
1040 };
1041 static const unsigned int bsc_bs_pins[] = {
1042 /* BS */
1043 19,
1044 };
1045 static const unsigned int bsc_bs_mux[] = {
1046 BS_MARK,
1047 };
1048 static const unsigned int bsc_rdwr_pins[] = {
1049 /* RDWR */
1050 75,
1051 };
1052 static const unsigned int bsc_rdwr_mux[] = {
1053 RDWR_MARK,
1054 };
1055 static const unsigned int bsc_wait_pins[] = {
1056 /* WAIT */
1057 74,
1058 };
1059 static const unsigned int bsc_wait_mux[] = {
1060 WAIT_MARK,
1061 };
1062 /* - CEU -------------------------------------------------------------------- */
1063 static const unsigned int ceu_data_0_7_pins[] = {
1064 /* D[0:7] */
1065 102, 103, 104, 105, 106, 107, 108, 109,
1066 };
1067 static const unsigned int ceu_data_0_7_mux[] = {
1068 VIO_D0_MARK, VIO_D1_MARK, VIO_D2_MARK, VIO_D3_MARK,
1069 VIO_D4_MARK, VIO_D5_MARK, VIO_D6_MARK, VIO_D7_MARK,
1070 };
1071 static const unsigned int ceu_data_8_15_pins[] = {
1072 /* D[8:15] */
1073 110, 111, 112, 113, 114, 115, 116, 117,
1074 };
1075 static const unsigned int ceu_data_8_15_mux[] = {
1076 VIO_D8_MARK, VIO_D9_MARK, VIO_D10_MARK, VIO_D11_MARK,
1077 VIO_D12_MARK, VIO_D13_MARK, VIO_D14_MARK, VIO_D15_MARK,
1078 };
1079 static const unsigned int ceu_clk_0_pins[] = {
1080 /* CKO */
1081 120,
1082 };
1083 static const unsigned int ceu_clk_0_mux[] = {
1084 VIO_CKO_MARK,
1085 };
1086 static const unsigned int ceu_clk_1_pins[] = {
1087 /* CKO */
1088 16,
1089 };
1090 static const unsigned int ceu_clk_1_mux[] = {
1091 VIO_CKO1_MARK,
1092 };
1093 static const unsigned int ceu_clk_2_pins[] = {
1094 /* CKO */
1095 17,
1096 };
1097 static const unsigned int ceu_clk_2_mux[] = {
1098 VIO_CKO2_MARK,
1099 };
1100 static const unsigned int ceu_sync_pins[] = {
1101 /* CLK, VD, HD */
1102 118, 100, 101,
1103 };
1104 static const unsigned int ceu_sync_mux[] = {
1105 VIO_CLK_MARK, VIO_VD_MARK, VIO_HD_MARK,
1106 };
1107 static const unsigned int ceu_field_pins[] = {
1108 /* FIELD */
1109 119,
1110 };
1111 static const unsigned int ceu_field_mux[] = {
1112 VIO_FIELD_MARK,
1113 };
1114 /* - FLCTL ------------------------------------------------------------------ */
1115 static const unsigned int flctl_data_pins[] = {
1116 /* NAF[0:15] */
1117 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
1118 };
1119 static const unsigned int flctl_data_mux[] = {
1120 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1121 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1122 D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
1123 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
1124 };
1125 static const unsigned int flctl_ce0_pins[] = {
1126 /* CE */
1127 68,
1128 };
1129 static const unsigned int flctl_ce0_mux[] = {
1130 FCE0_MARK,
1131 };
1132 static const unsigned int flctl_ce1_pins[] = {
1133 /* CE */
1134 66,
1135 };
1136 static const unsigned int flctl_ce1_mux[] = {
1137 FCE1_MARK,
1138 };
1139 static const unsigned int flctl_ctrl_pins[] = {
1140 /* FCDE, FOE, FSC, FWE, FRB */
1141 24, 23, 69, 70, 73,
1142 };
1143 static const unsigned int flctl_ctrl_mux[] = {
1144 A5_FCDE_MARK, A4_FOE_MARK, RD_FSC_MARK, WE0_FWE_MARK, FRB_MARK,
1145 };
1146 /* - FSIA ------------------------------------------------------------------- */
1147 static const unsigned int fsia_mclk_in_pins[] = {
1148 /* CK */
1149 4,
1150 };
1151 static const unsigned int fsia_mclk_in_mux[] = {
1152 FSIACK_MARK,
1153 };
1154 static const unsigned int fsia_mclk_out_pins[] = {
1155 /* OMC */
1156 8,
1157 };
1158 static const unsigned int fsia_mclk_out_mux[] = {
1159 FSIAOMC_MARK,
1160 };
1161 static const unsigned int fsia_sclk_in_pins[] = {
1162 /* ILR, IBT */
1163 5, 6,
1164 };
1165 static const unsigned int fsia_sclk_in_mux[] = {
1166 FSIAILR_MARK, FSIAIBT_MARK,
1167 };
1168 static const unsigned int fsia_sclk_out_pins[] = {
1169 /* OLR, OBT */
1170 9, 10,
1171 };
1172 static const unsigned int fsia_sclk_out_mux[] = {
1173 FSIAOLR_MARK, FSIAOBT_MARK,
1174 };
1175 static const unsigned int fsia_data_in_pins[] = {
1176 /* ISLD */
1177 7,
1178 };
1179 static const unsigned int fsia_data_in_mux[] = {
1180 FSIAISLD_MARK,
1181 };
1182 static const unsigned int fsia_data_out_pins[] = {
1183 /* OSLD */
1184 11,
1185 };
1186 static const unsigned int fsia_data_out_mux[] = {
1187 FSIAOSLD_MARK,
1188 };
1189 static const unsigned int fsia_spdif_0_pins[] = {
1190 /* SPDIF */
1191 11,
1192 };
1193 static const unsigned int fsia_spdif_0_mux[] = {
1194 FSIASPDIF_11_MARK,
1195 };
1196 static const unsigned int fsia_spdif_1_pins[] = {
1197 /* SPDIF */
1198 15,
1199 };
1200 static const unsigned int fsia_spdif_1_mux[] = {
1201 FSIASPDIF_15_MARK,
1202 };
1203 /* - FSIB ------------------------------------------------------------------- */
1204 static const unsigned int fsib_mclk_in_pins[] = {
1205 /* CK */
1206 4,
1207 };
1208 static const unsigned int fsib_mclk_in_mux[] = {
1209 FSIBCK_MARK,
1210 };
1211 /* - HDMI ------------------------------------------------------------------- */
1212 static const unsigned int hdmi_pins[] = {
1213 /* HPD, CEC */
1214 169, 170,
1215 };
1216 static const unsigned int hdmi_mux[] = {
1217 HDMI_HPD_MARK, HDMI_CEC_MARK,
1218 };
1219 /* - INTC ------------------------------------------------------------------- */
1220 IRQC_PINS_MUX(0, 6, 162);
1221 IRQC_PIN_MUX(1, 12);
1222 IRQC_PINS_MUX(2, 4, 5);
1223 IRQC_PINS_MUX(3, 8, 16);
1224 IRQC_PINS_MUX(4, 17, 163);
1225 IRQC_PIN_MUX(5, 18);
1226 IRQC_PINS_MUX(6, 39, 164);
1227 IRQC_PINS_MUX(7, 40, 167);
1228 IRQC_PINS_MUX(8, 41, 168);
1229 IRQC_PINS_MUX(9, 42, 169);
1230 IRQC_PIN_MUX(10, 65);
1231 IRQC_PIN_MUX(11, 67);
1232 IRQC_PINS_MUX(12, 80, 137);
1233 IRQC_PINS_MUX(13, 81, 145);
1234 IRQC_PINS_MUX(14, 82, 146);
1235 IRQC_PINS_MUX(15, 83, 147);
1236 IRQC_PINS_MUX(16, 84, 170);
1237 IRQC_PIN_MUX(17, 85);
1238 IRQC_PIN_MUX(18, 86);
1239 IRQC_PIN_MUX(19, 87);
1240 IRQC_PIN_MUX(20, 92);
1241 IRQC_PIN_MUX(21, 93);
1242 IRQC_PIN_MUX(22, 94);
1243 IRQC_PIN_MUX(23, 95);
1244 IRQC_PIN_MUX(24, 112);
1245 IRQC_PIN_MUX(25, 119);
1246 IRQC_PINS_MUX(26, 121, 172);
1247 IRQC_PINS_MUX(27, 122, 180);
1248 IRQC_PINS_MUX(28, 123, 181);
1249 IRQC_PINS_MUX(29, 129, 182);
1250 IRQC_PINS_MUX(30, 130, 183);
1251 IRQC_PINS_MUX(31, 138, 184);
1252 /* - KEYSC ------------------------------------------------------------------ */
1253 static const unsigned int keysc_in04_0_pins[] = {
1254 /* KEYIN[0:4] */
1255 136, 135, 134, 133, 132,
1256 };
1257 static const unsigned int keysc_in04_0_mux[] = {
1258 KEYIN0_136_MARK, KEYIN1_135_MARK, KEYIN2_134_MARK, KEYIN3_133_MARK,
1259 KEYIN4_MARK,
1260 };
1261 static const unsigned int keysc_in04_1_pins[] = {
1262 /* KEYIN[0:4] */
1263 121, 122, 123, 124, 132,
1264 };
1265 static const unsigned int keysc_in04_1_mux[] = {
1266 KEYIN0_121_MARK, KEYIN1_122_MARK, KEYIN2_123_MARK, KEYIN3_124_MARK,
1267 KEYIN4_MARK,
1268 };
1269 static const unsigned int keysc_in5_pins[] = {
1270 /* KEYIN5 */
1271 131,
1272 };
1273 static const unsigned int keysc_in5_mux[] = {
1274 KEYIN5_MARK,
1275 };
1276 static const unsigned int keysc_in6_pins[] = {
1277 /* KEYIN6 */
1278 130,
1279 };
1280 static const unsigned int keysc_in6_mux[] = {
1281 KEYIN6_MARK,
1282 };
1283 static const unsigned int keysc_in7_pins[] = {
1284 /* KEYIN7 */
1285 129,
1286 };
1287 static const unsigned int keysc_in7_mux[] = {
1288 KEYIN7_MARK,
1289 };
1290 static const unsigned int keysc_out4_pins[] = {
1291 /* KEYOUT[0:3] */
1292 128, 127, 126, 125,
1293 };
1294 static const unsigned int keysc_out4_mux[] = {
1295 KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
1296 };
1297 static const unsigned int keysc_out5_pins[] = {
1298 /* KEYOUT[0:4] */
1299 128, 127, 126, 125, 124,
1300 };
1301 static const unsigned int keysc_out5_mux[] = {
1302 KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
1303 KEYOUT4_MARK,
1304 };
1305 static const unsigned int keysc_out6_pins[] = {
1306 /* KEYOUT[0:5] */
1307 128, 127, 126, 125, 124, 123,
1308 };
1309 static const unsigned int keysc_out6_mux[] = {
1310 KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
1311 KEYOUT4_MARK, KEYOUT5_MARK,
1312 };
1313 static const unsigned int keysc_out8_pins[] = {
1314 /* KEYOUT[0:7] */
1315 128, 127, 126, 125, 124, 123, 122, 121,
1316 };
1317 static const unsigned int keysc_out8_mux[] = {
1318 KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
1319 KEYOUT4_MARK, KEYOUT5_MARK, KEYOUT6_MARK, KEYOUT7_MARK,
1320 };
1321 /* - LCD -------------------------------------------------------------------- */
1322 static const unsigned int lcd_data8_pins[] = {
1323 /* D[0:7] */
1324 121, 122, 123, 124, 125, 126, 127, 128,
1325 };
1326 static const unsigned int lcd_data8_mux[] = {
1327 /* LCDC */
1328 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1329 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1330 };
1331 static const unsigned int lcd_data9_pins[] = {
1332 /* D[0:8] */
1333 121, 122, 123, 124, 125, 126, 127, 128,
1334 129,
1335 137, 138, 139, 140, 141, 142, 143, 144,
1336 };
1337 static const unsigned int lcd_data9_mux[] = {
1338 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1339 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1340 LCDD8_MARK,
1341 };
1342 static const unsigned int lcd_data12_pins[] = {
1343 /* D[0:11] */
1344 121, 122, 123, 124, 125, 126, 127, 128,
1345 129, 130, 131, 132,
1346 };
1347 static const unsigned int lcd_data12_mux[] = {
1348 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1349 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1350 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1351 };
1352 static const unsigned int lcd_data16_pins[] = {
1353 /* D[0:15] */
1354 121, 122, 123, 124, 125, 126, 127, 128,
1355 129, 130, 131, 132, 133, 134, 135, 136,
1356 };
1357 static const unsigned int lcd_data16_mux[] = {
1358 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1359 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1360 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1361 LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
1362 };
1363 static const unsigned int lcd_data18_pins[] = {
1364 /* D[0:17] */
1365 121, 122, 123, 124, 125, 126, 127, 128,
1366 129, 130, 131, 132, 133, 134, 135, 136,
1367 137, 138,
1368 };
1369 static const unsigned int lcd_data18_mux[] = {
1370 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1371 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1372 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1373 LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
1374 LCDD16_MARK, LCDD17_MARK,
1375 };
1376 static const unsigned int lcd_data24_pins[] = {
1377 /* D[0:23] */
1378 121, 122, 123, 124, 125, 126, 127, 128,
1379 129, 130, 131, 132, 133, 134, 135, 136,
1380 137, 138, 139, 140, 141, 142, 143, 144,
1381 };
1382 static const unsigned int lcd_data24_mux[] = {
1383 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1384 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1385 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1386 LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
1387 LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK,
1388 LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK,
1389 };
1390 static const unsigned int lcd_display_pins[] = {
1391 /* DON */
1392 151,
1393 };
1394 static const unsigned int lcd_display_mux[] = {
1395 LCDDON_MARK,
1396 };
1397 static const unsigned int lcd_lclk_pins[] = {
1398 /* LCLK */
1399 150,
1400 };
1401 static const unsigned int lcd_lclk_mux[] = {
1402 LCDLCLK_MARK,
1403 };
1404 static const unsigned int lcd_sync_pins[] = {
1405 /* VSYN, HSYN, DCK, DISP */
1406 146, 145, 147, 149,
1407 };
1408 static const unsigned int lcd_sync_mux[] = {
1409 LCDVSYN_MARK, LCDHSYN_MARK, LCDDCK_MARK, LCDDISP_MARK,
1410 };
1411 static const unsigned int lcd_sys_pins[] = {
1412 /* CS, WR, RD, RS */
1413 145, 147, 148, 149,
1414 };
1415 static const unsigned int lcd_sys_mux[] = {
1416 LCDCS_MARK, LCDWR_MARK, LCDRD_MARK, LCDRS_MARK,
1417 };
1418 /* - MMCIF ------------------------------------------------------------------ */
1419 static const unsigned int mmc0_data1_0_pins[] = {
1420 /* D[0] */
1421 84,
1422 };
1423 static const unsigned int mmc0_data1_0_mux[] = {
1424 MMCD0_0_MARK,
1425 };
1426 static const unsigned int mmc0_data4_0_pins[] = {
1427 /* D[0:3] */
1428 84, 85, 86, 87,
1429 };
1430 static const unsigned int mmc0_data4_0_mux[] = {
1431 MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
1432 };
1433 static const unsigned int mmc0_data8_0_pins[] = {
1434 /* D[0:7] */
1435 84, 85, 86, 87, 88, 89, 90, 91,
1436 };
1437 static const unsigned int mmc0_data8_0_mux[] = {
1438 MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
1439 MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
1440 };
1441 static const unsigned int mmc0_ctrl_0_pins[] = {
1442 /* CMD, CLK */
1443 92, 99,
1444 };
1445 static const unsigned int mmc0_ctrl_0_mux[] = {
1446 MMCCMD0_MARK, MMCCLK0_MARK,
1447 };
1448
1449 static const unsigned int mmc0_data1_1_pins[] = {
1450 /* D[0] */
1451 54,
1452 };
1453 static const unsigned int mmc0_data1_1_mux[] = {
1454 MMCD1_0_MARK,
1455 };
1456 static const unsigned int mmc0_data4_1_pins[] = {
1457 /* D[0:3] */
1458 54, 55, 56, 57,
1459 };
1460 static const unsigned int mmc0_data4_1_mux[] = {
1461 MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
1462 };
1463 static const unsigned int mmc0_data8_1_pins[] = {
1464 /* D[0:7] */
1465 54, 55, 56, 57, 58, 59, 60, 61,
1466 };
1467 static const unsigned int mmc0_data8_1_mux[] = {
1468 MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
1469 MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
1470 };
1471 static const unsigned int mmc0_ctrl_1_pins[] = {
1472 /* CMD, CLK */
1473 67, 66,
1474 };
1475 static const unsigned int mmc0_ctrl_1_mux[] = {
1476 MMCCMD1_MARK, MMCCLK1_MARK,
1477 };
1478 /* - SCIFA0 ----------------------------------------------------------------- */
1479 static const unsigned int scifa0_data_pins[] = {
1480 /* RXD, TXD */
1481 153, 152,
1482 };
1483 static const unsigned int scifa0_data_mux[] = {
1484 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
1485 };
1486 static const unsigned int scifa0_clk_pins[] = {
1487 /* SCK */
1488 156,
1489 };
1490 static const unsigned int scifa0_clk_mux[] = {
1491 SCIFA0_SCK_MARK,
1492 };
1493 static const unsigned int scifa0_ctrl_pins[] = {
1494 /* RTS, CTS */
1495 157, 158,
1496 };
1497 static const unsigned int scifa0_ctrl_mux[] = {
1498 SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
1499 };
1500 /* - SCIFA1 ----------------------------------------------------------------- */
1501 static const unsigned int scifa1_data_pins[] = {
1502 /* RXD, TXD */
1503 155, 154,
1504 };
1505 static const unsigned int scifa1_data_mux[] = {
1506 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
1507 };
1508 static const unsigned int scifa1_clk_pins[] = {
1509 /* SCK */
1510 159,
1511 };
1512 static const unsigned int scifa1_clk_mux[] = {
1513 SCIFA1_SCK_MARK,
1514 };
1515 static const unsigned int scifa1_ctrl_pins[] = {
1516 /* RTS, CTS */
1517 160, 161,
1518 };
1519 static const unsigned int scifa1_ctrl_mux[] = {
1520 SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
1521 };
1522 /* - SCIFA2 ----------------------------------------------------------------- */
1523 static const unsigned int scifa2_data_pins[] = {
1524 /* RXD, TXD */
1525 97, 96,
1526 };
1527 static const unsigned int scifa2_data_mux[] = {
1528 SCIFA2_RXD1_MARK, SCIFA2_TXD1_MARK,
1529 };
1530 static const unsigned int scifa2_clk_pins[] = {
1531 /* SCK */
1532 98,
1533 };
1534 static const unsigned int scifa2_clk_mux[] = {
1535 SCIFA2_SCK1_MARK,
1536 };
1537 static const unsigned int scifa2_ctrl_pins[] = {
1538 /* RTS, CTS */
1539 95, 94,
1540 };
1541 static const unsigned int scifa2_ctrl_mux[] = {
1542 SCIFA2_RTS1_MARK, SCIFA2_CTS1_MARK,
1543 };
1544 /* - SCIFA3 ----------------------------------------------------------------- */
1545 static const unsigned int scifa3_data_pins[] = {
1546 /* RXD, TXD */
1547 144, 143,
1548 };
1549 static const unsigned int scifa3_data_mux[] = {
1550 SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
1551 };
1552 static const unsigned int scifa3_clk_pins[] = {
1553 /* SCK */
1554 142,
1555 };
1556 static const unsigned int scifa3_clk_mux[] = {
1557 SCIFA3_SCK_MARK,
1558 };
1559 static const unsigned int scifa3_ctrl_0_pins[] = {
1560 /* RTS, CTS */
1561 44, 43,
1562 };
1563 static const unsigned int scifa3_ctrl_0_mux[] = {
1564 SCIFA3_RTS_44_MARK, SCIFA3_CTS_43_MARK,
1565 };
1566 static const unsigned int scifa3_ctrl_1_pins[] = {
1567 /* RTS, CTS */
1568 141, 140,
1569 };
1570 static const unsigned int scifa3_ctrl_1_mux[] = {
1571 SCIFA3_RTS_141_MARK, SCIFA3_CTS_140_MARK,
1572 };
1573 /* - SCIFA4 ----------------------------------------------------------------- */
1574 static const unsigned int scifa4_data_pins[] = {
1575 /* RXD, TXD */
1576 5, 6,
1577 };
1578 static const unsigned int scifa4_data_mux[] = {
1579 SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
1580 };
1581 /* - SCIFA5 ----------------------------------------------------------------- */
1582 static const unsigned int scifa5_data_pins[] = {
1583 /* RXD, TXD */
1584 8, 12,
1585 };
1586 static const unsigned int scifa5_data_mux[] = {
1587 SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
1588 };
1589 /* - SCIFB ------------------------------------------------------------------ */
1590 static const unsigned int scifb_data_pins[] = {
1591 /* RXD, TXD */
1592 166, 165,
1593 };
1594 static const unsigned int scifb_data_mux[] = {
1595 SCIFB_RXD_MARK, SCIFB_TXD_MARK,
1596 };
1597 static const unsigned int scifb_clk_pins[] = {
1598 /* SCK */
1599 162,
1600 };
1601 static const unsigned int scifb_clk_mux[] = {
1602 SCIFB_SCK_MARK,
1603 };
1604 static const unsigned int scifb_ctrl_pins[] = {
1605 /* RTS, CTS */
1606 163, 164,
1607 };
1608 static const unsigned int scifb_ctrl_mux[] = {
1609 SCIFB_RTS_MARK, SCIFB_CTS_MARK,
1610 };
1611 /* - SDHI0 ------------------------------------------------------------------ */
1612 static const unsigned int sdhi0_data1_pins[] = {
1613 /* D0 */
1614 173,
1615 };
1616 static const unsigned int sdhi0_data1_mux[] = {
1617 SDHID0_0_MARK,
1618 };
1619 static const unsigned int sdhi0_data4_pins[] = {
1620 /* D[0:3] */
1621 173, 174, 175, 176,
1622 };
1623 static const unsigned int sdhi0_data4_mux[] = {
1624 SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
1625 };
1626 static const unsigned int sdhi0_ctrl_pins[] = {
1627 /* CMD, CLK */
1628 177, 171,
1629 };
1630 static const unsigned int sdhi0_ctrl_mux[] = {
1631 SDHICMD0_MARK, SDHICLK0_MARK,
1632 };
1633 static const unsigned int sdhi0_cd_pins[] = {
1634 /* CD */
1635 172,
1636 };
1637 static const unsigned int sdhi0_cd_mux[] = {
1638 SDHICD0_MARK,
1639 };
1640 static const unsigned int sdhi0_wp_pins[] = {
1641 /* WP */
1642 178,
1643 };
1644 static const unsigned int sdhi0_wp_mux[] = {
1645 SDHIWP0_MARK,
1646 };
1647 /* - SDHI1 ------------------------------------------------------------------ */
1648 static const unsigned int sdhi1_data1_pins[] = {
1649 /* D0 */
1650 180,
1651 };
1652 static const unsigned int sdhi1_data1_mux[] = {
1653 SDHID1_0_MARK,
1654 };
1655 static const unsigned int sdhi1_data4_pins[] = {
1656 /* D[0:3] */
1657 180, 181, 182, 183,
1658 };
1659 static const unsigned int sdhi1_data4_mux[] = {
1660 SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
1661 };
1662 static const unsigned int sdhi1_ctrl_pins[] = {
1663 /* CMD, CLK */
1664 184, 179,
1665 };
1666 static const unsigned int sdhi1_ctrl_mux[] = {
1667 SDHICMD1_MARK, SDHICLK1_MARK,
1668 };
1669
1670 static const unsigned int sdhi2_data1_pins[] = {
1671 /* D0 */
1672 186,
1673 };
1674 static const unsigned int sdhi2_data1_mux[] = {
1675 SDHID2_0_MARK,
1676 };
1677 static const unsigned int sdhi2_data4_pins[] = {
1678 /* D[0:3] */
1679 186, 187, 188, 189,
1680 };
1681 static const unsigned int sdhi2_data4_mux[] = {
1682 SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
1683 };
1684 static const unsigned int sdhi2_ctrl_pins[] = {
1685 /* CMD, CLK */
1686 190, 185,
1687 };
1688 static const unsigned int sdhi2_ctrl_mux[] = {
1689 SDHICMD2_MARK, SDHICLK2_MARK,
1690 };
1691 /* - USB0 ------------------------------------------------------------------- */
1692 static const unsigned int usb0_vbus_pins[] = {
1693 /* VBUS */
1694 167,
1695 };
1696 static const unsigned int usb0_vbus_mux[] = {
1697 VBUS0_0_MARK,
1698 };
1699 static const unsigned int usb0_otg_id_pins[] = {
1700 /* IDIN */
1701 113,
1702 };
1703 static const unsigned int usb0_otg_id_mux[] = {
1704 IDIN_0_MARK,
1705 };
1706 static const unsigned int usb0_otg_ctrl_pins[] = {
1707 /* PWEN, EXTLP, OVCN, OVCN2 */
1708 116, 114, 117, 115,
1709 };
1710 static const unsigned int usb0_otg_ctrl_mux[] = {
1711 PWEN_0_MARK, EXTLP_0_MARK, OVCN_0_MARK, OVCN2_0_MARK,
1712 };
1713 /* - USB1 ------------------------------------------------------------------- */
1714 static const unsigned int usb1_vbus_pins[] = {
1715 /* VBUS */
1716 168,
1717 };
1718 static const unsigned int usb1_vbus_mux[] = {
1719 VBUS0_1_MARK,
1720 };
1721 static const unsigned int usb1_otg_id_0_pins[] = {
1722 /* IDIN */
1723 113,
1724 };
1725 static const unsigned int usb1_otg_id_0_mux[] = {
1726 IDIN_1_113_MARK,
1727 };
1728 static const unsigned int usb1_otg_id_1_pins[] = {
1729 /* IDIN */
1730 18,
1731 };
1732 static const unsigned int usb1_otg_id_1_mux[] = {
1733 IDIN_1_18_MARK,
1734 };
1735 static const unsigned int usb1_otg_ctrl_0_pins[] = {
1736 /* PWEN, EXTLP, OVCN, OVCN2 */
1737 115, 116, 114, 117, 113,
1738 };
1739 static const unsigned int usb1_otg_ctrl_0_mux[] = {
1740 PWEN_1_115_MARK, EXTLP_1_MARK, OVCN_1_114_MARK, OVCN2_1_MARK,
1741 };
1742 static const unsigned int usb1_otg_ctrl_1_pins[] = {
1743 /* PWEN, EXTLP, OVCN, OVCN2 */
1744 138, 116, 162, 117, 18,
1745 };
1746 static const unsigned int usb1_otg_ctrl_1_mux[] = {
1747 PWEN_1_138_MARK, EXTLP_1_MARK, OVCN_1_162_MARK, OVCN2_1_MARK,
1748 };
1749
1750 static const struct sh_pfc_pin_group pinmux_groups[] = {
1751 SH_PFC_PIN_GROUP(bsc_data8),
1752 SH_PFC_PIN_GROUP(bsc_data16),
1753 SH_PFC_PIN_GROUP(bsc_cs0),
1754 SH_PFC_PIN_GROUP(bsc_cs2),
1755 SH_PFC_PIN_GROUP(bsc_cs4),
1756 SH_PFC_PIN_GROUP(bsc_cs5a),
1757 SH_PFC_PIN_GROUP(bsc_cs5b),
1758 SH_PFC_PIN_GROUP(bsc_cs6a),
1759 SH_PFC_PIN_GROUP(bsc_rd_we8),
1760 SH_PFC_PIN_GROUP(bsc_rd_we16),
1761 SH_PFC_PIN_GROUP(bsc_bs),
1762 SH_PFC_PIN_GROUP(bsc_rdwr),
1763 SH_PFC_PIN_GROUP(ceu_data_0_7),
1764 SH_PFC_PIN_GROUP(ceu_data_8_15),
1765 SH_PFC_PIN_GROUP(ceu_clk_0),
1766 SH_PFC_PIN_GROUP(ceu_clk_1),
1767 SH_PFC_PIN_GROUP(ceu_clk_2),
1768 SH_PFC_PIN_GROUP(ceu_sync),
1769 SH_PFC_PIN_GROUP(ceu_field),
1770 SH_PFC_PIN_GROUP(flctl_data),
1771 SH_PFC_PIN_GROUP(flctl_ce0),
1772 SH_PFC_PIN_GROUP(flctl_ce1),
1773 SH_PFC_PIN_GROUP(flctl_ctrl),
1774 SH_PFC_PIN_GROUP(fsia_mclk_in),
1775 SH_PFC_PIN_GROUP(fsia_mclk_out),
1776 SH_PFC_PIN_GROUP(fsia_sclk_in),
1777 SH_PFC_PIN_GROUP(fsia_sclk_out),
1778 SH_PFC_PIN_GROUP(fsia_data_in),
1779 SH_PFC_PIN_GROUP(fsia_data_out),
1780 SH_PFC_PIN_GROUP(fsia_spdif_0),
1781 SH_PFC_PIN_GROUP(fsia_spdif_1),
1782 SH_PFC_PIN_GROUP(fsib_mclk_in),
1783 SH_PFC_PIN_GROUP(hdmi),
1784 SH_PFC_PIN_GROUP(intc_irq0_0),
1785 SH_PFC_PIN_GROUP(intc_irq0_1),
1786 SH_PFC_PIN_GROUP(intc_irq1),
1787 SH_PFC_PIN_GROUP(intc_irq2_0),
1788 SH_PFC_PIN_GROUP(intc_irq2_1),
1789 SH_PFC_PIN_GROUP(intc_irq3_0),
1790 SH_PFC_PIN_GROUP(intc_irq3_1),
1791 SH_PFC_PIN_GROUP(intc_irq4_0),
1792 SH_PFC_PIN_GROUP(intc_irq4_1),
1793 SH_PFC_PIN_GROUP(intc_irq5),
1794 SH_PFC_PIN_GROUP(intc_irq6_0),
1795 SH_PFC_PIN_GROUP(intc_irq6_1),
1796 SH_PFC_PIN_GROUP(intc_irq7_0),
1797 SH_PFC_PIN_GROUP(intc_irq7_1),
1798 SH_PFC_PIN_GROUP(intc_irq8_0),
1799 SH_PFC_PIN_GROUP(intc_irq8_1),
1800 SH_PFC_PIN_GROUP(intc_irq9_0),
1801 SH_PFC_PIN_GROUP(intc_irq9_1),
1802 SH_PFC_PIN_GROUP(intc_irq10),
1803 SH_PFC_PIN_GROUP(intc_irq11),
1804 SH_PFC_PIN_GROUP(intc_irq12_0),
1805 SH_PFC_PIN_GROUP(intc_irq12_1),
1806 SH_PFC_PIN_GROUP(intc_irq13_0),
1807 SH_PFC_PIN_GROUP(intc_irq13_1),
1808 SH_PFC_PIN_GROUP(intc_irq14_0),
1809 SH_PFC_PIN_GROUP(intc_irq14_1),
1810 SH_PFC_PIN_GROUP(intc_irq15_0),
1811 SH_PFC_PIN_GROUP(intc_irq15_1),
1812 SH_PFC_PIN_GROUP(intc_irq16_0),
1813 SH_PFC_PIN_GROUP(intc_irq16_1),
1814 SH_PFC_PIN_GROUP(intc_irq17),
1815 SH_PFC_PIN_GROUP(intc_irq18),
1816 SH_PFC_PIN_GROUP(intc_irq19),
1817 SH_PFC_PIN_GROUP(intc_irq20),
1818 SH_PFC_PIN_GROUP(intc_irq21),
1819 SH_PFC_PIN_GROUP(intc_irq22),
1820 SH_PFC_PIN_GROUP(intc_irq23),
1821 SH_PFC_PIN_GROUP(intc_irq24),
1822 SH_PFC_PIN_GROUP(intc_irq25),
1823 SH_PFC_PIN_GROUP(intc_irq26_0),
1824 SH_PFC_PIN_GROUP(intc_irq26_1),
1825 SH_PFC_PIN_GROUP(intc_irq27_0),
1826 SH_PFC_PIN_GROUP(intc_irq27_1),
1827 SH_PFC_PIN_GROUP(intc_irq28_0),
1828 SH_PFC_PIN_GROUP(intc_irq28_1),
1829 SH_PFC_PIN_GROUP(intc_irq29_0),
1830 SH_PFC_PIN_GROUP(intc_irq29_1),
1831 SH_PFC_PIN_GROUP(intc_irq30_0),
1832 SH_PFC_PIN_GROUP(intc_irq30_1),
1833 SH_PFC_PIN_GROUP(intc_irq31_0),
1834 SH_PFC_PIN_GROUP(intc_irq31_1),
1835 SH_PFC_PIN_GROUP(keysc_in04_0),
1836 SH_PFC_PIN_GROUP(keysc_in04_1),
1837 SH_PFC_PIN_GROUP(keysc_in5),
1838 SH_PFC_PIN_GROUP(keysc_in6),
1839 SH_PFC_PIN_GROUP(keysc_in7),
1840 SH_PFC_PIN_GROUP(keysc_out4),
1841 SH_PFC_PIN_GROUP(keysc_out5),
1842 SH_PFC_PIN_GROUP(keysc_out6),
1843 SH_PFC_PIN_GROUP(keysc_out8),
1844 SH_PFC_PIN_GROUP(lcd_data8),
1845 SH_PFC_PIN_GROUP(lcd_data9),
1846 SH_PFC_PIN_GROUP(lcd_data12),
1847 SH_PFC_PIN_GROUP(lcd_data16),
1848 SH_PFC_PIN_GROUP(lcd_data18),
1849 SH_PFC_PIN_GROUP(lcd_data24),
1850 SH_PFC_PIN_GROUP(lcd_display),
1851 SH_PFC_PIN_GROUP(lcd_lclk),
1852 SH_PFC_PIN_GROUP(lcd_sync),
1853 SH_PFC_PIN_GROUP(lcd_sys),
1854 SH_PFC_PIN_GROUP(mmc0_data1_0),
1855 SH_PFC_PIN_GROUP(mmc0_data4_0),
1856 SH_PFC_PIN_GROUP(mmc0_data8_0),
1857 SH_PFC_PIN_GROUP(mmc0_ctrl_0),
1858 SH_PFC_PIN_GROUP(mmc0_data1_1),
1859 SH_PFC_PIN_GROUP(mmc0_data4_1),
1860 SH_PFC_PIN_GROUP(mmc0_data8_1),
1861 SH_PFC_PIN_GROUP(mmc0_ctrl_1),
1862 SH_PFC_PIN_GROUP(scifa0_data),
1863 SH_PFC_PIN_GROUP(scifa0_clk),
1864 SH_PFC_PIN_GROUP(scifa0_ctrl),
1865 SH_PFC_PIN_GROUP(scifa1_data),
1866 SH_PFC_PIN_GROUP(scifa1_clk),
1867 SH_PFC_PIN_GROUP(scifa1_ctrl),
1868 SH_PFC_PIN_GROUP(scifa2_data),
1869 SH_PFC_PIN_GROUP(scifa2_clk),
1870 SH_PFC_PIN_GROUP(scifa2_ctrl),
1871 SH_PFC_PIN_GROUP(scifa3_data),
1872 SH_PFC_PIN_GROUP(scifa3_clk),
1873 SH_PFC_PIN_GROUP(scifa3_ctrl_0),
1874 SH_PFC_PIN_GROUP(scifa3_ctrl_1),
1875 SH_PFC_PIN_GROUP(scifa4_data),
1876 SH_PFC_PIN_GROUP(scifa5_data),
1877 SH_PFC_PIN_GROUP(scifb_data),
1878 SH_PFC_PIN_GROUP(scifb_clk),
1879 SH_PFC_PIN_GROUP(scifb_ctrl),
1880 SH_PFC_PIN_GROUP(sdhi0_data1),
1881 SH_PFC_PIN_GROUP(sdhi0_data4),
1882 SH_PFC_PIN_GROUP(sdhi0_ctrl),
1883 SH_PFC_PIN_GROUP(sdhi0_cd),
1884 SH_PFC_PIN_GROUP(sdhi0_wp),
1885 SH_PFC_PIN_GROUP(sdhi1_data1),
1886 SH_PFC_PIN_GROUP(sdhi1_data4),
1887 SH_PFC_PIN_GROUP(sdhi1_ctrl),
1888 SH_PFC_PIN_GROUP(sdhi2_data1),
1889 SH_PFC_PIN_GROUP(sdhi2_data4),
1890 SH_PFC_PIN_GROUP(sdhi2_ctrl),
1891 SH_PFC_PIN_GROUP(usb0_vbus),
1892 SH_PFC_PIN_GROUP(usb0_otg_id),
1893 SH_PFC_PIN_GROUP(usb0_otg_ctrl),
1894 SH_PFC_PIN_GROUP(usb1_vbus),
1895 SH_PFC_PIN_GROUP(usb1_otg_id_0),
1896 SH_PFC_PIN_GROUP(usb1_otg_id_1),
1897 SH_PFC_PIN_GROUP(usb1_otg_ctrl_0),
1898 SH_PFC_PIN_GROUP(usb1_otg_ctrl_1),
1899 };
1900
1901 static const char * const bsc_groups[] = {
1902 "bsc_data8",
1903 "bsc_data16",
1904 "bsc_cs0",
1905 "bsc_cs2",
1906 "bsc_cs4",
1907 "bsc_cs5a",
1908 "bsc_cs5b",
1909 "bsc_cs6a",
1910 "bsc_rd_we8",
1911 "bsc_rd_we16",
1912 "bsc_bs",
1913 "bsc_rdwr",
1914 };
1915
1916 static const char * const ceu_groups[] = {
1917 "ceu_data_0_7",
1918 "ceu_data_8_15",
1919 "ceu_clk_0",
1920 "ceu_clk_1",
1921 "ceu_clk_2",
1922 "ceu_sync",
1923 "ceu_field",
1924 };
1925
1926 static const char * const flctl_groups[] = {
1927 "flctl_data",
1928 "flctl_ce0",
1929 "flctl_ce1",
1930 "flctl_ctrl",
1931 };
1932
1933 static const char * const fsia_groups[] = {
1934 "fsia_mclk_in",
1935 "fsia_mclk_out",
1936 "fsia_sclk_in",
1937 "fsia_sclk_out",
1938 "fsia_data_in",
1939 "fsia_data_out",
1940 "fsia_spdif_0",
1941 "fsia_spdif_1",
1942 };
1943
1944 static const char * const fsib_groups[] = {
1945 "fsib_mclk_in",
1946 };
1947
1948 static const char * const hdmi_groups[] = {
1949 "hdmi",
1950 };
1951
1952 static const char * const intc_groups[] = {
1953 "intc_irq0_0",
1954 "intc_irq0_1",
1955 "intc_irq1",
1956 "intc_irq2_0",
1957 "intc_irq2_1",
1958 "intc_irq3_0",
1959 "intc_irq3_1",
1960 "intc_irq4_0",
1961 "intc_irq4_1",
1962 "intc_irq5",
1963 "intc_irq6_0",
1964 "intc_irq6_1",
1965 "intc_irq7_0",
1966 "intc_irq7_1",
1967 "intc_irq8_0",
1968 "intc_irq8_1",
1969 "intc_irq9_0",
1970 "intc_irq9_1",
1971 "intc_irq10",
1972 "intc_irq11",
1973 "intc_irq12_0",
1974 "intc_irq12_1",
1975 "intc_irq13_0",
1976 "intc_irq13_1",
1977 "intc_irq14_0",
1978 "intc_irq14_1",
1979 "intc_irq15_0",
1980 "intc_irq15_1",
1981 "intc_irq16_0",
1982 "intc_irq16_1",
1983 "intc_irq17",
1984 "intc_irq18",
1985 "intc_irq19",
1986 "intc_irq20",
1987 "intc_irq21",
1988 "intc_irq22",
1989 "intc_irq23",
1990 "intc_irq24",
1991 "intc_irq25",
1992 "intc_irq26_0",
1993 "intc_irq26_1",
1994 "intc_irq27_0",
1995 "intc_irq27_1",
1996 "intc_irq28_0",
1997 "intc_irq28_1",
1998 "intc_irq29_0",
1999 "intc_irq29_1",
2000 "intc_irq30_0",
2001 "intc_irq30_1",
2002 "intc_irq31_0",
2003 "intc_irq31_1",
2004 };
2005
2006 static const char * const keysc_groups[] = {
2007 "keysc_in04_0",
2008 "keysc_in04_1",
2009 "keysc_in5",
2010 "keysc_in6",
2011 "keysc_in7",
2012 "keysc_out4",
2013 "keysc_out5",
2014 "keysc_out6",
2015 "keysc_out8",
2016 };
2017
2018 static const char * const lcd_groups[] = {
2019 "lcd_data8",
2020 "lcd_data9",
2021 "lcd_data12",
2022 "lcd_data16",
2023 "lcd_data18",
2024 "lcd_data24",
2025 "lcd_display",
2026 "lcd_lclk",
2027 "lcd_sync",
2028 "lcd_sys",
2029 };
2030
2031 static const char * const mmc0_groups[] = {
2032 "mmc0_data1_0",
2033 "mmc0_data4_0",
2034 "mmc0_data8_0",
2035 "mmc0_ctrl_0",
2036 "mmc0_data1_1",
2037 "mmc0_data4_1",
2038 "mmc0_data8_1",
2039 "mmc0_ctrl_1",
2040 };
2041
2042 static const char * const scifa0_groups[] = {
2043 "scifa0_data",
2044 "scifa0_clk",
2045 "scifa0_ctrl",
2046 };
2047
2048 static const char * const scifa1_groups[] = {
2049 "scifa1_data",
2050 "scifa1_clk",
2051 "scifa1_ctrl",
2052 };
2053
2054 static const char * const scifa2_groups[] = {
2055 "scifa2_data",
2056 "scifa2_clk",
2057 "scifa2_ctrl",
2058 };
2059
2060 static const char * const scifa3_groups[] = {
2061 "scifa3_data",
2062 "scifa3_clk",
2063 "scifa3_ctrl_0",
2064 "scifa3_ctrl_1",
2065 };
2066
2067 static const char * const scifa4_groups[] = {
2068 "scifa4_data",
2069 };
2070
2071 static const char * const scifa5_groups[] = {
2072 "scifa5_data",
2073 };
2074
2075 static const char * const scifb_groups[] = {
2076 "scifb_data",
2077 "scifb_clk",
2078 "scifb_ctrl",
2079 };
2080
2081 static const char * const sdhi0_groups[] = {
2082 "sdhi0_data1",
2083 "sdhi0_data4",
2084 "sdhi0_ctrl",
2085 "sdhi0_cd",
2086 "sdhi0_wp",
2087 };
2088
2089 static const char * const sdhi1_groups[] = {
2090 "sdhi1_data1",
2091 "sdhi1_data4",
2092 "sdhi1_ctrl",
2093 };
2094
2095 static const char * const sdhi2_groups[] = {
2096 "sdhi2_data1",
2097 "sdhi2_data4",
2098 "sdhi2_ctrl",
2099 };
2100
2101 static const char * const usb0_groups[] = {
2102 "usb0_vbus",
2103 "usb0_otg_id",
2104 "usb0_otg_ctrl",
2105 };
2106
2107 static const char * const usb1_groups[] = {
2108 "usb1_vbus",
2109 "usb1_otg_id_0",
2110 "usb1_otg_id_1",
2111 "usb1_otg_ctrl_0",
2112 "usb1_otg_ctrl_1",
2113 };
2114
2115 static const struct sh_pfc_function pinmux_functions[] = {
2116 SH_PFC_FUNCTION(bsc),
2117 SH_PFC_FUNCTION(ceu),
2118 SH_PFC_FUNCTION(flctl),
2119 SH_PFC_FUNCTION(fsia),
2120 SH_PFC_FUNCTION(fsib),
2121 SH_PFC_FUNCTION(hdmi),
2122 SH_PFC_FUNCTION(intc),
2123 SH_PFC_FUNCTION(keysc),
2124 SH_PFC_FUNCTION(lcd),
2125 SH_PFC_FUNCTION(mmc0),
2126 SH_PFC_FUNCTION(scifa0),
2127 SH_PFC_FUNCTION(scifa1),
2128 SH_PFC_FUNCTION(scifa2),
2129 SH_PFC_FUNCTION(scifa3),
2130 SH_PFC_FUNCTION(scifa4),
2131 SH_PFC_FUNCTION(scifa5),
2132 SH_PFC_FUNCTION(scifb),
2133 SH_PFC_FUNCTION(sdhi0),
2134 SH_PFC_FUNCTION(sdhi1),
2135 SH_PFC_FUNCTION(sdhi2),
2136 SH_PFC_FUNCTION(usb0),
2137 SH_PFC_FUNCTION(usb1),
2138 };
2139
2140 #undef PORTCR
2141 #define PORTCR(nr, reg) \
2142 { \
2143 PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
2144 _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \
2145 PORT##nr##_FN0, PORT##nr##_FN1, \
2146 PORT##nr##_FN2, PORT##nr##_FN3, \
2147 PORT##nr##_FN4, PORT##nr##_FN5, \
2148 PORT##nr##_FN6, PORT##nr##_FN7 } \
2149 }
2150
2151 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2152 PORTCR(0, 0xE6051000), /* PORT0CR */
2153 PORTCR(1, 0xE6051001), /* PORT1CR */
2154 PORTCR(2, 0xE6051002), /* PORT2CR */
2155 PORTCR(3, 0xE6051003), /* PORT3CR */
2156 PORTCR(4, 0xE6051004), /* PORT4CR */
2157 PORTCR(5, 0xE6051005), /* PORT5CR */
2158 PORTCR(6, 0xE6051006), /* PORT6CR */
2159 PORTCR(7, 0xE6051007), /* PORT7CR */
2160 PORTCR(8, 0xE6051008), /* PORT8CR */
2161 PORTCR(9, 0xE6051009), /* PORT9CR */
2162 PORTCR(10, 0xE605100A), /* PORT10CR */
2163 PORTCR(11, 0xE605100B), /* PORT11CR */
2164 PORTCR(12, 0xE605100C), /* PORT12CR */
2165 PORTCR(13, 0xE605100D), /* PORT13CR */
2166 PORTCR(14, 0xE605100E), /* PORT14CR */
2167 PORTCR(15, 0xE605100F), /* PORT15CR */
2168 PORTCR(16, 0xE6051010), /* PORT16CR */
2169 PORTCR(17, 0xE6051011), /* PORT17CR */
2170 PORTCR(18, 0xE6051012), /* PORT18CR */
2171 PORTCR(19, 0xE6051013), /* PORT19CR */
2172 PORTCR(20, 0xE6051014), /* PORT20CR */
2173 PORTCR(21, 0xE6051015), /* PORT21CR */
2174 PORTCR(22, 0xE6051016), /* PORT22CR */
2175 PORTCR(23, 0xE6051017), /* PORT23CR */
2176 PORTCR(24, 0xE6051018), /* PORT24CR */
2177 PORTCR(25, 0xE6051019), /* PORT25CR */
2178 PORTCR(26, 0xE605101A), /* PORT26CR */
2179 PORTCR(27, 0xE605101B), /* PORT27CR */
2180 PORTCR(28, 0xE605101C), /* PORT28CR */
2181 PORTCR(29, 0xE605101D), /* PORT29CR */
2182 PORTCR(30, 0xE605101E), /* PORT30CR */
2183 PORTCR(31, 0xE605101F), /* PORT31CR */
2184 PORTCR(32, 0xE6051020), /* PORT32CR */
2185 PORTCR(33, 0xE6051021), /* PORT33CR */
2186 PORTCR(34, 0xE6051022), /* PORT34CR */
2187 PORTCR(35, 0xE6051023), /* PORT35CR */
2188 PORTCR(36, 0xE6051024), /* PORT36CR */
2189 PORTCR(37, 0xE6051025), /* PORT37CR */
2190 PORTCR(38, 0xE6051026), /* PORT38CR */
2191 PORTCR(39, 0xE6051027), /* PORT39CR */
2192 PORTCR(40, 0xE6051028), /* PORT40CR */
2193 PORTCR(41, 0xE6051029), /* PORT41CR */
2194 PORTCR(42, 0xE605102A), /* PORT42CR */
2195 PORTCR(43, 0xE605102B), /* PORT43CR */
2196 PORTCR(44, 0xE605102C), /* PORT44CR */
2197 PORTCR(45, 0xE605102D), /* PORT45CR */
2198 PORTCR(46, 0xE605202E), /* PORT46CR */
2199 PORTCR(47, 0xE605202F), /* PORT47CR */
2200 PORTCR(48, 0xE6052030), /* PORT48CR */
2201 PORTCR(49, 0xE6052031), /* PORT49CR */
2202 PORTCR(50, 0xE6052032), /* PORT50CR */
2203 PORTCR(51, 0xE6052033), /* PORT51CR */
2204 PORTCR(52, 0xE6052034), /* PORT52CR */
2205 PORTCR(53, 0xE6052035), /* PORT53CR */
2206 PORTCR(54, 0xE6052036), /* PORT54CR */
2207 PORTCR(55, 0xE6052037), /* PORT55CR */
2208 PORTCR(56, 0xE6052038), /* PORT56CR */
2209 PORTCR(57, 0xE6052039), /* PORT57CR */
2210 PORTCR(58, 0xE605203A), /* PORT58CR */
2211 PORTCR(59, 0xE605203B), /* PORT59CR */
2212 PORTCR(60, 0xE605203C), /* PORT60CR */
2213 PORTCR(61, 0xE605203D), /* PORT61CR */
2214 PORTCR(62, 0xE605203E), /* PORT62CR */
2215 PORTCR(63, 0xE605203F), /* PORT63CR */
2216 PORTCR(64, 0xE6052040), /* PORT64CR */
2217 PORTCR(65, 0xE6052041), /* PORT65CR */
2218 PORTCR(66, 0xE6052042), /* PORT66CR */
2219 PORTCR(67, 0xE6052043), /* PORT67CR */
2220 PORTCR(68, 0xE6052044), /* PORT68CR */
2221 PORTCR(69, 0xE6052045), /* PORT69CR */
2222 PORTCR(70, 0xE6052046), /* PORT70CR */
2223 PORTCR(71, 0xE6052047), /* PORT71CR */
2224 PORTCR(72, 0xE6052048), /* PORT72CR */
2225 PORTCR(73, 0xE6052049), /* PORT73CR */
2226 PORTCR(74, 0xE605204A), /* PORT74CR */
2227 PORTCR(75, 0xE605204B), /* PORT75CR */
2228 PORTCR(76, 0xE605004C), /* PORT76CR */
2229 PORTCR(77, 0xE605004D), /* PORT77CR */
2230 PORTCR(78, 0xE605004E), /* PORT78CR */
2231 PORTCR(79, 0xE605004F), /* PORT79CR */
2232 PORTCR(80, 0xE6050050), /* PORT80CR */
2233 PORTCR(81, 0xE6050051), /* PORT81CR */
2234 PORTCR(82, 0xE6050052), /* PORT82CR */
2235 PORTCR(83, 0xE6050053), /* PORT83CR */
2236 PORTCR(84, 0xE6050054), /* PORT84CR */
2237 PORTCR(85, 0xE6050055), /* PORT85CR */
2238 PORTCR(86, 0xE6050056), /* PORT86CR */
2239 PORTCR(87, 0xE6050057), /* PORT87CR */
2240 PORTCR(88, 0xE6050058), /* PORT88CR */
2241 PORTCR(89, 0xE6050059), /* PORT89CR */
2242 PORTCR(90, 0xE605005A), /* PORT90CR */
2243 PORTCR(91, 0xE605005B), /* PORT91CR */
2244 PORTCR(92, 0xE605005C), /* PORT92CR */
2245 PORTCR(93, 0xE605005D), /* PORT93CR */
2246 PORTCR(94, 0xE605005E), /* PORT94CR */
2247 PORTCR(95, 0xE605005F), /* PORT95CR */
2248 PORTCR(96, 0xE6050060), /* PORT96CR */
2249 PORTCR(97, 0xE6050061), /* PORT97CR */
2250 PORTCR(98, 0xE6050062), /* PORT98CR */
2251 PORTCR(99, 0xE6050063), /* PORT99CR */
2252 PORTCR(100, 0xE6053064), /* PORT100CR */
2253 PORTCR(101, 0xE6053065), /* PORT101CR */
2254 PORTCR(102, 0xE6053066), /* PORT102CR */
2255 PORTCR(103, 0xE6053067), /* PORT103CR */
2256 PORTCR(104, 0xE6053068), /* PORT104CR */
2257 PORTCR(105, 0xE6053069), /* PORT105CR */
2258 PORTCR(106, 0xE605306A), /* PORT106CR */
2259 PORTCR(107, 0xE605306B), /* PORT107CR */
2260 PORTCR(108, 0xE605306C), /* PORT108CR */
2261 PORTCR(109, 0xE605306D), /* PORT109CR */
2262 PORTCR(110, 0xE605306E), /* PORT110CR */
2263 PORTCR(111, 0xE605306F), /* PORT111CR */
2264 PORTCR(112, 0xE6053070), /* PORT112CR */
2265 PORTCR(113, 0xE6053071), /* PORT113CR */
2266 PORTCR(114, 0xE6053072), /* PORT114CR */
2267 PORTCR(115, 0xE6053073), /* PORT115CR */
2268 PORTCR(116, 0xE6053074), /* PORT116CR */
2269 PORTCR(117, 0xE6053075), /* PORT117CR */
2270 PORTCR(118, 0xE6053076), /* PORT118CR */
2271 PORTCR(119, 0xE6053077), /* PORT119CR */
2272 PORTCR(120, 0xE6053078), /* PORT120CR */
2273 PORTCR(121, 0xE6050079), /* PORT121CR */
2274 PORTCR(122, 0xE605007A), /* PORT122CR */
2275 PORTCR(123, 0xE605007B), /* PORT123CR */
2276 PORTCR(124, 0xE605007C), /* PORT124CR */
2277 PORTCR(125, 0xE605007D), /* PORT125CR */
2278 PORTCR(126, 0xE605007E), /* PORT126CR */
2279 PORTCR(127, 0xE605007F), /* PORT127CR */
2280 PORTCR(128, 0xE6050080), /* PORT128CR */
2281 PORTCR(129, 0xE6050081), /* PORT129CR */
2282 PORTCR(130, 0xE6050082), /* PORT130CR */
2283 PORTCR(131, 0xE6050083), /* PORT131CR */
2284 PORTCR(132, 0xE6050084), /* PORT132CR */
2285 PORTCR(133, 0xE6050085), /* PORT133CR */
2286 PORTCR(134, 0xE6050086), /* PORT134CR */
2287 PORTCR(135, 0xE6050087), /* PORT135CR */
2288 PORTCR(136, 0xE6050088), /* PORT136CR */
2289 PORTCR(137, 0xE6050089), /* PORT137CR */
2290 PORTCR(138, 0xE605008A), /* PORT138CR */
2291 PORTCR(139, 0xE605008B), /* PORT139CR */
2292 PORTCR(140, 0xE605008C), /* PORT140CR */
2293 PORTCR(141, 0xE605008D), /* PORT141CR */
2294 PORTCR(142, 0xE605008E), /* PORT142CR */
2295 PORTCR(143, 0xE605008F), /* PORT143CR */
2296 PORTCR(144, 0xE6050090), /* PORT144CR */
2297 PORTCR(145, 0xE6050091), /* PORT145CR */
2298 PORTCR(146, 0xE6050092), /* PORT146CR */
2299 PORTCR(147, 0xE6050093), /* PORT147CR */
2300 PORTCR(148, 0xE6050094), /* PORT148CR */
2301 PORTCR(149, 0xE6050095), /* PORT149CR */
2302 PORTCR(150, 0xE6050096), /* PORT150CR */
2303 PORTCR(151, 0xE6050097), /* PORT151CR */
2304 PORTCR(152, 0xE6053098), /* PORT152CR */
2305 PORTCR(153, 0xE6053099), /* PORT153CR */
2306 PORTCR(154, 0xE605309A), /* PORT154CR */
2307 PORTCR(155, 0xE605309B), /* PORT155CR */
2308 PORTCR(156, 0xE605009C), /* PORT156CR */
2309 PORTCR(157, 0xE605009D), /* PORT157CR */
2310 PORTCR(158, 0xE605009E), /* PORT158CR */
2311 PORTCR(159, 0xE605009F), /* PORT159CR */
2312 PORTCR(160, 0xE60500A0), /* PORT160CR */
2313 PORTCR(161, 0xE60500A1), /* PORT161CR */
2314 PORTCR(162, 0xE60500A2), /* PORT162CR */
2315 PORTCR(163, 0xE60500A3), /* PORT163CR */
2316 PORTCR(164, 0xE60500A4), /* PORT164CR */
2317 PORTCR(165, 0xE60500A5), /* PORT165CR */
2318 PORTCR(166, 0xE60500A6), /* PORT166CR */
2319 PORTCR(167, 0xE60520A7), /* PORT167CR */
2320 PORTCR(168, 0xE60520A8), /* PORT168CR */
2321 PORTCR(169, 0xE60520A9), /* PORT169CR */
2322 PORTCR(170, 0xE60520AA), /* PORT170CR */
2323 PORTCR(171, 0xE60520AB), /* PORT171CR */
2324 PORTCR(172, 0xE60520AC), /* PORT172CR */
2325 PORTCR(173, 0xE60520AD), /* PORT173CR */
2326 PORTCR(174, 0xE60520AE), /* PORT174CR */
2327 PORTCR(175, 0xE60520AF), /* PORT175CR */
2328 PORTCR(176, 0xE60520B0), /* PORT176CR */
2329 PORTCR(177, 0xE60520B1), /* PORT177CR */
2330 PORTCR(178, 0xE60520B2), /* PORT178CR */
2331 PORTCR(179, 0xE60520B3), /* PORT179CR */
2332 PORTCR(180, 0xE60520B4), /* PORT180CR */
2333 PORTCR(181, 0xE60520B5), /* PORT181CR */
2334 PORTCR(182, 0xE60520B6), /* PORT182CR */
2335 PORTCR(183, 0xE60520B7), /* PORT183CR */
2336 PORTCR(184, 0xE60520B8), /* PORT184CR */
2337 PORTCR(185, 0xE60520B9), /* PORT185CR */
2338 PORTCR(186, 0xE60520BA), /* PORT186CR */
2339 PORTCR(187, 0xE60520BB), /* PORT187CR */
2340 PORTCR(188, 0xE60520BC), /* PORT188CR */
2341 PORTCR(189, 0xE60520BD), /* PORT189CR */
2342 PORTCR(190, 0xE60520BE), /* PORT190CR */
2343
2344 { PINMUX_CFG_REG("MSEL1CR", 0xE605800C, 32, 1) {
2345 MSEL1CR_31_0, MSEL1CR_31_1,
2346 MSEL1CR_30_0, MSEL1CR_30_1,
2347 MSEL1CR_29_0, MSEL1CR_29_1,
2348 MSEL1CR_28_0, MSEL1CR_28_1,
2349 MSEL1CR_27_0, MSEL1CR_27_1,
2350 MSEL1CR_26_0, MSEL1CR_26_1,
2351 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2352 0, 0, 0, 0, 0, 0, 0, 0,
2353 MSEL1CR_16_0, MSEL1CR_16_1,
2354 MSEL1CR_15_0, MSEL1CR_15_1,
2355 MSEL1CR_14_0, MSEL1CR_14_1,
2356 MSEL1CR_13_0, MSEL1CR_13_1,
2357 MSEL1CR_12_0, MSEL1CR_12_1,
2358 0, 0, 0, 0,
2359 MSEL1CR_9_0, MSEL1CR_9_1,
2360 MSEL1CR_8_0, MSEL1CR_8_1,
2361 MSEL1CR_7_0, MSEL1CR_7_1,
2362 MSEL1CR_6_0, MSEL1CR_6_1,
2363 0, 0,
2364 MSEL1CR_4_0, MSEL1CR_4_1,
2365 MSEL1CR_3_0, MSEL1CR_3_1,
2366 MSEL1CR_2_0, MSEL1CR_2_1,
2367 0, 0,
2368 MSEL1CR_0_0, MSEL1CR_0_1,
2369 }
2370 },
2371 { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) {
2372 0, 0, 0, 0,
2373 0, 0, 0, 0,
2374 MSEL3CR_27_0, MSEL3CR_27_1,
2375 MSEL3CR_26_0, MSEL3CR_26_1,
2376 0, 0, 0, 0,
2377 0, 0, 0, 0,
2378 MSEL3CR_21_0, MSEL3CR_21_1,
2379 MSEL3CR_20_0, MSEL3CR_20_1,
2380 0, 0, 0, 0,
2381 0, 0, 0, 0,
2382 MSEL3CR_15_0, MSEL3CR_15_1,
2383 0, 0, 0, 0,
2384 0, 0, 0, 0,
2385 0, 0,
2386 MSEL3CR_9_0, MSEL3CR_9_1,
2387 0, 0, 0, 0,
2388 MSEL3CR_6_0, MSEL3CR_6_1,
2389 0, 0, 0, 0,
2390 0, 0, 0, 0,
2391 0, 0, 0, 0,
2392 }
2393 },
2394 { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) {
2395 0, 0, 0, 0,
2396 0, 0, 0, 0,
2397 0, 0, 0, 0,
2398 0, 0, 0, 0,
2399 0, 0, 0, 0,
2400 0, 0, 0, 0,
2401 MSEL4CR_19_0, MSEL4CR_19_1,
2402 MSEL4CR_18_0, MSEL4CR_18_1,
2403 MSEL4CR_17_0, MSEL4CR_17_1,
2404 MSEL4CR_16_0, MSEL4CR_16_1,
2405 MSEL4CR_15_0, MSEL4CR_15_1,
2406 MSEL4CR_14_0, MSEL4CR_14_1,
2407 0, 0, 0, 0,
2408 0, 0,
2409 MSEL4CR_10_0, MSEL4CR_10_1,
2410 0, 0, 0, 0,
2411 0, 0,
2412 MSEL4CR_6_0, MSEL4CR_6_1,
2413 0, 0,
2414 MSEL4CR_4_0, MSEL4CR_4_1,
2415 0, 0, 0, 0,
2416 MSEL4CR_1_0, MSEL4CR_1_1,
2417 0, 0,
2418 }
2419 },
2420 { },
2421 };
2422
2423 static const struct pinmux_data_reg pinmux_data_regs[] = {
2424 { PINMUX_DATA_REG("PORTL095_064DR", 0xE6054008, 32) {
2425 PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
2426 PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
2427 PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
2428 PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
2429 PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
2430 0, 0, 0, 0,
2431 0, 0, 0, 0,
2432 0, 0, 0, 0,
2433 }
2434 },
2435 { PINMUX_DATA_REG("PORTL127_096DR", 0xE605400C, 32) {
2436 PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA,
2437 PORT123_DATA, PORT122_DATA, PORT121_DATA, 0,
2438 0, 0, 0, 0,
2439 0, 0, 0, 0,
2440 0, 0, 0, 0,
2441 0, 0, 0, 0,
2442 0, 0, 0, 0,
2443 PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA,
2444 }
2445 },
2446 { PINMUX_DATA_REG("PORTL159_128DR", 0xE6054010, 32) {
2447 PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
2448 0, 0, 0, 0,
2449 PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
2450 PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
2451 PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
2452 PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
2453 PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
2454 PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA,
2455 }
2456 },
2457 { PINMUX_DATA_REG("PORTL191_160DR", 0xE6054014, 32) {
2458 0, 0, 0, 0,
2459 0, 0, 0, 0,
2460 0, 0, 0, 0,
2461 0, 0, 0, 0,
2462 0, 0, 0, 0,
2463 0, 0, 0, 0,
2464 0, PORT166_DATA, PORT165_DATA, PORT164_DATA,
2465 PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA,
2466 }
2467 },
2468 { PINMUX_DATA_REG("PORTD031_000DR", 0xE6055000, 32) {
2469 PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
2470 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
2471 PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
2472 PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
2473 PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
2474 PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
2475 PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
2476 PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA,
2477 }
2478 },
2479 { PINMUX_DATA_REG("PORTD063_032DR", 0xE6055004, 32) {
2480 0, 0, 0, 0, 0, 0, 0, 0,
2481 0, 0, 0, 0, 0, 0, 0, 0,
2482 0, 0, PORT45_DATA, PORT44_DATA,
2483 PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
2484 PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
2485 PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA,
2486 }
2487 },
2488 { PINMUX_DATA_REG("PORTR063_032DR", 0xE6056004, 32) {
2489 PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
2490 PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
2491 PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
2492 PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
2493 PORT47_DATA, PORT46_DATA, 0, 0,
2494 0, 0, 0, 0,
2495 0, 0, 0, 0,
2496 0, 0, 0, 0,
2497 }
2498 },
2499 { PINMUX_DATA_REG("PORTR095_064DR", 0xE6056008, 32) {
2500 0, 0, 0, 0,
2501 0, 0, 0, 0,
2502 0, 0, 0, 0,
2503 0, 0, 0, 0,
2504 0, 0, 0, 0,
2505 PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
2506 PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
2507 PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA,
2508 }
2509 },
2510 { PINMUX_DATA_REG("PORTR191_160DR", 0xE6056014, 32) {
2511 0, PORT190_DATA, PORT189_DATA, PORT188_DATA,
2512 PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA,
2513 PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA,
2514 PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA,
2515 PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
2516 PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
2517 PORT167_DATA, 0, 0, 0,
2518 0, 0, 0, 0,
2519 }
2520 },
2521 { PINMUX_DATA_REG("PORTU127_096DR", 0xE605700C, 32) {
2522 0, 0, 0, 0,
2523 0, 0, 0, PORT120_DATA,
2524 PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
2525 PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
2526 PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
2527 PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
2528 PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
2529 0, 0, 0, 0,
2530 }
2531 },
2532 { PINMUX_DATA_REG("PORTU159_128DR", 0xE6057010, 32) {
2533 0, 0, 0, 0,
2534 PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
2535 0, 0, 0, 0,
2536 0, 0, 0, 0,
2537 0, 0, 0, 0,
2538 0, 0, 0, 0,
2539 0, 0, 0, 0,
2540 0, 0, 0, 0,
2541 }
2542 },
2543 { },
2544 };
2545
2546 #define EXT_IRQ16L(n) evt2irq(0x200 + ((n) << 5))
2547 #define EXT_IRQ16H(n) evt2irq(0x3200 + (((n) - 16) << 5))
2548 static const struct pinmux_irq pinmux_irqs[] = {
2549 PINMUX_IRQ(EXT_IRQ16L(0), 6, 162),
2550 PINMUX_IRQ(EXT_IRQ16L(1), 12),
2551 PINMUX_IRQ(EXT_IRQ16L(2), 4, 5),
2552 PINMUX_IRQ(EXT_IRQ16L(3), 8, 16),
2553 PINMUX_IRQ(EXT_IRQ16L(4), 17, 163),
2554 PINMUX_IRQ(EXT_IRQ16L(5), 18),
2555 PINMUX_IRQ(EXT_IRQ16L(6), 39, 164),
2556 PINMUX_IRQ(EXT_IRQ16L(7), 40, 167),
2557 PINMUX_IRQ(EXT_IRQ16L(8), 41, 168),
2558 PINMUX_IRQ(EXT_IRQ16L(9), 42, 169),
2559 PINMUX_IRQ(EXT_IRQ16L(10), 65),
2560 PINMUX_IRQ(EXT_IRQ16L(11), 67),
2561 PINMUX_IRQ(EXT_IRQ16L(12), 80, 137),
2562 PINMUX_IRQ(EXT_IRQ16L(13), 81, 145),
2563 PINMUX_IRQ(EXT_IRQ16L(14), 82, 146),
2564 PINMUX_IRQ(EXT_IRQ16L(15), 83, 147),
2565 PINMUX_IRQ(EXT_IRQ16H(16), 84, 170),
2566 PINMUX_IRQ(EXT_IRQ16H(17), 85),
2567 PINMUX_IRQ(EXT_IRQ16H(18), 86),
2568 PINMUX_IRQ(EXT_IRQ16H(19), 87),
2569 PINMUX_IRQ(EXT_IRQ16H(20), 92),
2570 PINMUX_IRQ(EXT_IRQ16H(21), 93),
2571 PINMUX_IRQ(EXT_IRQ16H(22), 94),
2572 PINMUX_IRQ(EXT_IRQ16H(23), 95),
2573 PINMUX_IRQ(EXT_IRQ16H(24), 112),
2574 PINMUX_IRQ(EXT_IRQ16H(25), 119),
2575 PINMUX_IRQ(EXT_IRQ16H(26), 121, 172),
2576 PINMUX_IRQ(EXT_IRQ16H(27), 122, 180),
2577 PINMUX_IRQ(EXT_IRQ16H(28), 123, 181),
2578 PINMUX_IRQ(EXT_IRQ16H(29), 129, 182),
2579 PINMUX_IRQ(EXT_IRQ16H(30), 130, 183),
2580 PINMUX_IRQ(EXT_IRQ16H(31), 138, 184),
2581 };
2582
2583 #define PORTnCR_PULMD_OFF (0 << 6)
2584 #define PORTnCR_PULMD_DOWN (2 << 6)
2585 #define PORTnCR_PULMD_UP (3 << 6)
2586 #define PORTnCR_PULMD_MASK (3 << 6)
2587
2588 struct sh7372_portcr_group {
2589 unsigned int end_pin;
2590 unsigned int offset;
2591 };
2592
2593 static const struct sh7372_portcr_group sh7372_portcr_offsets[] = {
2594 { 45, 0x1000 }, { 75, 0x2000 }, { 99, 0x0000 }, { 120, 0x3000 },
2595 { 151, 0x0000 }, { 155, 0x3000 }, { 166, 0x0000 }, { 190, 0x2000 },
2596 };
2597
2598 static void __iomem *sh7372_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin)
2599 {
2600 unsigned int i;
2601
2602 for (i = 0; i < ARRAY_SIZE(sh7372_portcr_offsets); ++i) {
2603 const struct sh7372_portcr_group *group =
2604 &sh7372_portcr_offsets[i];
2605
2606 if (i <= group->end_pin)
2607 return pfc->window->virt + group->offset + pin;
2608 }
2609
2610 return NULL;
2611 }
2612
2613 static unsigned int sh7372_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
2614 {
2615 void __iomem *addr = sh7372_pinmux_portcr(pfc, pin);
2616 u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
2617
2618 switch (value) {
2619 case PORTnCR_PULMD_UP:
2620 return PIN_CONFIG_BIAS_PULL_UP;
2621 case PORTnCR_PULMD_DOWN:
2622 return PIN_CONFIG_BIAS_PULL_DOWN;
2623 case PORTnCR_PULMD_OFF:
2624 default:
2625 return PIN_CONFIG_BIAS_DISABLE;
2626 }
2627 }
2628
2629 static void sh7372_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
2630 unsigned int bias)
2631 {
2632 void __iomem *addr = sh7372_pinmux_portcr(pfc, pin);
2633 u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
2634
2635 switch (bias) {
2636 case PIN_CONFIG_BIAS_PULL_UP:
2637 value |= PORTnCR_PULMD_UP;
2638 break;
2639 case PIN_CONFIG_BIAS_PULL_DOWN:
2640 value |= PORTnCR_PULMD_DOWN;
2641 break;
2642 }
2643
2644 iowrite8(value, addr);
2645 }
2646
2647 static const struct sh_pfc_soc_operations sh7372_pinmux_ops = {
2648 .get_bias = sh7372_pinmux_get_bias,
2649 .set_bias = sh7372_pinmux_set_bias,
2650 };
2651
2652 const struct sh_pfc_soc_info sh7372_pinmux_info = {
2653 .name = "sh7372_pfc",
2654 .ops = &sh7372_pinmux_ops,
2655
2656 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
2657 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
2658 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2659
2660 .pins = pinmux_pins,
2661 .nr_pins = ARRAY_SIZE(pinmux_pins),
2662 .groups = pinmux_groups,
2663 .nr_groups = ARRAY_SIZE(pinmux_groups),
2664 .functions = pinmux_functions,
2665 .nr_functions = ARRAY_SIZE(pinmux_functions),
2666
2667 .cfg_regs = pinmux_config_regs,
2668 .data_regs = pinmux_data_regs,
2669
2670 .gpio_data = pinmux_data,
2671 .gpio_data_size = ARRAY_SIZE(pinmux_data),
2672
2673 .gpio_irq = pinmux_irqs,
2674 .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
2675 };
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