drivers/pinctrl/sirf/pinctrl-atlas6.c

   1 /*
   2  * pinctrl pads, groups, functions for CSR SiRFatlasVI
   3  *
   4  * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 #include <linux/pinctrl/pinctrl.h>
  10 #include <linux/bitops.h>
  11
  12 #include "pinctrl-sirf.h"
  13
  14 /*
  15  * pad list for the pinmux subsystem
  16  * refer to atlasVI_io_table_v0.93.xls
  17  */
  18 static const struct pinctrl_pin_desc sirfsoc_pads[] = {
  19         PINCTRL_PIN(0, "gpio0-0"),
  20         PINCTRL_PIN(1, "gpio0-1"),
  21         PINCTRL_PIN(2, "gpio0-2"),
  22         PINCTRL_PIN(3, "gpio0-3"),
  23         PINCTRL_PIN(4, "pwm0"),
  24         PINCTRL_PIN(5, "pwm1"),
  25         PINCTRL_PIN(6, "pwm2"),
  26         PINCTRL_PIN(7, "pwm3"),
  27         PINCTRL_PIN(8, "warm_rst_b"),
  28         PINCTRL_PIN(9, "odo_0"),
  29         PINCTRL_PIN(10, "odo_1"),
  30         PINCTRL_PIN(11, "dr_dir"),
  31         PINCTRL_PIN(12, "rts_0"),
  32         PINCTRL_PIN(13, "scl_1"),
  33         PINCTRL_PIN(14, "ntrst"),
  34         PINCTRL_PIN(15, "sda_1"),
  35         PINCTRL_PIN(16, "x_ldd[16]"),
  36         PINCTRL_PIN(17, "x_ldd[17]"),
  37         PINCTRL_PIN(18, "x_ldd[18]"),
  38         PINCTRL_PIN(19, "x_ldd[19]"),
  39         PINCTRL_PIN(20, "x_ldd[20]"),
  40         PINCTRL_PIN(21, "x_ldd[21]"),
  41         PINCTRL_PIN(22, "x_ldd[22]"),
  42         PINCTRL_PIN(23, "x_ldd[23]"),
  43         PINCTRL_PIN(24, "gps_sgn"),
  44         PINCTRL_PIN(25, "gps_mag"),
  45         PINCTRL_PIN(26, "gps_clk"),
  46         PINCTRL_PIN(27, "sd_cd_b_2"),
  47         PINCTRL_PIN(28, "sd_vcc_on_2"),
  48         PINCTRL_PIN(29, "sd_wp_b_2"),
  49         PINCTRL_PIN(30, "sd_clk_3"),
  50         PINCTRL_PIN(31, "sd_cmd_3"),
  51
  52         PINCTRL_PIN(32, "x_sd_dat_3[0]"),
  53         PINCTRL_PIN(33, "x_sd_dat_3[1]"),
  54         PINCTRL_PIN(34, "x_sd_dat_3[2]"),
  55         PINCTRL_PIN(35, "x_sd_dat_3[3]"),
  56         PINCTRL_PIN(36, "usb_clk"),
  57         PINCTRL_PIN(37, "usb_dir"),
  58         PINCTRL_PIN(38, "usb_nxt"),
  59         PINCTRL_PIN(39, "usb_stp"),
  60         PINCTRL_PIN(40, "usb_dat[7]"),
  61         PINCTRL_PIN(41, "usb_dat[6]"),
  62         PINCTRL_PIN(42, "x_cko_1"),
  63         PINCTRL_PIN(43, "spi_clk_1"),
  64         PINCTRL_PIN(44, "spi_dout_1"),
  65         PINCTRL_PIN(45, "spi_din_1"),
  66         PINCTRL_PIN(46, "spi_en_1"),
  67         PINCTRL_PIN(47, "x_txd_1"),
  68         PINCTRL_PIN(48, "x_txd_2"),
  69         PINCTRL_PIN(49, "x_rxd_1"),
  70         PINCTRL_PIN(50, "x_rxd_2"),
  71         PINCTRL_PIN(51, "x_usclk_0"),
  72         PINCTRL_PIN(52, "x_utxd_0"),
  73         PINCTRL_PIN(53, "x_urxd_0"),
  74         PINCTRL_PIN(54, "x_utfs_0"),
  75         PINCTRL_PIN(55, "x_urfs_0"),
  76         PINCTRL_PIN(56, "usb_dat5"),
  77         PINCTRL_PIN(57, "usb_dat4"),
  78         PINCTRL_PIN(58, "usb_dat3"),
  79         PINCTRL_PIN(59, "usb_dat2"),
  80         PINCTRL_PIN(60, "usb_dat1"),
  81         PINCTRL_PIN(61, "usb_dat0"),
  82         PINCTRL_PIN(62, "x_ldd[14]"),
  83         PINCTRL_PIN(63, "x_ldd[15]"),
  84
  85         PINCTRL_PIN(64, "x_gps_gpio"),
  86         PINCTRL_PIN(65, "x_ldd[13]"),
  87         PINCTRL_PIN(66, "x_df_we_b"),
  88         PINCTRL_PIN(67, "x_df_re_b"),
  89         PINCTRL_PIN(68, "x_txd_0"),
  90         PINCTRL_PIN(69, "x_rxd_0"),
  91         PINCTRL_PIN(70, "x_l_lck"),
  92         PINCTRL_PIN(71, "x_l_fck"),
  93         PINCTRL_PIN(72, "x_l_de"),
  94         PINCTRL_PIN(73, "x_ldd[0]"),
  95         PINCTRL_PIN(74, "x_ldd[1]"),
  96         PINCTRL_PIN(75, "x_ldd[2]"),
  97         PINCTRL_PIN(76, "x_ldd[3]"),
  98         PINCTRL_PIN(77, "x_ldd[4]"),
  99         PINCTRL_PIN(78, "x_cko_0"),
 100         PINCTRL_PIN(79, "x_ldd[5]"),
 101         PINCTRL_PIN(80, "x_ldd[6]"),
 102         PINCTRL_PIN(81, "x_ldd[7]"),
 103         PINCTRL_PIN(82, "x_ldd[8]"),
 104         PINCTRL_PIN(83, "x_ldd[9]"),
 105         PINCTRL_PIN(84, "x_ldd[10]"),
 106         PINCTRL_PIN(85, "x_ldd[11]"),
 107         PINCTRL_PIN(86, "x_ldd[12]"),
 108         PINCTRL_PIN(87, "x_vip_vsync"),
 109         PINCTRL_PIN(88, "x_vip_hsync"),
 110         PINCTRL_PIN(89, "x_vip_pxclk"),
 111         PINCTRL_PIN(90, "x_sda_0"),
 112         PINCTRL_PIN(91, "x_scl_0"),
 113         PINCTRL_PIN(92, "x_df_ry_by"),
 114         PINCTRL_PIN(93, "x_df_cs_b[1]"),
 115         PINCTRL_PIN(94, "x_df_cs_b[0]"),
 116         PINCTRL_PIN(95, "x_l_pclk"),
 117
 118         PINCTRL_PIN(96, "x_df_dqs"),
 119         PINCTRL_PIN(97, "x_df_wp_b"),
 120         PINCTRL_PIN(98, "ac97_sync"),
 121         PINCTRL_PIN(99, "ac97_bit_clk "),
 122         PINCTRL_PIN(100, "ac97_dout"),
 123         PINCTRL_PIN(101, "ac97_din"),
 124         PINCTRL_PIN(102, "x_rtc_io"),
 125 };
 126
 127 static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
 128         {
 129                 .group = 1,
 130                 .mask = BIT(30) | BIT(31),
 131         }, {
 132                 .group = 2,
 133                 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
 134                         BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) |
 135                         BIT(20) | BIT(21) | BIT(22) | BIT(31),
 136         },
 137 };
 138
 139 static const struct sirfsoc_padmux lcd_16bits_padmux = {
 140         .muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask),
 141         .muxmask = lcd_16bits_sirfsoc_muxmask,
 142         .funcmask = BIT(4),
 143         .funcval = 0,
 144 };
 145
 146 static const unsigned lcd_16bits_pins[] = { 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83,
 147         84, 85, 86, 95 };
 148
 149 static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = {
 150         {
 151                 .group = 2,
 152                 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
 153                         BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) |
 154                         BIT(20) | BIT(21) | BIT(22) | BIT(31),
 155         }, {
 156                 .group = 1,
 157                 .mask = BIT(30) | BIT(31),
 158         }, {
 159                 .group = 0,
 160                 .mask = BIT(16) | BIT(17),
 161         },
 162 };
 163
 164 static const struct sirfsoc_padmux lcd_18bits_padmux = {
 165         .muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask),
 166         .muxmask = lcd_18bits_muxmask,
 167         .funcmask = BIT(4) | BIT(15),
 168         .funcval = 0,
 169 };
 170
 171 static const unsigned lcd_18bits_pins[] = { 16, 17, 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83,
 172         84, 85, 86, 95 };
 173
 174 static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = {
 175         {
 176                 .group = 2,
 177                 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
 178                         BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) |
 179                         BIT(20) | BIT(21) | BIT(22) | BIT(31),
 180         }, {
 181                 .group = 1,
 182                 .mask = BIT(30) | BIT(31),
 183         }, {
 184                 .group = 0,
 185                 .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
 186         },
 187 };
 188
 189 static const struct sirfsoc_padmux lcd_24bits_padmux = {
 190         .muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask),
 191         .muxmask = lcd_24bits_muxmask,
 192         .funcmask = BIT(4) | BIT(15),
 193         .funcval = 0,
 194 };
 195
 196 static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79,
 197         80, 81, 82, 83, 84, 85, 86, 95};
 198
 199 static const struct sirfsoc_muxmask lcdrom_muxmask[] = {
 200         {
 201                 .group = 2,
 202                 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
 203                         BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) |
 204                         BIT(20) | BIT(21) | BIT(22) | BIT(31),
 205         }, {
 206                 .group = 1,
 207                 .mask = BIT(30) | BIT(31),
 208         }, {
 209                 .group = 0,
 210                 .mask = BIT(8),
 211         },
 212 };
 213
 214 static const struct sirfsoc_padmux lcdrom_padmux = {
 215         .muxmask_counts = ARRAY_SIZE(lcdrom_muxmask),
 216         .muxmask = lcdrom_muxmask,
 217         .funcmask = BIT(4),
 218         .funcval = BIT(4),
 219 };
 220
 221 static const unsigned lcdrom_pins[] = { 8, 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83,
 222         84, 85, 86, 95};
 223
 224 static const struct sirfsoc_muxmask uart0_muxmask[] = {
 225         {
 226                 .group = 0,
 227                 .mask = BIT(12),
 228         }, {
 229                 .group = 1,
 230                 .mask = BIT(23),
 231         }, {
 232                 .group = 2,
 233                 .mask = BIT(4) | BIT(5),
 234         },
 235 };
 236
 237 static const struct sirfsoc_padmux uart0_padmux = {
 238         .muxmask_counts = ARRAY_SIZE(uart0_muxmask),
 239         .muxmask = uart0_muxmask,
 240         .funcmask = BIT(9),
 241         .funcval = BIT(9),
 242 };
 243
 244 static const unsigned uart0_pins[] = { 12, 55, 68, 69 };
 245
 246 static const struct sirfsoc_muxmask uart0_nostreamctrl_muxmask[] = {
 247         {
 248                 .group = 2,
 249                 .mask = BIT(4) | BIT(5),
 250         },
 251 };
 252
 253 static const struct sirfsoc_padmux uart0_nostreamctrl_padmux = {
 254         .muxmask_counts = ARRAY_SIZE(uart0_nostreamctrl_muxmask),
 255         .muxmask = uart0_nostreamctrl_muxmask,
 256 };
 257
 258 static const unsigned uart0_nostreamctrl_pins[] = { 68, 69 };
 259
 260 static const struct sirfsoc_muxmask uart1_muxmask[] = {
 261         {
 262                 .group = 1,
 263                 .mask = BIT(15) | BIT(17),
 264         },
 265 };
 266
 267 static const struct sirfsoc_padmux uart1_padmux = {
 268         .muxmask_counts = ARRAY_SIZE(uart1_muxmask),
 269         .muxmask = uart1_muxmask,
 270 };
 271
 272 static const unsigned uart1_pins[] = { 47, 49 };
 273
 274 static const struct sirfsoc_muxmask uart2_muxmask[] = {
 275         {
 276                 .group = 0,
 277                 .mask = BIT(10) | BIT(14),
 278         }, {
 279                 .group = 1,
 280                 .mask = BIT(16) | BIT(18),
 281         },
 282 };
 283
 284 static const struct sirfsoc_padmux uart2_padmux = {
 285         .muxmask_counts = ARRAY_SIZE(uart2_muxmask),
 286         .muxmask = uart2_muxmask,
 287         .funcmask = BIT(10),
 288         .funcval = BIT(10),
 289 };
 290
 291 static const unsigned uart2_pins[] = { 10, 14, 48, 50 };
 292
 293 static const struct sirfsoc_muxmask uart2_nostreamctrl_muxmask[] = {
 294         {
 295                 .group = 1,
 296                 .mask = BIT(16) | BIT(18),
 297         },
 298 };
 299
 300 static const struct sirfsoc_padmux uart2_nostreamctrl_padmux = {
 301         .muxmask_counts = ARRAY_SIZE(uart2_nostreamctrl_muxmask),
 302         .muxmask = uart2_nostreamctrl_muxmask,
 303 };
 304
 305 static const unsigned uart2_nostreamctrl_pins[] = { 48, 50 };
 306
 307 static const struct sirfsoc_muxmask sdmmc3_muxmask[] = {
 308         {
 309                 .group = 0,
 310                 .mask = BIT(30) | BIT(31),
 311         }, {
 312                 .group = 1,
 313                 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
 314         },
 315 };
 316
 317 static const struct sirfsoc_padmux sdmmc3_padmux = {
 318         .muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask),
 319         .muxmask = sdmmc3_muxmask,
 320         .funcmask = BIT(7),
 321         .funcval = 0,
 322 };
 323
 324 static const unsigned sdmmc3_pins[] = { 30, 31, 32, 33, 34, 35 };
 325
 326 static const struct sirfsoc_muxmask spi0_muxmask[] = {
 327         {
 328                 .group = 0,
 329                 .mask = BIT(30),
 330         }, {
 331                 .group = 1,
 332                 .mask = BIT(0) | BIT(2) | BIT(3),
 333         },
 334 };
 335
 336 static const struct sirfsoc_padmux spi0_padmux = {
 337         .muxmask_counts = ARRAY_SIZE(spi0_muxmask),
 338         .muxmask = spi0_muxmask,
 339         .funcmask = BIT(7),
 340         .funcval = BIT(7),
 341 };
 342
 343 static const unsigned spi0_pins[] = { 30, 32, 34, 35 };
 344
 345 static const struct sirfsoc_muxmask cko1_muxmask[] = {
 346         {
 347                 .group = 1,
 348                 .mask = BIT(10),
 349         },
 350 };
 351
 352 static const struct sirfsoc_padmux cko1_padmux = {
 353         .muxmask_counts = ARRAY_SIZE(cko1_muxmask),
 354         .muxmask = cko1_muxmask,
 355         .funcmask = BIT(3),
 356         .funcval = 0,
 357 };
 358
 359 static const unsigned cko1_pins[] = { 42 };
 360
 361 static const struct sirfsoc_muxmask i2s_muxmask[] = {
 362         {
 363                 .group = 1,
 364                 .mask = BIT(10),
 365         }, {
 366                 .group = 3,
 367                 .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
 368         },
 369 };
 370
 371 static const struct sirfsoc_padmux i2s_padmux = {
 372         .muxmask_counts = ARRAY_SIZE(i2s_muxmask),
 373         .muxmask = i2s_muxmask,
 374         .funcmask = BIT(3),
 375         .funcval = BIT(3),
 376 };
 377
 378 static const unsigned i2s_pins[] = { 42, 98, 99, 100, 101 };
 379
 380 static const struct sirfsoc_muxmask i2s_no_din_muxmask[] = {
 381         {
 382                 .group = 1,
 383                 .mask = BIT(10),
 384         }, {
 385                 .group = 3,
 386                 .mask = BIT(2) | BIT(3) | BIT(4),
 387         },
 388 };
 389
 390 static const struct sirfsoc_padmux i2s_no_din_padmux = {
 391         .muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask),
 392         .muxmask = i2s_no_din_muxmask,
 393         .funcmask = BIT(3),
 394         .funcval = BIT(3),
 395 };
 396
 397 static const unsigned i2s_no_din_pins[] = { 42, 98, 99, 100 };
 398
 399 static const struct sirfsoc_muxmask i2s_6chn_muxmask[] = {
 400         {
 401                 .group = 1,
 402                 .mask = BIT(10) | BIT(20) | BIT(23),
 403         }, {
 404                 .group = 3,
 405                 .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
 406         },
 407 };
 408
 409 static const struct sirfsoc_padmux i2s_6chn_padmux = {
 410         .muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask),
 411         .muxmask = i2s_6chn_muxmask,
 412         .funcmask = BIT(1) | BIT(3) | BIT(9),
 413         .funcval = BIT(1) | BIT(3) | BIT(9),
 414 };
 415
 416 static const unsigned i2s_6chn_pins[] = { 42, 52, 55, 98, 99, 100, 101 };
 417
 418 static const struct sirfsoc_muxmask ac97_muxmask[] = {
 419         {
 420                 .group = 3,
 421                 .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
 422         },
 423 };
 424
 425 static const struct sirfsoc_padmux ac97_padmux = {
 426         .muxmask_counts = ARRAY_SIZE(ac97_muxmask),
 427         .muxmask = ac97_muxmask,
 428 };
 429
 430 static const unsigned ac97_pins[] = { 98, 99, 100, 101 };
 431
 432 static const struct sirfsoc_muxmask spi1_muxmask[] = {
 433         {
 434                 .group = 1,
 435                 .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
 436         },
 437 };
 438
 439 static const struct sirfsoc_padmux spi1_padmux = {
 440         .muxmask_counts = ARRAY_SIZE(spi1_muxmask),
 441         .muxmask = spi1_muxmask,
 442         .funcmask = BIT(16),
 443         .funcval = 0,
 444 };
 445
 446 static const unsigned spi1_pins[] = { 43, 44, 45, 46 };
 447
 448 static const struct sirfsoc_muxmask sdmmc1_muxmask[] = {
 449         {
 450                 .group = 2,
 451                 .mask = BIT(2) | BIT(3),
 452         },
 453 };
 454
 455 static const struct sirfsoc_padmux sdmmc1_padmux = {
 456         .muxmask_counts = ARRAY_SIZE(sdmmc1_muxmask),
 457         .muxmask = sdmmc1_muxmask,
 458         .funcmask = BIT(5),
 459         .funcval = BIT(5),
 460 };
 461
 462 static const unsigned sdmmc1_pins[] = { 66, 67 };
 463
 464 static const struct sirfsoc_muxmask gps_muxmask[] = {
 465         {
 466                 .group = 0,
 467                 .mask = BIT(24) | BIT(25) | BIT(26),
 468         },
 469 };
 470
 471 static const struct sirfsoc_padmux gps_padmux = {
 472         .muxmask_counts = ARRAY_SIZE(gps_muxmask),
 473         .muxmask = gps_muxmask,
 474         .funcmask = BIT(13),
 475         .funcval = 0,
 476 };
 477
 478 static const unsigned gps_pins[] = { 24, 25, 26 };
 479
 480 static const struct sirfsoc_muxmask sdmmc5_muxmask[] = {
 481         {
 482                 .group = 0,
 483                 .mask = BIT(24) | BIT(25) | BIT(26),
 484         },
 485 };
 486
 487 static const struct sirfsoc_padmux sdmmc5_padmux = {
 488         .muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask),
 489         .muxmask = sdmmc5_muxmask,
 490         .funcmask = BIT(13),
 491         .funcval = BIT(13),
 492 };
 493
 494 static const unsigned sdmmc5_pins[] = { 24, 25, 26 };
 495
 496 static const struct sirfsoc_muxmask usp0_muxmask[] = {
 497         {
 498                 .group = 1,
 499                 .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
 500         },
 501 };
 502
 503 static const struct sirfsoc_padmux usp0_padmux = {
 504         .muxmask_counts = ARRAY_SIZE(usp0_muxmask),
 505         .muxmask = usp0_muxmask,
 506         .funcmask = BIT(1) | BIT(2) | BIT(9),
 507         .funcval = 0,
 508 };
 509
 510 static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 };
 511
 512 static const struct sirfsoc_muxmask usp0_uart_nostreamctrl_muxmask[] = {
 513         {
 514                 .group = 1,
 515                 .mask = BIT(20) | BIT(21),
 516         },
 517 };
 518
 519 static const struct sirfsoc_padmux usp0_uart_nostreamctrl_padmux = {
 520         .muxmask_counts = ARRAY_SIZE(usp0_uart_nostreamctrl_muxmask),
 521         .muxmask = usp0_uart_nostreamctrl_muxmask,
 522 };
 523
 524 static const unsigned usp0_uart_nostreamctrl_pins[] = { 52, 53 };
 525 static const struct sirfsoc_muxmask usp1_muxmask[] = {
 526         {
 527                 .group = 0,
 528                 .mask = BIT(15),
 529         }, {
 530                 .group = 1,
 531                 .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
 532         },
 533 };
 534
 535 static const struct sirfsoc_padmux usp1_padmux = {
 536         .muxmask_counts = ARRAY_SIZE(usp1_muxmask),
 537         .muxmask = usp1_muxmask,
 538         .funcmask = BIT(16),
 539         .funcval = BIT(16),
 540 };
 541
 542 static const unsigned usp1_pins[] = { 15, 43, 44, 45, 46 };
 543
 544 static const struct sirfsoc_muxmask nand_muxmask[] = {
 545         {
 546                 .group = 2,
 547                 .mask = BIT(2) | BIT(3) | BIT(28) | BIT(29) | BIT(30),
 548         }, {
 549                 .group = 3,
 550                 .mask = BIT(0) | BIT(1),
 551         },
 552 };
 553
 554 static const struct sirfsoc_padmux nand_padmux = {
 555         .muxmask_counts = ARRAY_SIZE(nand_muxmask),
 556         .muxmask = nand_muxmask,
 557         .funcmask = BIT(5) | BIT(19),
 558         .funcval = 0,
 559 };
 560
 561 static const unsigned nand_pins[] = { 66, 67, 92, 93, 94, 96, 97 };
 562
 563 static const struct sirfsoc_muxmask sdmmc0_muxmask[] = {
 564         {
 565                 .group = 3,
 566                 .mask = BIT(1),
 567         },
 568 };
 569
 570 static const struct sirfsoc_padmux sdmmc0_padmux = {
 571         .muxmask_counts = ARRAY_SIZE(sdmmc0_muxmask),
 572         .muxmask = sdmmc0_muxmask,
 573         .funcmask = BIT(5) | BIT(19),
 574         .funcval = BIT(19),
 575 };
 576
 577 static const unsigned sdmmc0_pins[] = { 97 };
 578
 579 static const struct sirfsoc_muxmask sdmmc2_muxmask[] = {
 580         {
 581                 .group = 0,
 582                 .mask = BIT(27) | BIT(28) | BIT(29),
 583         },
 584 };
 585
 586 static const struct sirfsoc_padmux sdmmc2_padmux = {
 587         .muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask),
 588         .muxmask = sdmmc2_muxmask,
 589         .funcmask = BIT(11),
 590         .funcval = 0,
 591 };
 592
 593 static const unsigned sdmmc2_pins[] = { 27, 28, 29 };
 594
 595 static const struct sirfsoc_muxmask sdmmc2_nowp_muxmask[] = {
 596         {
 597                 .group = 0,
 598                 .mask = BIT(27) | BIT(28),
 599         },
 600 };
 601
 602 static const struct sirfsoc_padmux sdmmc2_nowp_padmux = {
 603         .muxmask_counts = ARRAY_SIZE(sdmmc2_nowp_muxmask),
 604         .muxmask = sdmmc2_nowp_muxmask,
 605         .funcmask = BIT(11),
 606         .funcval = 0,
 607 };
 608
 609 static const unsigned sdmmc2_nowp_pins[] = { 27, 28 };
 610
 611 static const struct sirfsoc_muxmask cko0_muxmask[] = {
 612         {
 613                 .group = 2,
 614                 .mask = BIT(14),
 615         },
 616 };
 617
 618 static const struct sirfsoc_padmux cko0_padmux = {
 619         .muxmask_counts = ARRAY_SIZE(cko0_muxmask),
 620         .muxmask = cko0_muxmask,
 621 };
 622
 623 static const unsigned cko0_pins[] = { 78 };
 624
 625 static const struct sirfsoc_muxmask vip_muxmask[] = {
 626         {
 627                 .group = 1,
 628                 .mask = BIT(4) | BIT(5) | BIT(6) | BIT(8) | BIT(9)
 629                         | BIT(24) | BIT(25) | BIT(26) | BIT(27) | BIT(28) |
 630                         BIT(29),
 631         },
 632 };
 633
 634 static const struct sirfsoc_padmux vip_padmux = {
 635         .muxmask_counts = ARRAY_SIZE(vip_muxmask),
 636         .muxmask = vip_muxmask,
 637         .funcmask = BIT(18),
 638         .funcval = BIT(18),
 639 };
 640
 641 static const unsigned vip_pins[] = { 36, 37, 38, 40, 41, 56, 57, 58, 59, 60, 61 };
 642
 643 static const struct sirfsoc_muxmask vip_noupli_muxmask[] = {
 644         {
 645                 .group = 0,
 646                 .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20)
 647                         | BIT(21) | BIT(22) | BIT(23),
 648         }, {
 649                 .group = 2,
 650                 .mask = BIT(23) | BIT(24) | BIT(25),
 651         },
 652 };
 653
 654 static const struct sirfsoc_padmux vip_noupli_padmux = {
 655         .muxmask_counts = ARRAY_SIZE(vip_noupli_muxmask),
 656         .muxmask = vip_noupli_muxmask,
 657         .funcmask = BIT(15),
 658         .funcval = BIT(15),
 659 };
 660
 661 static const unsigned vip_noupli_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 87, 88, 89 };
 662
 663 static const struct sirfsoc_muxmask i2c0_muxmask[] = {
 664         {
 665                 .group = 2,
 666                 .mask = BIT(26) | BIT(27),
 667         },
 668 };
 669
 670 static const struct sirfsoc_padmux i2c0_padmux = {
 671         .muxmask_counts = ARRAY_SIZE(i2c0_muxmask),
 672         .muxmask = i2c0_muxmask,
 673 };
 674
 675 static const unsigned i2c0_pins[] = { 90, 91 };
 676
 677 static const struct sirfsoc_muxmask i2c1_muxmask[] = {
 678         {
 679                 .group = 0,
 680                 .mask = BIT(13) | BIT(15),
 681         },
 682 };
 683
 684 static const struct sirfsoc_padmux i2c1_padmux = {
 685         .muxmask_counts = ARRAY_SIZE(i2c1_muxmask),
 686         .muxmask = i2c1_muxmask,
 687         .funcmask = BIT(16),
 688         .funcval = 0,
 689 };
 690
 691 static const unsigned i2c1_pins[] = { 13, 15 };
 692
 693 static const struct sirfsoc_muxmask pwm0_muxmask[] = {
 694         {
 695                 .group = 0,
 696                 .mask = BIT(4),
 697         },
 698 };
 699
 700 static const struct sirfsoc_padmux pwm0_padmux = {
 701         .muxmask_counts = ARRAY_SIZE(pwm0_muxmask),
 702         .muxmask = pwm0_muxmask,
 703         .funcmask = BIT(12),
 704         .funcval = 0,
 705 };
 706
 707 static const unsigned pwm0_pins[] = { 4 };
 708
 709 static const struct sirfsoc_muxmask pwm1_muxmask[] = {
 710         {
 711                 .group = 0,
 712                 .mask = BIT(5),
 713         },
 714 };
 715
 716 static const struct sirfsoc_padmux pwm1_padmux = {
 717         .muxmask_counts = ARRAY_SIZE(pwm1_muxmask),
 718         .muxmask = pwm1_muxmask,
 719 };
 720
 721 static const unsigned pwm1_pins[] = { 5 };
 722
 723 static const struct sirfsoc_muxmask pwm2_muxmask[] = {
 724         {
 725                 .group = 0,
 726                 .mask = BIT(6),
 727         },
 728 };
 729
 730 static const struct sirfsoc_padmux pwm2_padmux = {
 731         .muxmask_counts = ARRAY_SIZE(pwm2_muxmask),
 732         .muxmask = pwm2_muxmask,
 733 };
 734
 735 static const unsigned pwm2_pins[] = { 6 };
 736
 737 static const struct sirfsoc_muxmask pwm3_muxmask[] = {
 738         {
 739                 .group = 0,
 740                 .mask = BIT(7),
 741         },
 742 };
 743
 744 static const struct sirfsoc_padmux pwm3_padmux = {
 745         .muxmask_counts = ARRAY_SIZE(pwm3_muxmask),
 746         .muxmask = pwm3_muxmask,
 747 };
 748
 749 static const unsigned pwm3_pins[] = { 7 };
 750
 751 static const struct sirfsoc_muxmask pwm4_muxmask[] = {
 752         {
 753                 .group = 2,
 754                 .mask = BIT(14),
 755         },
 756 };
 757
 758 static const struct sirfsoc_padmux pwm4_padmux = {
 759         .muxmask_counts = ARRAY_SIZE(pwm4_muxmask),
 760         .muxmask = pwm4_muxmask,
 761 };
 762
 763 static const unsigned pwm4_pins[] = { 78 };
 764
 765 static const struct sirfsoc_muxmask warm_rst_muxmask[] = {
 766         {
 767                 .group = 0,
 768                 .mask = BIT(8),
 769         },
 770 };
 771
 772 static const struct sirfsoc_padmux warm_rst_padmux = {
 773         .muxmask_counts = ARRAY_SIZE(warm_rst_muxmask),
 774         .muxmask = warm_rst_muxmask,
 775         .funcmask = BIT(4),
 776         .funcval = 0,
 777 };
 778
 779 static const unsigned warm_rst_pins[] = { 8 };
 780
 781 static const struct sirfsoc_muxmask usb0_upli_drvbus_muxmask[] = {
 782         {
 783                 .group = 1,
 784                 .mask = BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8)
 785                         | BIT(9) | BIT(24) | BIT(25) | BIT(26) |
 786                         BIT(27) | BIT(28) | BIT(29),
 787         },
 788 };
 789 static const struct sirfsoc_padmux usb0_upli_drvbus_padmux = {
 790         .muxmask_counts = ARRAY_SIZE(usb0_upli_drvbus_muxmask),
 791         .muxmask = usb0_upli_drvbus_muxmask,
 792         .funcmask = BIT(18),
 793         .funcval = 0,
 794 };
 795
 796 static const unsigned usb0_upli_drvbus_pins[] = { 36, 37, 38, 39, 40, 41, 56, 57, 58, 59, 60, 61 };
 797
 798 static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = {
 799         {
 800                 .group = 0,
 801                 .mask = BIT(28),
 802         },
 803 };
 804
 805 static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = {
 806         .muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask),
 807         .muxmask = usb1_utmi_drvbus_muxmask,
 808         .funcmask = BIT(11),
 809         .funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */
 810 };
 811
 812 static const unsigned usb1_utmi_drvbus_pins[] = { 28 };
 813
 814 static const struct sirfsoc_muxmask pulse_count_muxmask[] = {
 815         {
 816                 .group = 0,
 817                 .mask = BIT(9) | BIT(10) | BIT(11),
 818         },
 819 };
 820
 821 static const struct sirfsoc_padmux pulse_count_padmux = {
 822         .muxmask_counts = ARRAY_SIZE(pulse_count_muxmask),
 823         .muxmask = pulse_count_muxmask,
 824 };
 825
 826 static const unsigned pulse_count_pins[] = { 9, 10, 11 };
 827
 828 static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
 829         SIRFSOC_PIN_GROUP("lcd_16bitsgrp", lcd_16bits_pins),
 830         SIRFSOC_PIN_GROUP("lcd_18bitsgrp", lcd_18bits_pins),
 831         SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins),
 832         SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins),
 833         SIRFSOC_PIN_GROUP("uart0grp", uart0_pins),
 834         SIRFSOC_PIN_GROUP("uart1grp", uart1_pins),
 835         SIRFSOC_PIN_GROUP("uart2grp", uart2_pins),
 836         SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins),
 837         SIRFSOC_PIN_GROUP("usp0grp", usp0_pins),
 838         SIRFSOC_PIN_GROUP("usp0_uart_nostreamctrl_grp",
 839                                         usp0_uart_nostreamctrl_pins),
 840         SIRFSOC_PIN_GROUP("usp1grp", usp1_pins),
 841         SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins),
 842         SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins),
 843         SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins),
 844         SIRFSOC_PIN_GROUP("pwm1grp", pwm1_pins),
 845         SIRFSOC_PIN_GROUP("pwm2grp", pwm2_pins),
 846         SIRFSOC_PIN_GROUP("pwm3grp", pwm3_pins),
 847         SIRFSOC_PIN_GROUP("pwm4grp", pwm4_pins),
 848         SIRFSOC_PIN_GROUP("vipgrp", vip_pins),
 849         SIRFSOC_PIN_GROUP("vip_noupligrp", vip_noupli_pins),
 850         SIRFSOC_PIN_GROUP("warm_rstgrp", warm_rst_pins),
 851         SIRFSOC_PIN_GROUP("cko0grp", cko0_pins),
 852         SIRFSOC_PIN_GROUP("cko1grp", cko1_pins),
 853         SIRFSOC_PIN_GROUP("sdmmc0grp", sdmmc0_pins),
 854         SIRFSOC_PIN_GROUP("sdmmc1grp", sdmmc1_pins),
 855         SIRFSOC_PIN_GROUP("sdmmc2grp", sdmmc2_pins),
 856         SIRFSOC_PIN_GROUP("sdmmc2_nowpgrp", sdmmc2_nowp_pins),
 857         SIRFSOC_PIN_GROUP("sdmmc3grp", sdmmc3_pins),
 858         SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins),
 859         SIRFSOC_PIN_GROUP("usb0_upli_drvbusgrp", usb0_upli_drvbus_pins),
 860         SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins),
 861         SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
 862         SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
 863         SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins),
 864         SIRFSOC_PIN_GROUP("i2s_6chngrp", i2s_6chn_pins),
 865         SIRFSOC_PIN_GROUP("ac97grp", ac97_pins),
 866         SIRFSOC_PIN_GROUP("nandgrp", nand_pins),
 867         SIRFSOC_PIN_GROUP("spi0grp", spi0_pins),
 868         SIRFSOC_PIN_GROUP("spi1grp", spi1_pins),
 869         SIRFSOC_PIN_GROUP("gpsgrp", gps_pins),
 870 };
 871
 872 static const char * const lcd_16bitsgrp[] = { "lcd_16bitsgrp" };
 873 static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" };
 874 static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" };
 875 static const char * const lcdromgrp[] = { "lcdromgrp" };
 876 static const char * const uart0grp[] = { "uart0grp" };
 877 static const char * const uart1grp[] = { "uart1grp" };
 878 static const char * const uart2grp[] = { "uart2grp" };
 879 static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" };
 880 static const char * const usp0_uart_nostreamctrl_grp[] = {
 881                                         "usp0_uart_nostreamctrl_grp" };
 882 static const char * const usp0grp[] = { "usp0grp" };
 883 static const char * const usp1grp[] = { "usp1grp" };
 884 static const char * const i2c0grp[] = { "i2c0grp" };
 885 static const char * const i2c1grp[] = { "i2c1grp" };
 886 static const char * const pwm0grp[] = { "pwm0grp" };
 887 static const char * const pwm1grp[] = { "pwm1grp" };
 888 static const char * const pwm2grp[] = { "pwm2grp" };
 889 static const char * const pwm3grp[] = { "pwm3grp" };
 890 static const char * const pwm4grp[] = { "pwm4grp" };
 891 static const char * const vipgrp[] = { "vipgrp" };
 892 static const char * const vip_noupligrp[] = { "vip_noupligrp" };
 893 static const char * const warm_rstgrp[] = { "warm_rstgrp" };
 894 static const char * const cko0grp[] = { "cko0grp" };
 895 static const char * const cko1grp[] = { "cko1grp" };
 896 static const char * const sdmmc0grp[] = { "sdmmc0grp" };
 897 static const char * const sdmmc1grp[] = { "sdmmc1grp" };
 898 static const char * const sdmmc2grp[] = { "sdmmc2grp" };
 899 static const char * const sdmmc3grp[] = { "sdmmc3grp" };
 900 static const char * const sdmmc5grp[] = { "sdmmc5grp" };
 901 static const char * const sdmmc2_nowpgrp[] = { "sdmmc2_nowpgrp" };
 902 static const char * const usb0_upli_drvbusgrp[] = { "usb0_upli_drvbusgrp" };
 903 static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" };
 904 static const char * const pulse_countgrp[] = { "pulse_countgrp" };
 905 static const char * const i2sgrp[] = { "i2sgrp" };
 906 static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" };
 907 static const char * const i2s_6chngrp[] = { "i2s_6chngrp" };
 908 static const char * const ac97grp[] = { "ac97grp" };
 909 static const char * const nandgrp[] = { "nandgrp" };
 910 static const char * const spi0grp[] = { "spi0grp" };
 911 static const char * const spi1grp[] = { "spi1grp" };
 912 static const char * const gpsgrp[] = { "gpsgrp" };
 913
 914 static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
 915         SIRFSOC_PMX_FUNCTION("lcd_16bits", lcd_16bitsgrp, lcd_16bits_padmux),
 916         SIRFSOC_PMX_FUNCTION("lcd_18bits", lcd_18bitsgrp, lcd_18bits_padmux),
 917         SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux),
 918         SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux),
 919         SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux),
 920         SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux),
 921         SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux),
 922         SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
 923         SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux),
 924         SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl",
 925                                                 usp0_uart_nostreamctrl_grp,
 926                                                 usp0_uart_nostreamctrl_padmux),
 927         SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux),
 928         SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux),
 929         SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux),
 930         SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux),
 931         SIRFSOC_PMX_FUNCTION("pwm1", pwm1grp, pwm1_padmux),
 932         SIRFSOC_PMX_FUNCTION("pwm2", pwm2grp, pwm2_padmux),
 933         SIRFSOC_PMX_FUNCTION("pwm3", pwm3grp, pwm3_padmux),
 934         SIRFSOC_PMX_FUNCTION("pwm4", pwm4grp, pwm4_padmux),
 935         SIRFSOC_PMX_FUNCTION("vip", vipgrp, vip_padmux),
 936         SIRFSOC_PMX_FUNCTION("vip_noupli", vip_noupligrp, vip_noupli_padmux),
 937         SIRFSOC_PMX_FUNCTION("warm_rst", warm_rstgrp, warm_rst_padmux),
 938         SIRFSOC_PMX_FUNCTION("cko0", cko0grp, cko0_padmux),
 939         SIRFSOC_PMX_FUNCTION("cko1", cko1grp, cko1_padmux),
 940         SIRFSOC_PMX_FUNCTION("sdmmc0", sdmmc0grp, sdmmc0_padmux),
 941         SIRFSOC_PMX_FUNCTION("sdmmc1", sdmmc1grp, sdmmc1_padmux),
 942         SIRFSOC_PMX_FUNCTION("sdmmc2", sdmmc2grp, sdmmc2_padmux),
 943         SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux),
 944         SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux),
 945         SIRFSOC_PMX_FUNCTION("sdmmc2_nowp", sdmmc2_nowpgrp, sdmmc2_nowp_padmux),
 946         SIRFSOC_PMX_FUNCTION("usb0_upli_drvbus", usb0_upli_drvbusgrp, usb0_upli_drvbus_padmux),
 947         SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
 948         SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
 949         SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
 950         SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux),
 951         SIRFSOC_PMX_FUNCTION("i2s_6chn", i2s_6chngrp, i2s_6chn_padmux),
 952         SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux),
 953         SIRFSOC_PMX_FUNCTION("nand", nandgrp, nand_padmux),
 954         SIRFSOC_PMX_FUNCTION("spi0", spi0grp, spi0_padmux),
 955         SIRFSOC_PMX_FUNCTION("spi1", spi1grp, spi1_padmux),
 956         SIRFSOC_PMX_FUNCTION("gps", gpsgrp, gps_padmux),
 957 };
 958
 959 struct sirfsoc_pinctrl_data atlas6_pinctrl_data = {
 960         (struct pinctrl_pin_desc *)sirfsoc_pads,
 961         ARRAY_SIZE(sirfsoc_pads),
 962         (struct sirfsoc_pin_group *)sirfsoc_pin_groups,
 963         ARRAY_SIZE(sirfsoc_pin_groups),
 964         (struct sirfsoc_pmx_func *)sirfsoc_pmx_functions,
 965         ARRAY_SIZE(sirfsoc_pmx_functions),
 966 };
 967